From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031775; cv=none; d=zohomail.com; s=zohoarc; b=lbCavr54rb5NZQF0i+YZjFOtNVVqeX3I2fQMkDg8R9zeQXor4c3qBz7shTks0+AOEMS8RIxL/OsWc2KpEiXtbIXMQSag4RKq6S64xT8t2lqXHaS9+jJ5EoB7xxGFZAwmVRvnY2qjUJUsaCGF3pstrQ0HHJWpSPVqZyH1kSukhMg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031775; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qEe9bxPY78rzldhxeSl0yGcr1LEt/gfI/ABj5JQK6lg=; b=Id+XamikhZQgUolBEJJKVyUzHrAdzvBA8deqDfJztj90bVTTNcRAh++9qXVRWXl+nhU8c6rJxGS1DZ+9NWSVw7jKdJ2IU5+8uhwkEG6F3PC7rn9fTKsnRAoPEMeHBmBsODwJ/LCn4cKBYLlIhs+8DaQxSXY9QqO8TF/OwfoO2sw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031775341282.8180390427872; Wed, 30 Apr 2025 09:49:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcG-0004so-PZ; Wed, 30 Apr 2025 12:49:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcF-0004o7-Cl for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:48:59 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcD-0001t1-Ql for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:48:59 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-736dd9c4b40so1239482b3a.0 for ; Wed, 30 Apr 2025 09:48:57 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031736; x=1746636536; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qEe9bxPY78rzldhxeSl0yGcr1LEt/gfI/ABj5JQK6lg=; b=KK7nyOnes8LsJ3/kuzaFefB9ID7cmyhbHtG2RgXh1YWkdEj7VSrP7n3X11qBrQqAah Yu68vJwvUFZ0FdKChRCP1xGtCNCukF08IPl69zIGS0eCbbyt5v3psrIGZWrRfRsVVUVk 3OuIJtlmgMaWLbY9I+aeRM6AMGhDdd9G/yzcxiBYqg3IFlPfhWWKOQHvrPjjGl5insOG GrQ30LwjDh5+gYfj0cn40G3qFl6kSAbiobUY0p0ueBVGM6bEMJkPhMIrNulq5r6oVF73 yAoj+zaCHqcW1kI+vQGMlWuogdTNKPwX62McBZ9w90KF4364hS32AXwcrEgQ+DySkdkS 2YuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031736; x=1746636536; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qEe9bxPY78rzldhxeSl0yGcr1LEt/gfI/ABj5JQK6lg=; b=oMz1qyjtkEjAml3U8k56ueXhNoqjsWoUT7RUeQ1RRcLkpw09WiljBmTm8AmMHhBQIi bREtGYY6x0AaTSD+Pb3QkfwakdNhc/g1DnjUjzy9OSFPDE8AGk8Btv3Zz5EC9JAogLyU K7ISCNb+tp7/LYna0hL25EWcMua3Ecam61vogGh+iaj+pQ7zSiCZ6QDMSnIEEeARXGiJ dgFL1s1OhKiSDPfjF/isC79LH2uYfnLlKfat3/GRGslNByQa6ckHV5Nn7Dv4STaY+8cs zLE/kN7uhBN3iN3F6KabitvSa2pvl5nicJUl+qfBUHwMEXpqZb8AAas/9ziuECNl72V1 +u0A== X-Gm-Message-State: AOJu0YwfjPezXgjCH5dKclj+EghnL/tt8Opuug/gE867lYae91fBnQkz JwPCeQ6jVG31Oyx8dnuicT1fjGmFw3bq51ETSLBxhenpMM02X2GKqQvpToi6UWh+k4GhDn0MQyr s X-Gm-Gg: ASbGncuHhRfB4hqF4Xk/Y+9qj4TMH3oD1iKGVIig1yFo8rGH3eFoBH2e9R3FWQlJ1La Qom9vbs4nOMyZ5WBO7bQCnm49ycbl3R55jWDA3cKix+tO6UjnFcqJCKzJLuPEpWD7NIdS9gYq6r 6uLf6fI6YKiLFt5XN1OTBxtLJdtU6R1nGyOSdtaQ6hOZvnVOLXOluYGK/tREB4VvQKqivp2xwFH PiZEjAdi1rLLXC7vCjq766Eot1NVF55pDQ+vyc6vFq2+ibCr1LowFStJwA3AZS195hcxoH/XpHJ AYe1siq4o6JfWSiyEX4BT9gipIffSbM1TLOvTBqgPRwN1rw0dL4d9d5mOBwxcafk4buQyWRlccU = X-Google-Smtp-Source: AGHT+IGI3/QXBrZKOsMmPLeYSI3uNZ6/5PtDuhNqCMRPomMAnvVbazYYqketqmBdKVMjbPgADmgb0A== X-Received: by 2002:a05:6a20:9e06:b0:1ee:d664:17a4 with SMTP id adf61e73a8af0-20b972547damr238217637.10.1746031736316; Wed, 30 Apr 2025 09:48:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 01/16] accel/tcg: Generalize fake_user_interrupt test Date: Wed, 30 Apr 2025 09:48:39 -0700 Message-ID: <20250430164854.2233995-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031776754019100 Test for the hook being present instead of ifdef TARGET_I386. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 279df5fae7..8ff4a34509 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -732,10 +732,10 @@ static inline bool cpu_handle_exception(CPUState *cpu= , int *ret) * If user mode only, we simulate a fake exception which will be * handled outside the cpu execution loop. */ -#if defined(TARGET_I386) const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; - tcg_ops->fake_user_interrupt(cpu); -#endif /* TARGET_I386 */ + if (tcg_ops->fake_user_interrupt) { + tcg_ops->fake_user_interrupt(cpu); + } *ret =3D cpu->exception_index; cpu->exception_index =3D -1; return true; --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031768; cv=none; d=zohomail.com; s=zohoarc; b=Pbcyi18kUddExAGGHTik9BVog8r+1S85D0V1+QGaMXr2ksGdfFefNcS2vMxUuNci1LBBa4nO9a5/oNEFcDF6if4HAMsJTLzndKo6ACx78cOSxwdBlyQJ0KOcUz6G8EqlwRvI7L85iieWdfsyyTc8V3k4b0KqqOPfNXDNfyePsNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031768; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m8QQZQVqZoC308ckvLV+kB4d6m4SiPb0nD+im6xT08U=; b=jMRQI+eXb4nBQ00mW/3hbOWvHZLk+Ghk/ZD4EoZpLk4rM3GPAYjhDvbBLe7h95mOsKae2CI0vZvwEAhpX0FAZXPsgvBXhk3MjfJQ3Cw6BkEkFcsOF2ur+QlOxLrqxHHkfHEtioioyWDy4HM6UW4TF3nzg3PYwGsgxnOXzhZGYJE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031768793772.1855591534204; Wed, 30 Apr 2025 09:49:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcI-0004w7-5k; Wed, 30 Apr 2025 12:49:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcG-0004sk-JM for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:00 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcE-0001tQ-Cy for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:00 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-736dd9c4b40so1239492b3a.0 for ; Wed, 30 Apr 2025 09:48:58 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031737; x=1746636537; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m8QQZQVqZoC308ckvLV+kB4d6m4SiPb0nD+im6xT08U=; b=L5u/+81YhJyXNbFsj+0l/R+iIMl/pQ2cMEcChT3uNym59EIhSQ2x1pKwablYeYJyi/ ZZpOhKpjo5kE/AVwFgznUPOmETkeWKklUMUnwwt7L/sfmNO9YbSHpAXHVc1ZqXnXB3pw 95875TiICjMp0QgXR09r4dpd7yT65PBX3LhtWOIACyEjNHtRhMXYRKYuW8Kmc9BARFgx Wo+4K+wLFgQK+AjFpf1Ig8EPvn70aM46FPH/BT6uiRvGmGhFSf4ftGeCahHY8D/UaH22 Z4KdKQTg9CHMmhmo7CbHFO812MAfYKxsCBvEThCGnZO8aMmi+fOCIpOBBvdLuwLgLDIv vYOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031737; x=1746636537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m8QQZQVqZoC308ckvLV+kB4d6m4SiPb0nD+im6xT08U=; b=nmZWrzUGW5sqJXwIeEYhdRleWu160hd5RTRyLicMwM8z53gghKzSFWKtxv2Ksv+Vqw R0zzS/r6T/XJj4RMQ965Aipvdyi2wrptGWG/QNLRu/xkmpxns4y/XZIW10uSoQDXrUoS yLEUDNRhBHRlS7T8f7P5e3SbZ7wnhNWDQIVHuxEpiGIDE+CETXwOA+3EOKrQNJhG4UAf X+f9ESBZm0ODsZ5VNRiJChwUJPOn9O2H7+bFGid/LuTsw5zQUPbyrF17Rz4Vo8pk1OCY XTmuXLBtQyBEUmADFnVc7LNpYZuJE/46k9xHqyPfHm5K8C6j75zgNXCeHmiPNtp8WrXX KE7A== X-Gm-Message-State: AOJu0Yx1CehaklE8sMnGjUFupXyddM7aZ22CUlZ7927E0B1utGCxNTHr bPHzO10WH0S5p/7n40R4osru5BDxEe7RlyHv3M6EjVKg5zZxOE6Q9IwHVz/whnYJYCdtzjqeOuA h X-Gm-Gg: ASbGncuW6LUTfc0zHCQapGERM2ikUqWr1stkWzA/4atT8XZtK/G3EYEDqH/fUBYoJmI 7OyJHCxa51V76ZKUPQOSWr/xhrxhS04pnYnpGOmwq9Bn5ZLA5THzKZbilfB5cKA4XxFCLQcs4Nf fm1KJDEmb+6P0Gf3YxDV77XJPcYYRyKoUZGykwMQ0R6p4bK7C4jpNw15gKchJnF3P659/wTVyJ4 +NQoxIEqvDfmTtFiSHvuM3PnNwZFsEuAIpZ3AYldhpq/u6ZK2jTQZGw9QP0MBQfQE+MbL9+raPx T/wxw6MdIWdvtFJXHzP++aQ+oZk0tRNCzBjBL8k37nEA8D1YyIjUwgy4eJVIt3aruSwTDDKy0C4 = X-Google-Smtp-Source: AGHT+IEjiXGq65W3AQN3yQZif1AObQuuPkPWlyk066RbUvm4BqWosniNjxe71pT3TZkFsUui7vqjmg== X-Received: by 2002:a05:6a21:1796:b0:1f0:e6db:b382 with SMTP id adf61e73a8af0-20b96d5f470mr247574637.8.1746031737052; Wed, 30 Apr 2025 09:48:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 02/16] accel/tcg: Unconditionally use CPU_DUMP_CCOP in log_cpu_exec Date: Wed, 30 Apr 2025 09:48:40 -0700 Message-ID: <20250430164854.2233995-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031770737019100 Content-Type: text/plain; charset="utf-8" This flag is only tested by target/i386, so including this makes no functional change. This is similar to other places like cpu-target.c which use CPU_DUMP_CCOP unconditionally. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8ff4a34509..ff979a2c57 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -285,14 +285,11 @@ static void log_cpu_exec(vaddr pc, CPUState *cpu, if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { - int flags =3D 0; + int flags =3D CPU_DUMP_CCOP; =20 if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) { flags |=3D CPU_DUMP_FPU; } -#if defined(TARGET_I386) - flags |=3D CPU_DUMP_CCOP; -#endif if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) { flags |=3D CPU_DUMP_VPU; } --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031796; cv=none; d=zohomail.com; s=zohoarc; b=axUahgJ7c8I0fBd1bSxAxDmc1izjexYvuIKYjuQicqiS2prL8JLgkeNP4Iy2YvsbfPUsFk12JWeYxcdgLP3tx1MoZ6MIY30Uo9Zkj/qKwYviiywxSyvbbt57MQb2XRexBjRPnDjmGG+86raH2qjwgbJ+pQsqhT+pqVDJGAoSlcY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031796; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JFC0lIwrLvv96xyWA8HMukwFYVh25GBIzBMcz0FbVPQ=; b=DuiI87hMWPDiMEUV65X36Wj52Jo/YwZmdzi69ZNugoRUOvla2K33UHthIH7sYnBBqYM9UQAEzVIaYwnQJz0sMPDQuV069NW4+1cxJsqBvd9petIPcldjOYWFjBTd5nZdD6rG5KCGc17xG741Y48vznpbrFCNKMm6z5uMsrxVq5w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031796127330.2478580975817; Wed, 30 Apr 2025 09:49:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcc-0005OV-9m; Wed, 30 Apr 2025 12:49:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcH-0004w2-Jx for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:01 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcF-0001tb-At for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:01 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-b074d908e56so35518a12.2 for ; Wed, 30 Apr 2025 09:48:58 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031738; x=1746636538; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JFC0lIwrLvv96xyWA8HMukwFYVh25GBIzBMcz0FbVPQ=; b=qPBg558VM4SJ9LFPs8Z9Kt4Yfi5H9maFDTyuwCnbZZJKAKfUwSPAjdS7ezOjuWq9tP AoxYljYJbTpozNDRuo+4+UOIeesa2Wg5FN7gtMSRcBIpAwdBo/7lXERX35Nw55Ksxal5 AZ6u3HNq4z5z0Xq8XvIgETYll/D+L7L6VI1r3tLqDfrY4D/ewoT0dLdQmbmNTP5KXvdq IXNUkAdy0Cn3SR/38qhh/FAy5naFSmq17goghUhW3Jr8y/9MiLy7ZZWjiV8UI7xiq/f4 zJ8HV8LZR1DiMnk+FylH1JrKEwWoLCvOvy2qlP1U/GUgotkLT+D8KH7NZgp40c5s7TpJ mRSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031738; x=1746636538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JFC0lIwrLvv96xyWA8HMukwFYVh25GBIzBMcz0FbVPQ=; b=CMZOHA1DCKguO9Z48yErQuy0QufP56ixCjY1sjO2u/lGo39AlbzR8k+DizVWIEeuZe jkgpHKmK1CJpGkF7wuvKFZ2O6QJIam7H4kP10j7eiaJrBhCKEsqyXFPqwj492qAuWuir h5yCULR54Zd7LlZ/hgRUYXsLwx0yb2GGEVhewzd/1xgTegw3fUDEGA4wqYIVnJCuI5oF Qyu9EZhcefsePbS/zFimOw0GmJ/4M2jMVwk9wE4cQG5c2e+aKVzlnRS2kx9rz7vMjW9j hi4qVFO1CBju9XZDUJ8i5U/IPB1v05XoXAqkKySJCDFyu+zJBG91423V5TrGzvC+Q7l/ 69qw== X-Gm-Message-State: AOJu0YyJRQytMwtpuLC9v62pFrnNHB4kfbaeOFWuPCYXLNX4uY/0ItiA ASZ0w1SKU1bDe1AGWx48ZNJcjsjH67SAhdX0OzVs9krplrrV2BMzpqLaS0wszBt4vFpLH8rvV6R i X-Gm-Gg: ASbGncuhLmJmkeTuMA39ikQ09Nq4LnvSC7w3s5M35VM9+dj6L4aiCmzHTxiZNvJ+IrT P7FnPPgjHiS2SBMYXzALqzV0or1Ie5JjRYj7V8YnikKQjimGM0r6HlQkhC7OqvSa5JrJw46vD3N WWmO/L8DvIRyN/7Ty37aVrLK8YzngmvdYCEXuW2cf/7/f2JGxjzVjLnpiLGhBEJ8ZlzY8ntgZBo aR66XlFe7iYBNRSCvoxLFFqdQVmWpQJp1UgfAh3VG2Row4as2LUQWMMrMrz1RxF3DXB3EWEM0ys 6tLPWW9lICZbehS+mLygopeIpXhyi24dwsmYulCFqTFhHdk3MPBDnBT8hoKJ/B8nW+APnGTadpk = X-Google-Smtp-Source: AGHT+IFFinpGj1wGxjE8r8RoqfOaW9QluKm1I6UkFA3nCEa0OU5TMuPIzibStmQcPELhl26MrLfFoQ== X-Received: by 2002:a05:6a21:8dcc:b0:1f5:8f65:a6e6 with SMTP id adf61e73a8af0-20aa4182f25mr5356154637.27.1746031737873; Wed, 30 Apr 2025 09:48:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 03/16] accel/tcg: Introduce TCGCPUOps.cpu_exec_reset Date: Wed, 30 Apr 2025 09:48:41 -0700 Message-ID: <20250430164854.2233995-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031796900019100 Initialize all instances with cpu_reset(), so that there is no functional change. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 2 ++ accel/tcg/cpu-exec.c | 3 ++- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 21 files changed, 23 insertions(+), 1 deletion(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 60b5e97205..3ff72b8d9d 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -155,6 +155,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @cpu_exec_reset: Callback for reset in cpu_exec. */ + void (*cpu_exec_reset)(CPUState *cpu); /** * @cpu_exec_halt: Callback for handling halt in cpu_exec. * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ff979a2c57..010f38edaa 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -834,7 +834,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, #else else if (interrupt_request & CPU_INTERRUPT_RESET) { replay_interrupt(); - cpu_reset(cpu); + cpu->cc->tcg_ops->cpu_exec_reset(cpu); bql_unlock(); return true; } @@ -1070,6 +1070,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) #ifndef CONFIG_USER_ONLY assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); + assert(tcg_ops->cpu_exec_reset); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); assert(tcg_ops->mmu_index); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 68414af8d3..d4e66aa432 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -251,6 +251,7 @@ static const TCGCPUOps alpha_tcg_ops =3D { .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .cpu_exec_halt =3D alpha_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D alpha_cpu_do_interrupt, .do_transaction_failed =3D alpha_cpu_do_transaction_failed, .do_unaligned_access =3D alpha_cpu_do_unaligned_access, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7b801eb3aa..3dde70b04a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2705,6 +2705,7 @@ static const TCGCPUOps arm_tcg_ops =3D { .tlb_fill_align =3D arm_cpu_tlb_fill_align, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .cpu_exec_halt =3D arm_cpu_exec_halt, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index b34b657857..5c8c374885 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -250,6 +250,7 @@ static const TCGCPUOps arm_v7m_tcg_ops =3D { .tlb_fill_align =3D arm_cpu_tlb_fill_align, .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .cpu_exec_halt =3D arm_cpu_exec_halt, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 69fface7e9..50b835e1ae 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -232,6 +232,7 @@ static const TCGCPUOps avr_tcg_ops =3D { .mmu_index =3D avr_cpu_mmu_index, .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, .cpu_exec_halt =3D avr_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .tlb_fill =3D avr_cpu_tlb_fill, .do_interrupt =3D avr_cpu_do_interrupt, }; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b083693b57..60b618a22b 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -271,6 +271,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { .tlb_fill_align =3D hppa_cpu_tlb_fill_align, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .cpu_exec_halt =3D hppa_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D hppa_cpu_do_interrupt, .do_unaligned_access =3D hppa_cpu_do_unaligned_access, .do_transaction_failed =3D hppa_cpu_do_transaction_failed, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 192812656c..5d1c758ae3 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -147,6 +147,7 @@ const TCGCPUOps x86_tcg_ops =3D { .do_interrupt =3D x86_cpu_do_interrupt, .cpu_exec_halt =3D x86_cpu_exec_halt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, + .cpu_exec_reset =3D cpu_reset, .do_unaligned_access =3D x86_cpu_do_unaligned_access, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c083ad4fd9..c64cba72dd 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -877,6 +877,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { .tlb_fill =3D loongarch_cpu_tlb_fill, .cpu_exec_interrupt =3D loongarch_cpu_exec_interrupt, .cpu_exec_halt =3D loongarch_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D loongarch_cpu_do_interrupt, .do_transaction_failed =3D loongarch_cpu_do_transaction_failed, #endif diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 6f33b86c7d..f446c6c8f7 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -602,6 +602,7 @@ static const TCGCPUOps m68k_tcg_ops =3D { .tlb_fill =3D m68k_cpu_tlb_fill, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .cpu_exec_halt =3D m68k_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D m68k_cpu_do_interrupt, .do_transaction_failed =3D m68k_cpu_transaction_failed, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 2720e5c1d2..f305ed04f6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -440,6 +440,7 @@ static const TCGCPUOps mb_tcg_ops =3D { .tlb_fill =3D mb_cpu_tlb_fill, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .cpu_exec_halt =3D mb_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D mb_cpu_do_interrupt, .do_transaction_failed =3D mb_cpu_transaction_failed, .do_unaligned_access =3D mb_cpu_do_unaligned_access, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 96fe4da255..09ed330027 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -563,6 +563,7 @@ static const TCGCPUOps mips_tcg_ops =3D { .tlb_fill =3D mips_cpu_tlb_fill, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .cpu_exec_halt =3D mips_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, .do_unaligned_access =3D mips_cpu_do_unaligned_access, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 8c8165d666..94776e0ad8 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -255,6 +255,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { .tlb_fill =3D openrisc_cpu_tlb_fill, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .cpu_exec_halt =3D openrisc_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index b0973b6df9..3a01731402 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7492,6 +7492,7 @@ static const TCGCPUOps ppc_tcg_ops =3D { .tlb_fill =3D ppc_cpu_tlb_fill, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .cpu_exec_halt =3D ppc_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, .cpu_exec_exit =3D ppc_cpu_exec_exit, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2f757c2a5e..50782e0f0e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -153,6 +153,7 @@ const TCGCPUOps riscv_tcg_ops =3D { .tlb_fill =3D riscv_cpu_tlb_fill, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .cpu_exec_halt =3D riscv_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index a51b543028..de2e6a22ff 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -217,6 +217,7 @@ static const TCGCPUOps rx_tcg_ops =3D { =20 .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, .cpu_exec_halt =3D rx_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D rx_cpu_do_interrupt, }; =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 99ff58affc..71338aae77 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -365,6 +365,7 @@ static const TCGCPUOps s390_tcg_ops =3D { .tlb_fill =3D s390_cpu_tlb_fill, .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, .cpu_exec_halt =3D s390_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D s390_cpu_do_interrupt, .debug_excp_handler =3D s390x_cpu_debug_excp_handler, .do_unaligned_access =3D s390x_cpu_do_unaligned_access, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 1885e7d5b2..681237c511 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -275,6 +275,7 @@ static const TCGCPUOps superh_tcg_ops =3D { .tlb_fill =3D superh_cpu_tlb_fill, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .cpu_exec_halt =3D superh_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D superh_cpu_do_interrupt, .do_unaligned_access =3D superh_cpu_do_unaligned_access, .io_recompile_replay_branch =3D superh_io_recompile_replay_branch, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 690e74f109..bbdea8556a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1034,6 +1034,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { .tlb_fill =3D sparc_cpu_tlb_fill, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .cpu_exec_halt =3D sparc_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, .do_unaligned_access =3D sparc_cpu_do_unaligned_access, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 9f19e903bc..0fcac697f6 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -182,6 +182,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .tlb_fill =3D tricore_cpu_tlb_fill, .cpu_exec_interrupt =3D tricore_cpu_exec_interrupt, .cpu_exec_halt =3D tricore_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, }; =20 static void tricore_cpu_class_init(ObjectClass *c, const void *data) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 27d6e40195..9dcb883208 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -246,6 +246,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { .tlb_fill =3D xtensa_cpu_tlb_fill, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .cpu_exec_halt =3D xtensa_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031903; cv=none; d=zohomail.com; s=zohoarc; b=Q7S/VoedfBfO9WwbWZl+FnoAvud8HdiOht5D9UhNatzUs5osAuT98CR0IrQN8ySkhjAriQJIQ4OupVpOwf6CcU9ELkAVnViNMjkKFTqSDP7sw4kJYvrZbtEax6oxJeioE6iWVy+YrJUsrZTBlpuDUmdY1G2w9H+HBf0QuIpXwdY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031903; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bj7bdjIxhUGMCWdPS49pLEhAXBQWGoqis5NhDT45PZA=; b=T5vHddHZjrrdYI1hrLCvrs9LQILhf3AUWGrVqY66NM11eyATLbtK2XO/ZDRnZfREH+74CGJ2AoG5rcw6LdfSLmVt27G9d9qF97dauBUFesKR+K5wdICvvzsvhqNnMBdlYN8xR5wwkK4zKuhQcufwHkMswgCyuERJzKccE21p6Yg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031903116499.5328628314297; Wed, 30 Apr 2025 09:51:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcj-0005uC-6Z; Wed, 30 Apr 2025 12:49:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcI-0004wO-1d for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:02 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcG-0001tn-2e for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:01 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-2255003f4c6so962775ad.0 for ; Wed, 30 Apr 2025 09:48:59 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031739; x=1746636539; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bj7bdjIxhUGMCWdPS49pLEhAXBQWGoqis5NhDT45PZA=; b=AUXdtJSbfPfA4WE7q21CoEHKs13uSbohaEXcNlckZMvVCdQ0F1BqKWQwQqzqGafluR 8pwOmMblaRoYLRMhaD7rKQdMzpFtUj3OA4/SX3oQyULJ/oMH8Q444Lv/k40F4+3Df/YH fRwEDCi86OmsI9uRDlywpTHj0FX0oG4Ymxko01+Rsw/cDWlVpDigCnli3ayL2YWhyNjk U0Q1TGbZRr58w1/Nhe29zsHoSdudMFzbxHcd0z4qcbxmd8/33xVJLponuF1PywLiM9Z0 6Pe8tOkvO1qmobZMl3zjuy9z0lGiu7NEdW2sxLLWw/7ygKdKQDb/llI+0pjrAdeWkGUN l3nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031739; x=1746636539; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bj7bdjIxhUGMCWdPS49pLEhAXBQWGoqis5NhDT45PZA=; b=etOkAk99PTnhJk6QBhwdzZX5GmxH6Z8xa3k3VKBwwjs2Qcj2UyNN54DAL8LpVKKOnT IVCXrpp5B0NBD/NiqAyOiw2v8+FutYQUpM8W7ADezgimOOu6CVXZElMlMDq1SoBM6KlS QfkZtIkd775ywMdK7nudY1USeAyVqytwydUjk7J2VwZNsdAR7jb5k8gvWG0dxxHMKsYS Sl6egt2fzlMh3YeCgoNoBpALEzSyh5Mvf0bKP598+GXGydAjMJ1MRdEx/3arb2WSu3Z9 /cf64Cb1P1KWRGOJS9KfmoktaK2gQTf4Q9N52V+aCZaJaA/k38us7PWBOi+xiwAOJQPz dZYw== X-Gm-Message-State: AOJu0YxiYH2XPgSILF7RltzBJsSOgMhjaG2CwyYIFtYndtytYjPd3h2M HPCsevpUxRwBKB2SqvuLPJVTGmxSOBosim+/iHQcULVCI6uUHOAfa57DUUMZCV3DGJ2gpRXqjXZ R X-Gm-Gg: ASbGncvPIm1q4L3Jnhwo53Z709PbEqBC2ZiSUf4vUOxEB8QivuV/+HlIZyDIqR+CUYH L0WcWWrv4EK6ENiQdpeDWO+C00uEWrENSZ42fB5dWwg2VzGDIlV9fpKh+Q/pbq/b/8fNm5KL4Nv dROaCpCwMzQ6wV9wo7UBapokZxIutIFBH5AABiwsBHgS40lDxzSB2z0PFZM73v2eBN8m8uVXGeX pDhSqA3jUwrCn5y2xE+xWCltII9NdId6mMCPU3+3STCXsPum10vtQcoGU+at7cc8DR+iS5Yj/D8 0dt6vOoGW4V8CE4FsWhNHKtwpHJrWUHJI0zkQ3KbJ3SVN1ho9FhLAmW7CvpCtBWuHpacCX8ZiMA = X-Google-Smtp-Source: AGHT+IH8p9hTIkPhwLtOWTGQqssRSu2Dp/OZtJS2y6rM3de+/Dc8KgMYqK/Z4c5zuO0LBF/We1rDsQ== X-Received: by 2002:a17:903:18b:b0:220:c911:3f60 with SMTP id d9443c01a7336-22df35ca8a0mr55955305ad.47.1746031738702; Wed, 30 Apr 2025 09:48:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 04/16] target/i386: Split out x86_cpu_exec_reset Date: Wed, 30 Apr 2025 09:48:42 -0700 Message-ID: <20250430164854.2233995-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031904651019000 Content-Type: text/plain; charset="utf-8" Note that target/i386/cpu.h defines CPU_INTERRUPT_INIT as CPU_INTERRUPT_RESET. Therefore we can handle the new TCGCPUOps.cpu_exec_reset hook. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 39 ++++++++++++++------------------------- target/i386/tcg/tcg-cpu.c | 11 ++++++++++- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 010f38edaa..c21c5d202d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -819,33 +819,22 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu->exception_index =3D EXCP_HLT; bql_unlock(); return true; - } -#if defined(TARGET_I386) - else if (interrupt_request & CPU_INTERRUPT_INIT) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUArchState *env =3D &x86_cpu->env; - replay_interrupt(); - cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); - do_cpu_init(x86_cpu); - cpu->exception_index =3D EXCP_HALTED; - bql_unlock(); - return true; - } -#else - else if (interrupt_request & CPU_INTERRUPT_RESET) { - replay_interrupt(); - cpu->cc->tcg_ops->cpu_exec_reset(cpu); - bql_unlock(); - return true; - } -#endif /* !TARGET_I386 */ - /* The target hook has 3 exit conditions: - False when the interrupt isn't processed, - True when it is, and we should restart on a new TB, - and via longjmp via cpu_loop_exit. */ - else { + } else { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; =20 + if (interrupt_request & CPU_INTERRUPT_RESET) { + replay_interrupt(); + tcg_ops->cpu_exec_reset(cpu); + bql_unlock(); + return true; + } + + /* + * The target hook has 3 exit conditions: + * False when the interrupt isn't processed, + * True when it is, and we should restart on a new TB, + * and via longjmp via cpu_loop_exit. + */ if (tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (!tcg_ops->need_replay_interrupt || tcg_ops->need_replay_interrupt(interrupt_request)) { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 5d1c758ae3..f3f0380e70 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -120,6 +120,15 @@ static bool x86_debug_check_breakpoint(CPUState *cs) /* RF disables all architectural breakpoints. */ return !(env->eflags & RF_MASK); } + +static void x86_cpu_exec_reset(CPUState *cs) +{ + CPUArchState *env =3D cpu_env(cs); + + cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); + do_cpu_init(env_archcpu(env)); + cs->exception_index =3D EXCP_HALTED; +} #endif =20 #include "accel/tcg/cpu-ops.h" @@ -147,7 +156,7 @@ const TCGCPUOps x86_tcg_ops =3D { .do_interrupt =3D x86_cpu_do_interrupt, .cpu_exec_halt =3D x86_cpu_exec_halt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, - .cpu_exec_reset =3D cpu_reset, + .cpu_exec_reset =3D x86_cpu_exec_reset, .do_unaligned_access =3D x86_cpu_do_unaligned_access, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031903; cv=none; d=zohomail.com; s=zohoarc; b=IBMikTRD1IBcZ4dYkydzopHGLvOdPJWS2QVLqdI0++OxGsG7ryxbfDQozfKkBq8b1dB+q8o5s8jBqHFfhVcX69XNrrK1SlGwLJBUtCP+Ot3rgjp5MDtJG2rBLTZqRYm31zIiD1rRMHpJWWP9wocfRb0wv5K+FXUpm9pf9D0GCYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031903; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Eqgq53P8go7GbjpbQfo5/cBeTkOCPr27bFA5RO1C29o=; b=UdamfHA+YNSCb8nYtRSph9aNmtctMTDNZ9zv8jcHVHTm8VXXAlXa7Ijg0TST8rwX7Frcd0UNULSwYvgo3sQByF01ogu7eqdVmqGPaNdioOCbT4rc05vm0/Si2CxWL+dpd0VrsUL9yQniWnsT6Nf182FSRYZWf1LtFVFMhEajAoU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031903393848.3774478012014; Wed, 30 Apr 2025 09:51:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcg-0005hR-Q8; Wed, 30 Apr 2025 12:49:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcK-0004zE-Uv for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:07 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcG-0001u3-Uw for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:04 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-736c3e7b390so137555b3a.2 for ; Wed, 30 Apr 2025 09:49:00 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031739; x=1746636539; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Eqgq53P8go7GbjpbQfo5/cBeTkOCPr27bFA5RO1C29o=; b=rnU51Zj/1IYd0s12MZSVOcW40BZyZmphSipQGXDfZ5JlNc/gUi44UQLm82e2gd00ai gf+YCmAMPV8w9BcgKACtnnuhTPceXJsmqhwIuaVoxJf+ASQjH6OIlt1/EIkNQU3qq+eL u345cfxJn/KfICYXVPXwPqxyi6Fq9n+VWvCmovCpA0y7CT6WkkEqOdE3hN6hdnB4TBAc 3D/sjvHfZ6QMfkkk9wbFtKt5d69BI9ilH3RMBJbE/ougsmV3A/AhCObORkn3VRTDiiVr +neIYo08jaltHUTyZ0zoAJQO8Je3eJw4KVLU2vPLk2zhbqh/uQ4cisZ5Y/8/1byoln/0 VANQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031739; x=1746636539; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Eqgq53P8go7GbjpbQfo5/cBeTkOCPr27bFA5RO1C29o=; b=dpvfDGEeX2TmpE7R91+MIytCo/FiaOsqQ4wCUE9dzf2nASQYC5hxJfq9KBlBAGYdb6 ETC/i37xTjUrdj8eokg4ZCO0kddz5TfIjlI4ikf52r4cGL0tzGMYgH3y2+pR34zg69E0 8/l3f9qpbFZdPx+FYKs0jd1WW8v4kYAygY5Bnjr1txE662FO2anwrUQzMU75I3+XiYuo +AF01nYsFwutDA+2R72KVA7wXFgFYUTTAJnlbrwVwL3MY+NpQv/nFNkWe8gbqQi04Q3L 8yIzvjV1+CtVTH67eicmXQXNo7UpZJuWjHozssbYOpRpxs3UIj6hn6lQe4nkoMwACbE6 pXWA== X-Gm-Message-State: AOJu0YzQg8YILEe0mrn9kXBA3rC/yuJKK169ZRaxzcM4G2/A3TtuyRw1 7jNr24pvBpD2A3Uyvew8Y/l6fdt7c2xBkfPKT7cGGyjjQ9rDYmFbKypxDX7o82VEnTW2XGbVTel p X-Gm-Gg: ASbGncsonpR+zdDo8m7TK7UulDvqCx9a3tWdO1hwLWiTHaUNnRselc6WkEcV8D8ltqm HlAOqpik8t7J5K9+bNbS70grYfJSLd+/wm4i9IL8NenTitTYXs/YBSViVkYwm7dhd3EK1Oolc2z Exjr5pTgkG1sJqaXL9LXmk2FFhiRohVX/EwDekt1vpAP4g6s8jLpYxvsBbYADfetWkUfDqQk/YU +jkyIaGZhiBI8CdYFv4ix9NaIUfNkG5QLkK52Cak/Rz5VAc45qqqcPQdMpr1sQoLisZxh9ubtLf Ow/DUpA3QPWnnvj0HdBdeu+/PYc6wCs+NqZ+72MacZkzGNLB0qwNec2zqvo+D3oxTjcG8Xc4PCJ 74EqOhznmEw== X-Google-Smtp-Source: AGHT+IGvpw27urqZCWYCXCsjMFH4B9PG3bRB9DWO0sf35D9B9uN1rFF5C++1k0FHNrZZX3cMoK4N/Q== X-Received: by 2002:a05:6a20:c68e:b0:1f5:7007:9eb8 with SMTP id adf61e73a8af0-20a87740ba3mr5316650637.16.1746031739401; Wed, 30 Apr 2025 09:48:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 05/16] accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.h Date: Wed, 30 Apr 2025 09:48:43 -0700 Message-ID: <20250430164854.2233995-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031905019019000 Content-Type: text/plain; charset="utf-8" For some targets, simply remove the local definition. For other targets, move the inline definition out of line. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 3 ++ target/alpha/cpu.h | 11 ------ target/arm/cpu.h | 3 -- target/avr/cpu.h | 18 ---------- target/hexagon/cpu.h | 15 -------- target/hppa/cpu.h | 3 -- target/i386/cpu.h | 14 -------- target/loongarch/cpu.h | 12 ------- target/m68k/cpu.h | 16 --------- target/microblaze/cpu.h | 8 ----- target/mips/cpu.h | 9 ----- target/openrisc/cpu.h | 10 ------ target/ppc/cpu.h | 13 ------- target/riscv/cpu.h | 3 -- target/rx/cpu.h | 9 ----- target/s390x/cpu.h | 9 ----- target/sh4/cpu.h | 15 -------- target/sparc/cpu.h | 3 -- target/tricore/cpu.h | 12 ------- target/xtensa/cpu.h | 68 ----------------------------------- target/alpha/cpu.c | 14 ++++++-- target/arm/helper.c | 1 + target/avr/cpu.c | 21 +++++++++-- target/hexagon/cpu.c | 18 ++++++++-- target/hppa/cpu.c | 3 +- target/i386/tcg/tcg-cpu.c | 17 +++++++-- target/loongarch/cpu.c | 15 ++++++-- target/m68k/cpu.c | 19 ++++++++-- target/microblaze/cpu.c | 11 ++++-- target/mips/cpu.c | 9 +++++ target/openrisc/cpu.c | 13 +++++-- target/ppc/helper_regs.c | 16 ++++----- target/rx/cpu.c | 12 +++++-- target/s390x/cpu.c | 1 + target/sh4/cpu.c | 18 ++++++++-- target/tricore/cpu.c | 15 ++++++-- target/xtensa/cpu.c | 71 +++++++++++++++++++++++++++++++++++-- 37 files changed, 243 insertions(+), 285 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 3ff72b8d9d..f5e5746976 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -18,6 +18,9 @@ #include "exec/vaddr.h" #include "tcg/tcg-mo.h" =20 +void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags); + struct TCGCPUOps { /** * mttcg_supported: multi-threaded TCG is supported diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 849f673489..45944e46b5 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -464,17 +464,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retad= dr); #endif =20 -static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; -#ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #ifdef CONFIG_USER_ONLY /* Copied from linux ieee_swcr_to_fpcr. */ static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fdcf8cd1ae..be4449ca06 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3119,9 +3119,6 @@ static inline bool bswap_code(bool sctlr_b) #endif } =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - enum { QEMU_PSCI_CONDUIT_DISABLED =3D 0, QEMU_PSCI_CONDUIT_SMC =3D 1, diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d6666175a9..518e243d81 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -205,24 +205,6 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags =3D 0; - - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - - if (env->fullacc) { - flags |=3D TB_FLAGS_FULL_ACCESS; - } - if (env->skip) { - flags |=3D TB_FLAGS_SKIP; - } - - *pflags =3D flags; -} - static inline int cpu_interrupts_enabled(CPUAVRState *env) { return env->sregI !=3D 0; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c065fa8ddc..43a854f517 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -137,21 +137,6 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagon= State *env, uint32_t exception, uintptr_t pc); =20 -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { - hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); - } - *flags =3D hex_flags; - if (*pc & PCALIGN_MASK) { - hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); - } -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index acc9937240..11d59d11ca 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -351,9 +351,6 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define CS_BASE_DIFFPAGE (1 << 12) #define CS_BASE_DIFFSPACE (1 << 13) =20 -void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); void update_gva_offset_mask(CPUHPPAState *env); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3182ba413b..4f8ed8868e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2599,20 +2599,6 @@ static inline bool is_mmu_index_32(int mmu_index) #include "hw/i386/apic.h" #endif =20 -static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *flags =3D env->hflags | - (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); - if (env->hflags & HF_CS64_MASK) { - *cs_base =3D 0; - *pc =3D env->eip; - } else { - *cs_base =3D env->segs[R_CS].base; - *pc =3D (uint32_t)(*cs_base + env->eip); - } -} - void do_cpu_init(X86CPU *cpu); =20 #define MCE_INJECT_BROADCAST 1 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 70ff56e60c..262bf87f7b 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -492,18 +492,6 @@ static inline void set_pc(CPULoongArchState *env, uint= 64_t value) #define HW_FLAGS_VA32 0x20 #define HW_FLAGS_EUEN_ASXE 0x40 =20 -static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; -} - #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU =20 void loongarch_cpu_post_init(Object *obj); diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 39d0b9d6d7..d9db6a486a 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -605,22 +605,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr = physaddr, vaddr addr, #define TB_FLAGS_TRACE 16 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) =20 -static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; - if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; - } - if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; - } -} - void dump_mmu(CPUM68KState *env); =20 #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d511f22a55..6ad8643f2e 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -419,14 +419,6 @@ static inline bool mb_cpu_is_big_endian(CPUState *cs) return !cpu->cfg.endi; } =20 -static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); -} - #if !defined(CONFIG_USER_ONLY) bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d16f9a7220..5cd4c6c818 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1366,15 +1366,6 @@ void cpu_mips_clock_init(MIPSCPU *cpu); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); =20 -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); -} - /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 569819bfb0..f4bcf00b07 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -349,16 +349,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, = int i, uint32_t val) env->shadow_gpr[0][i] =3D val; } =20 -static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 13115a89ff..6b90543811 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2751,19 +2751,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xe= r); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) =20 -#ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); -#else -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D env->hflags; -} -#endif - G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exceptio= n, uint32_t error_code, uintptr_t radd= r); =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 167909c89b..c66ac3bc27 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -802,9 +802,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, u= int32_t vsew, return vlen >> (vsew + 3 - lmul); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 5c19c83219..ba5761b647 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -153,15 +153,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, = int rte); #define RX_CPU_IRQ 0 #define RX_CPU_FIR 1 =20 -static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 530d97ccf1..aa931cb674 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -411,15 +411,6 @@ static inline int s390x_env_mmu_index(CPUS390XState *e= nv, bool ifetch) #endif } =20 -#ifdef CONFIG_TCG - -#include "tcg/tcg_s390x.h" - -void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - -#endif /* CONFIG_TCG */ - /* PER bits from control register 9 */ #define PER_CR9_EVENT_BRANCH 0x80000000 #define PER_CR9_EVENT_IFETCH 0x40000000 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 906f99ddf0..c41ab70dd7 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -380,19 +380,4 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 -static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags - | (env->fpscr & TB_FLAG_FPSCR_MASK) - | (env->sr & TB_FLAG_SR_MASK) - | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ -#ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #endif /* SH4_CPU_H */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 37fd1e066e..31cb3d97eb 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -741,9 +741,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_FSR_QNE (1 << 8) #define TB_FLAG_ASI_SHIFT 24 =20 -void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - static inline bool tb_fpu_enabled(int tb_flags) { #if defined(CONFIG_USER_ONLY) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c76e65f818..82085fbc32 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -258,18 +258,6 @@ void tricore_tcg_init(void); void tricore_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); =20 -static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; - - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; -} - #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU =20 /* helpers.c */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c03ed71c94..74122ebe15 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -733,74 +733,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 =20 -static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); - if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { - target_ulong lend_dist =3D - env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); - - /* - * 0 in the csbase_lend field means that there may not be a loopba= ck - * for any instruction that starts inside this page. Any other val= ue - * means that an instruction that ends at this offset from the page - * start may loop back and will need loopback code to be generated. - * - * lend_dist is 0 when LEND points to the start of the page, but - * no instruction that starts inside this page may end at offset 0, - * so it's still correct. - * - * When an instruction ends at a page boundary it may only start in - * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE - * for the TB that contains this instruction. - */ - if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { - target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; - - *cs_base =3D lend_dist; - if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; - } - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && - (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; - } - if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && - (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { - uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> - (env->sregs[WINDOW_BASE] + 1); - uint32_t w =3D ctz32(windowstart | 0x8); - - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, - PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; - } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; - } - if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; - } -} - XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index d4e66aa432..134806e755 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "exec/translation-block.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "fpu/softfloat.h" =20 =20 @@ -40,6 +41,17 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 +void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void alpha_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -231,8 +243,6 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps alpha_tcg_ops =3D { /* Alpha processors have a weak memory model */ .guest_default_memory_order =3D 0, diff --git a/target/arm/helper.c b/target/arm/helper.c index 8de4eb2c1f..98adeb7086 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,6 +30,7 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG #include "accel/tcg/probe.h" +#include "accel/tcg/cpu-ops.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 50b835e1ae..d9fecb272e 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -27,6 +27,7 @@ #include "disas/dis-asm.h" #include "tcg/debug-assert.h" #include "hw/qdev-properties.h" +#include "accel/tcg/cpu-ops.h" =20 static void avr_cpu_set_pc(CPUState *cs, vaddr value) { @@ -53,6 +54,24 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 +void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags =3D 0; + + *pc =3D env->pc_w * 2; + *cs_base =3D 0; + + if (env->fullacc) { + flags |=3D TB_FLAGS_FULL_ACCESS; + } + if (env->skip) { + flags |=3D TB_FLAGS_SKIP; + } + + *pflags =3D flags; +} + static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -220,8 +239,6 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, }; =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps avr_tcg_ops =3D { .guest_default_memory_order =3D 0, .mttcg_supported =3D false, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c1bfa80252..2272f1222b 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -25,6 +25,7 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" #include "exec/gdbstub.h" +#include "accel/tcg/cpu-ops.h" =20 static void hexagon_v66_cpu_init(Object *obj) { } static void hexagon_v67_cpu_init(Object *obj) { } @@ -254,6 +255,21 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 +void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t hex_flags =3D 0; + *pc =3D env->gpr[HEX_REG_PC]; + *cs_base =3D 0; + if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); + } + *flags =3D hex_flags; + if (*pc & PCALIGN_MASK) { + hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); + } +} + static void hexagon_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -321,8 +337,6 @@ static void hexagon_cpu_init(Object *obj) { } =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps hexagon_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 60b618a22b..4cdaf98ab1 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -29,6 +29,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg.h" #include "hw/hppa/hppa_hardware.h" +#include "accel/tcg/cpu-ops.h" =20 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { @@ -249,8 +250,6 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps hppa_tcg_ops =3D { /* PA-RISC 1.x processors have a strong memory model. */ /* diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index f3f0380e70..bb6f82befb 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -24,6 +24,7 @@ #include "accel/accel-cpu-target.h" #include "exec/translation-block.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "tcg-cpu.h" =20 /* Frob eflags into and out of the CPU temporary format. */ @@ -47,6 +48,20 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 +void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *flags =3D env->hflags | + (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); + if (env->hflags & HF_CS64_MASK) { + *cs_base =3D 0; + *pc =3D env->eip; + } else { + *cs_base =3D env->segs[R_CS].base; + *pc =3D (uint32_t)(*cs_base + env->eip); + } +} + static void x86_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -131,8 +146,6 @@ static void x86_cpu_exec_reset(CPUState *cs) } #endif =20 -#include "accel/tcg/cpu-ops.h" - const TCGCPUOps x86_tcg_ops =3D { .mttcg_supported =3D true, .precise_smc =3D true, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c64cba72dd..be770b7e19 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -29,6 +29,7 @@ #endif #ifdef CONFIG_TCG #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" #endif #include "tcg/tcg_loongarch.h" @@ -335,6 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs,= int interrupt_request) } #endif =20 +void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; + *flags |=3D is_va32(env) * HW_FLAGS_VA32; +} + static void loongarch_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -861,8 +874,6 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) } =20 #ifdef CONFIG_TCG -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps loongarch_tcg_ops =3D { .guest_default_memory_order =3D 0, .mttcg_supported =3D true, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f446c6c8f7..2b4ec40509 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "fpu/softfloat.h" +#include "accel/tcg/cpu-ops.h" =20 static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { @@ -38,6 +39,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |=3D TB_FLAGS_MSR_S; + *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; + *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + } + if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { + *flags |=3D TB_FLAGS_TRACE; + } +} + static void m68k_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -586,8 +603,6 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { }; #endif /* !CONFIG_USER_ONLY */ =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps m68k_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f305ed04f6..105ede0b1e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -31,6 +31,7 @@ #include "exec/gdbstub.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" =20 static const struct { @@ -94,6 +95,14 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); + *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); +} + static void mb_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -423,8 +432,6 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps mb_tcg_ops =3D { /* MicroBlaze is always in-order. */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 09ed330027..ab00adf86b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,6 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) return mips_env_mmu_index(cpu_env(cs)); } =20 +void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->active_tc.PC; + *cs_base =3D 0; + *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR); +} + static const TCGCPUOps mips_tcg_ops =3D { .mttcg_supported =3D TARGET_LONG_BITS =3D=3D 32, .guest_default_memory_order =3D 0, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 94776e0ad8..d798127d67 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" =20 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -40,6 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); +} + static void openrisc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -239,8 +250,6 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps openrisc_tcg_ops =3D { .guest_default_memory_order =3D 0, .mttcg_supported =3D true, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index f211bc9830..8d248bcbb9 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -27,6 +27,7 @@ #include "power8-pmu.h" #include "cpu-models.h" #include "spr_common.h" +#include "accel/tcg/cpu-ops.h" =20 /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -255,26 +256,25 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -#ifdef CONFIG_DEBUG_TCG void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { uint32_t hflags_current =3D env->hflags; - uint32_t hflags_rebuilt; =20 - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D hflags_current; - - hflags_rebuilt =3D hreg_compute_hflags_value(env); +#ifdef CONFIG_DEBUG_TCG + uint32_t hflags_rebuilt =3D hreg_compute_hflags_value(env); if (unlikely(hflags_current !=3D hflags_rebuilt)) { cpu_abort(env_cpu(env), "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", hflags_current, hflags_rebuilt); } -} #endif =20 + *pc =3D env->nip; + *cs_base =3D 0; + *flags =3D hflags_current; +} + void cpu_interrupt_exittb(CPUState *cs) { /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index de2e6a22ff..e8b47be675 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -28,6 +28,7 @@ #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" +#include "accel/tcg/cpu-ops.h" =20 static void rx_cpu_set_pc(CPUState *cs, vaddr value) { @@ -43,6 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); + *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); +} + static void rx_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -201,8 +211,6 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, }; =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps rx_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 71338aae77..435b2034ff 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -302,6 +302,7 @@ static const Property s390x_cpu_properties[] =3D { =20 #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" +#include "tcg/tcg_s390x.h" =20 static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 681237c511..5fb18bf55e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -26,6 +26,7 @@ #include "migration/vmstate.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" =20 static void superh_cpu_set_pc(CPUState *cs, vaddr value) @@ -42,6 +43,21 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + /* For a gUSA region, notice the end of the region. */ + *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; + *flags =3D env->flags + | (env->fpscr & TB_FLAG_FPSCR_MASK) + | (env->sr & TB_FLAG_SR_MASK) + | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void superh_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -258,8 +274,6 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps superh_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0fcac697f6..81b3bb6362 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -23,6 +23,7 @@ #include "exec/translation-block.h" #include "qemu/error-report.h" #include "tcg/debug-assert.h" +#include "accel/tcg/cpu-ops.h" =20 static inline void set_feature(CPUTriCoreState *env, int feature) { @@ -44,6 +45,18 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 +void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t new_flags =3D 0; + *pc =3D env->PC; + *cs_base =3D 0; + + new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, + extract32(env->PSW, 10, 2)); + *flags =3D new_flags; +} + static void tricore_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -168,8 +181,6 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, }; =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps tricore_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 9dcb883208..c78ef9421c 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -35,6 +35,7 @@ #include "qemu/module.h" #include "migration/vmstate.h" #include "hw/qdev-clock.h" +#include "accel/tcg/cpu-ops.h" #ifndef CONFIG_USER_ONLY #include "system/memory.h" #endif @@ -54,6 +55,74 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D 0; + *flags |=3D xtensa_get_ring(env); + if (env->sregs[PS] & PS_EXCM) { + *flags |=3D XTENSA_TBFLAG_EXCM; + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { + target_ulong lend_dist =3D + env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); + + /* + * 0 in the csbase_lend field means that there may not be a loopba= ck + * for any instruction that starts inside this page. Any other val= ue + * means that an instruction that ends at this offset from the page + * start may loop back and will need loopback code to be generated. + * + * lend_dist is 0 when LEND points to the start of the page, but + * no instruction that starts inside this page may end at offset 0, + * so it's still correct. + * + * When an instruction ends at a page boundary it may only start in + * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE + * for the TB that contains this instruction. + */ + if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { + target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; + + *cs_base =3D lend_dist; + if (lbeg_off < 256) { + *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + } + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |=3D XTENSA_TBFLAG_LITBASE; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + *flags |=3D XTENSA_TBFLAG_DEBUG; + } + if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + *flags |=3D XTENSA_TBFLAG_ICOUNT; + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { + *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && + (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { + uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> + (env->sregs[WINDOW_BASE] + 1); + uint32_t w =3D ctz32(windowstart | 0x8); + + *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; + } else { + *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + } + if (env->yield_needed) { + *flags |=3D XTENSA_TBFLAG_YIELD; + } +} + static void xtensa_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -229,8 +298,6 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps xtensa_tcg_ops =3D { /* Xtensa processors have a weak memory model */ .guest_default_memory_order =3D 0, --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031812; cv=none; d=zohomail.com; s=zohoarc; b=jXPsm7/GFf3ItnR4ef9ywThgnAlH+/8QyT9ouYDIwGsysnUW4JKFi3wgTjj6OsLEyFvp2Li7GtEL6DqOBfkOzQFXj2dJCKLg6xQOhdA/L6/Xa/S4QINKnZgQHo87Vj5gXyOIaq/+M+GzxRmlZTxyP5VXyF6A8yJe1fyd7j+N4J4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031812; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JSX6D5vgzNk6RAgZyLyRqAirOJHp5W5gvXuRkK9XdPE=; b=k89vJV2y1MQGHN96eb8xK0bCGJO8EyI9yE5aFoiQRHg/J45704Gyx1yDN94MN/zqvE+4hjhz1MePfQ8AWxWcW1925ik0/BX4YIwsF9uGNu/QXeSfvhQlnhKbrQQmxmdPHEzrZJ5Y+FbyoEbydYANJk2RNFY2Gz4NZDUKOei/QUM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174603181254611.762845346269955; Wed, 30 Apr 2025 09:50:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcq-0006SN-41; Wed, 30 Apr 2025 12:49:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcJ-0004z2-NR for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:07 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcH-0001uC-OL for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:03 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-af91fc1fa90so51661a12.0 for ; Wed, 30 Apr 2025 09:49:01 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.48.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:48:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031740; x=1746636540; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JSX6D5vgzNk6RAgZyLyRqAirOJHp5W5gvXuRkK9XdPE=; b=EHPl3b09oMcEOcNw+JBFGkVAdb1cxBN71ZrJdqd3lgzASWumuBjx3XXABL1af1Bmlg gaLSJfgtbzjNJ4TRe6CEg0zR9xVNLBjKaL4OOYnJNz/sWbLK0ceqmlxsSmeV2yoT1G7V leKiigsPbmX02CGghHlnClWT5ogAmZI5Qo/6J4O3xBfB0TUp4Xri/xOK0ZlJS9UMeUSM oFIpqMLlrpUvoEm5mcaCdSR01aQ2eqnCJQrsOSgXMowYNeSkHUiGbD7SV1IbCMqgx6tU STS2qi39Eye/CV/N+PPvfbOpUGlM+zn5IxgtdvsqMenhr6tnn/lhZ/K23d+lnFi/d/GP 0XdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031740; x=1746636540; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JSX6D5vgzNk6RAgZyLyRqAirOJHp5W5gvXuRkK9XdPE=; b=llhATPR18TbxatbnDRejRxD6KsZSwJmeSHG2MLKXHD4iWM89zQufa+Rpl7Ql3zq5RK 3QMkZWa4FkT3Wnx7mLnatjYDCOlD75lgaw7mB5UYiGXO1gc/eFnYiipEZFySLaqnmvaX dijzn7/49CjB8hnTe8i5/e1QGTaslAMWoYpuiJZ2tHuE/xkB3GKQEXJriZCG8KD3AM0L yk6EBivUqh5dsj4xep+z+7zebaiRHPVJqjMvt7nyRp8+naZtDCnw+C9pyJtmERV1ZSN5 pb74u22xstrJmSXxr08DscBb2AOxBtka6VttDr6IxMp9g1X2CAVRIsgi7rBCYGC04I+p bUoA== X-Gm-Message-State: AOJu0YyUS5cmAUMBhxPvRWCRfz8OL0NixOSvE/dUvKTu9G4693NoncHw FtGuMzjx8h5xcZL4GlJrZVW5lZWpq7E2FCOEZLnBY+4P7sfYfU8t3Elcp1ctuOXu+o4xdINoRX/ j X-Gm-Gg: ASbGncvHocD8wOmv2VXf/3qV9sxIpEl2DE2WlZ0hHezcGakJYUYc+ZBq3zXKF/n+OLU aQnHnbq0rYwfww3wVUvlADdXFAmQ1gVx0XGLcsBtHbB5PuONIwsbAh1oZfWG6KRGA+u4QWbCm4p aiEmNaqjqwQakw/bGPiRs+ulPp4ubVKr0UHUfoWzoUUjJ5/MdQx9EmQ+KLxY8puUoJVEQYIxtTp lTEfloWWKBO+Wq3UN1kCOKaj7h7AnyM/DIeJG8/ea+s+1SkKF+5YLDgL4JsVehFwSgFPXz8PH1Y jAheSwcEZqtt/j7O7v34KLdDXKzdZ6KWWjv94TkFvndvrN48Sea7fJI/X7h6tjQ6fL2QcK4vaTg = X-Google-Smtp-Source: AGHT+IHwX52ET+cXJlMDflVEIME0PIbODaerdMhirkf2IpEJaiBRKupSSQboRJkfO7ovn20NihJnhA== X-Received: by 2002:a05:6a20:7f87:b0:1f5:6680:82b6 with SMTP id adf61e73a8af0-20a8980df0bmr4897921637.38.1746031740371; Wed, 30 Apr 2025 09:49:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 06/16] target/arm: Move cpu_get_tb_cpu_state to hflags.c Date: Wed, 30 Apr 2025 09:48:44 -0700 Message-ID: <20250430164854.2233995-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031814494019000 Content-Type: text/plain; charset="utf-8" This is a tcg-specific function, so move it to a tcg file. Also move mve_no_pred, a static function only used within cpu_get_tb_cpu_state. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/arm/helper.c | 110 ---------------------------------------- target/arm/tcg/hflags.c | 110 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 110 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 98adeb7086..360e6ac0f5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,7 +30,6 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG #include "accel/tcg/probe.h" -#include "accel/tcg/cpu-ops.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" @@ -11424,115 +11423,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } =20 -static bool mve_no_pred(CPUARMState *env) -{ - /* - * Return true if there is definitely no predication of MVE - * instructions by VPR or LTPSIZE. (Returning false even if there - * isn't any predication is OK; generated code will just be - * a little worse.) - * If the CPU does not implement MVE then this TB flag is always 0. - * - * NOTE: if you change this logic, the "recalculate s->mve_no_pred" - * logic in gen_update_fp_context() needs to be updated to match. - * - * We do not include the effect of the ECI bits here -- they are - * tracked in other TB flags. This simplifies the logic for - * "when did we emit code that changes the MVE_NO_PRED TB flag - * and thus need to end the TB?". - */ - if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { - return false; - } - if (env->v7m.vpr) { - return false; - } - if (env->v7m.ltpsize < 4) { - return false; - } - return true; -} - -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - CPUARMTBFlags flags; - - assert_hflags_rebuild_correctly(env); - flags =3D env->hflags; - - if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { - *pc =3D env->pc; - if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { - DP_TBFLAG_A64(flags, BTYPE, env->btype); - } - } else { - *pc =3D env->regs[15]; - - if (arm_feature(env, ARM_FEATURE_M)) { - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && - FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) - !=3D env->v7m.secure) { - DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); - } - - if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK)= && - (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || - (env->v7m.secure && - !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))= ) { - /* - * ASPEN is set, but FPCA/SFPA indicate that there is no - * active FP context; we must create a new FP context befo= re - * executing any FP insn. - */ - DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); - } - - bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MAS= K; - if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { - DP_TBFLAG_M32(flags, LSPACT, 1); - } - - if (mve_no_pred(env)) { - DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); - } - } else { - /* - * Note that XSCALE_CPAR shares bits with VECSTRIDE. - * Note that VECLEN+VECSTRIDE are RES0 for M-profile. - */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); - } else { - DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); - DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); - } - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { - DP_TBFLAG_A32(flags, VFPEN, 1); - } - } - - DP_TBFLAG_AM32(flags, THUMB, env->thumb); - DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); - } - - /* - * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine - * states defined in the ARM ARM for software singlestep: - * SS_ACTIVE PSTATE.SS State - * 0 x Inactive (the TB flag for SS is always 0) - * 1 0 Active-pending - * 1 1 Active-not-pending - * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. - */ - if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { - DP_TBFLAG_ANY(flags, PSTATE__SS, 1); - } - - *pflags =3D flags.flags; - *cs_base =3D flags.flags2; -} - #ifdef TARGET_AARCH64 /* * The manual says that when SVE is enabled and VQ is widened the diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index e51d9f7b15..e530f65ed7 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -10,6 +10,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/helper-proto.h" +#include "accel/tcg/cpu-ops.h" #include "cpregs.h" =20 static inline bool fgt_svc(CPUARMState *env, int el) @@ -513,3 +514,112 @@ void assert_hflags_rebuild_correctly(CPUARMState *env) } #endif } + +static bool mve_no_pred(CPUARMState *env) +{ + /* + * Return true if there is definitely no predication of MVE + * instructions by VPR or LTPSIZE. (Returning false even if there + * isn't any predication is OK; generated code will just be + * a little worse.) + * If the CPU does not implement MVE then this TB flag is always 0. + * + * NOTE: if you change this logic, the "recalculate s->mve_no_pred" + * logic in gen_update_fp_context() needs to be updated to match. + * + * We do not include the effect of the ECI bits here -- they are + * tracked in other TB flags. This simplifies the logic for + * "when did we emit code that changes the MVE_NO_PRED TB flag + * and thus need to end the TB?". + */ + if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { + return false; + } + if (env->v7m.vpr) { + return false; + } + if (env->v7m.ltpsize < 4) { + return false; + } + return true; +} + +void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + CPUARMTBFlags flags; + + assert_hflags_rebuild_correctly(env); + flags =3D env->hflags; + + if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { + *pc =3D env->pc; + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { + DP_TBFLAG_A64(flags, BTYPE, env->btype); + } + } else { + *pc =3D env->regs[15]; + + if (arm_feature(env, ARM_FEATURE_M)) { + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) + !=3D env->v7m.secure) { + DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); + } + + if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK)= && + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || + (env->v7m.secure && + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))= ) { + /* + * ASPEN is set, but FPCA/SFPA indicate that there is no + * active FP context; we must create a new FP context befo= re + * executing any FP insn. + */ + DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); + } + + bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MAS= K; + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { + DP_TBFLAG_M32(flags, LSPACT, 1); + } + + if (mve_no_pred(env)) { + DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); + } + } else { + /* + * Note that XSCALE_CPAR shares bits with VECSTRIDE. + * Note that VECLEN+VECSTRIDE are RES0 for M-profile. + */ + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); + } else { + DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); + DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); + } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { + DP_TBFLAG_A32(flags, VFPEN, 1); + } + } + + DP_TBFLAG_AM32(flags, THUMB, env->thumb); + DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); + } + + /* + * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + * states defined in the ARM ARM for software singlestep: + * SS_ACTIVE PSTATE.SS State + * 0 x Inactive (the TB flag for SS is always 0) + * 1 0 Active-pending + * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. + */ + if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { + DP_TBFLAG_ANY(flags, PSTATE__SS, 1); + } + + *pflags =3D flags.flags; + *cs_base =3D flags.flags2; +} --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031808; cv=none; d=zohomail.com; s=zohoarc; b=Q78goLQiOWrBPGnxRvxnX7yP3tbZlGGbtNK6Jj1KzATVBMNcsMTPZlYYSBUhWnXubnB1pqyJQV8gjswSlzN5YUCk+B5Z9OLB3gPwMsJo1Sxu+RGFMVZ0D7M+TxLD5/l9e8NhnSFlg+NgFGReULLRu3iaJreEhf8UJBCZA3kqFUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031808; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5f/+riQnhACWMUBAaDr1xpPHpL32m6PvI3+ANicr5Rs=; b=KFP5+dUMo1ZC+ohJ15zq7BfZViNIohgcbkMI6yQQTy85WNaNXIyYp3YGDykXn7KVPYEWWoHpZl9TbJRW+fQcaKLPwJPzKVwD1khD1dhF+RTRqZ3ut84N9kLUegp7MrBZZ0lqI52VS2+Ry7ZSNPtXb2v0XVt1RpT+Jmd+6ygpoRk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031808821378.15714572851857; Wed, 30 Apr 2025 09:50:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcs-0006ZL-LR; Wed, 30 Apr 2025 12:49:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcK-0004zD-L2 for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:07 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcI-0001uP-Pq for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:04 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-7399838db7fso173468b3a.0 for ; Wed, 30 Apr 2025 09:49:02 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031741; x=1746636541; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5f/+riQnhACWMUBAaDr1xpPHpL32m6PvI3+ANicr5Rs=; b=AQv3rNEq9uVWX4N4khWo9+Gjuj6mOvXk4shVdZiYUjV9+q+YGmelQnwBEFtlE/elnG 25ePBdinMIUJWU1+JO2znumyFi6bfmXnUYuiRlLmwwZonTJSm45gx7b3j2SPurm0bvz4 KoZ2YgfvP5f7YMJfnZDcv/gRve0bFWortSVxJcAZNe+7XvBfYrSR5IBcJX8wh31rMgO8 iQIHJXWOCMxXeL3KLyLv1uC5DF9OxzOdWYZOQ41DBkq2O+K7wwQiDRAeRMXdiC3BLW8A sGtNbl+tokGFg62KeDbJNQiDjauDJL6Js4Ua1e4XkWShavwbuEdgT17pkonefx69mhdd JCmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031741; x=1746636541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5f/+riQnhACWMUBAaDr1xpPHpL32m6PvI3+ANicr5Rs=; b=WGmmpDTJJnGdce0qw3BtVWfVidaIZDEp9Dyf/LHdqrq8tj25UiChjAO4AipDzdW3oC JkSfKE2H6zVpYnqMQot3qu3IIvFeQo//X+U0IyBoRcIV0EE1uL1WHdpcRgeQulE072pI kS2M7Wg6Dd9/Z89S69a2kOjnwyIc4yku96rVfuPpHXwYRVm7EAsBVmCTy5OPIypJXDa/ 5FKpaGZW2QYQjkkBfEFnEi+5jKrtzCpw7wbVLkUAC1hXs1FknSHbugBFbEnBJkqDfuQU WF/ESCdE1D8dwdC1ujb0562KxURafEC+o+WqlBBN0m0MLVMa43oEVzWoWC6RkJoKUwZA eyBA== X-Gm-Message-State: AOJu0YxvZ95ObrQWZsk9Hqq/zYExPppyKHrOFMtTM8WDz+yPk5zx6h0i hYoRvIlJBuJM1XfY1VO6BLvC1iCxPXmSk2MR16cqRNQoGNuuOycmwvEzou3xMU7phw/CKLbliCi z X-Gm-Gg: ASbGncs7SwgSy9j2vzwZSyri8W0O7wqhic16hwsy0DHWe9Hh066MrTxIH5KyRuPoEX/ HllFwXkT9u8tWVYy0qEU2oJG7ttvX58D0eynmUE9x13qpZobl1fRpSm0/V8Ps1+4ha3EV+Op+Fr GmQQ2IfUAy2X5/gXTFrG3ABki/0Ierh9r4V9LMjMARBn7XsRD54HMCctLCI1UQs/wpV29nvEKJ8 TS7R8aDP7ydDkkujRSaaifiwW5d5resJIAyujVFB7EWs36SrbfH+E0dg+nSPOGrEtuufXFy8UC4 jLyCvf4rfiykL+2+r1N9EoFJmmCbiVmP9JOgXKbWGB0+yBLZVJjDiWNKAKBuH9PAW10GoFwjHcs = X-Google-Smtp-Source: AGHT+IHAUFLOalQwmsptYaqhImyWpM3L2Juli4ZF+qGkGy92TbQMptBm7ngzny10ECh7zQebBR5i7g== X-Received: by 2002:aa7:8c05:0:b0:73b:ac3d:9d6b with SMTP id d2e1a72fcca58-7404616d99amr209914b3a.4.1746031741268; Wed, 30 Apr 2025 09:49:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 07/16] target/arm: Unexport assert_hflags_rebuild_correctly Date: Wed, 30 Apr 2025 09:48:45 -0700 Message-ID: <20250430164854.2233995-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031810836019100 Content-Type: text/plain; charset="utf-8" This function is no longer used outside of hflags.c. We can remove the stub as well. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/arm/internals.h | 2 -- target/arm/tcg-stubs.c | 4 ---- target/arm/tcg/hflags.c | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4d3d84ffeb..382a4d1015 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1906,8 +1906,6 @@ static inline bool arm_fgt_active(CPUARMState *env, i= nt el) (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FG= TEN)); } =20 -void assert_hflags_rebuild_correctly(CPUARMState *env); - /* * Although the ARM implementation of hardware assisted debugging * allows for different breakpoints per-core, the current GDB diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c index 93a15cad61..5e5166c049 100644 --- a/target/arm/tcg-stubs.c +++ b/target/arm/tcg-stubs.c @@ -21,10 +21,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp,= uint32_t syndrome, { g_assert_not_reached(); } -/* Temporarily while cpu_get_tb_cpu_state() is still in common code */ -void assert_hflags_rebuild_correctly(CPUARMState *env) -{ -} =20 /* TLBI insns are only used by TCG, so we don't need to do anything for KV= M */ void define_tlb_insn_regs(ARMCPU *cpu) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index e530f65ed7..5315264c28 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -499,7 +499,7 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int e= l) env->hflags =3D rebuild_hflags_a64(env, el, fp_el, mmu_idx); } =20 -void assert_hflags_rebuild_correctly(CPUARMState *env) +static void assert_hflags_rebuild_correctly(CPUARMState *env) { #ifdef CONFIG_DEBUG_TCG CPUARMTBFlags c =3D env->hflags; --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031905; cv=none; d=zohomail.com; s=zohoarc; b=Ms8ttPCWhUQryn8daCC4nJaolIGYeibHp/qDBcUeNIWJD5sFR9z5P0lssRcTh1ZST1qnvlFa0VuZKayCXryBfGIil38I15z74SkhtXRDeUHp0aW0XGxlwMArv+ugMzlnp7eA6q+spaIZlgZZNG08Fdwh2UMx8NLOYrgjpIlQu7g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031905; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SpjRSP299/Pwnlg0y40yyEXNMYiNnhME3gCevLegoTY=; b=FkynEUQ9Fag9gcdoYYJQeNCxQ+KbH6G6P/lfyAqo3ttk+Pc/ANr1iPlNEA8NnQbDA3kriUiHm3mfImvlOY6I1f7kxkKEQIAvix/pU8SdGWf+V4DRGsWv0iHKxQtvGVpD9XaVoqEuC/J/66Rkk8SuA3wyRrff/p19X+rIWZjQnng= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031904738757.2540452916318; Wed, 30 Apr 2025 09:51:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcn-0006GO-RT; Wed, 30 Apr 2025 12:49:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcL-0004zx-UD for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:07 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcJ-0001ua-Sm for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:05 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-224171d6826so696425ad.3 for ; Wed, 30 Apr 2025 09:49:03 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031742; x=1746636542; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SpjRSP299/Pwnlg0y40yyEXNMYiNnhME3gCevLegoTY=; b=WkdPK8LA6wpGGZPCL2F+cjc4j5w/khr5x8CtUgoP4WqMLT4QaKyAhMLljr90PGeNfj VUpJkqEGi+xN6HjYbL3GYQGGbbpN1wV74pASgzlohcbkihTt+BYhxAqI+HwuUfH5fMFk 18y1rX+saNZ0V1TwYs48IhAkOUlkyTU+a8EYRjjAoZwhP9jdLTYAHvH840kFEP80ERVh fwFRRJwnhvJakq6lD+CJOP/KPtqIu9m8sz4W3xy1X10a1Kwe8WO0ctr3gs4d1NznMOe7 DXkU6Or/a35yZ+AsBxYBDLC9n5K/iOUYeaZK4gxifHohJajaPxE9iV9xqJbxM1qNYewL 4ZnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031742; x=1746636542; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SpjRSP299/Pwnlg0y40yyEXNMYiNnhME3gCevLegoTY=; b=X5i5OesaZ7b3yVUBeluq+/fnHOMooS6wYoNnPqVtxHhN6dLYO4BgFUlFX7TPSoONMw vCG/yurTCBK6b+PkFnsfwJiuMVQIxksTSbjgHj/1QgDy6V5zBzCq0cHfiwSX5FbKPMHj zZ1gU1AKf5rf2iE0HXQ3mZaJ43COPNWXgfqld9jXa8JhFJN8PModsDqRaKXbDnbxZe+D D6c5sG6Zqm28J0ICcjoh0AB2SXk4h4SoEZHfsJlYN6F3/IzyLlu2TXdHdzAY5ehxnYYf tTE6P0fPmVQQAimwdSMcv7hg1p8Y0FESSkGaQYXR26//n+e9bmswJfKTc7ZT4pkPEUUm 1Bzw== X-Gm-Message-State: AOJu0YwIsGYxaB0xGQNs6NCeWRJP+Y6ZZEB1RvbGh3+81wSCv1aBI3++ eWIAjNScc8d4bnvCCZ/a8XqigNBysVcGFNi5nCCdbCfUCp+EJhTHyPgh7wJWv4RJptxyZ0arP6t N X-Gm-Gg: ASbGncsw5UnFsswChUlv+deknmCjhT+wo9f7lUgUNbL937chs2+CqOayMxEKq/W2f2+ Bke/mrX3EFBWWfF1C/J9fLhOIfNvgiCCd5G8MHxq80PJwdWZYhQQ1Zh4rEpG8I24zc12rpXvOdf yfQK+qym4IboE9qICfupqDO4U2YSVGJXGTquE8khd2hRtbBogL973Fm1+pfGFhHvy4ocL0ObrPS VaVdyUp2spJJ5eaAWyWaQ5pdIU3T5ggR2Ffkr3IFU58T57fCXlnUdVbQmtA1s7WAgNWTlLh1I7a y/c3Dqfvzd6v+y1V2srz5yy6yJ7cPHMbMwqpSGHxaAH465f4stD6rlXBkzey2po1Hkar7Ps8yhM = X-Google-Smtp-Source: AGHT+IE0f4StZ3a+Ko0eGg1l8nzoaC4cDEV+tpfeAUb/PoGk2nsWmLZBko/o13ZkiLuNyo/wU6YC7Q== X-Received: by 2002:a17:902:f68d:b0:224:1acc:14db with SMTP id d9443c01a7336-22df57b3b99mr48133755ad.29.1746031742196; Wed, 30 Apr 2025 09:49:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 08/16] target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.c Date: Wed, 30 Apr 2025 09:48:46 -0700 Message-ID: <20250430164854.2233995-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031907105019100 This function is only relevant to tcg. Move it to a tcg-specific file. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 97 ------------------------------------- target/riscv/tcg/tcg-cpu.c | 98 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+), 97 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f2e90a9889..d5039f69a9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -135,103 +135,6 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *en= v, bool virt) #endif } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - RISCVCPU *cpu =3D env_archcpu(env); - RISCVExtStatus fs, vs; - uint32_t flags =3D 0; - bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); - - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - - if (cpu->cfg.ext_zve32x) { - /* - * If env->vl equals to VLMAX, we can use generic vector operation - * expanders (GVEC) to accerlate the vector operations. - * However, as LMUL could be a fractional number. The maximum - * vector size can be operated might be less than 8 bytes, - * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue - * only when maxsz >=3D 8 bytes. - */ - - /* lmul encoded as in DisasContext::lmul */ - int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); - uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); - uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); - uint32_t maxsz =3D vlmax << vsew; - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && - (maxsz >=3D 8); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); - flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, - FIELD_EX64(env->vtype, VTYPE, VTA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, - FIELD_EX64(env->vtype, VTYPE, VMA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); - } else { - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - - if (cpu_get_fcfien(env)) { - /* - * For Forward CFI, only the expectation of a lpad at - * the start of the block is tracked via env->elp. env->elp - * is turned on during jalr translation. - */ - flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); - flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); - } - - if (cpu_get_bcfien(env)) { - flags =3D FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); - } - -#ifdef CONFIG_USER_ONLY - fs =3D EXT_STATUS_DIRTY; - vs =3D EXT_STATUS_DIRTY; -#else - flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); - - flags |=3D riscv_env_mmu_index(env, 0); - fs =3D get_field(env->mstatus, MSTATUS_FS); - vs =3D get_field(env->mstatus, MSTATUS_VS); - - if (env->virt_enabled) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } - - /* With Zfinx, floating point is enabled/disabled by Smstateen. */ - if (!riscv_has_ext(env, RVF)) { - fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) - ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; - } - - if (cpu->cfg.debug && !icount_enabled()) { - flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); - } -#endif - - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); - flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); - - *pflags =3D flags; -} - RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 50782e0f0e..e67de7dfe2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "system/tcg.h" +#include "exec/icount.h" #endif =20 /* Hash that stores user set extensions */ @@ -97,6 +98,103 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetc= h) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 +void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + RISCVCPU *cpu =3D env_archcpu(env); + RISCVExtStatus fs, vs; + uint32_t flags =3D 0; + bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); + + *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; + *cs_base =3D 0; + + if (cpu->cfg.ext_zve32x) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ + + /* lmul encoded as in DisasContext::lmul */ + int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); + uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); + uint32_t maxsz =3D vlmax << vsew; + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && + (maxsz >=3D 8); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); + flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, + FIELD_EX64(env->vtype, VTYPE, VTA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); + } else { + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + + if (cpu_get_fcfien(env)) { + /* + * For Forward CFI, only the expectation of a lpad at + * the start of the block is tracked via env->elp. env->elp + * is turned on during jalr translation. + */ + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); + } + + if (cpu_get_bcfien(env)) { + flags =3D FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); + } + +#ifdef CONFIG_USER_ONLY + fs =3D EXT_STATUS_DIRTY; + vs =3D EXT_STATUS_DIRTY; +#else + flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); + + flags |=3D riscv_env_mmu_index(env, 0); + fs =3D get_field(env->mstatus, MSTATUS_FS); + vs =3D get_field(env->mstatus, MSTATUS_VS); + + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } + + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ + if (!riscv_has_ext(env, RVF)) { + fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; + } + + if (cpu->cfg.debug && !icount_enabled()) { + flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); + } +#endif + + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); + + *pflags =3D flags; +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031807; cv=none; d=zohomail.com; s=zohoarc; b=nq+I9dACCtqHnPcK9Ymb1L8MOUdo9loj92MWmJWBNjT6TxdE1A4L7+nj6AGq7HQJjKwRktnb1elBjDA7Ml3vbsRyWAyUXnv7/+Fw5L9E2OaImOy4rKvtsY3C3StxT3tTsUYTTGAy2mKYezQac96D4y3MAXB+TvxD22mI04611E0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031807; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZrgNHkmVFQwH5odIUzOQLc+ZFJWjL7PB2mBMvbUpVdg=; b=WaQ8+K/RNI5yD/wS7AXZrOBjfizZwokmzaawxksQ0ms2Flldnt8mXLJUH7DRWtbbsKFH5xyITOZHwuYBDse/ztlI1oqFWzNqYD9GQ5oHWGx+0VIC6ue+hc80d0AVr/LUWxrTKrFqbGgPklsGYoaDmH8LYW/tuq9N36GktIqB80Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031807484156.64580216900072; Wed, 30 Apr 2025 09:50:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAci-0005o4-Ip; Wed, 30 Apr 2025 12:49:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcO-00056Q-7X for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:11 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcK-0001ur-Hw for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:07 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-736a72220edso132511b3a.3 for ; Wed, 30 Apr 2025 09:49:04 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031743; x=1746636543; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZrgNHkmVFQwH5odIUzOQLc+ZFJWjL7PB2mBMvbUpVdg=; b=VgJXJLnZz2yZs29l4Gyv45vtOCRCuL+1o3i8q0bwPzTDp1pCqn7QCdc85myOWexWwz OfwON1nzpwAZSODBBkr6a9gtEWsdYe2l7Bo7t9SbQhtl8yHzsQ5ism+VwR2TvZpGvxcy AbOFKkZnK50c31SrJ1AIe1uJEZ4zNiD62F2TRyYSJx/Fqnp9grvEqh8+bNUNi5CAxFOj hwbkK2ii/Fcy5enKE7v2agcyIDcDLMtDR6I1zRW8p8Ko5wodnq8HPCe8DWHrMVvkzsfV WvyYvLsjLuJDfMFDStPpPj465j7tMlV2Z+R1Upa9gDMNXzPoxXIq8SYVMk4v/zM7V+vD R9FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031743; x=1746636543; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZrgNHkmVFQwH5odIUzOQLc+ZFJWjL7PB2mBMvbUpVdg=; b=wGbS4XZOSD1Xe18X9YP+NUNNw1E24aAtWYETclsIs2tMg2cWGISxxBR0LWJyIjCOqX W2jgoKVZnMwHTKVkIB6U0zEHrIPhAVpks/M8JUn4M6U3Bm+Uu9PVe36nQbnRP14AdtvV GyAmfnqk3DlNUp2MhXbWcn/Z8KpFoGQ6c/1xHHOwGgFNeVAHZlQcWGcixYvDc/am5HW/ 9qxh5Snii7rEWB18EkxFPewViWlffJasTIycSMGp+1jsT0rWINbYGELCdOX0fN/g4h8M dVtj0vVblLX9HX+n0oIbbOmzMENwB1/mn1G2nlXy8dKcelUEUFqBPkdKR1zjRBgcW9+A 2E0w== X-Gm-Message-State: AOJu0Yxs4INKfYefsd/LVQKyLWIrO+uKYNFgtdiOskBZ1pP8IDKEVAtz LxDe5WH1gpFDrbIR5gNPwp7CzQWOJQHFqPNwedyIiuOF6N+CqWFaPg9KnttUDzoN2qrjZlMmABE p X-Gm-Gg: ASbGncvUAYXqTBRcG/4wyZAoeDGo23tpmR0wT+Ryzvr5zIU8CSNvXBda/EENE327JyA Zx+d9+EG7XL/MkBLNVBB9mE6l4Pho7PHHuCxu3wGApCfQsOeFLtr0rpUm8Gt3BkRFHvBJzBFAiH 2BvphTyDOxGK392tCJayEVL8MgFGsI6rPyPc5bjEQody5G2/Mt+SD4KNx0Xy11kJqjBgcaaQSgI KtexXgYiN6/dvnUrlYRj/G2zx78qLHjMIzAVxrHzBQ+S9CzbOd2tDuZDpmWlKjWtAhiHMGiarXr 3U4Ew5jTPatGQv/FHCFzu/9ZZ6aXgEFSxpOUME8zhZpyLGhUPmCh21QXp34KDIue1Wcp7pPKx4Y = X-Google-Smtp-Source: AGHT+IH2JtGj8gO/vv6GLZ2ZFNjPX53o9s6y8Y1/sbAVJwRFyB8Ec+56mHFG2aXFhdry78ssQ5XNhA== X-Received: by 2002:a05:6a20:cf83:b0:1f5:7c6f:6c96 with SMTP id adf61e73a8af0-20a88036a7cmr5645915637.22.1746031743023; Wed, 30 Apr 2025 09:49:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 09/16] accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state Date: Wed, 30 Apr 2025 09:48:47 -0700 Message-ID: <20250430164854.2233995-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031808444019000 Content-Type: text/plain; charset="utf-8" Combine 3 different pointer returns into one structure return. Include a cflags field in TCGTBCPUState, not filled in by cpu_get_tb_cpu_state, but used by all callers. This fills a hole in the structure and is useful in some subroutines. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/accel/tcg/cpu-ops.h | 4 +-- include/accel/tcg/tb-cpu-state.h | 18 ++++++++++ accel/tcg/cpu-exec.c | 56 +++++++++++++------------------- accel/tcg/translate-all.c | 8 ++--- target/alpha/cpu.c | 13 ++++---- target/arm/tcg/hflags.c | 17 ++++++---- target/avr/cpu.c | 9 ++--- target/hexagon/cpu.c | 15 +++++---- target/hppa/cpu.c | 10 +++--- target/i386/tcg/tcg-cpu.c | 19 +++++++---- target/loongarch/cpu.c | 20 +++++++----- target/m68k/cpu.c | 21 +++++++----- target/microblaze/cpu.c | 13 +++++--- target/mips/cpu.c | 14 ++++---- target/openrisc/cpu.c | 16 +++++---- target/ppc/helper_regs.c | 8 ++--- target/riscv/tcg/tcg-cpu.c | 12 +++---- target/rx/cpu.c | 14 ++++---- target/s390x/cpu.c | 14 ++++---- target/sh4/cpu.c | 22 +++++++++---- target/sparc/cpu.c | 17 ++++++---- target/tricore/cpu.c | 14 ++++---- target/xtensa/cpu.c | 40 +++++++++++++---------- 23 files changed, 218 insertions(+), 176 deletions(-) create mode 100644 include/accel/tcg/tb-cpu-state.h diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f5e5746976..43a39c2e13 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -16,10 +16,10 @@ #include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" +#include "accel/tcg/tb-cpu-state.h" #include "tcg/tcg-mo.h" =20 -void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); =20 struct TCGCPUOps { /** diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-st= ate.h new file mode 100644 index 0000000000..8f912900ca --- /dev/null +++ b/include/accel/tcg/tb-cpu-state.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ +/* + * Definition of TCGTBCPUState. + */ + +#ifndef EXEC_TB_CPU_STATE_H +#define EXEC_TB_CPU_STATE_H + +#include "exec/vaddr.h" + +typedef struct TCGTBCPUState { + vaddr pc; + uint32_t flags; + uint32_t cflags; + uint64_t cs_base; +} TCGTBCPUState; + +#endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c21c5d202d..f7e7e7949d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -385,9 +385,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; =20 /* * By definition we've just finished a TB, so I/O is OK. @@ -397,20 +394,21 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) * The next TB, if we chain to it, will clear the flag again. */ cpu->neg.can_do_io =3D true; - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 - cflags =3D curr_cflags(cpu); - if (check_for_breakpoints(cpu, pc, &cflags)) { + TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + s.cflags =3D curr_cflags(cpu); + + if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { cpu_loop_exit(cpu); } =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } =20 if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { - log_cpu_exec(pc, cpu, tb); + log_cpu_exec(s.pc, cpu, tb); } =20 return tb->tc.ptr; @@ -560,11 +558,7 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu) =20 void cpu_exec_step_atomic(CPUState *cpu) { - CPUArchState *env =3D cpu_env(cpu); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; int tb_exit; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { @@ -573,13 +567,13 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running =3D true; =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + s.cflags =3D curr_cflags(cpu); =20 - cflags =3D curr_cflags(cpu); /* Execute in a serial context. */ - cflags &=3D ~CF_PARALLEL; + s.cflags &=3D ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ - cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + s.cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; /* * No need to check_for_breakpoints here. * We only arrive in cpu_exec_step_atomic after beginning execution @@ -587,16 +581,16 @@ void cpu_exec_step_atomic(CPUState *cpu) * Any breakpoint for this insn will have been recognized earlier. */ =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb =3D=3D NULL) { mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); mmap_unlock(); } =20 cpu_exec_enter(cpu); /* execute the generated code */ - trace_exec_tb(tb, pc); + trace_exec_tb(tb, s.pc); cpu_tb_exec(cpu, tb, &tb_exit); cpu_exec_exit(cpu); } else { @@ -941,11 +935,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; - - cpu_get_tb_cpu_state(cpu_env(cpu), &pc, &cs_base, &flags); + TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + s.cflags =3D cpu->cflags_next_tb; =20 /* * When requested, use an exact setting for cflags for the next @@ -954,33 +945,32 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) * have CF_INVALID set, -1 is a convenient invalid value that * does not require tcg headers for cpu_common_reset. */ - cflags =3D cpu->cflags_next_tb; - if (cflags =3D=3D -1) { - cflags =3D curr_cflags(cpu); + if (s.cflags =3D=3D -1) { + s.cflags =3D curr_cflags(cpu); } else { cpu->cflags_next_tb =3D -1; } =20 - if (check_for_breakpoints(cpu, pc, &cflags)) { + if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { break; } =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb =3D=3D NULL) { CPUJumpCache *jc; uint32_t h; =20 mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags= ); mmap_unlock(); =20 /* * We add the TB in the virtual pc hash table * for the fast lookup */ - h =3D tb_jmp_cache_hash_func(pc); + h =3D tb_jmp_cache_hash_func(s.pc); jc =3D cpu->tb_jmp_cache; - jc->array[h].pc =3D pc; + jc->array[h].pc =3D s.pc; qatomic_set(&jc->array[h].tb, tb); } =20 @@ -1000,7 +990,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) tb_add_jump(last_tb, tb_exit, tb); } =20 - cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit); + cpu_loop_exec_tb(cpu, tb, s.pc, &last_tb, &tb_exit); =20 /* Try to align the host and virtual clocks if the guest is in advance */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 31c7f9927f..f2766cedfc 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -590,13 +590,9 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t reta= ddr) /* The exception probably happened in a helper. The CPU state sho= uld have been saved before calling it. Fetch the PC from there. */ CPUArchState *env =3D cpu_env(cpu); - vaddr pc; - uint64_t cs_base; - tb_page_addr_t addr; - uint32_t flags; + TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + tb_page_addr_t addr =3D get_page_addr_code(env, s.pc); =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - addr =3D get_page_addr_code(env, pc); if (addr !=3D -1) { tb_invalidate_phys_range(cpu, addr, addr); } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 134806e755..90e3a2e748 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -41,15 +41,16 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 -void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; + CPUAlphaState *env =3D cpu_env(cs); + uint32_t flags =3D env->flags & ENV_FLAG_TB_MASK; + #ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |=3D TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void alpha_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 5315264c28..b49381924b 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -10,6 +10,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/helper-proto.h" +#include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" #include "cpregs.h" =20 @@ -544,21 +545,22 @@ static bool mve_no_pred(CPUARMState *env) return true; } =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUARMState *env =3D cpu_env(cs); CPUARMTBFlags flags; + vaddr pc; =20 assert_hflags_rebuild_correctly(env); flags =3D env->hflags; =20 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { - *pc =3D env->pc; + pc =3D env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { DP_TBFLAG_A64(flags, BTYPE, env->btype); } } else { - *pc =3D env->regs[15]; + pc =3D env->regs[15]; =20 if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY) && @@ -620,6 +622,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } =20 - *pflags =3D flags.flags; - *cs_base =3D flags.flags2; + return (TCGTBCPUState){ + .pc =3D pc, + .flags =3D flags.flags, + .cs_base =3D flags.flags2, + }; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index d9fecb272e..683195b61d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,14 +54,11 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 -void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUAVRState *env =3D cpu_env(cs); uint32_t flags =3D 0; =20 - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - if (env->fullacc) { flags |=3D TB_FLAGS_FULL_ACCESS; } @@ -69,7 +66,7 @@ void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, flags |=3D TB_FLAGS_SKIP; } =20 - *pflags =3D flags; + return (TCGTBCPUState){ .pc =3D env->pc_w * 2, .flags =3D flags }; } =20 static void avr_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 2272f1222b..a7f76dd089 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -255,19 +255,20 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 -void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHexagonState *env =3D cpu_env(cs); + vaddr pc =3D env->gpr[HEX_REG_PC]; uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + + if (pc =3D=3D env->gpr[HEX_REG_SA0]) { hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); } - *flags =3D hex_flags; - if (*pc & PCALIGN_MASK) { + if (pc & PCALIGN_MASK) { hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); } + + return (TCGTBCPUState){ .pc =3D pc, .flags =3D hex_flags }; } =20 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4cdaf98ab1..40cbc191bb 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -51,11 +51,12 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) env->iaoq_f & -4); } =20 -void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *pcsbase, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHPPAState *env =3D cpu_env(cs); uint32_t flags =3D 0; uint64_t cs_base =3D 0; + vaddr pc; =20 /* * TB lookup assumes that PC contains the complete virtual address. @@ -63,7 +64,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, * incomplete virtual address. This also means that we must separate * out current cpu privilege from the low bits of IAOQ_F. */ - *pc =3D hppa_cpu_get_pc(env_cpu(env)); + pc =3D hppa_cpu_get_pc(env_cpu(env)); flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; =20 /* @@ -99,8 +100,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, } #endif =20 - *pcsbase =3D cs_base; - *pflags =3D flags; + return (TCGTBCPUState){ .pc =3D pc, .flags =3D flags, .cs_base =3D cs_= base }; } =20 static void hppa_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index bb6f82befb..3004fb3023 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -48,18 +48,23 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 -void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *flags =3D env->hflags | + CPUX86State *env =3D cpu_env(cs); + uint32_t flags, cs_base; + vaddr pc; + + flags =3D env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); if (env->hflags & HF_CS64_MASK) { - *cs_base =3D 0; - *pc =3D env->eip; + cs_base =3D 0; + pc =3D env->eip; } else { - *cs_base =3D env->segs[R_CS].base; - *pc =3D (uint32_t)(*cs_base + env->eip); + cs_base =3D env->segs[R_CS].base; + pc =3D (uint32_t)(cs_base + env->eip); } + + return (TCGTBCPUState){ .pc =3D pc, .flags =3D flags, .cs_base =3D cs_= base }; } =20 static void x86_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index be770b7e19..446cf43914 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,16 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs= , int interrupt_request) } #endif =20 -void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; + CPULoongArchState *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FP= E; + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SX= E; + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_A= SXE; + flags |=3D is_va32(env) * HW_FLAGS_VA32; + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 2b4ec40509..b75ed6e887 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "fpu/softfloat.h" +#include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" =20 static void m68k_cpu_set_pc(CPUState *cs, vaddr value) @@ -39,20 +40,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + CPUM68KState *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + flags |=3D TB_FLAGS_MSR_S; + flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; + flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; } if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; + flags |=3D TB_FLAGS_TRACE; } + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void m68k_restore_state_to_opc(CPUState *cs, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 105ede0b1e..72a0d0583c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -95,12 +95,15 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); + CPUMBState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MAS= K), + .cs_base =3D (env->iflags & IMM_FLAG ? env->imm : 0), + }; } =20 static void mb_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ab00adf86b..b0f7612a64 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,13 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifun= c) return mips_env_mmu_index(cpu_env(cs)); } =20 -void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); + CPUMIPSState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->active_tc.PC, + .flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR), + }; } =20 static const TCGCPUOps mips_tcg_ops =3D { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index d798127d67..aba4639bbb 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,14 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); + CPUOpenRISCState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D ((env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE))), + }; } =20 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 8d248bcbb9..ccaf2b0343 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -256,9 +256,9 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUPPCState *env =3D cpu_env(cs); uint32_t hflags_current =3D env->hflags; =20 #ifdef CONFIG_DEBUG_TCG @@ -270,9 +270,7 @@ void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, } #endif =20 - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D hflags_current; + return (TCGTBCPUState){ .pc =3D env->nip, .flags =3D hflags_current }; } =20 void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e67de7dfe2..927153377e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -98,17 +98,14 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetc= h) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPURISCVState *env =3D cpu_env(cs); RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); =20 - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - if (cpu->cfg.ext_zve32x) { /* * If env->vl equals to VLMAX, we can use generic vector operation @@ -192,7 +189,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 - *pflags =3D flags; + return (TCGTBCPUState){ + .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, + .flags =3D flags + }; } =20 static void riscv_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index e8b47be675..be778c9f65 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,13 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); + CPURXState *env =3D cpu_env(cs); + uint32_t flags =3D 0; + + flags =3D FIELD_DP32(flags, PSW, PM, env->psw_pm); + flags =3D FIELD_DP32(flags, PSW, U, env->psw_u); + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void rx_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 435b2034ff..279289f265 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,9 +309,9 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetc= h) return s390x_env_mmu_index(cpu_env(cs), ifetch); } =20 -void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUS390XState *env =3D cpu_env(cs); uint32_t flags; =20 if (env->psw.addr & 1) { @@ -323,9 +323,6 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); } =20 - *pc =3D env->psw.addr; - *cs_base =3D env->ex_value; - flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; if (env->psw.mask & PSW_MASK_PER) { flags |=3D env->cregs[9] & (FLAG_MASK_PER_BRANCH | @@ -342,7 +339,12 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *p= c, if (env->cregs[0] & CR0_VECTOR) { flags |=3D FLAG_MASK_VECTOR; } - *pflags =3D flags; + + return (TCGTBCPUState){ + .pc =3D env->psw.addr, + .flags =3D flags, + .cs_base =3D env->ex_value, + }; } =20 static const TCGCPUOps s390_tcg_ops =3D { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 5fb18bf55e..cbd43b55e5 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,19 +43,27 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags + CPUSH4State *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D env->flags | (env->fpscr & TB_FLAG_FPSCR_MASK) | (env->sr & TB_FLAG_SR_MASK) | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ #ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |=3D TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, +#ifdef CONFIG_USER_ONLY + /* For a gUSA region, notice the end of the region. */ + .cs_base =3D flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0, +#endif + }; } =20 static void superh_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bbdea8556a..6166b81f71 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -716,13 +716,11 @@ static void sparc_cpu_synchronize_from_tb(CPUState *c= s, cpu->env.npc =3D tb->cs_base; } =20 -void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t flags; - *pc =3D env->pc; - *cs_base =3D env->npc; - flags =3D cpu_mmu_index(env_cpu(env), false); + CPUSPARCState *env =3D cpu_env(cs); + uint32_t flags =3D cpu_mmu_index(cs, false); + #ifndef CONFIG_USER_ONLY if (cpu_supervisor_mode(env)) { flags |=3D TB_FLAG_SUPER; @@ -751,7 +749,12 @@ void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *p= c, } #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_SPARC64 */ - *pflags =3D flags; + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, + .cs_base =3D env->npc, + }; } =20 static void sparc_restore_state_to_opc(CPUState *cs, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 81b3bb6362..1151a812b6 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -45,16 +45,14 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 -void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; + CPUTriCoreState *env =3D cpu_env(cs); =20 - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; + return (TCGTBCPUState){ + .pc =3D env->PC, + .flags =3D FIELD_DP32(0, TB_FLAGS, PRIV, extract32(env->PSW, 10, 2= )), + }; } =20 static void tricore_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c78ef9421c..431b7ebd7b 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -55,15 +55,15 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); + CPUXtensaState *env =3D cpu_env(cs); + uint32_t flags =3D 0; + target_ulong cs_base =3D 0; + + flags |=3D xtensa_get_ring(env); if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; + flags |=3D XTENSA_TBFLAG_EXCM; } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { target_ulong lend_dist =3D env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); @@ -85,26 +85,26 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *p= c, if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; =20 - *cs_base =3D lend_dist; + cs_base =3D lend_dist; if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; } } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; + flags |=3D XTENSA_TBFLAG_LITBASE; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; + flags |=3D XTENSA_TBFLAG_DEBUG; } if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; + flags |=3D XTENSA_TBFLAG_ICOUNT; } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { @@ -112,15 +112,21 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr = *pc, (env->sregs[WINDOW_BASE] + 1); uint32_t w =3D ctz32(windowstart | 0x8); =20 - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; } if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; + flags |=3D XTENSA_TBFLAG_YIELD; } + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, + .cs_base =3D cs_base, + }; } =20 static void xtensa_restore_state_to_opc(CPUState *cs, --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031931; cv=none; d=zohomail.com; s=zohoarc; b=O/uGHwWBrmyXuqKzc11mA6gWODZn8+gPC4YnPmmtxmq6Mv5ZJFiXOUHPj2mMQ2x0XBwtVK8krVAp8Hy8m9azTYy9/VK3UISEu17OmLe142xO4xvdkGfpIpKoz6cY9D4tscPF1gHvY+JW8HKAEbQupvnzrpuZtIUUIx6J0yFjh6M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031931; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wNT5Z/b9p+1dr/iEIvcApv/bdjCSakHasHj7w3R0SoY=; b=Rosr92K7eccTQpl1Vs0TZZ1lCc5G3/0q6hMN6B3dkZhISUAFnpVgAPODNHKCTu5ODEufSlUrgSdZ0UCIA+JXFwxMq6WJVu21h75aUbJtvjU0Tvox6zVFa42wXM/w9QE4s8lsXOhxUIs8LUIbBS/bXYZKK6sECAWq7c9DkpcsFwA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031931925255.62905777465903; Wed, 30 Apr 2025 09:52:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcl-00063m-Da; Wed, 30 Apr 2025 12:49:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcP-00059v-F5 for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:14 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcL-0001v2-EL for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:08 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-736dd9c4b40so1239579b3a.0 for ; Wed, 30 Apr 2025 09:49:05 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031744; x=1746636544; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wNT5Z/b9p+1dr/iEIvcApv/bdjCSakHasHj7w3R0SoY=; b=wghYmN4MXUvO0Z7hLSGtyw9oDKSAhO/Kr3jPaPKH9SuXoNpNsiLOM46u5LXSgv4Qr6 v8QAvHsYjS2A/rPd5OWOhT2m5vaL8AoWOIyiDQGy9TbTsaY5Y/M/SD7Pt+cK2kOZiTRl xhtjp0CmmVY5GeoP80HUwxpWYulYV4uOMpJ9LQF101lrNydQg4adjQciZmVGC7+d2Cpv ElCO68pMgCDhjo0bDeO7/MPIZ5TFsSjAufHluac7uaRdiyUNctkBGs342WBvKwBG/dd0 2BLLEZgnhp0QxmSX1rypRxWAqKjlH3v4DJsBvT3BkOC+ODEV52uAYd0MVZ4yh4bFbB/6 akpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031744; x=1746636544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wNT5Z/b9p+1dr/iEIvcApv/bdjCSakHasHj7w3R0SoY=; b=oeqnTAOycb5/SPcu0iHGVUnsjajgDNIa8jfD/m/AHFXuQGzCUzCWOctJOzjR9/ceMS wvT3JP8J2sahQnc/AZF9WfS0AZjVs5JMAW0fbUIQNsAkcLdQ8DTjrI6JY4QwvmDl2Nnq 9zby/Fc72iiEwIhr7H3fmusdGJS03e87K4AnmU9wuVwedgjBIWcogt03H8ObWtfmQTMz yzxqGPUWSctNmoM7gpnBX9wUlf1M4jGbBNT95k0meQbhs1UUP1tHea+UeXTJ4z3GZsJm dNhDrEn94bT2pHBud1GyM8hahKHYcUsvS2ZVBwXeibK7s9bk7/W/nfKZA+RAkG7nF20U IW3g== X-Gm-Message-State: AOJu0Yzn6T5YF0HX9n6UrwxGVN6wVCTDN5Wk9TxHm2HoPn38LAyxKaVn 5FxLO9+hiuqa/Iy0J3TIFO9+VSpXX80AXTH8+CgPEHboNXJy9e2ls51EjYne+h4fPKwTuNP9uA4 G X-Gm-Gg: ASbGnct0muAQfnnmVhML6ykkVJ7XkDQWUjAVSpYfx+rsk4OEdp2MRJDrk3qFlLspEnp zQuqicmni0lpoWLfsRIQOyF5wa+sLRLcYOXBpPMLbS+qtdV3XrX0EeEV6E/5IR4U29v9AzzD8We gD7HtTl8Yq8SVHoIbzmO8NES8xRDWWchvyv//3YO3vNO0dYGiFjuy3MquJF/B4mm2Svx/efx3V9 q3Z86mlvbt8EyNazPoCcijSP9u3fxuYe0YYHZQ5V1a4amAgmT2xZExjS7kQ29kQzuZJ13a1J47W wgQ+dNMXFQUpdsvbQU93Ks0GPGf/SFAxGIPy9yw/CXo+sRMAwciV53RifFR8DhE3dy8JoSK0JvU = X-Google-Smtp-Source: AGHT+IE+z6N/lxgoRkH/VUvS6bhOTpXTY7IoKHdcCYUSggxAGdvB5dI7fZg+SgR7WHOKY4WbUn3iKA== X-Received: by 2002:a05:6a00:3a07:b0:736:b400:b58f with SMTP id d2e1a72fcca58-74045fbdb07mr341339b3a.0.1746031744002; Wed, 30 Apr 2025 09:49:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 10/16] accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps Date: Wed, 30 Apr 2025 09:48:48 -0700 Message-ID: <20250430164854.2233995-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031933053019000 Content-Type: text/plain; charset="utf-8" Move the global function name to a hook on TCGCPUOps. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 8 ++++++-- target/arm/internals.h | 2 ++ target/ppc/internal.h | 3 +++ accel/tcg/cpu-exec.c | 7 ++++--- accel/tcg/translate-all.c | 2 +- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/arm/tcg/hflags.c | 2 +- target/avr/cpu.c | 3 ++- target/hexagon/cpu.c | 3 ++- target/hppa/cpu.c | 3 ++- target/i386/tcg/tcg-cpu.c | 3 ++- target/loongarch/cpu.c | 3 ++- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 3 ++- target/openrisc/cpu.c | 3 ++- target/ppc/cpu_init.c | 2 +- target/ppc/helper_regs.c | 3 ++- target/riscv/tcg/tcg-cpu.c | 3 ++- target/rx/cpu.c | 3 ++- target/s390x/cpu.c | 3 ++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 3 ++- target/tricore/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- 27 files changed, 56 insertions(+), 26 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 43a39c2e13..23cd6af0b2 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,8 +19,6 @@ #include "accel/tcg/tb-cpu-state.h" #include "tcg/tcg-mo.h" =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); - struct TCGCPUOps { /** * mttcg_supported: multi-threaded TCG is supported @@ -63,6 +61,12 @@ struct TCGCPUOps { */ void (*translate_code)(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); + /** + * @get_tb_cpu_state: Extract CPU state for a TCG #TranslationBlock + * + * Fill in all data required to select or compile a TranslationBlock. + */ + TCGTBCPUState (*get_tb_cpu_state)(CPUState *cs); /** * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock * diff --git a/target/arm/internals.h b/target/arm/internals.h index 382a4d1015..660d3a88e0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -28,6 +28,7 @@ #include "exec/hwaddr.h" #include "exec/vaddr.h" #include "exec/breakpoint.h" +#include "accel/tcg/tb-cpu-state.h" #include "hw/registerfields.h" #include "tcg/tcg-gvec-desc.h" #include "system/memory.h" @@ -372,6 +373,7 @@ void arm_restore_state_to_opc(CPUState *cs, const uint64_t *data); =20 #ifdef CONFIG_TCG +TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); =20 /* Our implementation of TCGCPUOps::cpu_exec_halt */ diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 9012d3809c..7723350227 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -21,6 +21,7 @@ #include "exec/breakpoint.h" #include "hw/registerfields.h" #include "exec/page-protection.h" +#include "accel/tcg/tb-cpu-state.h" =20 /* PM instructions */ typedef enum { @@ -308,4 +309,6 @@ static inline int ger_pack_masks(int pmsk, int ymsk, in= t xmsk) return msk; } =20 +TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs); + #endif /* PPC_INTERNAL_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f7e7e7949d..4a405d7b56 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -395,7 +395,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) */ cpu->neg.can_do_io =3D true; =20 - TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s =3D cpu->cc->tcg_ops->get_tb_cpu_state(cpu); s.cflags =3D curr_cflags(cpu); =20 if (check_for_breakpoints(cpu, s.pc, &s.cflags)) { @@ -567,7 +567,7 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running =3D true; =20 - TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s =3D cpu->cc->tcg_ops->get_tb_cpu_state(cpu); s.cflags =3D curr_cflags(cpu); =20 /* Execute in a serial context. */ @@ -935,7 +935,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { TranslationBlock *tb; - TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s =3D cpu->cc->tcg_ops->get_tb_cpu_state(cpu); s.cflags =3D cpu->cflags_next_tb; =20 /* @@ -1052,6 +1052,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_reset); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); + assert(tcg_ops->get_tb_cpu_state); assert(tcg_ops->mmu_index); tcg_ops->initialize(); tcg_target_initialized =3D true; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f2766cedfc..97aadee52c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -590,7 +590,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retad= dr) /* The exception probably happened in a helper. The CPU state sho= uld have been saved before calling it. Fetch the PC from there. */ CPUArchState *env =3D cpu_env(cpu); - TCGTBCPUState s =3D cpu_get_tb_cpu_state(cpu); + TCGTBCPUState s =3D cpu->cc->tcg_ops->get_tb_cpu_state(cpu); tb_page_addr_t addr =3D get_page_addr_code(env, s.pc); =20 if (addr !=3D -1) { diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 90e3a2e748..890b84c032 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -41,7 +41,7 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState alpha_get_tb_cpu_state(CPUState *cs) { CPUAlphaState *env =3D cpu_env(cs); uint32_t flags =3D env->flags & ENV_FLAG_TB_MASK; @@ -251,6 +251,7 @@ static const TCGCPUOps alpha_tcg_ops =3D { =20 .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, + .get_tb_cpu_state =3D alpha_get_tb_cpu_state, .synchronize_from_tb =3D alpha_cpu_synchronize_from_tb, .restore_state_to_opc =3D alpha_restore_state_to_opc, .mmu_index =3D alpha_cpu_mmu_index, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3dde70b04a..2020aec54a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2693,6 +2693,7 @@ static const TCGCPUOps arm_tcg_ops =3D { =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, + .get_tb_cpu_state =3D arm_get_tb_cpu_state, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, .restore_state_to_opc =3D arm_restore_state_to_opc, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 5c8c374885..95b23d9b55 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -238,6 +238,7 @@ static const TCGCPUOps arm_v7m_tcg_ops =3D { =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, + .get_tb_cpu_state =3D arm_get_tb_cpu_state, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, .restore_state_to_opc =3D arm_restore_state_to_opc, diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index b49381924b..fd407a7b28 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -545,7 +545,7 @@ static bool mve_no_pred(CPUARMState *env) return true; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs) { CPUARMState *env =3D cpu_env(cs); CPUARMTBFlags flags; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 683195b61d..250241541b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,7 +54,7 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState avr_get_tb_cpu_state(CPUState *cs) { CPUAVRState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -241,6 +241,7 @@ static const TCGCPUOps avr_tcg_ops =3D { .mttcg_supported =3D false, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, + .get_tb_cpu_state =3D avr_get_tb_cpu_state, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .restore_state_to_opc =3D avr_restore_state_to_opc, .mmu_index =3D avr_cpu_mmu_index, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a7f76dd089..a5a04173ab 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -255,7 +255,7 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs) { CPUHexagonState *env =3D cpu_env(cs); vaddr pc =3D env->gpr[HEX_REG_PC]; @@ -344,6 +344,7 @@ static const TCGCPUOps hexagon_tcg_ops =3D { .mttcg_supported =3D false, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, + .get_tb_cpu_state =3D hexagon_get_tb_cpu_state, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, .restore_state_to_opc =3D hexagon_restore_state_to_opc, .mmu_index =3D hexagon_cpu_mmu_index, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 40cbc191bb..6465181543 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -51,7 +51,7 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) env->iaoq_f & -4); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState hppa_get_tb_cpu_state(CPUState *cs) { CPUHPPAState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -262,6 +262,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { =20 .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, + .get_tb_cpu_state =3D hppa_get_tb_cpu_state, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, .restore_state_to_opc =3D hppa_restore_state_to_opc, .mmu_index =3D hppa_cpu_mmu_index, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3004fb3023..179dfdf064 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -48,7 +48,7 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState x86_get_tb_cpu_state(CPUState *cs) { CPUX86State *env =3D cpu_env(cs); uint32_t flags, cs_base; @@ -160,6 +160,7 @@ const TCGCPUOps x86_tcg_ops =3D { .guest_default_memory_order =3D TCG_MO_ALL & ~TCG_MO_ST_LD, .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, + .get_tb_cpu_state =3D x86_get_tb_cpu_state, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .restore_state_to_opc =3D x86_restore_state_to_opc, .mmu_index =3D x86_cpu_mmu_index, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 446cf43914..f7535d1be7 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,7 +336,7 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, = int interrupt_request) } #endif =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState loongarch_get_tb_cpu_state(CPUState *cs) { CPULoongArchState *env =3D cpu_env(cs); uint32_t flags; @@ -882,6 +882,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { =20 .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, + .get_tb_cpu_state =3D loongarch_get_tb_cpu_state, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, .restore_state_to_opc =3D loongarch_restore_state_to_opc, .mmu_index =3D loongarch_cpu_mmu_index, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b75ed6e887..c5196a612e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -40,7 +40,7 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState m68k_get_tb_cpu_state(CPUState *cs) { CPUM68KState *env =3D cpu_env(cs); uint32_t flags; @@ -613,6 +613,7 @@ static const TCGCPUOps m68k_tcg_ops =3D { =20 .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, + .get_tb_cpu_state =3D m68k_get_tb_cpu_state, .restore_state_to_opc =3D m68k_restore_state_to_opc, .mmu_index =3D m68k_cpu_mmu_index, =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 72a0d0583c..d069e40e70 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -95,7 +95,7 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState mb_get_tb_cpu_state(CPUState *cs) { CPUMBState *env =3D cpu_env(cs); =20 @@ -442,6 +442,7 @@ static const TCGCPUOps mb_tcg_ops =3D { =20 .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, + .get_tb_cpu_state =3D mb_get_tb_cpu_state, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, .restore_state_to_opc =3D mb_restore_state_to_opc, .mmu_index =3D mb_cpu_mmu_index, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index b0f7612a64..4cbfb9435a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,7 +549,7 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) return mips_env_mmu_index(cpu_env(cs)); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs) { CPUMIPSState *env =3D cpu_env(cs); =20 @@ -566,6 +566,7 @@ static const TCGCPUOps mips_tcg_ops =3D { =20 .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, + .get_tb_cpu_state =3D mips_get_tb_cpu_state, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, .restore_state_to_opc =3D mips_restore_state_to_opc, .mmu_index =3D mips_cpu_mmu_index, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index aba4639bbb..054ad33360 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,7 +41,7 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState openrisc_get_tb_cpu_state(CPUState *cs) { CPUOpenRISCState *env =3D cpu_env(cs); =20 @@ -258,6 +258,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { =20 .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, + .get_tb_cpu_state =3D openrisc_get_tb_cpu_state, .synchronize_from_tb =3D openrisc_cpu_synchronize_from_tb, .restore_state_to_opc =3D openrisc_restore_state_to_opc, .mmu_index =3D openrisc_cpu_mmu_index, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3a01731402..cf88a18244 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -45,7 +45,6 @@ #include "internal.h" #include "spr_common.h" #include "power8-pmu.h" - #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "hw/intc/intc.h" @@ -7483,6 +7482,7 @@ static const TCGCPUOps ppc_tcg_ops =3D { .guest_default_memory_order =3D 0, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, + .get_tb_cpu_state =3D ppc_get_tb_cpu_state, .restore_state_to_opc =3D ppc_restore_state_to_opc, .mmu_index =3D ppc_cpu_mmu_index, =20 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index ccaf2b0343..7e5726871e 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -28,6 +28,7 @@ #include "cpu-models.h" #include "spr_common.h" #include "accel/tcg/cpu-ops.h" +#include "internal.h" =20 /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -256,7 +257,7 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs) { CPUPPCState *env =3D cpu_env(cs); uint32_t hflags_current =3D env->hflags; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 927153377e..55e00972b7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -98,7 +98,7 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) { CPURISCVState *env =3D cpu_env(cs); RISCVCPU *cpu =3D env_archcpu(env); @@ -243,6 +243,7 @@ const TCGCPUOps riscv_tcg_ops =3D { =20 .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, + .get_tb_cpu_state =3D riscv_get_tb_cpu_state, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .restore_state_to_opc =3D riscv_restore_state_to_opc, .mmu_index =3D riscv_cpu_mmu_index, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index be778c9f65..36eba75545 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,7 +44,7 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState rx_get_tb_cpu_state(CPUState *cs) { CPURXState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -220,6 +220,7 @@ static const TCGCPUOps rx_tcg_ops =3D { =20 .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, + .get_tb_cpu_state =3D rx_get_tb_cpu_state, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, .restore_state_to_opc =3D rx_restore_state_to_opc, .mmu_index =3D rx_cpu_mmu_index, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 279289f265..9c1158ebcc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,7 +309,7 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetc= h) return s390x_env_mmu_index(cpu_env(cs), ifetch); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState s390x_get_tb_cpu_state(CPUState *cs) { CPUS390XState *env =3D cpu_env(cs); uint32_t flags; @@ -358,6 +358,7 @@ static const TCGCPUOps s390_tcg_ops =3D { =20 .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, + .get_tb_cpu_state =3D s390x_get_tb_cpu_state, .restore_state_to_opc =3D s390x_restore_state_to_opc, .mmu_index =3D s390x_cpu_mmu_index, =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index cbd43b55e5..b35f18e250 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,7 +43,7 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState superh_get_tb_cpu_state(CPUState *cs) { CPUSH4State *env =3D cpu_env(cs); uint32_t flags; @@ -289,6 +289,7 @@ static const TCGCPUOps superh_tcg_ops =3D { =20 .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, + .get_tb_cpu_state =3D superh_get_tb_cpu_state, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, .restore_state_to_opc =3D superh_restore_state_to_opc, .mmu_index =3D sh4_cpu_mmu_index, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 6166b81f71..2a3e408923 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -716,7 +716,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.npc =3D tb->cs_base; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState sparc_get_tb_cpu_state(CPUState *cs) { CPUSPARCState *env =3D cpu_env(cs); uint32_t flags =3D cpu_mmu_index(cs, false); @@ -1029,6 +1029,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { =20 .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, + .get_tb_cpu_state =3D sparc_get_tb_cpu_state, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, .restore_state_to_opc =3D sparc_restore_state_to_opc, .mmu_index =3D sparc_cpu_mmu_index, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 1151a812b6..e56f90fde9 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -45,7 +45,7 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState tricore_get_tb_cpu_state(CPUState *cs) { CPUTriCoreState *env =3D cpu_env(cs); =20 @@ -185,6 +185,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .mttcg_supported =3D false, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, + .get_tb_cpu_state =3D tricore_get_tb_cpu_state, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .restore_state_to_opc =3D tricore_restore_state_to_opc, .mmu_index =3D tricore_cpu_mmu_index, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 431b7ebd7b..91b71b6caa 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -55,7 +55,7 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState xtensa_get_tb_cpu_state(CPUState *cs) { CPUXtensaState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -312,6 +312,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, .debug_excp_handler =3D xtensa_breakpoint_handler, + .get_tb_cpu_state =3D xtensa_get_tb_cpu_state, .restore_state_to_opc =3D xtensa_restore_state_to_opc, .mmu_index =3D xtensa_cpu_mmu_index, =20 --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031922; cv=none; d=zohomail.com; s=zohoarc; b=dB9V/zNYUfHo0NST/c1UfLJmkJ2cKHyKYDFE5jL22W53T2ZjXhVW4Rfv1BF6IsVDfL0NdkJbvRq3tBmXQopr7GUziv2pJHjN/gRIYO2yBu19V4YzF7jEXmodAPnCRD4eTbDzW3QQ/DXGrL5J9HZsntl0hjUX6aJcwvHjzts+6CY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031922; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+nN+VhF6i+pyNwMFDScdlcKn4qf+d1VgVsfcYGuBPgk=; b=PDtGSODGhdTWaNBJRgzFLRMnjN5ERupyVuWgvjw+vX1Zy27sWOqua7GS77eALw9p0IvnbqMH9akqGuNhQK2NYkG0uh3HNtofBNHeXZMQhbXjg0m+j/41dlaFluQ6rs6LFFlhPaI+X0CyAsiRbDLdaDHigJ87niGnxIWHa4MkJpU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031922552649.1577248651904; Wed, 30 Apr 2025 09:52:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcj-00060g-Vt; Wed, 30 Apr 2025 12:49:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcP-00059u-FA for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:14 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcM-0001vA-Sd for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:08 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-7394945d37eso123161b3a.3 for ; Wed, 30 Apr 2025 09:49:05 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031745; x=1746636545; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+nN+VhF6i+pyNwMFDScdlcKn4qf+d1VgVsfcYGuBPgk=; b=N0ckhziHavNlFPS6jTpxvsIJZkPpMd5FSwD4CDBrKLf1opDQjLlm0PY+8Yj+pKQnyO a3o4vV93HBFBD0QJRiYSAqFIxc2dzl1FAmBeFv428w1e0fCQE1r6+qknGmi6U5qW/cNf 3ZJQTfXZdRtVu1pdT30WqczF94QKWhPAVXRH2e3WM+Yz+95d4EijC08NiWG1SvXj2gHi DFvD7AHp9SSMyftqF/DdiiVmfQuo/7OlIcx4/qeyyY8WbQwpv54UZAL3uk/Jx/u1bW+W BysTyIdPRcSRRRUotEpp0O2fyTop+Zqs9Z6NUJXDoMSeUbI+WutGn8Jvf1bjcUsqvrv0 FzSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031745; x=1746636545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+nN+VhF6i+pyNwMFDScdlcKn4qf+d1VgVsfcYGuBPgk=; b=gLIozX/oXp69TVEttWj7OFCP5C6P2fJQEmbxUhri7yEMsa7s15TfmUVknfuLt1rTWd 28SRjzugmeZAxPjFDwrCT7Mt5GCisyGlky1BsJt0cnuQyK+/Va2GwPmqbJ1DkoQt2QwN Ix6stuZpdjQRXOH+A71gqqNmEthlJJyzLrlCNPdiVuBRK4wAUGlHClSAuRbw6JA3pmZi 399DeOnqRRHv2OdUTs+3l68YjdoEjn/mnPx7LipSCQIgRvWTrbhSC1PoqlNtYg0hyyb0 t7dVW5N46aFmK4D+qqCGKrsVaZsSxJ1ZRrUQ1defoBmbCzRdYjMcZ9sQI47wGAgiKUgt Au+Q== X-Gm-Message-State: AOJu0Yy0NRPGAZ4eNWibE54KaVCsygKulN5AzVPetm0cA3i5NfD0eAmD 2jO/BB2Y3MNzOp2mE3OtC/q1F5MTvxsrCnS18RqbpjCtZTHsT4yjq8ueN+wldq9wSrl5T0tYDEG n X-Gm-Gg: ASbGncuzExWAol35rG6CTzfEwHbqoej1oY0h3n/rOG7bcAGCY4Zja1ZlHf802DS4hWS y/B6tw85EuYiHRtfwQrGAgB6x7ACQ6ZWpFXtj3Tq9Imfj0T0lkPyvbx+W76P5Q3J0NFr+uMkkMs T609+OIUD9X5QjGX7cdhs4oRY3oUR2XswLpRxg02l3dcJ+qzEokT3g4GMIBUGVvIocsoq9Xu952 WotYMfbEc/x0OmOsyGX2JVuA9G8DSP18Ic/QLL2TJn3MtYL/IWJNJjRx71hTzmEvA5Q/3UpetAa jXRgKNXoY4a8hc4IDuQZCeeV75m2aq9ZeH25iwY5oocjHB/3WzWyUshB/fJTJqpLCgPndG9NJIJ 6xUynetVqeA== X-Google-Smtp-Source: AGHT+IHnOcKwmRXIJF1cFlSqM1U1OBhDPMVLQSl6TTBIThOI/V0/WpobNbEIg39I4G6FsX+aZqTkGQ== X-Received: by 2002:a05:6a20:cfa4:b0:1f5:9208:3ac7 with SMTP id adf61e73a8af0-20aa468607fmr5534473637.41.1746031744677; Wed, 30 Apr 2025 09:49:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 11/16] accel/tcg: Pass TCGTBCPUState to tb_lookup Date: Wed, 30 Apr 2025 09:48:49 -0700 Message-ID: <20250430164854.2233995-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031925157019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cpu-exec.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4a405d7b56..808983e461 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -232,35 +232,33 @@ static TranslationBlock *tb_htable_lookup(CPUState *c= pu, vaddr pc, * * Returns: an existing translation block or NULL. */ -static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - uint32_t cflags) +static inline TranslationBlock *tb_lookup(CPUState *cpu, TCGTBCPUState s) { TranslationBlock *tb; CPUJumpCache *jc; uint32_t hash; =20 /* we should never be trying to look up an INVALID tb */ - tcg_debug_assert(!(cflags & CF_INVALID)); + tcg_debug_assert(!(s.cflags & CF_INVALID)); =20 - hash =3D tb_jmp_cache_hash_func(pc); + hash =3D tb_jmp_cache_hash_func(s.pc); jc =3D cpu->tb_jmp_cache; =20 tb =3D qatomic_read(&jc->array[hash].tb); if (likely(tb && - jc->array[hash].pc =3D=3D pc && - tb->cs_base =3D=3D cs_base && - tb->flags =3D=3D flags && - tb_cflags(tb) =3D=3D cflags)) { + jc->array[hash].pc =3D=3D s.pc && + tb->cs_base =3D=3D s.cs_base && + tb->flags =3D=3D s.flags && + tb_cflags(tb) =3D=3D s.cflags)) { goto hit; } =20 - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_htable_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); if (tb =3D=3D NULL) { return NULL; } =20 - jc->array[hash].pc =3D pc; + jc->array[hash].pc =3D s.pc; qatomic_set(&jc->array[hash].tb, tb); =20 hit: @@ -268,7 +266,7 @@ hit: * As long as tb is not NULL, the contents are consistent. Therefore, * the virtual PC has to match for non-CF_PCREL translations. */ - assert((tb_cflags(tb) & CF_PCREL) || tb->pc =3D=3D pc); + assert((tb_cflags(tb) & CF_PCREL) || tb->pc =3D=3D s.pc); return tb; } =20 @@ -402,7 +400,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) cpu_loop_exit(cpu); } =20 - tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } @@ -581,7 +579,7 @@ void cpu_exec_step_atomic(CPUState *cpu) * Any breakpoint for this insn will have been recognized earlier. */ =20 - tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { mmap_lock(); tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); @@ -955,7 +953,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) break; } =20 - tb =3D tb_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { CPUJumpCache *jc; uint32_t h; --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031939; cv=none; d=zohomail.com; s=zohoarc; b=jtk9u93NkPBGyA+EnLamfkBx3wC7TM+G1UItbhVhS7dKcYL3JNEnmINbnod+GNAgwaiD647setPOyQLu2bjhoVPBLKYs+IMJ+i/Cak8aQ+gQi8083YnZum/mrvpPCqeHvtyWMj3HN7+Yu1ksSp87tQrNi7Ljy/sHLIOG3dZgPAI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031939; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+erat6AyDf4aFwvHPMIYlKBGQpGrVV5ItGv/2Xtf4+w=; b=Oyu6N7IoYrlzs5xa00xNStwXvPCtMm6Zd3EB/tz6qFDafPiUd9d246kBFIxmBdbhyg/0cKkxx+EIBx7TX3NGZzfKgtVkKICXTNcRIw962S/XPgBjefpOEAFGftXhoEaIQ9NVK/n92o/nlUFvnOXjOKSs+6Z/uo+vjGCoNnUbRbM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031939254350.5204522081792; Wed, 30 Apr 2025 09:52:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcl-00065h-Q2; Wed, 30 Apr 2025 12:49:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcR-0005AO-BP for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:18 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcM-0001vM-Vu for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:09 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-227a8cdd241so569905ad.3 for ; Wed, 30 Apr 2025 09:49:06 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031745; x=1746636545; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+erat6AyDf4aFwvHPMIYlKBGQpGrVV5ItGv/2Xtf4+w=; b=ZKpfl0KDntT/DpJwTDb4HC4UX7Bb6qwfmF/pgpyN4NwHlxSyk6rjDsYDGhuMfVOxci a7D2WC20fTtB7TCwIA2iqHSpQwA02Iz74WM8hRIX5JyQ1+mWo6BReINkMQ/DKpj//Mri 1Kbm3dqYqgsKeZxrWORuruhNxR9gc34u+AkoFg9OQUKCWVi/qK5Fs8BH6Ck2XRYDbebx T8Cjb3CCmONkmDER0Jz4F4f5CbbfhIey/ouKPGOyfz/xobrXoBJ/o0LXSg2ceczMHHVk 8tfFAxW3UZZtcd02m9rH/NCD6uqO6Gev7fOSkzoddUCwdI2lna4OOgczZ/SauBI+OaAd oUcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031745; x=1746636545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+erat6AyDf4aFwvHPMIYlKBGQpGrVV5ItGv/2Xtf4+w=; b=MD+PfZifZS3I/NuPKQbKzJLhqXs9WQwVNNrlxGimIOe1XCVPUcMHGkZctTvCzrZePF e95OU7fUti7hJ8MUHWzDFTX821aIPcZM4rVdU88Zd0FD/uwO6mmNZb9qPuBCunz1NqUP jYBCKHd9LyR8+DuYD4YUfCxmTEWpD8T/oFbukdHKbHY6+fwUDDX8lyOQ4nqVEm8C0MTN IofH7lU38HkjD83UJpwl77lPDoZWi38UoUDW3hw9H4TCYIFbe8/+zjcqUshx3t75AxBs w2OC89naIdCtK6ldrWwZca/EIYatZBES71v0G6FfHRWg9N/UiT2iFt+JSIklqrzWFPB2 5evg== X-Gm-Message-State: AOJu0Ywc5iu1vXomjofBS/XF1ykc0Moiqp4w4JYLvgGi1xrFE6m3weaE TL/ecK/eJvqDOK+EitBCUCnrZ24ed+t7HdmXKedb4Wn49/Lrgm0OQT/5ebgApEv3ou8JVlfVpT5 I X-Gm-Gg: ASbGncsMKZ3PpCwmxHyscyDudKekNUwvjktK3h1Oq48u+vDNwpuR7w363V1uMYKbHhk FCG1D3e27zPVV4CI3/8x1LPRGAR8gwXItOFkFc2SC6kfyH85lkZ6/87QgnjU3dw6brlEcVXjsF3 wfK+nmSWxd/d48KFhArJCH8V0Q+/w4Tb8S7zhsuWwW3xzxoi+SE/PxQ3ZiNC/QchzKzGDHJGizE nAgyQQ9jVmfROPwckkVIM2WWv2JWM9CKmMcfAKaZOqHqHvrw2Wh8yFqfHjyvS6lePbowVITjMc0 h8kmQNvQeqUY74c1kLOlGTqp0oR9FrZh0sA5hbRu/ARj5uH/V7+5mtEjUpHfP87S1aaUp+kg9Xs = X-Google-Smtp-Source: AGHT+IGs+lIDMy/b3BaUa7Qa1EEcbxrTuqFAon3iIDzTwDAL7mFRwh/KaHSMQeNo3amMmH5BCIPRDQ== X-Received: by 2002:a17:903:3bce:b0:220:cd9a:a167 with SMTP id d9443c01a7336-22df34b862cmr65616825ad.4.1746031745497; Wed, 30 Apr 2025 09:49:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 12/16] accel/tcg: Pass TCGTBCPUState to tb_htable_lookup Date: Wed, 30 Apr 2025 09:48:50 -0700 Message-ID: <20250430164854.2233995-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031941313019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cpu-exec.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 808983e461..8e6899950e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -195,26 +195,24 @@ static bool tb_lookup_cmp(const void *p, const void *= d) return false; } =20 -static TranslationBlock *tb_htable_lookup(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - uint32_t cflags) +static TranslationBlock *tb_htable_lookup(CPUState *cpu, TCGTBCPUState s) { tb_page_addr_t phys_pc; struct tb_desc desc; uint32_t h; =20 desc.env =3D cpu_env(cpu); - desc.cs_base =3D cs_base; - desc.flags =3D flags; - desc.cflags =3D cflags; - desc.pc =3D pc; - phys_pc =3D get_page_addr_code(desc.env, pc); + desc.cs_base =3D s.cs_base; + desc.flags =3D s.flags; + desc.cflags =3D s.cflags; + desc.pc =3D s.pc; + phys_pc =3D get_page_addr_code(desc.env, s.pc); if (phys_pc =3D=3D -1) { return NULL; } desc.page_addr0 =3D phys_pc; - h =3D tb_hash_func(phys_pc, (cflags & CF_PCREL ? 0 : pc), - flags, cs_base, cflags); + h =3D tb_hash_func(phys_pc, (s.cflags & CF_PCREL ? 0 : s.pc), + s.flags, s.cs_base, s.cflags); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } =20 @@ -253,7 +251,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu= , TCGTBCPUState s) goto hit; } =20 - tb =3D tb_htable_lookup(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_htable_lookup(cpu, s); if (tb =3D=3D NULL) { return NULL; } --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031801; cv=none; d=zohomail.com; s=zohoarc; b=QTeZcTLNdIuSEqO4ZQmyeVtloY4V1zu94nN2KfdTTSVa221LjEx1h5WX9sIb4XmoCcpWmtxY13ounUt0PG/GeD4bDl5g8IVNtKMLb96EH79Vq2YCQNLaaFKPRh+zAc1rKT58RhzNdqPCUcqa4iWF2HNqRwoZTBcNu0qeq9LyTOk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031801; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3OA/Cegqwe9p0yD6ikSN7G53T07JOQms4URcLJNl+RA=; b=Bf4n7HTNCuCk6sqCxF9WJlIna5A88ZefMDCOTaOSKdV72jJbiSiK+P0sDxSLtVh/MCwkQaROd6PNllyUUFeUzU2Pya85txiQf9unJ+0e8rql7Lw3J40RsgpvHoSmM7cGAl0UNxLWU05E7rqFcf7QNAjOhTdnkoOvInS8is09x9Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031801847541.4475302184572; Wed, 30 Apr 2025 09:50:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcf-0005au-Id; Wed, 30 Apr 2025 12:49:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcR-0005AN-Aj for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:14 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcN-0001vO-I1 for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:09 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-2295d78b45cso1186975ad.0 for ; Wed, 30 Apr 2025 09:49:07 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031746; x=1746636546; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3OA/Cegqwe9p0yD6ikSN7G53T07JOQms4URcLJNl+RA=; b=sbq1nLre1TDYiSDkDFl+7gFSk4M0gb+DuZj/mmne5Ah5wzor26ZZFb7dL8fRY0iMb1 19GLjAhX/8ViQPvxF6lklfnx//MNHOUgt2XFxkMXGTodadLn89j1RVPGRvb99BbaHEfE HdScgt+JRZdG5Ybd9Cf5iv/9qEMvzQSxl6OA7/yrNFFLdsnZ5w2ruVQbVkWQIRTvXxn3 OWpYjWM9KyYILfdSeWKrMC+38iH4cRlh7A7+cwaVplptz3NQRTCWZRsZqnOPmuEG9FNf FcfM5sX9dpciS7ITFobrCiSUp5OSGNt2DGo36P7EzN7rd1BjgiXOS/MGuq2rwKWNjQzB mW5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031746; x=1746636546; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3OA/Cegqwe9p0yD6ikSN7G53T07JOQms4URcLJNl+RA=; b=iiaL+BMHWhYKbi5kMaRjhCvwH5q4g07dQAWtrg3tTzKt7+CxgIyPzJbgpPm62mMQTA eDoP2CAj754HVeMa9+3STkLH9yPD6hOz/gvW9FjOhudICLiKah9OCWtQYiJc+qKRFLLP ZTSyQsl+7MUkyvufBURQvSThy+HE+Ad5OBvitaNOBCKnBVLChL4kOZYz50Y/mqgSqIJq Y5x23fmMT6fW8Jf4Wv4fAqNS/j4UHEKqYVthkvmWjqsYYTkNdOgNJB2v5kEngcoCLKrX nPdkvzEI5oBQyYFxUZXg+TT8Pzi9arJXAHXr0BBOPTdgFuhqkX3CbaqQsK3iz6PgrTlT pk1Q== X-Gm-Message-State: AOJu0YxlVQ9Se+dfn6HZ2Mxrandw9RPMCZO/htjS9A6eDlDzNzHJ9Bz3 2VoPFdN8yoqb35GSSJOHoMrguozkSpl1IwG22XcDERL992pPEKYM76XGcegNXzQpPoQAffNmQ3e 0 X-Gm-Gg: ASbGncuC8pazUMFkdRKRFjcF1DcRTwbklSPpI9fPmcvhAFyQwXfwEVfagE+w/8ulaUp 3Dv+nNPXNX7Brolh2SfOkIoCU9bFVoyy/+y7VW8+Bmdkj2VY3ourR4wD400JHgLL2BTDNQgNyBK saYko0KmaXnQY1yV5vZpjps487qFlPUd2ZrXlXZ2kVOL8jSzhDF+KNSxnKoDXZ1G4f8FaF73dP2 VvvdTfrJy+UIu7etJZo5VPoB628VymMEN1DBZ+PAbr1Vuq6HBCsIsKh6WjFJIEISiMXuM5ZX//A WqegrPft2FU+xeas5n6s6vNH3c0OpMTgEzuAQxbeJiTP5rZ7pId1HnPQwOjgukrLFwBPYlCpW/A = X-Google-Smtp-Source: AGHT+IGPbSP6tUPSBCFcNoPnOm4tFFoeFJYYU4pvDCPIXfE+V7WGsEUVydKEPQXMkdywJuDAeuiCmA== X-Received: by 2002:a17:902:e88d:b0:223:f928:4553 with SMTP id d9443c01a7336-22df5836c5emr52767025ad.44.1746031746084; Wed, 30 Apr 2025 09:49:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 13/16] accel/tcg: Use TCGTBCPUState in struct tb_desc Date: Wed, 30 Apr 2025 09:48:51 -0700 Message-ID: <20250430164854.2233995-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031804786019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cpu-exec.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8e6899950e..4ad84c2db8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,12 +150,9 @@ static void init_delay_params(SyncClocks *sc, const CP= UState *cpu) #endif /* CONFIG USER ONLY */ =20 struct tb_desc { - vaddr pc; - uint64_t cs_base; + TCGTBCPUState s; CPUArchState *env; tb_page_addr_t page_addr0; - uint32_t flags; - uint32_t cflags; }; =20 static bool tb_lookup_cmp(const void *p, const void *d) @@ -163,11 +160,11 @@ static bool tb_lookup_cmp(const void *p, const void *= d) const TranslationBlock *tb =3D p; const struct tb_desc *desc =3D d; =20 - if ((tb_cflags(tb) & CF_PCREL || tb->pc =3D=3D desc->pc) && + if ((tb_cflags(tb) & CF_PCREL || tb->pc =3D=3D desc->s.pc) && tb_page_addr0(tb) =3D=3D desc->page_addr0 && - tb->cs_base =3D=3D desc->cs_base && - tb->flags =3D=3D desc->flags && - tb_cflags(tb) =3D=3D desc->cflags) { + tb->cs_base =3D=3D desc->s.cs_base && + tb->flags =3D=3D desc->s.flags && + tb_cflags(tb) =3D=3D desc->s.cflags) { /* check next page if needed */ tb_page_addr_t tb_phys_page1 =3D tb_page_addr1(tb); if (tb_phys_page1 =3D=3D -1) { @@ -185,7 +182,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) * is different for the new TB. Therefore any exception raised * here by the faulting lookup is not premature. */ - virt_page1 =3D TARGET_PAGE_ALIGN(desc->pc); + virt_page1 =3D TARGET_PAGE_ALIGN(desc->s.pc); phys_page1 =3D get_page_addr_code(desc->env, virt_page1); if (tb_phys_page1 =3D=3D phys_page1) { return true; @@ -201,11 +198,8 @@ static TranslationBlock *tb_htable_lookup(CPUState *cp= u, TCGTBCPUState s) struct tb_desc desc; uint32_t h; =20 + desc.s =3D s; desc.env =3D cpu_env(cpu); - desc.cs_base =3D s.cs_base; - desc.flags =3D s.flags; - desc.cflags =3D s.cflags; - desc.pc =3D s.pc; phys_pc =3D get_page_addr_code(desc.env, s.pc); if (phys_pc =3D=3D -1) { return NULL; --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031837; cv=none; d=zohomail.com; s=zohoarc; b=COxdD7F06v/zv+sZhPSUT6JcXnP65TL7dLeKRXDvz4K2AH+HDsrM+f6luRAxusBKIB/mQroY3aC7n1Hdmx1awUaOicoBOu9TtM3pPZUvLd+Dq8pGO+LdoI451dTkn7r+nfl/N2MQGXQB8gaOH9ZCT6P9JfXGMotxZFgyEVQ0Hv0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031837; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TNItTYCqljpWXCYmXErceMTzMhdQ1ZlNvx1ZSBZc8tk=; b=aHuanWGTk5FSH+Gvs6AJ/CddfPxMJQhgejNoLUfJ3o/xORCd3TGm63lZPFECE7nZS+5NFjPRLcswVK+5vsd3WcY7CBERfVWpihsPyUQk4KHdo4/5U2Hf5TpWuzrtDKnVFhFCI4E25tfjvnQyf7frfCvzLVi9C7z8v9PyeyprwPU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031837568186.51646070335846; Wed, 30 Apr 2025 09:50:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcu-0006ky-M9; Wed, 30 Apr 2025 12:49:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcT-0005F2-9B for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:18 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcP-0001vY-5R for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:11 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-73bf1cef6ceso169663b3a.0 for ; Wed, 30 Apr 2025 09:49:07 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031747; x=1746636547; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TNItTYCqljpWXCYmXErceMTzMhdQ1ZlNvx1ZSBZc8tk=; b=g41GqAogsc29mLkM+uU6lZSmCVnPF97u8idsrXxM3aIgjK7l6BY6zgDd+1ClbVZwe6 Mt2mP0WCELRxbcM/BE9N+C+yPm+YxJRiqAfHFUuqMyXVaPxdWwIdtv5Faah10QnGVQ6i hNg1me8VhwGLBNOeDJjACCQy2gfQmPsfmnsU1UKMWh8XiEEFr1UWlgKrFRiROW/x8ND2 Udgk4L4xstK0nZGrFF7M2z9WhDlY3dQy3nmIUGGbNGTg13dL8NSYrbnhe9YUgBhIfNW6 lUZzQNTVcggPAeGzhPmzRy0ex/hP3iBC4Xn6ItCeFwqGgasvb/gC27s/F8GDeX/8yIUA G8Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031747; x=1746636547; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TNItTYCqljpWXCYmXErceMTzMhdQ1ZlNvx1ZSBZc8tk=; b=Sv/tMz6upQ0Rycy/tAkTEq6vSgodlYtrEfuHijnU/G4NNn4fT6NIXVCbwZrvJY9RDh kwP3ylmvsOs7KayzqBmuNzi+WpTFaEAxSQkkppjhmz4W6DO4OEvUEuUaLzrnbQ73xYOQ 7GP0ktofx4wTLuFwLuJj76sMETxecz2WYqOLPf+HfAIm/bgS9SsROeumcKZO8i/HftdE ntyL3jcIsVKwPfkB9I4wLQbJsxYrnh1FpfjpZ9l9D2oz8IMrk1aTebT0soVRjG7ABQeh MbRpyXoQHpiCkV8ITv35RzzBCq6ySzWdf+N7Xf5yibQW0uEE5d2VwtkanWFFeLIfE12s QmdQ== X-Gm-Message-State: AOJu0YwcfxawqCvwm+1ypzHiccurxC3EyAedWuQLZfxL9kiiX216U4V3 djOl5eoSXXnDvuXIxAL0UET7JEnJ/PQl9Dd0x2dinn+FSMYOpLlpfTTDQoveH3h+PnuvX1d8lsS m X-Gm-Gg: ASbGncsngCpOW8IewSNvPlVKfY/FOBolE4jpFz3/WJb8MFpZwxUiHyOJ0umhrNoRrpB FAhRXg5W0Mqr1Q0uqTL+6Spi3PiY1V4ilWEOlazg8s9EmVr5roRqlF4AT9Eiq3D0GlfIiMWXjH1 2O59+emp2rDY4UCrC9lLdQsthx0mj3y78HvDWkm/SGPOI/b1eij7JLgj7SCNf4j+RxbT0z3XEMl Bqzd//DjD/cllN1ajTp0tYOpUUNUtAdSvocH/CbdBwO3JTm1pfwE7SpMSRfEiOewq+7CeIzWgCc SsttimMeAYhmqH+m8cUiz8BCtH6Hkj/XAjNhK/ECeMbKLRkgE37t5hWTELB7YoCnkIxREVEEDAc = X-Google-Smtp-Source: AGHT+IEZUb64eDJnTtOSb4gVDYBTxU/1+2ahoDFAxTIV1MMqSExpd5h5asji5aQsou6V7+mZ5GhxCQ== X-Received: by 2002:a05:6a20:9f4e:b0:1f5:7eb5:72dc with SMTP id adf61e73a8af0-20aa26d41ccmr5129356637.3.1746031746767; Wed, 30 Apr 2025 09:49:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 14/16] accel/tcg: Pass TCGTBCPUState to tb_gen_code Date: Wed, 30 Apr 2025 09:48:52 -0700 Message-ID: <20250430164854.2233995-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031838880019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/internal-common.h | 5 ++--- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/translate-all.c | 28 +++++++++++++--------------- 3 files changed, 17 insertions(+), 20 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 98c702422f..1dbc45dd95 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -12,6 +12,7 @@ #include "exec/cpu-common.h" #include "exec/translation-block.h" #include "exec/mmap-lock.h" +#include "accel/tcg/tb-cpu-state.h" =20 extern int64_t max_delay; extern int64_t max_advance; @@ -46,9 +47,7 @@ static inline bool cpu_plugin_mem_cbs_enabled(const CPUSt= ate *cpu) #endif } =20 -TranslationBlock *tb_gen_code(CPUState *cpu, vaddr pc, - uint64_t cs_base, uint32_t flags, - int cflags); +TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s); void page_init(void); void tb_htable_init(void); void tb_reset_jump(TranslationBlock *tb, int n); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4ad84c2db8..a7436d2873 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -574,7 +574,7 @@ void cpu_exec_step_atomic(CPUState *cpu) tb =3D tb_lookup(cpu, s); if (tb =3D=3D NULL) { mmap_lock(); - tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags); + tb =3D tb_gen_code(cpu, s); mmap_unlock(); } =20 @@ -951,7 +951,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) uint32_t h; =20 mmap_lock(); - tb =3D tb_gen_code(cpu, s.pc, s.cs_base, s.flags, s.cflags= ); + tb =3D tb_gen_code(cpu, s); mmap_unlock(); =20 /* diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 97aadee52c..7b0bd50904 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -290,9 +290,7 @@ static int setjmp_gen_code(CPUArchState *env, Translati= onBlock *tb, } =20 /* Called with mmap_lock held for user mode emulation. */ -TranslationBlock *tb_gen_code(CPUState *cpu, - vaddr pc, uint64_t cs_base, - uint32_t flags, int cflags) +TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s) { CPUArchState *env =3D cpu_env(cpu); TranslationBlock *tb, *existing_tb; @@ -305,14 +303,14 @@ TranslationBlock *tb_gen_code(CPUState *cpu, assert_memory_lock(); qemu_thread_jit_write(); =20 - phys_pc =3D get_page_addr_code_hostp(env, pc, &host_pc); + phys_pc =3D get_page_addr_code_hostp(env, s.pc, &host_pc); =20 if (phys_pc =3D=3D -1) { /* Generate a one-shot TB with 1 insn in it */ - cflags =3D (cflags & ~CF_COUNT_MASK) | 1; + s.cflags =3D (s.cflags & ~CF_COUNT_MASK) | 1; } =20 - max_insns =3D cflags & CF_COUNT_MASK; + max_insns =3D s.cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D TCG_MAX_INSNS; } @@ -332,12 +330,12 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 gen_code_buf =3D tcg_ctx->code_gen_ptr; tb->tc.ptr =3D tcg_splitwx_to_rx(gen_code_buf); - if (!(cflags & CF_PCREL)) { - tb->pc =3D pc; + if (!(s.cflags & CF_PCREL)) { + tb->pc =3D s.pc; } - tb->cs_base =3D cs_base; - tb->flags =3D flags; - tb->cflags =3D cflags; + tb->cs_base =3D s.cs_base; + tb->flags =3D s.flags; + tb->cflags =3D s.cflags; tb_set_page_addr0(tb, phys_pc); tb_set_page_addr1(tb, -1); if (phys_pc !=3D -1) { @@ -355,9 +353,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->guest_mo =3D cpu->cc->tcg_ops->guest_default_memory_order; =20 restart_translate: - trace_translate_block(tb, pc, tb->tc.ptr); + trace_translate_block(tb, s.pc, tb->tc.ptr); =20 - gen_code_size =3D setjmp_gen_code(env, tb, pc, host_pc, &max_insns, &t= i); + gen_code_size =3D setjmp_gen_code(env, tb, s.pc, host_pc, &max_insns, = &ti); if (unlikely(gen_code_size < 0)) { switch (gen_code_size) { case -1: @@ -434,10 +432,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, * For CF_PCREL, attribute all executions of the generated code * to its first mapping. */ - perf_report_code(pc, tb, tcg_splitwx_to_rx(gen_code_buf)); + perf_report_code(s.pc, tb, tcg_splitwx_to_rx(gen_code_buf)); =20 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && - qemu_log_in_addr_range(pc)) { + qemu_log_in_addr_range(s.pc)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { int code_size, data_size; --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031923; cv=none; d=zohomail.com; s=zohoarc; b=W6OnJFzc/DW+aYBEjMZieGpMOznUzOtEKQy70564PYZCJRbfncZXghoxXVfsoCSLI1sLKT4u81gT10W6OvSQvYgNLd8FMNzIDvN2GGyrPKt+5Ax2hxNgh1sl3tHYKdtnpBJWoP+eaDl3dN2nsFUjPQPQdSrkRCtF985Md6UGtwg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031923; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D0jG93rvSyOgsjKDUChcn5N32sYYanMJMMGrdtwKZxY=; b=my/jMGGs5o+p39BAotRPB4NmI5/NgnTOf9kcMnCH0Lhk9UQSP8PllzqDClW4Dq8Xmf+TtOJplu2yG1F69qwNxpitGG498xu0HkZxUpyU5IUELUEUhuZDwq/pzCF2dmmRNlV+Vk6bd8XPVzVcS25WAZ4+sHCj0wKiCOnA4OEGaR8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1746031923500387.06506106629115; Wed, 30 Apr 2025 09:52:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcj-0005ya-Nv; Wed, 30 Apr 2025 12:49:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcT-0005F3-99 for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:18 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcP-0001vn-7h for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:12 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-b03bc416962so43699a12.0 for ; Wed, 30 Apr 2025 09:49:08 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031747; x=1746636547; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D0jG93rvSyOgsjKDUChcn5N32sYYanMJMMGrdtwKZxY=; b=PiGdAqXpPPyKGvNHgI91bzwSa1cze1cph3qgwBilpjzsGJ/sSNeRk6ar3zoIahmWFr W+rR7pkhXpDcm3GhNZOx/kK8klcXkryIJ/tE4Jyhpj98rStv4uK44jQbIEFkuWHt1DgQ 1PT7ChGY+Kzx858vubmxZBLtKENbhtVXUgopHbXWCWkCePpJ48a3pexmWKj1ezf9Uv7a UeW2r5wJK2LP9WyJzuaaVJIApQbLe8nlH5+rSY1VZMXs71t8GewA/3sROmgQ59VI8F4L lKSz3m5DSGeXKKVxJcPdtqLgiAaHE1xwxzVd4lkxvqPtmZ2A7J6OTsby6HMtIPq5nl1X 7SxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031747; x=1746636547; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D0jG93rvSyOgsjKDUChcn5N32sYYanMJMMGrdtwKZxY=; b=Jjg2yQKXc/7gQGwnOu4CATe2Euqvt1tkzmK/KxZ34HpBAFoCrliVq5pTxPLKL4WKwL 7OIbGVCzJyGosaqHPnjaF+zk/I4kR9YIptNpZZ72MuACZAZQWr9G7uSMpCaRPFtlX5Ss jLpktVkkOSEPqCOpWBkOXNZPMZupIJfwdnAT6Fd8C7SE/0n05/92ArVNT0BHPoHPamES rNFn0q2MXd8DoMmJYfj+gdN1eB3DAm7MiMmXRAzXUiDt/+p2nOl17qpaviQok0c7tixE DNQygy82tctZIrqAJiI8XPn/EZaH2+fCx/Tz/xcBf4fdacRdHMJHL+F7GpbUVo0rb2VB Co+Q== X-Gm-Message-State: AOJu0YzTsoKxpgN0oYkMv0ygqx/GDmynFurMtvGvrjoCI2rL0FkTW0kQ V1vOEh2JBO91fGWi+K3cbkaRzs3zw8walMK7P44bOtRUquPInrraRyIQFQ8lPj/YlJQ+6ZVWcsq A X-Gm-Gg: ASbGncvaLvxm6EUMjmmjeHxqMfsvWlXg1CO8n9cFbZxlMOm3QpPRZUth6UrFmZ1dZE3 KbQOsLuoCv/NTQpbpZEwJQlttv0ZTxhSDiuySOucd+VJG/V0qL+YeAp10pvz8rP3Rt3ZNwR5wjO pDkPzlhJFrFGDvegMsvli6ZUa/AcyHIRMEpyiI6NgLvsqg65ZWJPdKsI+vr/uGZcfgA1umQw6Qm mDh3gAmiWG9F9uMxI0R1zrkMpMt8XquN8Ex5acEkGPvx1wRMA+8QRKggEM2itmF5AwMiPJUazqI vluM/8h351BlJWX/nmcQBjIIUi+IfvorN1wWnYKGxnUYUl3Lex5q1vgZ36CmAsXCZ6Z+JjXcHSd hwdAYAg5ITQ== X-Google-Smtp-Source: AGHT+IEPXUuYeTHsdXisrV8N4xcvlXucSuRxi85RlWWGRIc2sPSfwCuNmpgNoz53rUEttV+CnWiHOg== X-Received: by 2002:a05:6a20:9f4e:b0:1f5:7eb5:72dc with SMTP id adf61e73a8af0-20aa26d41ccmr5129430637.3.1746031747637; Wed, 30 Apr 2025 09:49:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 15/16] accel/tcg: Split out accel/tcg/helper-retaddr.h Date: Wed, 30 Apr 2025 09:48:53 -0700 Message-ID: <20250430164854.2233995-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031925229019100 Move set_helper_retaddr and clear_helper_retaddr to a new header file. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ldst.h | 34 ----------------------- include/accel/tcg/helper-retaddr.h | 43 ++++++++++++++++++++++++++++++ accel/tcg/cpu-exec.c | 1 + accel/tcg/user-exec.c | 1 + target/arm/tcg/helper-a64.c | 1 + target/arm/tcg/sme_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/ppc/mem_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + 9 files changed, 50 insertions(+), 34 deletions(-) create mode 100644 include/accel/tcg/helper-retaddr.h diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h index f97a730703..44a62b54da 100644 --- a/include/accel/tcg/cpu-ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -526,38 +526,4 @@ void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, MMUAccessType access_type, int mmu_idx); #endif =20 -/* - * For user-only, helpers that use guest to host address translation - * must protect the actual host memory access by recording 'retaddr' - * for the signal handler. This is required for a race condition in - * which another thread unmaps the page between a probe and the - * actual access. - */ -#ifdef CONFIG_USER_ONLY -extern __thread uintptr_t helper_retaddr; - -static inline void set_helper_retaddr(uintptr_t ra) -{ - helper_retaddr =3D ra; - /* - * Ensure that this write is visible to the SIGSEGV handler that - * may be invoked due to a subsequent invalid memory operation. - */ - signal_barrier(); -} - -static inline void clear_helper_retaddr(void) -{ - /* - * Ensure that previous memory operations have succeeded before - * removing the data visible to the signal handler. - */ - signal_barrier(); - helper_retaddr =3D 0; -} -#else -#define set_helper_retaddr(ra) do { } while (0) -#define clear_helper_retaddr() do { } while (0) -#endif - #endif /* ACCEL_TCG_CPU_LDST_H */ diff --git a/include/accel/tcg/helper-retaddr.h b/include/accel/tcg/helper-= retaddr.h new file mode 100644 index 0000000000..037fda2b83 --- /dev/null +++ b/include/accel/tcg/helper-retaddr.h @@ -0,0 +1,43 @@ +/* + * Get user helper pc for memory unwinding. + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_HELPER_RETADDR_H +#define ACCEL_TCG_HELPER_RETADDR_H + +/* + * For user-only, helpers that use guest to host address translation + * must protect the actual host memory access by recording 'retaddr' + * for the signal handler. This is required for a race condition in + * which another thread unmaps the page between a probe and the + * actual access. + */ +#ifdef CONFIG_USER_ONLY +extern __thread uintptr_t helper_retaddr; + +static inline void set_helper_retaddr(uintptr_t ra) +{ + helper_retaddr =3D ra; + /* + * Ensure that this write is visible to the SIGSEGV handler that + * may be invoked due to a subsequent invalid memory operation. + */ + signal_barrier(); +} + +static inline void clear_helper_retaddr(void) +{ + /* + * Ensure that previous memory operations have succeeded before + * removing the data visible to the signal handler. + */ + signal_barrier(); + helper_retaddr =3D 0; +} +#else +#define set_helper_retaddr(ra) do { } while (0) +#define clear_helper_retaddr() do { } while (0) +#endif + +#endif /* ACCEL_TCG_HELPER_RETADDR_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index a7436d2873..a8fbda31ba 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -24,6 +24,7 @@ #include "hw/core/cpu.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/helper-retaddr.h" #include "trace.h" #include "disas/disas.h" #include "exec/cpu-common.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 70feee8df9..68e01fc584 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -26,6 +26,7 @@ #include "qemu/bitops.h" #include "qemu/rcu.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "user/cpu_loop.h" #include "qemu/main-loop.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 9cffda07cd..4f618ae390 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -30,6 +30,7 @@ #include "qemu/crc32c.h" #include "exec/cpu-common.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 3226895cae..de0c6e54d4 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -23,6 +23,7 @@ #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" #include "fpu/softfloat.h" #include "vec_internal.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 9f20ecb51d..a2c363a4e1 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -30,6 +30,7 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/probe.h" #ifdef CONFIG_USER_ONLY diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index aa1af44d22..6ab71a6fcb 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "internal.h" #include "qemu/atomic128.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 857005b120..a03609a140 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -32,6 +32,7 @@ #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" #include "qemu/atomic128.h" =20 --=20 2.43.0 From nobody Sat Nov 15 22:25:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1746031908; cv=none; d=zohomail.com; s=zohoarc; b=IpQ+MrHn8wfyIAeWBriDvsGFM+wy2xzghuO26AERMgW8gItknJ8gMdxjQ42+e2KAtuRiC0zHh7FmRN0BenIer4CKliCQWI7Oc59600U5n1urmRy+Dqulu+DY9uHTEfMXCVXdIPlXxSuqlpfFywOOQZd4GCJhGt93sxfqXlBihjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1746031908; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BDXEkP41hr8unW2CYQoxGQEU1dZcDdkH6hmvqIdSZek=; b=fT6VrM2yrG6DUfKJEprwOcgsHa9doC+q4DjUbEvSWHjEIyVZCDg8wRD9nljp9A+0Eq2dZaKPzxlIVmjPflCa4sKxanTDbw8U3EiyD4DX+TfaO6H9o8N43JiH4CbBtaYjx2ClVyb/JeqQJX7luZdwD0n/gtTGf/K9SQjPb0yzDo0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174603190845719.70235146282107; Wed, 30 Apr 2025 09:51:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uAAcn-0006Em-AQ; Wed, 30 Apr 2025 12:49:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uAAcX-0005GV-08 for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:18 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uAAcR-0001vs-2S for qemu-devel@nongnu.org; Wed, 30 Apr 2025 12:49:13 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-736aa9d0f2aso202914b3a.0 for ; Wed, 30 Apr 2025 09:49:09 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f580asm9129704a12.2.2025.04.30.09.49.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Apr 2025 09:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1746031748; x=1746636548; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BDXEkP41hr8unW2CYQoxGQEU1dZcDdkH6hmvqIdSZek=; b=zRdEWEIKd4wk1g3dIyDx+6nLy4mF9ZYIFp+Q1MPLbGdKQkez0DQR8Ak5pOl2B45376 2nAP2AtPZnidEsjNfCwCeiHBfBxLU625ZPJ/4X8YUbwyvAg1FYYsh7y/xPYk8X1faxr8 s9YwEAthxyY3MQ4+N7DOjbo/BDH0YVpz4naYBzMJ3/8qBG2kehRkrhJHJeyrewZUb66y kYpXXtaxFUCbphcwQVXs03RLxJk7fk9lahmYJVgAn/m6oPiwKDBZfjEnycFsmSoI7eDd Ft9/Qw6qtXhQwVVjx3WPQ5Ouee3eU+aACbhO0yCtJzlUa1AD+Y8xZ7r7R1xNshPwckMy lrSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746031748; x=1746636548; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BDXEkP41hr8unW2CYQoxGQEU1dZcDdkH6hmvqIdSZek=; b=Tn5Bnmc3vR+u22mb7gpa7m1i/uuhcT9tqU6Xh7KkRfsluVoTaKtjghDvr/pEpUsD8e xcr4cVKLxBr1CS3kHYkg6M+S8sQuca92gnn0o/OCRns994z2KWEMbrviKgmvHQPBhsO4 IeQepNawmUwMNb3zxY8hpmvXADGbhXkljqNYUL+lbJoedK/8ZIZxIZ9OPCSXHXLbFOrT vRj9ndfJTvXc8w/EQCA9g6R4X1IUjLsQd4wo4R+4XYmO2o2Z9+60jeMsaeVfCSum50TT pY+3zWKwyjL/uAIAe5MXqNwVb4nwz1DkbBA9pZREH0vHgJ5bUi3avA75jYibwljCa/Yl Cvfg== X-Gm-Message-State: AOJu0Yy3KfWqJajdi/O6Q3s8XAjXtGgALtGLBDZpgYB7UyKghUyQN8VM 04Ga7MZmD4oZ/2c0lo6ZfDy9dDQXFxK1Bxfd5851XVPuzb2+xKxN7k8unL2soPnI7FEl+BVD14r d X-Gm-Gg: ASbGncvB0asgh0W9KgWt2Y3YFmBLgdT97BEMJvWIyGS2PLoxuknoVEsYeMrIgBglTQK OWf/VhoE4bWm2UQnQlEu8ycKIard/INZLJ0utfzkTfhkLNbWwZxGajF59AlTe2Ea38HNZZbqlGs jRFwV0P0NNK8kzQOFcqh2YSs3G8eayRBBPv/q7AXZUnFUQ1xIXdLH0ymJg3qPoiMuvSU+d0AcNH WMQz/d/5K0lDk4m9YWi8DO6xj/suz/TuAzKfFbH2tHe9//zP8/ltU0+Ty8pl5YGgF3MxrFTWOTi 0pCb+UBRhWGBaQNj4JIjgA1Gx5qV1Pjoc74SKcskacrRzpfXJBnGJK4nAZr+0VVTbCIs6eVSI/M = X-Google-Smtp-Source: AGHT+IFX4saEsqc4H+VJnoVaR2OP0bDQxkQNsbrJPLFxFxcUE1Cq02AFDk/sP9OwTi2iv82XGY6oPQ== X-Received: by 2002:a05:6a21:168b:b0:1ee:e24d:8fe3 with SMTP id adf61e73a8af0-20a87947e3bmr5794917637.10.1746031748329; Wed, 30 Apr 2025 09:49:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH v2 16/16] accel/tcg: Compile cpu-exec.c twice Date: Wed, 30 Apr 2025 09:48:54 -0700 Message-ID: <20250430164854.2233995-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250430164854.2233995-1-richard.henderson@linaro.org> References: <20250430164854.2233995-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1746031911073019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 2 -- accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index a8fbda31ba..cc5f362305 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,7 +22,6 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/cpu.h" -#include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/helper-retaddr.h" #include "trace.h" @@ -37,7 +36,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#include "cpu.h" #include "exec/icount.h" #include "exec/replay-core.h" #include "system/tcg.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 3f7b127130..0bb089299b 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -5,6 +5,7 @@ endif tcg_ss =3D ss.source_set() =20 tcg_ss.add(files( + 'cpu-exec.c', 'cpu-exec-common.c', 'tcg-runtime.c', 'tcg-runtime-gvec.c', @@ -21,7 +22,6 @@ libsystem_ss.add_all(tcg_ss) tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', - 'cpu-exec.c', 'translate-all.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) --=20 2.43.0