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Iglesias" Subject: [PATCH v2 1/7] target/microblaze: Use 'obj' in DEVICE() casts in mb_cpu_initfn() Date: Tue, 29 Apr 2025 14:21:54 +0100 Message-ID: <20250429132200.605611-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745933122851019100 Content-Type: text/plain; charset="utf-8" We're about to make a change that removes the only other use of the 'cpu' local variable in mb_cpu_initfn(); since the DEVICE() casts work fine with the Object*, use that instead, so that we can remove the local variable when we make the following change. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 00a2730de4d..d92a43191bd 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -333,11 +333,11 @@ static void mb_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ - qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); - qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); + qdev_init_gpio_in(DEVICE(obj), microblaze_cpu_set_irq, 2); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); + qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); #endif =20 /* Restricted 'endianness' property is equivalent of 'little-endian' */ --=20 2.43.0 From nobody Sat Nov 15 22:25:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745933049; cv=none; d=zohomail.com; s=zohoarc; b=CEHkUQoCEKJHzNnawUVxu82wc5oTT539ZGeRWHdq9nXjE+hFkPs2IwR8ooYpl8DKfsgsvdtD7GZJdW3wDmcepF9/TiKffS4Qo4UdWA3+eRCHV4urgKXuaUAq2PJYVnzCOOrfv98iIdwyiirnamxtGcd6yDs/Z9I0U3WeXRQKr1I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745933049; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1K2H3VE4tCQOLcXEpqGHsbFF7wzsGTavlqzL6DY4PxQ=; b=bc6RFB0CXgmYi9TN83v59QqUDrozh0j59KWyCFpQ1cSe22eszKrzS1xcB9DX1xwwpEhx73z0o1O8wZfTq8XDCzyDTdLnPyh4hHofEdFX0R0dX5/HDoMN2yUVgNyCiYeVP3fRQECVVW3zi5mt6uGcjsOynRxcnnThG7L/FbTW/y8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745933049513144.29283309504126; Tue, 29 Apr 2025 06:24:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kvc-0005Mm-Ir; Tue, 29 Apr 2025 09:23:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kuj-00056i-G4 for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:23 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kud-0005ch-DD for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:19 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43d2d952eb1so39867595e9.1 for ; Tue, 29 Apr 2025 06:22:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Iglesias" Subject: [PATCH v2 2/7] target/microblaze: Delay gdb_register_coprocessor() to realize Date: Tue, 29 Apr 2025 14:21:55 +0100 Message-ID: <20250429132200.605611-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745933050702019000 Content-Type: text/plain; charset="utf-8" Currently the microblaze code calls gdb_register_coprocessor() in its initfn. This works, but we would like to delay setting up GDB registers until realize. All other target architectures only call gdb_register_coprocessor() in realize, after the call to cpu_exec_realizefn(). Move the microblaze gdb_register_coprocessor() use, bringing it in line with other targets. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d92a43191bd..b8dae83ce0c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -252,6 +252,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error *= *errp) return; } =20 + gdb_register_coprocessor(cs, mb_cpu_gdb_read_stack_protect, + mb_cpu_gdb_write_stack_protect, + gdb_find_static_feature("microblaze-stack-pro= tect.xml"), + 0); + qemu_init_vcpu(cs); =20 version =3D cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; @@ -324,13 +329,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error *= *errp) =20 static void mb_cpu_initfn(Object *obj) { - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(obj); - - gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, - mb_cpu_gdb_write_stack_protect, - gdb_find_static_feature("microblaze-stack-pro= tect.xml"), - 0); - #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ qdev_init_gpio_in(DEVICE(obj), microblaze_cpu_set_irq, 2); --=20 2.43.0 From nobody Sat Nov 15 22:25:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745933115; cv=none; d=zohomail.com; s=zohoarc; b=Ob5tbFqGcGlqSB2TMoDo2S2YwOxD2YH5smUZSm2xVyVCw7dC/WsNc0iToyjSG8jOEgMC2scWTiZic9TFp50+9ddjw880DaGF/meDpfdJSQEop0C3hTPszbDiSvvLBYkH/Ke8iF1rcfC98gDjoil3rm6IUL2ccdXwTjjDiStR3EQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745933115; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=U0MilJhhj9cXGSYSZ37HStWvLOYbPls0FXWBsHGtjT4=; b=AZQuTia/q+9PoRWgjE9HKMWo3mmjY1OortgRb//zwIuNFavTDDMj5DONz4cFU8LaEJW5fT3n5UT+V6S2AHlzGU38/KzLCu+hx54YuoEOvG2BJJjpy+DY1orfFiNp/oFUA/LlekyNnl6TDh0eaBscj9orlOMTtHJH8kMi+i2tG90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17459331158621020.8601138347334; Tue, 29 Apr 2025 06:25:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kvZ-0005Iu-0W; Tue, 29 Apr 2025 09:23:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kuj-00056q-W3 for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:24 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kud-0005dD-Ur for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:21 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4394a823036so59061655e9.0 for ; Tue, 29 Apr 2025 06:22:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Iglesias" Subject: [PATCH v2 3/7] hw/core/cpu-common: Don't init gdbstub until cpu_exec_realizefn() Date: Tue, 29 Apr 2025 14:21:56 +0100 Message-ID: <20250429132200.605611-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745933117985019000 Content-Type: text/plain; charset="utf-8" Currently we call gdb_init_cpu() in cpu_common_initfn(), which is very early in the CPU object's init->realize creation sequence. In particular this happens before the architecture-specific subclass's init fn has even run. This means that gdb_init_cpu() can only do things that depend strictly on the class, not on the object, because the CPUState* that it is passed is currently half-initialized. In commit a1f728ecc90cf6c6 we accidentally broke this rule, by adding a call to the gdb_get_core_xml_file method which takes the CPUState. At the moment we get away with this because the only implementation doesn't actually look at the pointer it is passed. However the whole reason we created that method was so that we could make the "which XML file?" decision based on a property of the CPU object, and we currently can't change the Arm implementation of the method to do what we want without causing wrong behaviour or a crash. The ordering restrictions here are: * we must call gdb_init_cpu before: - any call to gdb_register_coprocessor() - any use of the gdb_num_regs field (this is only used in code that's about to call gdb_register_coprocessor() and wants to know the first register number of the set of registers it's about to add) * we must call gdb_init_cpu after CPU properties have been set, which is to say somewhere in realize The function cpu_exec_realizefn() meets both of these requirements, as it is called by the architecture-specific CPU realize function early in realize, before any calls ot gdb_register_coprocessor(). Move the gdb_init_cpu() call to there. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/core/cpu-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 92c40b6bf83..39e674aca21 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -234,6 +234,8 @@ bool cpu_exec_realizefn(CPUState *cpu, Error **errp) return false; } =20 + gdb_init_cpu(cpu); + /* Wait until cpu initialization complete before exposing cpu. */ cpu_list_add(cpu); =20 @@ -304,7 +306,6 @@ static void cpu_common_initfn(Object *obj) /* cache the cpu class for the hotpath */ cpu->cc =3D CPU_GET_CLASS(cpu); =20 - gdb_init_cpu(cpu); cpu->cpu_index =3D UNASSIGNED_CPU_INDEX; cpu->cluster_index =3D UNASSIGNED_CLUSTER_INDEX; cpu->as =3D NULL; --=20 2.43.0 From nobody Sat Nov 15 22:25:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745933040; cv=none; d=zohomail.com; s=zohoarc; b=FyqNrsQLIEqP3OQHMMrABvmMyUvswI+fCAeHrFbLYzi5glS8VniYb5JV6oXfyWNFwxdP7yBj8FmS4UP4QNnzhZPavnC/Vfsk0Riw7sWYG0YElCoUvIFx/qgpG2eR+JKcSFmEUjLMgoZgNkMPxsOuxmycYPRr7VprdqHc6iJsOq0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745933040; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PW9jN2yS/TAOGn5xgs3qpwNb9whA0g2Y1AVjroSf5VQ=; b=Phwwks0/LIeWsm8ntzTQjjbVG7kC+ID+RTp/3EwLRjYve+myjgZ9rKbufmr93IKviryHn9qdh/TTWVEqxgRvjI+jVVSZ42z23ahIr/jiHfmMa25nVGl2X2lbZJ/1DQCYKmxUrdAHsoBV+G4CoT0T0DuzOl54RtDcsq7m/EW/Ka8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745933040179773.9410325654534; Tue, 29 Apr 2025 06:24:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kvP-0005EU-DD; Tue, 29 Apr 2025 09:23:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kuk-00056r-03 for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:24 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kue-0005eH-1x for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:21 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-39c14016868so6066680f8f.1 for ; Tue, 29 Apr 2025 06:22:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Iglesias" Subject: [PATCH v2 4/7] target/arm: Present AArch64 gdbstub based on ARM_FEATURE_AARCH64 Date: Tue, 29 Apr 2025 14:21:57 +0100 Message-ID: <20250429132200.605611-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745933042723019100 Currently we provide an AArch64 gdbstub for CPUs which are TYPE_AARCH64_CPU, and an AArch32 gdbstub for those which are only TYPE_ARM_CPU. This mostly does the right thing, except in the corner case of KVM with -cpu host,aarch64=3Doff. That produces a CPU which is TYPE_AARCH64_CPU but which has ARM_FEATURE_AARCH64 removed and which to the guest is in AArch32 mode. Now we have moved all the handling of AArch64-vs-AArch32 gdbstub behaviour into TYPE_ARM_CPU we can change the condition we use for whether to select the AArch64 gdbstub to look at ARM_FEATURE_AARCH64. This will mean that we now correctly provide an AArch32 gdbstub for aarch64=3Doff CPUs. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/internals.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4d3d84ffebd..f1c06a3fd89 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1831,7 +1831,7 @@ void aarch64_add_sme_properties(Object *obj); /* Return true if the gdbstub is presenting an AArch64 CPU */ static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu) { - return object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU); + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); } =20 /* Read the CONTROL register as the MRS instruction would. */ --=20 2.43.0 From nobody Sat Nov 15 22:25:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745933044; cv=none; d=zohomail.com; s=zohoarc; b=CpYhI7vVp46MDfYpwN/Zsw27zDff90/Vaxb6hOg3hueJw5p5mTroKMWqNFdE/FUkVOxSkeHW8TpX80UtDW6lt4/NuG1PWKNkmHrP5JsOEohioizRcovO6/HsgUoon4MwcwOvZZwealCKlMqtXpi+6J+cjz/5ai6fnvGQHc2MYq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745933044; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DjSG1O4sqyvihfU4YBjpfGe20pFEFSZo62gLO5k4z4k=; b=eC4mktlbf4OpWmWir2kia1MNPKwEj9xGR2944Vre7h9liRrYpJ0TnuzeggSgNOg3l7haYnf50XFN/VKm0TfPnr/Qf+7YgzAy7v35tf8LrtyRQDSduZ0nDEQcakCZj0AAX0RlJ7eK7PKdzsh8drmBEWb5FOYKQ0HpEvc9vGfBj1Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745933044571356.80992388494576; Tue, 29 Apr 2025 06:24:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kvb-0005LF-8a; Tue, 29 Apr 2025 09:23:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kuj-00056e-Ca for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:23 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kud-0005en-DO for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:20 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-3a064a3e143so3072579f8f.3 for ; Tue, 29 Apr 2025 06:22:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a073ca5219sm13729371f8f.27.2025.04.29.06.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 06:22:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745932927; x=1746537727; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DjSG1O4sqyvihfU4YBjpfGe20pFEFSZo62gLO5k4z4k=; b=SzhdpLNC6SAe0ElUdfmQ95kcWMsf8FDCdDMn49VDIgUimOAHm8ZlBLba4lrwgaza/H Zsips9aPT25RyZfcN/WrNE9tXeh5SEMmzWfoclzehm2SzcIadUe0s9b6t/EYuI2HFqJx FbN17u71Pa1YF30QmKVKablDASzB24wTAuA6z+pvg6t4EFoxk/Gi4jYLXAfONkUubDo4 FK4BO7HmcksA2tEvqIeYCeHLr5xcO7o/lre/yiiqFR6eoVlrRTT0ruIVXW3UFbIXekfo wk0Nc6aDTSCOXHc7r6i2DAVm+AA580bxhScrN7ol2SNP2yWhavaB7XyvKU0EAy8GGCrV uTpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745932927; x=1746537727; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DjSG1O4sqyvihfU4YBjpfGe20pFEFSZo62gLO5k4z4k=; b=Smig3Z6egvSvi7V7hmmiLunb37nr8f6wKNzflt43+ofHlgZ9SQsBBJ9710Z2H9ng1L SxxLPUJmBKy6IRZmoOmORSVlJ7NOxZGfBdkn0x1mgxPhpd2tkcBitOVAoloYpm5EiQy+ +TEjqZCQD8zRpJc1kVJjcZk2HaDtvQrnWSOW9hervM0p16fUfuAINKB5KJ8GujzjLOS+ AuFYftKTRILFvr5VWJRNucOO6ogHwsvu8AVtqMyRwEWbAs0Gma0GlDzmHBpvYkEceH27 dQzqWSdQp0alPmZ+vHKcadFWAV7OTKqQZyuY64Myhw4WvzYuVkeqyFA2RMp32Oe8v4uY 36uA== X-Forwarded-Encrypted: i=1; AJvYcCVXIItWbZN6dYv0oX6PY6RhhN3KjMEcS/ihS7Y/WCoJd7S8NRiGncHtQASpbb0sBgT1rtkk1LR63eZ3@nongnu.org X-Gm-Message-State: AOJu0YzYSoJmqCMTKGEqqL01XIq3pTBx9JdJyTn33F3npTc7KvL+Frqp rpNpGylJF0XSC7gsfIX656b8WFzCTE8pypSwVD17VkeYbeQdOouC2g5TgYjG8TwGoPwP8zpG0CN d X-Gm-Gg: ASbGncvy0UcBPbbcc63YtPF+mjARqj4/7Vo6a9le1gydFm8sM8jzGXZh0ScmlK1okUZ uvK3Z+6wCXiKoaO1csEw6rmJTom7cWJv8kS67UxOt49XOA2CH7rJ2wRwt5SP0Zpx7VTMzukgp/l paCJon3ApIg/rEPc+oqT3LwN8+jP/3eXzPESh2cK09WxmS2dVsjfi1hisOJCDpvQHQH6hKVyslp vpuZbg64D5/GM0ELBWYTku+Y9BlVH3qrI9OF8g9HfmTSRb64MMUcRXU/+M9VeXmbTrlojR2aVA6 AsR3Cxztc1R45jadhJVH9au2/P5/q9hhabQAU+kNge7YU8a0aORb6Fyd9A== X-Google-Smtp-Source: AGHT+IHUqSXUoZjCPqu+mXZN8fT//UMxUYpYLWKP+euiVEBY5su0iLgY6sEzdYbwjQlJ7z6rVEFmIQ== X-Received: by 2002:adf:efd0:0:b0:39c:1159:fe1f with SMTP id ffacd0b85a97d-3a0891ac019mr2454018f8f.32.1745932927612; Tue, 29 Apr 2025 06:22:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH v2 5/7] target/arm: Move aarch64 CPU property code to TYPE_ARM_CPU Date: Tue, 29 Apr 2025 14:21:58 +0100 Message-ID: <20250429132200.605611-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745933046730019100 The only thing we have left in the TYPE_AARCH64_CPU class that makes it different to TYPE_ARM_CPU is that we register the handling of the "aarch64" property there. Move the handling of this property to the base class, where we make it a property of the object rather than of the class, and add it to the CPU if it has the ARM_FEATURE_AARCH64 property present at init. This is in line with how we handle other Arm CPU properties, and should not change which CPUs it's visible for. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ target/arm/cpu64.c | 33 --------------------------------- 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5e951675c60..73a2a197667 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1610,6 +1610,35 @@ static void arm_set_pmu(Object *obj, bool value, Err= or **errp) cpu->has_pmu =3D value; } =20 +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); +} + +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + /* + * At this time, this property is only allowed if KVM is enabled. This + * restriction allows us to avoid fixing up functionality that assumes= a + * uniform execution state like do_interrupt. + */ + if (value =3D=3D false) { + if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { + error_setg(errp, "'aarch64' feature cannot be disabled " + "unless KVM is enabled and 32-bit EL1 " + "is supported"); + return; + } + unset_feature(&cpu->env, ARM_FEATURE_AARCH64); + } else { + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + } +} + unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) { /* @@ -1737,6 +1766,13 @@ void arm_cpu_post_init(Object *obj) */ arm_cpu_propagate_feature_implications(cpu); =20 + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, + aarch64_cpu_set_aarch64); + object_property_set_description(obj, "aarch64", + "Set on/off to enable/disable aarc= h64 " + "execution state "); + } if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property= ); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 00629a5d1d1..e527465a3ca 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,45 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] =3D { #endif }; =20 -static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); -} - -static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - /* At this time, this property is only allowed if KVM is enabled. This - * restriction allows us to avoid fixing up functionality that assumes= a - * uniform execution state like do_interrupt. - */ - if (value =3D=3D false) { - if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { - error_setg(errp, "'aarch64' feature cannot be disabled " - "unless KVM is enabled and 32-bit EL1 " - "is supported"); - return; - } - unset_feature(&cpu->env, ARM_FEATURE_AARCH64); - } else { - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - } -} - static void aarch64_cpu_finalizefn(Object *obj) { } =20 static void aarch64_cpu_class_init(ObjectClass *oc, const void *data) { - object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, - aarch64_cpu_set_aarch64); - object_class_property_set_description(oc, "aarch64", - "Set on/off to enable/disable aa= rch64 " - "execution state "); } =20 static void aarch64_cpu_instance_init(Object *obj) --=20 2.43.0 From nobody Sat Nov 15 22:25:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745933031; cv=none; d=zohomail.com; s=zohoarc; b=Ob29tF4EdTp+1W+uYThKV/11AcUldFQ4QpcGHr8N5uJjG/gt02FI3viIkiNdg5tu99D3R0ptzplA5uYOqQ72iSUtGgLtrWAytmdiwt+GXx3wAO3a11pCMcs6VjKMDDqs2PyCt494impTxss7x99fmtuDuUvrQokXX7yaPQ/1WDE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745933031; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mr1QFeW43XnVmNc1okA19chi54m5Uhrocgufe8XGZeE=; b=L+6OUFJaoSCq7FQTJ1JTXhNVnnsaITts5v48ehwN7KZr7sEIQtJaHqE2eQQCqwKypUBb+Fdfowuh8BA9SSlLDEXxtS7oEbY+0EGJI4rwYq2PheNsDXRdWkOQbo9tvEOWewiBwqv3KNqoAj2RjeBktd6vmpM+BAN8vGDHylya65g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745933031932124.36109887263365; Tue, 29 Apr 2025 06:23:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kva-0005L0-QM; Tue, 29 Apr 2025 09:23:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kuj-00056o-UK for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:24 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kue-0005fJ-02 for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:21 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-43cf628cb14so50311135e9.1 for ; Tue, 29 Apr 2025 06:22:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Iglesias" Subject: [PATCH v2 6/7] target/arm/kvm: don't check TYPE_AARCH64_CPU Date: Tue, 29 Apr 2025 14:21:59 +0100 Message-ID: <20250429132200.605611-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745933034704019100 We want to merge TYPE_AARCH64_CPU with TYPE_ARM_CPU, so enforcing in kvm_arch_init_vcpu() that the CPU class is a subclass of TYPE_AARCH64_CPU will no longer be possible. It's safe to just remove this test, because any purely-AArch32 CPU will fail the "kvm_target isn't set" check, because we no longer support the old AArch32-host KVM setup and so CPUs like the Cortex-A7 no longer set cpu->kvm_target. Only the 'host', 'max', and the odd special cases 'cortex-a53' and 'cortex-a57' set kvm_target. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/kvm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 97de8c7e939..6b2c788e0fa 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1882,8 +1882,7 @@ int kvm_arch_init_vcpu(CPUState *cs) CPUARMState *env =3D &cpu->env; uint64_t psciver; =20 - if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE || - !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { + if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE) { error_report("KVM is not supported for this guest CPU type"); return -EINVAL; } --=20 2.43.0 From nobody Sat Nov 15 22:25:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745933022; cv=none; d=zohomail.com; s=zohoarc; b=LXuat/YU/iWt49g1ulbx7I+teRSV7RIOLVD37d4HHZbbn9ZAVvSK9P0IJ7nHMuGt2PX2NRkP1PE4Ok/nqUrfDIu+8okS3hQu3numLdDpuMd4ZczpuNRaJzmmw8SCq8XTkfFeSGgbRSr+Z0efJqC0zuX0NN1TmGkZ2MIwknjNexM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745933022; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1ZwkigIUy0IIiAszFNbLpeUVLw4uBqn4OmPKEQckEf8=; b=Hzfra7uSOjN/JZwRwtsv6/fEbfW+cqVfpetWto4Ep3e0oZZr2dtlN4ZYbyW0Am0ZZXbHWAxqDLB/s/PA93G5VMg/3HihCgkNwr7KFFdE16bigp1HRx2SDR2N4PfGPWL6fqSKCYfKZHIpMknLgwBFLnt+ki/0GEwoWaEDTGT/FBA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745933022927427.4128124731907; Tue, 29 Apr 2025 06:23:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9kvd-0005NP-PO; Tue, 29 Apr 2025 09:23:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9kuj-00056g-FE for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:23 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9kub-0005gN-PY for qemu-devel@nongnu.org; Tue, 29 Apr 2025 09:22:18 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-39c1efbefc6so4114091f8f.1 for ; Tue, 29 Apr 2025 06:22:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Iglesias" Subject: [PATCH v2 7/7] target/arm: Remove TYPE_AARCH64_CPU Date: Tue, 29 Apr 2025 14:22:00 +0100 Message-ID: <20250429132200.605611-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250429132200.605611-1-peter.maydell@linaro.org> References: <20250429132200.605611-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745933024702019000 The TYPE_AARCH64_CPU class is an abstract type that is the parent of all the AArch64 CPUs. It now has no special behaviour of its own, so we can eliminate it and make the AArch64 CPUs directly inherit from TYPE_ARM_CPU. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu-qom.h | 5 ----- target/arm/cpu.h | 4 ---- target/arm/internals.h | 1 - target/arm/cpu64.c | 49 +----------------------------------------- target/arm/tcg/cpu64.c | 2 +- 5 files changed, 2 insertions(+), 59 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index b497667d61e..2fcb0e12525 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -28,11 +28,6 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) =20 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU =20 -#define TYPE_AARCH64_CPU "aarch64-cpu" -typedef struct AArch64CPUClass AArch64CPUClass; -DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, - TYPE_AARCH64_CPU) - #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fdcf8cd1ae0..a394c7d46d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1141,10 +1141,6 @@ struct ARMCPUClass { ResettablePhases parent_phases; }; =20 -struct AArch64CPUClass { - ARMCPUClass parent_class; -}; - /* Callback functions for the generic timer's timers. */ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); diff --git a/target/arm/internals.h b/target/arm/internals.h index f1c06a3fd89..7be34388fc2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -353,7 +353,6 @@ static inline int r14_bank_number(int mode) } =20 void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); =20 void register_cp_regs_for_features(ARMCPU *cpu); void init_cpreg_list(ARMCPU *cpu); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e527465a3ca..200da1c489b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,59 +781,12 @@ static const ARMCPUInfo aarch64_cpus[] =3D { #endif }; =20 -static void aarch64_cpu_finalizefn(Object *obj) -{ -} - -static void aarch64_cpu_class_init(ObjectClass *oc, const void *data) -{ -} - -static void aarch64_cpu_instance_init(Object *obj) -{ - ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(obj); - - acc->info->initfn(obj); - arm_cpu_post_init(obj); -} - -static void cpu_register_class_init(ObjectClass *oc, const void *data) -{ - ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); - - acc->info =3D data; -} - -void aarch64_cpu_register(const ARMCPUInfo *info) -{ - TypeInfo type_info =3D { - .parent =3D TYPE_AARCH64_CPU, - .instance_init =3D aarch64_cpu_instance_init, - .class_init =3D info->class_init ?: cpu_register_class_init, - .class_data =3D info, - }; - - type_info.name =3D g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); - type_register_static(&type_info); - g_free((void *)type_info.name); -} - -static const TypeInfo aarch64_cpu_type_info =3D { - .name =3D TYPE_AARCH64_CPU, - .parent =3D TYPE_ARM_CPU, - .instance_finalize =3D aarch64_cpu_finalizefn, - .abstract =3D true, - .class_init =3D aarch64_cpu_class_init, -}; - static void aarch64_cpu_register_types(void) { size_t i; =20 - type_register_static(&aarch64_cpu_type_info); - for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { - aarch64_cpu_register(&aarch64_cpus[i]); + arm_cpu_register(&aarch64_cpus[i]); } } =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 29ab0ac79da..5d8ed2794d3 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1316,7 +1316,7 @@ static void aarch64_cpu_register_types(void) size_t i; =20 for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { - aarch64_cpu_register(&aarch64_cpus[i]); + arm_cpu_register(&aarch64_cpus[i]); } } =20 --=20 2.43.0