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Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/internal-common.h | 6 +++++ include/accel/tcg/cpu-ops.h | 9 +++++-- include/qemu/typedefs.h | 1 + accel/tcg/cpu-exec.c | 48 +++++++++++++++---------------------- accel/tcg/translate-all.c | 8 ++----- target/alpha/cpu.c | 13 +++++----- target/arm/helper.c | 16 ++++++++----- target/avr/cpu.c | 9 +++---- target/hexagon/cpu.c | 15 ++++++------ target/hppa/cpu.c | 10 ++++---- target/i386/tcg/tcg-cpu.c | 19 +++++++++------ target/loongarch/cpu.c | 20 +++++++++------- target/m68k/cpu.c | 20 +++++++++------- target/microblaze/cpu.c | 13 ++++++---- target/mips/cpu.c | 14 ++++++----- target/openrisc/cpu.c | 16 +++++++------ target/ppc/helper_regs.c | 8 +++---- target/riscv/tcg/tcg-cpu.c | 12 +++++----- target/rx/cpu.c | 14 ++++++----- target/s390x/cpu.c | 14 ++++++----- target/sh4/cpu.c | 22 +++++++++++------ target/sparc/cpu.c | 17 +++++++------ target/tricore/cpu.c | 14 +++++------ target/xtensa/cpu.c | 36 +++++++++++++++------------- 24 files changed, 202 insertions(+), 172 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 98c702422f..3ff4c1cb54 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -12,6 +12,7 @@ #include "exec/cpu-common.h" #include "exec/translation-block.h" #include "exec/mmap-lock.h" +#include "accel/tcg/cpu-ops.h" =20 extern int64_t max_delay; extern int64_t max_advance; @@ -56,6 +57,11 @@ TranslationBlock *tb_link_page(TranslationBlock *tb); void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc); =20 +static inline TCGTBCPUState get_tb_cpu_state(CPUState *cs) +{ + return cpu_get_tb_cpu_state(cs); +} + /** * tlb_init - initialize a CPU's TLB * @cpu: CPU whose TLB should be initialized diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f5e5746976..8dbe79ea7c 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -18,8 +18,13 @@ #include "exec/vaddr.h" #include "tcg/tcg-mo.h" =20 -void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); +struct TCGTBCPUState { + vaddr pc; + uint32_t flags; + uint64_t flags2; +}; + +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); =20 struct TCGCPUOps { /** diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 507f0814d5..551239ca61 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -114,6 +114,7 @@ typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; typedef struct TCGCPUOps TCGCPUOps; typedef struct TCGHelperInfo TCGHelperInfo; +typedef struct TCGTBCPUState TCGTBCPUState; typedef struct TaskState TaskState; typedef struct TranslationBlock TranslationBlock; typedef struct VirtIODevice VirtIODevice; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c21c5d202d..a48df5f291 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -385,9 +385,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; =20 /* * By definition we've just finished a TB, so I/O is OK. @@ -397,20 +394,21 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) * The next TB, if we chain to it, will clear the flag again. */ cpu->neg.can_do_io =3D true; - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 - cflags =3D curr_cflags(cpu); - if (check_for_breakpoints(cpu, pc, &cflags)) { + TCGTBCPUState s =3D get_tb_cpu_state(cpu); + uint32_t cflags =3D curr_cflags(cpu); + + if (check_for_breakpoints(cpu, s.pc, &cflags)) { cpu_loop_exit(cpu); } =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.flags2, s.flags, cflags); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } =20 if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { - log_cpu_exec(pc, cpu, tb); + log_cpu_exec(s.pc, cpu, tb); } =20 return tb->tc.ptr; @@ -560,11 +558,7 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu) =20 void cpu_exec_step_atomic(CPUState *cpu) { - CPUArchState *env =3D cpu_env(cpu); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; int tb_exit; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { @@ -573,9 +567,9 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running =3D true; =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + TCGTBCPUState s =3D get_tb_cpu_state(cpu); + uint32_t cflags =3D curr_cflags(cpu); =20 - cflags =3D curr_cflags(cpu); /* Execute in a serial context. */ cflags &=3D ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ @@ -587,16 +581,16 @@ void cpu_exec_step_atomic(CPUState *cpu) * Any breakpoint for this insn will have been recognized earlier. */ =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.flags2, s.flags, cflags); if (tb =3D=3D NULL) { mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_gen_code(cpu, s.pc, s.flags2, s.flags, cflags); mmap_unlock(); } =20 cpu_exec_enter(cpu); /* execute the generated code */ - trace_exec_tb(tb, pc); + trace_exec_tb(tb, s.pc); cpu_tb_exec(cpu, tb, &tb_exit); cpu_exec_exit(cpu); } else { @@ -941,11 +935,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; - - cpu_get_tb_cpu_state(cpu_env(cpu), &pc, &cs_base, &flags); + TCGTBCPUState s =3D get_tb_cpu_state(cpu); + uint32_t cflags =3D cpu->cflags_next_tb; =20 /* * When requested, use an exact setting for cflags for the next @@ -954,33 +945,32 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) * have CF_INVALID set, -1 is a convenient invalid value that * does not require tcg headers for cpu_common_reset. */ - cflags =3D cpu->cflags_next_tb; if (cflags =3D=3D -1) { cflags =3D curr_cflags(cpu); } else { cpu->cflags_next_tb =3D -1; } =20 - if (check_for_breakpoints(cpu, pc, &cflags)) { + if (check_for_breakpoints(cpu, s.pc, &cflags)) { break; } =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.flags2, s.flags, cflags); if (tb =3D=3D NULL) { CPUJumpCache *jc; uint32_t h; =20 mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_gen_code(cpu, s.pc, s.flags2, s.flags, cflags); mmap_unlock(); =20 /* * We add the TB in the virtual pc hash table * for the fast lookup */ - h =3D tb_jmp_cache_hash_func(pc); + h =3D tb_jmp_cache_hash_func(s.pc); jc =3D cpu->tb_jmp_cache; - jc->array[h].pc =3D pc; + jc->array[h].pc =3D s.pc; qatomic_set(&jc->array[h].tb, tb); } =20 @@ -1000,7 +990,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) tb_add_jump(last_tb, tb_exit, tb); } =20 - cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit); + cpu_loop_exec_tb(cpu, tb, s.pc, &last_tb, &tb_exit); =20 /* Try to align the host and virtual clocks if the guest is in advance */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 31c7f9927f..759ae77559 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -590,13 +590,9 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t reta= ddr) /* The exception probably happened in a helper. The CPU state sho= uld have been saved before calling it. Fetch the PC from there. */ CPUArchState *env =3D cpu_env(cpu); - vaddr pc; - uint64_t cs_base; - tb_page_addr_t addr; - uint32_t flags; + TCGTBCPUState s =3D get_tb_cpu_state(cpu); + tb_page_addr_t addr =3D get_page_addr_code(env, s.pc); =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - addr =3D get_page_addr_code(env, pc); if (addr !=3D -1) { tb_invalidate_phys_range(cpu, addr, addr); } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index d1fddef1f4..6efaa71543 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -41,15 +41,16 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 -void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; + CPUAlphaState *env =3D cpu_env(cs); + uint32_t flags =3D env->flags & ENV_FLAG_TB_MASK; + #ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |=3D TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void alpha_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/arm/helper.c b/target/arm/helper.c index 98adeb7086..aa887af50f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11453,21 +11453,22 @@ static bool mve_no_pred(CPUARMState *env) return true; } =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUARMState *env =3D cpu_env(cs); CPUARMTBFlags flags; + vaddr pc; =20 assert_hflags_rebuild_correctly(env); flags =3D env->hflags; =20 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { - *pc =3D env->pc; + pc =3D env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { DP_TBFLAG_A64(flags, BTYPE, env->btype); } } else { - *pc =3D env->regs[15]; + pc =3D env->regs[15]; =20 if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY) && @@ -11529,8 +11530,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, vaddr = *pc, DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } =20 - *pflags =3D flags.flags; - *cs_base =3D flags.flags2; + return (TCGTBCPUState){ + .pc =3D pc, + .flags =3D flags.flags, + .flags2 =3D flags.flags2, + }; } =20 #ifdef TARGET_AARCH64 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index fac8954c39..88a4b970df 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,14 +54,11 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 -void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUAVRState *env =3D cpu_env(cs); uint32_t flags =3D 0; =20 - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - if (env->fullacc) { flags |=3D TB_FLAGS_FULL_ACCESS; } @@ -69,7 +66,7 @@ void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, flags |=3D TB_FLAGS_SKIP; } =20 - *pflags =3D flags; + return (TCGTBCPUState){ .pc =3D env->pc_w * 2, .flags =3D flags }; } =20 static void avr_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index e1a93ce24f..08c9aef55e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -255,19 +255,20 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 -void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHexagonState *env =3D cpu_env(cs); + vaddr pc =3D env->gpr[HEX_REG_PC]; uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + + if (pc =3D=3D env->gpr[HEX_REG_SA0]) { hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); } - *flags =3D hex_flags; - if (*pc & PCALIGN_MASK) { + if (pc & PCALIGN_MASK) { hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); } + + return (TCGTBCPUState){ .pc =3D pc, .flags =3D hex_flags }; } =20 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 24ca2d7175..7270b0a2a7 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -51,11 +51,12 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) env->iaoq_f & -4); } =20 -void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *pcsbase, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHPPAState *env =3D cpu_env(cs); uint32_t flags =3D 0; uint64_t cs_base =3D 0; + vaddr pc; =20 /* * TB lookup assumes that PC contains the complete virtual address. @@ -63,7 +64,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, * incomplete virtual address. This also means that we must separate * out current cpu privilege from the low bits of IAOQ_F. */ - *pc =3D hppa_cpu_get_pc(env_cpu(env)); + pc =3D hppa_cpu_get_pc(env_cpu(env)); flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; =20 /* @@ -99,8 +100,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, } #endif =20 - *pcsbase =3D cs_base; - *pflags =3D flags; + return (TCGTBCPUState){ .pc =3D pc, .flags =3D flags, .flags2 =3D cs_b= ase }; } =20 static void hppa_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index cf9ce70139..950b3bfa76 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -48,18 +48,23 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 -void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *flags =3D env->hflags | + CPUX86State *env =3D cpu_env(cs); + uint32_t flags, cs_base; + vaddr pc; + + flags =3D env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); if (env->hflags & HF_CS64_MASK) { - *cs_base =3D 0; - *pc =3D env->eip; + cs_base =3D 0; + pc =3D env->eip; } else { - *cs_base =3D env->segs[R_CS].base; - *pc =3D (uint32_t)(*cs_base + env->eip); + cs_base =3D env->segs[R_CS].base; + pc =3D (uint32_t)(cs_base + env->eip); } + + return (TCGTBCPUState){ .pc =3D pc, .flags =3D flags, .flags2 =3D cs_b= ase }; } =20 static void x86_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index db66a6bdeb..1691fe1d9f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,16 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs= , int interrupt_request) } #endif =20 -void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; + CPULoongArchState *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FP= E; + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SX= E; + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_A= SXE; + flags |=3D is_va32(env) * HW_FLAGS_VA32; + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 0fc3ed316d..1786d9e0ce 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -39,20 +39,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + CPUM68KState *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + flags |=3D TB_FLAGS_MSR_S; + flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; + flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; } if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; + flags |=3D TB_FLAGS_TRACE; } + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void m68k_restore_state_to_opc(CPUState *cs, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index a91844e4bf..91e77a4e53 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -95,12 +95,15 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); + CPUMBState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MAS= K), + .flags2 =3D (env->iflags & IMM_FLAG ? env->imm : 0), + }; } =20 static void mb_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 066dadc71b..c514202fbc 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,13 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifun= c) return mips_env_mmu_index(cpu_env(cs)); } =20 -void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); + CPUMIPSState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->active_tc.PC, + .flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR), + }; } =20 static const TCGCPUOps mips_tcg_ops =3D { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cfb3f62663..6b31f9c80e 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,14 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); + CPUOpenRISCState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D ((env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE))), + }; } =20 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 8d248bcbb9..ccaf2b0343 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -256,9 +256,9 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUPPCState *env =3D cpu_env(cs); uint32_t hflags_current =3D env->hflags; =20 #ifdef CONFIG_DEBUG_TCG @@ -270,9 +270,7 @@ void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, } #endif =20 - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D hflags_current; + return (TCGTBCPUState){ .pc =3D env->nip, .flags =3D hflags_current }; } =20 void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f2cacef5e5..461b8c97b4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -98,17 +98,14 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetc= h) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPURISCVState *env =3D cpu_env(cs); RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); =20 - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - if (cpu->cfg.ext_zve32x) { /* * If env->vl equals to VLMAX, we can use generic vector operation @@ -192,7 +189,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 - *pflags =3D flags; + return (TCGTBCPUState){ + .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, + .flags =3D flags + }; } =20 static void riscv_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index f22737865e..b8bba1a0c7 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,13 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); + CPURXState *env =3D cpu_env(cs); + uint32_t flags =3D 0; + + flags =3D FIELD_DP32(flags, PSW, PM, env->psw_pm); + flags =3D FIELD_DP32(flags, PSW, U, env->psw_u); + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void rx_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 3ca3f880a7..127574c085 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,9 +309,9 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetc= h) return s390x_env_mmu_index(cpu_env(cs), ifetch); } =20 -void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUS390XState *env =3D cpu_env(cs); uint32_t flags; =20 if (env->psw.addr & 1) { @@ -323,9 +323,6 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); } =20 - *pc =3D env->psw.addr; - *cs_base =3D env->ex_value; - flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; if (env->psw.mask & PSW_MASK_PER) { flags |=3D env->cregs[9] & (FLAG_MASK_PER_BRANCH | @@ -342,7 +339,12 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *p= c, if (env->cregs[0] & CR0_VECTOR) { flags |=3D FLAG_MASK_VECTOR; } - *pflags =3D flags; + + return (TCGTBCPUState){ + .pc =3D env->psw.addr, + .flags =3D flags, + .flags2 =3D env->ex_value + }; } =20 static const TCGCPUOps s390_tcg_ops =3D { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index adbd59cd68..320cb8ddcc 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,19 +43,27 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags + CPUSH4State *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D env->flags | (env->fpscr & TB_FLAG_FPSCR_MASK) | (env->sr & TB_FLAG_SR_MASK) | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ #ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |=3D TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, +#ifdef CONFIG_USER_ONLY + /* For a gUSA region, notice the end of the region. */ + .flags2 =3D flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0, +#endif + }; } =20 static void superh_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 5a1f5b7915..77591e84ba 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -716,13 +716,11 @@ static void sparc_cpu_synchronize_from_tb(CPUState *c= s, cpu->env.npc =3D tb->cs_base; } =20 -void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t flags; - *pc =3D env->pc; - *cs_base =3D env->npc; - flags =3D cpu_mmu_index(env_cpu(env), false); + CPUSPARCState *env =3D cpu_env(cs); + uint32_t flags =3D cpu_mmu_index(cs, false); + #ifndef CONFIG_USER_ONLY if (cpu_supervisor_mode(env)) { flags |=3D TB_FLAG_SUPER; @@ -751,7 +749,12 @@ void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *p= c, } #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_SPARC64 */ - *pflags =3D flags; + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, + .flags2 =3D env->npc, + }; } =20 static void sparc_restore_state_to_opc(CPUState *cs, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8538066114..fdc2012d16 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -45,16 +45,14 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 -void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; + CPUTriCoreState *env =3D cpu_env(cs); =20 - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; + return (TCGTBCPUState){ + .pc =3D env->PC, + .flags =3D FIELD_DP32(0, TB_FLAGS, PRIV, extract32(env->PSW, 10, 2= )), + }; } =20 static void tricore_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index fe974e90f7..4a8de9f42c 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -55,15 +55,15 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); + CPUXtensaState *env =3D cpu_env(cs); + uint32_t flags =3D 0; + target_ulong cs_base =3D 0; + + flags |=3D xtensa_get_ring(env); if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; + flags |=3D XTENSA_TBFLAG_EXCM; } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { target_ulong lend_dist =3D env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); @@ -85,26 +85,26 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *p= c, if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; =20 - *cs_base =3D lend_dist; + cs_base =3D lend_dist; if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; } } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; + flags |=3D XTENSA_TBFLAG_LITBASE; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; + flags |=3D XTENSA_TBFLAG_DEBUG; } if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; + flags |=3D XTENSA_TBFLAG_ICOUNT; } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { @@ -112,15 +112,17 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr = *pc, (env->sregs[WINDOW_BASE] + 1); uint32_t w =3D ctz32(windowstart | 0x8); =20 - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; } if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; + flags |=3D XTENSA_TBFLAG_YIELD; } + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags, .flags2 =3D= cs_base }; } =20 static void xtensa_restore_state_to_opc(CPUState *cs, --=20 2.43.0