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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25912fb9sm8469976b3a.34.2025.04.28.13.10.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 13:10:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745871031; x=1746475831; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kb64jDbydlHs1gsAgmEL7amkIFYp+vQ2o3FW/Pq/bbI=; b=qSB1W+cJbxTJgPYztAd5jYORuoquCStrrLA9aBuWSu7Jnt2QfBfyjKDg+ADg10fVzs SPqE5BxIK+Fayh5qUL/BciXvGB3nCMhQlm9++B3dGB2bBwTvQlOGcfMijPecBMmZ97It 8oz4lPABuah0R2J2sKCdoBkJ4HDDZOAJ6YLDxd8XYH0UN6Q5vt9H1OgbKzMOJNhO9JHl C61Kvqw/d6ztu/QeJQHt0Z+ke1RBWIEepmGVE9Ubms3TUqZcGD1tw/ljLx6/dZIBb9nR IPPX9/VLNi/f/Aukn8wtZJFpUC49TPx6M7yqkoaYmE0Ke9595uHN8Oqo/2594Fxrsu6d LQCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745871031; x=1746475831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kb64jDbydlHs1gsAgmEL7amkIFYp+vQ2o3FW/Pq/bbI=; b=HG7Hijd/sJmjIyTp8PG9jAoGZQgADuaaieVmChViDMNLgJohN04A8pCR4uDi8/4U6r Tah5jVcncHQ7T9kPtDyHJc+htIFR5JVK6l3ZoSuM4K167Y+KXWk92q0IQbGHnUeQls7g nPcRc0EY75XGs/xCtqvf8jVi6cJkLqR1CSoIFdyWJ4+sbJZ8DjzSzYDTTSRV1AH+qjWJ tq6aS6+SCnp9OjtShz/azpgtMtVuxCF/HZ3X7TWLiDXiQAWM1gIGt/8q0cODATdOw3+x opdqQEQlCprTtQyryoSBWO/QtcEChmWyWmqPYkKAKxhq9kscklyTdL0PNYiQGRJgenZr m3YQ== X-Gm-Message-State: AOJu0YwooDY8nHABBuSSOqOuW8uv2Ze78XIg/IfSmXjYwL0cr2KWbOQr E6b8q4XBM8UeyeCQfuhDMyCWQuYsqqlg5AEzQmBy8CkWpqvz1dD17eWKTshe/4MUs7LNy/782Ug 4 X-Gm-Gg: ASbGncvyjQ6+9iIMy5IbtrHoJwSg5RXdIyRsEOx8rZTihSQkDlvtIpjsE/tbZ/z/RcR aDQIPnUmL3bsB9QnDiOEj459n450m7QTeM/iR9Po3GMzOGeMT91bkpFJ4nDlUJ0Qe+BJFZzMVYV Nz4CrbATUGH+1A0D6bhaeP3FtptX6keb/ZiaNOKEPG/mDS1DwWjSgq0qzhY8O4rj8Qae7ZHlQhd 6I0FX5gqAEdeKd5IW03x4UjVVFOCwC637UaZ4SH+S9vd54EGNClThd20H0XhE3gx+bi8j67Yps6 NqaDYA6zdK9lCsnCoFxIdCJcDrvpS69bpPGaHvf5dJ9QUMWyd0xSOkM7UMfXIRq4IqWkHXBk4Hf a0/k3O4T3rA== X-Google-Smtp-Source: AGHT+IFC3b6Di07GyZpJYiaR4ZgcBN9F49kuL3KhcdXdBVv0RW4CnvPiwy0HCbVpfc5ua/qzfbgTQg== X-Received: by 2002:a05:6a00:2286:b0:739:4a93:a5db with SMTP id d2e1a72fcca58-73ff7396ad8mr12590319b3a.22.1745871030766; Mon, 28 Apr 2025 13:10:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 01/10] accel/tcg: Generalize fake_user_interrupt test Date: Mon, 28 Apr 2025 13:10:19 -0700 Message-ID: <20250428201028.1699157-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250428201028.1699157-1-richard.henderson@linaro.org> References: <20250428201028.1699157-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745871146396019100 Content-Type: text/plain; charset="utf-8" Test for the hook being present instead of ifdef TARGET_I386. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- accel/tcg/cpu-exec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 279df5fae7..8ff4a34509 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -732,10 +732,10 @@ static inline bool cpu_handle_exception(CPUState *cpu= , int *ret) * If user mode only, we simulate a fake exception which will be * handled outside the cpu execution loop. */ -#if defined(TARGET_I386) const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; - tcg_ops->fake_user_interrupt(cpu); -#endif /* TARGET_I386 */ + if (tcg_ops->fake_user_interrupt) { + tcg_ops->fake_user_interrupt(cpu); + } *ret =3D cpu->exception_index; cpu->exception_index =3D -1; return true; --=20 2.43.0 From nobody Sat Nov 15 23:38:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745871102; cv=none; d=zohomail.com; s=zohoarc; b=AbpZv0geNAKbET45h7oQp+wOBRMf5rigA/hBhJ+OnTAf/n5D6NFJ/qyarYvnq3rT7/6EhTu1ZYijQkpDFRum4HfGfVE5tF82rh2Ag4oBcn4TA42eRDrZeTjufbgJo4meScgAi0SWfof1XyZY44P7ewiI/p/hESlJaQ7idwf9NZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745871102; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+okpcsP7PofS8VGlGl/0oZrZuuqV6z9iH9yWhQVjc+I=; b=feFNV3R49Q4JuCulo0ukVa6U+D2XLyjBxfbJkCEaG8qB4NRPet26xbtXBGYfwhoMCQZLG06SvvyI9It4mhCO+Dr8iZfCXo2xdNlGpBsdHc9FG8IMGclLZkrQ/wtnrgsxmL2v3NQXrmJi+jdDahwmvQUu87X4CUToiS4izYUK4FU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745871102047787.4381301512535; Mon, 28 Apr 2025 13:11:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9UoJ-00058v-Fd; Mon, 28 Apr 2025 16:10:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9UoF-00057j-Uc for qemu-devel@nongnu.org; Mon, 28 Apr 2025 16:10:35 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9UoD-0000bp-7V for qemu-devel@nongnu.org; Mon, 28 Apr 2025 16:10:35 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-7376e311086so7052598b3a.3 for ; Mon, 28 Apr 2025 13:10:32 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25912fb9sm8469976b3a.34.2025.04.28.13.10.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 13:10:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745871031; x=1746475831; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+okpcsP7PofS8VGlGl/0oZrZuuqV6z9iH9yWhQVjc+I=; b=e4kQ8zHgbQCKlOgkpzSXikMFaAgY5ANYFCuAw9FzfyLygERxRs/ZXy9geXIGhdqy/r iSlESQt1szM3+sKVy+3CnvGR1T6M0XIW7kS9EZO3+VtlguSt3qY96DtSR7TabPLyYOa2 BxWKcd94NEMQ3yW+EwepEunkIhvd0/SXUyMyNtoAg+hhI9W9riaLsy0FQ8PfwRoRAl4G 6zeHyMbR6bvca65Z4gp32SuxtjXEYcjzmNV1cTGof0igkg9mcPJgqzmy+ODnU1tAerVV GbKnR4R5gCGCg+mGtvRhq1nK0n/X0iKDq3ptddjdMoZZt8eYkuuts35/0g5eD2A+TpFv eQaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745871031; x=1746475831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+okpcsP7PofS8VGlGl/0oZrZuuqV6z9iH9yWhQVjc+I=; b=WwopLKrMNuRqEf7gU4whE5KiSvi+8HBS9ThBhlHqQusH7voLkSG5S8P+RQFLeWQvil xyhttgFZDJ4iVBbnpTP4xvJP+W3kXnJiT7UHRzFbR8UtT1vXobjN178NxnFvAST00NAG MzXMbGFRmn9WkyRS4rgEpjUhowp5Cc9XGWjKtHne1oQHQbs2Qy7gVF/pIioMzpUPsHqi jBWq2c5hYOPU6IKVbWc8DJyQtnGojW+YlMfrjl3/cgLcgcXmBZKiS5AGqUFCz791QCdT ToGhNAUJNTjLhZwYhelpMEfNnW0G8OofAaNgb2aLkeqPwq/U1D7DHAv0SULFF9qHzdEd RuFA== X-Gm-Message-State: AOJu0YzjszhuFF5FOTWCNn8/AhxQ1K/HMtv8HefaJ2T8Ha6btRhaF/Hk TZAzZov+pMROYsTu9JB3T7cov6o/O8N6rraEmHIwc9ixqBiXPv11UtYNTVDBTPUvO5Z6puIN+6N w X-Gm-Gg: ASbGncu8jkvkEH+kZZWXPUpHCxvFympCK9b40l1HbgffBC8iZHrMykQblEOJ8ceknXt c5RdXCmFK541FNHu68FVKd+tCSXA2WnLwbc8Wj5UMgwBIFOoyvqZ+32Rr54jCOoythJ3JdN2hGG RAQ8ZJrnaLiVa4AapirK8rKWm7QPKKPukh8Ol3ajviFBkqqobHXMHQB+QiYTQkhJax9+iImAPxq ZEV9MY/EvAoGO7BOjOsWP+oP+7S5B1oJ2efhsSkkNRG6Uh7ccanp4Fn0PyG+YG6MzlI9HDMiEO1 rE+NsX7WyRETBr7imcST1JpLa6y0g97ECkZsMFXjzAUBaOtF83EMxFrnj5Al4iLU3GvwJhFDqPV kKXjsbm1WwA== X-Google-Smtp-Source: AGHT+IHtSy1ue2ckAU4b2UfUXMPvmhZtqmdIRhHY4UIVZkMGQe9ANWmxeGTrloH0RH8h3XCdck2K6w== X-Received: by 2002:a05:6a20:e608:b0:1f5:8655:3287 with SMTP id adf61e73a8af0-2093e528f9bmr1407691637.40.1745871031343; Mon, 28 Apr 2025 13:10:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 02/10] accel/tcg: Unconditionally use CPU_DUMP_CCOP in log_cpu_exec Date: Mon, 28 Apr 2025 13:10:20 -0700 Message-ID: <20250428201028.1699157-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250428201028.1699157-1-richard.henderson@linaro.org> References: <20250428201028.1699157-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745871105348019000 Content-Type: text/plain; charset="utf-8" This flag is only tested by target/i386, so including this makes no functional change. This is similar to other places like cpu-target.c which use CPU_DUMP_CCOP unconditionally. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- We could just as easily remove CPU_DUMP_CCOP entirely, and let target/i386 dump CCOP along with general regs like other targets. --- accel/tcg/cpu-exec.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8ff4a34509..ff979a2c57 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -285,14 +285,11 @@ static void log_cpu_exec(vaddr pc, CPUState *cpu, if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { - int flags =3D 0; + int flags =3D CPU_DUMP_CCOP; =20 if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) { flags |=3D CPU_DUMP_FPU; } -#if defined(TARGET_I386) - flags |=3D CPU_DUMP_CCOP; -#endif if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) { flags |=3D CPU_DUMP_VPU; } --=20 2.43.0 From nobody Sat Nov 15 23:38:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745871090; cv=none; d=zohomail.com; s=zohoarc; b=TrzoIE8iHXQlYDOoiL3W/2T5K9hNhlEhAzyN/VBmZopgYWzyWUH104bGZo32zZ8qKPjgxL3byCfMNN3cU0ASo9tcLFM8fNXiv2BAjCPsRzcbgrGJtLPTqAi5p8OKYO6rMDzbHVwXbsXHBJjAps9CFzmqMeqyFKWbMZiHFqiElh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745871090; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BKPsJ6ZVAGJ0+GPlTFL3NdqK+t0dmAFv9HFtSqvjns0=; b=n/wLFqPn9oXZIwW4UdjCr5tzqRItRA/R9y/dAMZ/50DYPt4BbsCGHFs/X4Hw5b5Lk/TKodTo4eoaszejJ21NLBqobREiPX5RRhCOPG92ZJ2CwBd3YYdjsAYKEHwc9JHMFRyxVYgc07VIEPCbtu5qlAn34dOC+V4rMWhXVRpEwf8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745871090430113.27648496889981; Mon, 28 Apr 2025 13:11:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9UoJ-00058x-OR; Mon, 28 Apr 2025 16:10:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9UoG-00057w-FI for qemu-devel@nongnu.org; Mon, 28 Apr 2025 16:10:36 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9UoD-0000c5-VA for qemu-devel@nongnu.org; Mon, 28 Apr 2025 16:10:36 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-736c1cf75e4so4555123b3a.2 for ; Mon, 28 Apr 2025 13:10:33 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25912fb9sm8469976b3a.34.2025.04.28.13.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 13:10:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745871032; x=1746475832; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BKPsJ6ZVAGJ0+GPlTFL3NdqK+t0dmAFv9HFtSqvjns0=; b=uoVWWgogb+h/IyMOmggk9+2uP8/ENnZt8DXg3hChhJZOUD1I9YzI7L50t8OiKJoBTJ YivWsq4SHEb204qy76yQ5j19OAAB3fQL8n4rAbZevMVAympvT8/SaihratgEmve+6nSn I7KX0ZfVvL04glMJUg6AjBcj6ISR4XeIcFiDbafRSX2Rc7lJqSqpw0068lIOrvSkBcYn OBrUM4cPDRh2qejyp3U5VJ4577P1JScowb3+aGs1QYfEsjp60ckDf3hldKsyyPDSN7go PYcaQveoiujzjA4yTbR/RLv+XJAVSx3IdGGeQt7RG+rKA07wnvLENrnl3bLiX3RrhMAu aGbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745871032; x=1746475832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BKPsJ6ZVAGJ0+GPlTFL3NdqK+t0dmAFv9HFtSqvjns0=; b=ByLWNLSMrDN6sdf9WfaG9Fj4NAML4joKsxL3Xg8CDT786uXM3M+QHc6qoo52KBjlPU eUlyPzQ5vXAqQtFoKLxgCc/pwr9ADsYfXzKb7iLKJZO/L4m7P6eufpQWzOCqqWU009i4 MsKRpbH+eiQbUyVS1vKmJVXltAVckQUXCpigJKFxdF7N62DKZ0Dk9LQq8X0RhgONyN0J VpKhf1RiGZmtArOaW2fAZa6bwSRrFe8xRMfmH/O48/pI4oCvknJdE0ruvD0Vs+JAhsEV djWG/mIp51h/jgXuFv6hwMAOtNrNs0QweiwqJDurRmWLGLbGEfQymzI5gr83dErNJQDJ 94/g== X-Gm-Message-State: AOJu0YxZH/g4CpNdGV2U9ZY6nigpz/vZ2kIpPuCRHObhoKoZuw7G4Lj6 SzWWYQpHJcWQjI0gPIgiE8mK4JQZF29GKEZ0EBx/Pr/t+qX9iA8PLeZDQ2sODTVxJBYBURcoNGa F X-Gm-Gg: ASbGnctWWPbp8RTEfmDxkjtW3ySbieauQSjm2oNB3uTDlYUF6UwMsov2I8OYE5bwyBg 3xIoRgVVg7Lx9w6cJOiXlLc4vhPv+cNNQeZvXTtUyIPb8G+SFmWPEx+7kQCK1ZLFV8DG8KU7620 kbtLIDy/ljFlY0jd8EicfMnQ+C3CdPkq338kg3YGU4qkSwgYxHQgMTfEsUaLxrhIIwEJOl9gaLl gO33ylsa+O2jEjjN21jL27P76rY+L3bCChI392frqc+ydwuoeOmsV6r5aROS54uFi1b+yUAtYav kiu5iQwtW1tlaRhDEmD9IKFpYPh4knUqZ9DXMMgr44FsMNuqFzHUcxERikbPZ/bic76NrrPLK34 ytQKP1A38Iw== X-Google-Smtp-Source: AGHT+IHHuvzMm58ilZ3anBiZRcwXRzARoFElFXq/gGMZMIVJSWlEUYrbLg0RTFbFgdwahsUE5zN50w== X-Received: by 2002:a05:6a00:39a0:b0:736:2a73:675b with SMTP id d2e1a72fcca58-740271e1d3amr1605147b3a.19.1745871031974; Mon, 28 Apr 2025 13:10:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 03/10] accel/tcg: Introduce TCGCPUOps.cpu_exec_reset Date: Mon, 28 Apr 2025 13:10:21 -0700 Message-ID: <20250428201028.1699157-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250428201028.1699157-1-richard.henderson@linaro.org> References: <20250428201028.1699157-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745871095863019000 Content-Type: text/plain; charset="utf-8" Initialize all instances with cpu_reset(), so that there is no functional change. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/accel/tcg/cpu-ops.h | 2 ++ accel/tcg/cpu-exec.c | 3 ++- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 21 files changed, 23 insertions(+), 1 deletion(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 60b5e97205..3ff72b8d9d 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -155,6 +155,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @cpu_exec_reset: Callback for reset in cpu_exec. */ + void (*cpu_exec_reset)(CPUState *cpu); /** * @cpu_exec_halt: Callback for handling halt in cpu_exec. * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ff979a2c57..010f38edaa 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -834,7 +834,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, #else else if (interrupt_request & CPU_INTERRUPT_RESET) { replay_interrupt(); - cpu_reset(cpu); + cpu->cc->tcg_ops->cpu_exec_reset(cpu); bql_unlock(); return true; } @@ -1070,6 +1070,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) #ifndef CONFIG_USER_ONLY assert(tcg_ops->cpu_exec_halt); assert(tcg_ops->cpu_exec_interrupt); + assert(tcg_ops->cpu_exec_reset); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); assert(tcg_ops->mmu_index); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index cb3f382dc6..9dc1c7242b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -251,6 +251,7 @@ static const TCGCPUOps alpha_tcg_ops =3D { .tlb_fill =3D alpha_cpu_tlb_fill, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .cpu_exec_halt =3D alpha_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D alpha_cpu_do_interrupt, .do_transaction_failed =3D alpha_cpu_do_transaction_failed, .do_unaligned_access =3D alpha_cpu_do_unaligned_access, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e149a46250..9e74d7bc07 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2688,6 +2688,7 @@ static const TCGCPUOps arm_tcg_ops =3D { .tlb_fill_align =3D arm_cpu_tlb_fill_align, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .cpu_exec_halt =3D arm_cpu_exec_halt, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index f71560aa43..57ed3f3a06 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -250,6 +250,7 @@ static const TCGCPUOps arm_v7m_tcg_ops =3D { .tlb_fill_align =3D arm_cpu_tlb_fill_align, .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .cpu_exec_halt =3D arm_cpu_exec_halt, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, .do_unaligned_access =3D arm_cpu_do_unaligned_access, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 86e53ef9f6..e50ebfd8f8 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -232,6 +232,7 @@ static const TCGCPUOps avr_tcg_ops =3D { .mmu_index =3D avr_cpu_mmu_index, .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, .cpu_exec_halt =3D avr_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .tlb_fill =3D avr_cpu_tlb_fill, .do_interrupt =3D avr_cpu_do_interrupt, }; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6acbf3de27..300c6b809f 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -271,6 +271,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { .tlb_fill_align =3D hppa_cpu_tlb_fill_align, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .cpu_exec_halt =3D hppa_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D hppa_cpu_do_interrupt, .do_unaligned_access =3D hppa_cpu_do_unaligned_access, .do_transaction_failed =3D hppa_cpu_do_transaction_failed, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d441c0752e..63ddf87aa8 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -147,6 +147,7 @@ const TCGCPUOps x86_tcg_ops =3D { .do_interrupt =3D x86_cpu_do_interrupt, .cpu_exec_halt =3D x86_cpu_exec_halt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, + .cpu_exec_reset =3D cpu_reset, .do_unaligned_access =3D x86_cpu_do_unaligned_access, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 1fb6633581..3cb7aa6039 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -877,6 +877,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { .tlb_fill =3D loongarch_cpu_tlb_fill, .cpu_exec_interrupt =3D loongarch_cpu_exec_interrupt, .cpu_exec_halt =3D loongarch_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D loongarch_cpu_do_interrupt, .do_transaction_failed =3D loongarch_cpu_do_transaction_failed, #endif diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 99adc5eb91..c8c1dbeac9 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -602,6 +602,7 @@ static const TCGCPUOps m68k_tcg_ops =3D { .tlb_fill =3D m68k_cpu_tlb_fill, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .cpu_exec_halt =3D m68k_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D m68k_cpu_do_interrupt, .do_transaction_failed =3D m68k_cpu_transaction_failed, #endif /* !CONFIG_USER_ONLY */ diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 658d3cb3d7..6b14377819 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -440,6 +440,7 @@ static const TCGCPUOps mb_tcg_ops =3D { .tlb_fill =3D mb_cpu_tlb_fill, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .cpu_exec_halt =3D mb_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D mb_cpu_do_interrupt, .do_transaction_failed =3D mb_cpu_transaction_failed, .do_unaligned_access =3D mb_cpu_do_unaligned_access, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 26f4f038cd..9f6441d7af 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -563,6 +563,7 @@ static const TCGCPUOps mips_tcg_ops =3D { .tlb_fill =3D mips_cpu_tlb_fill, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .cpu_exec_halt =3D mips_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D mips_cpu_do_interrupt, .do_transaction_failed =3D mips_cpu_do_transaction_failed, .do_unaligned_access =3D mips_cpu_do_unaligned_access, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index d3c366dd86..ffdc011a44 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -255,6 +255,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { .tlb_fill =3D openrisc_cpu_tlb_fill, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .cpu_exec_halt =3D openrisc_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D openrisc_cpu_do_interrupt, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index fde7d71fc6..5981f607d2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7492,6 +7492,7 @@ static const TCGCPUOps ppc_tcg_ops =3D { .tlb_fill =3D ppc_cpu_tlb_fill, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .cpu_exec_halt =3D ppc_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, .cpu_exec_exit =3D ppc_cpu_exec_exit, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 916fd6fb43..e3e7fea66a 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -153,6 +153,7 @@ const TCGCPUOps riscv_tcg_ops =3D { .tlb_fill =3D riscv_cpu_tlb_fill, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .cpu_exec_halt =3D riscv_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 0a7a2b55b5..c9615f0655 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -217,6 +217,7 @@ static const TCGCPUOps rx_tcg_ops =3D { =20 .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, .cpu_exec_halt =3D rx_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D rx_cpu_do_interrupt, }; =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index e3623ad32a..f4289f9857 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -365,6 +365,7 @@ static const TCGCPUOps s390_tcg_ops =3D { .tlb_fill =3D s390_cpu_tlb_fill, .cpu_exec_interrupt =3D s390_cpu_exec_interrupt, .cpu_exec_halt =3D s390_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D s390_cpu_do_interrupt, .debug_excp_handler =3D s390x_cpu_debug_excp_handler, .do_unaligned_access =3D s390x_cpu_do_unaligned_access, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 0a04f149d7..2cafb56a23 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -275,6 +275,7 @@ static const TCGCPUOps superh_tcg_ops =3D { .tlb_fill =3D superh_cpu_tlb_fill, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .cpu_exec_halt =3D superh_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D superh_cpu_do_interrupt, .do_unaligned_access =3D superh_cpu_do_unaligned_access, .io_recompile_replay_branch =3D superh_io_recompile_replay_branch, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index c864217175..5a1f5b7915 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1034,6 +1034,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { .tlb_fill =3D sparc_cpu_tlb_fill, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .cpu_exec_halt =3D sparc_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D sparc_cpu_do_interrupt, .do_transaction_failed =3D sparc_cpu_do_transaction_failed, .do_unaligned_access =3D sparc_cpu_do_unaligned_access, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index bdbcaf0dfc..36c82888e8 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -182,6 +182,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .tlb_fill =3D tricore_cpu_tlb_fill, .cpu_exec_interrupt =3D tricore_cpu_exec_interrupt, .cpu_exec_halt =3D tricore_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, }; =20 static void tricore_cpu_class_init(ObjectClass *c, void *data) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 971e67ad97..a13f1f950a 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -246,6 +246,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { .tlb_fill =3D xtensa_cpu_tlb_fill, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .cpu_exec_halt =3D xtensa_cpu_has_work, + .cpu_exec_reset =3D cpu_reset, .do_interrupt =3D xtensa_cpu_do_interrupt, .do_transaction_failed =3D xtensa_cpu_do_transaction_failed, .do_unaligned_access =3D xtensa_cpu_do_unaligned_access, --=20 2.43.0 From nobody Sat Nov 15 23:38:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745871114; cv=none; d=zohomail.com; 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Therefore we can handle the #if TARGET_I386 block in cpu_handle_interrupt with the new TCGCPUOps.cpu_exec_reset hook. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cpu-exec.c | 39 ++++++++++++++------------------------- target/i386/tcg/tcg-cpu.c | 11 ++++++++++- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 010f38edaa..c21c5d202d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -819,33 +819,22 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu->exception_index =3D EXCP_HLT; bql_unlock(); return true; - } -#if defined(TARGET_I386) - else if (interrupt_request & CPU_INTERRUPT_INIT) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUArchState *env =3D &x86_cpu->env; - replay_interrupt(); - cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); - do_cpu_init(x86_cpu); - cpu->exception_index =3D EXCP_HALTED; - bql_unlock(); - return true; - } -#else - else if (interrupt_request & CPU_INTERRUPT_RESET) { - replay_interrupt(); - cpu->cc->tcg_ops->cpu_exec_reset(cpu); - bql_unlock(); - return true; - } -#endif /* !TARGET_I386 */ - /* The target hook has 3 exit conditions: - False when the interrupt isn't processed, - True when it is, and we should restart on a new TB, - and via longjmp via cpu_loop_exit. */ - else { + } else { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; =20 + if (interrupt_request & CPU_INTERRUPT_RESET) { + replay_interrupt(); + tcg_ops->cpu_exec_reset(cpu); + bql_unlock(); + return true; + } + + /* + * The target hook has 3 exit conditions: + * False when the interrupt isn't processed, + * True when it is, and we should restart on a new TB, + * and via longjmp via cpu_loop_exit. + */ if (tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (!tcg_ops->need_replay_interrupt || tcg_ops->need_replay_interrupt(interrupt_request)) { diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 63ddf87aa8..0184e308e6 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -120,6 +120,15 @@ static bool x86_debug_check_breakpoint(CPUState *cs) /* RF disables all architectural breakpoints. */ return !(env->eflags & RF_MASK); } + +static void x86_cpu_exec_reset(CPUState *cs) +{ + CPUArchState *env =3D cpu_env(cs); + + cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); + do_cpu_init(env_archcpu(env)); + cs->exception_index =3D EXCP_HALTED; +} #endif =20 #include "accel/tcg/cpu-ops.h" @@ -147,7 +156,7 @@ const TCGCPUOps x86_tcg_ops =3D { .do_interrupt =3D x86_cpu_do_interrupt, .cpu_exec_halt =3D x86_cpu_exec_halt, .cpu_exec_interrupt =3D x86_cpu_exec_interrupt, - .cpu_exec_reset =3D cpu_reset, + .cpu_exec_reset =3D x86_cpu_exec_reset, .do_unaligned_access =3D x86_cpu_do_unaligned_access, .debug_excp_handler =3D breakpoint_handler, .debug_check_breakpoint =3D x86_debug_check_breakpoint, --=20 2.43.0 From nobody Sat Nov 15 23:38:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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For other targets, move the inline definition out of line. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/accel/tcg/cpu-ops.h | 3 ++ target/alpha/cpu.h | 11 ------ target/arm/cpu.h | 3 -- target/avr/cpu.h | 18 ---------- target/hexagon/cpu.h | 15 -------- target/hppa/cpu.h | 3 -- target/i386/cpu.h | 14 -------- target/loongarch/cpu.h | 12 ------- target/m68k/cpu.h | 16 --------- target/microblaze/cpu.h | 8 ----- target/mips/cpu.h | 9 ----- target/openrisc/cpu.h | 10 ------ target/ppc/cpu.h | 13 ------- target/riscv/cpu.h | 3 -- target/rx/cpu.h | 9 ----- target/s390x/cpu.h | 9 ----- target/sh4/cpu.h | 15 -------- target/sparc/cpu.h | 3 -- target/tricore/cpu.h | 12 ------- target/xtensa/cpu.h | 68 ----------------------------------- target/alpha/cpu.c | 14 ++++++-- target/arm/helper.c | 1 + target/avr/cpu.c | 21 +++++++++-- target/hexagon/cpu.c | 18 ++++++++-- target/hppa/cpu.c | 3 +- target/i386/tcg/tcg-cpu.c | 17 +++++++-- target/loongarch/cpu.c | 15 ++++++-- target/m68k/cpu.c | 19 ++++++++-- target/microblaze/cpu.c | 11 ++++-- target/mips/cpu.c | 9 +++++ target/openrisc/cpu.c | 13 +++++-- target/ppc/helper_regs.c | 16 ++++----- target/rx/cpu.c | 12 +++++-- target/s390x/cpu.c | 1 + target/sh4/cpu.c | 18 ++++++++-- target/tricore/cpu.c | 15 ++++++-- target/xtensa/cpu.c | 71 +++++++++++++++++++++++++++++++++++-- 37 files changed, 243 insertions(+), 285 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 3ff72b8d9d..f5e5746976 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -18,6 +18,9 @@ #include "exec/vaddr.h" #include "tcg/tcg-mo.h" =20 +void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags); + struct TCGCPUOps { /** * mttcg_supported: multi-threaded TCG is supported diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 849f673489..45944e46b5 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -464,17 +464,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retad= dr); #endif =20 -static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; -#ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #ifdef CONFIG_USER_ONLY /* Copied from linux ieee_swcr_to_fpcr. */ static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3705b34285..8dd7c17533 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3119,9 +3119,6 @@ static inline bool bswap_code(bool sctlr_b) #endif } =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - enum { QEMU_PSCI_CONDUIT_DISABLED =3D 0, QEMU_PSCI_CONDUIT_SMC =3D 1, diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d6666175a9..518e243d81 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -205,24 +205,6 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflag= s) -{ - uint32_t flags =3D 0; - - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - - if (env->fullacc) { - flags |=3D TB_FLAGS_FULL_ACCESS; - } - if (env->skip) { - flags |=3D TB_FLAGS_SKIP; - } - - *pflags =3D flags; -} - static inline int cpu_interrupts_enabled(CPUAVRState *env) { return env->sregI !=3D 0; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c065fa8ddc..43a854f517 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -137,21 +137,6 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagon= State *env, uint32_t exception, uintptr_t pc); =20 -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { - hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); - } - *flags =3D hex_flags; - if (*pc & PCALIGN_MASK) { - hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); - } -} - typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index acc9937240..11d59d11ca 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -351,9 +351,6 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define CS_BASE_DIFFPAGE (1 << 12) #define CS_BASE_DIFFSPACE (1 << 13) =20 -void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); void update_gva_offset_mask(CPUHPPAState *env); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 877df7de1f..a7133c65ab 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2602,20 +2602,6 @@ static inline bool is_mmu_index_32(int mmu_index) #include "hw/i386/apic.h" #endif =20 -static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *flags =3D env->hflags | - (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); - if (env->hflags & HF_CS64_MASK) { - *cs_base =3D 0; - *pc =3D env->eip; - } else { - *cs_base =3D env->segs[R_CS].base; - *pc =3D (uint32_t)(*cs_base + env->eip); - } -} - void do_cpu_init(X86CPU *cpu); =20 #define MCE_INJECT_BROADCAST 1 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 70ff56e60c..262bf87f7b 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -492,18 +492,6 @@ static inline void set_pc(CPULoongArchState *env, uint= 64_t value) #define HW_FLAGS_VA32 0x20 #define HW_FLAGS_EUEN_ASXE 0x40 =20 -static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; -} - #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU =20 void loongarch_cpu_post_init(Object *obj); diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 39d0b9d6d7..d9db6a486a 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -605,22 +605,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr = physaddr, vaddr addr, #define TB_FLAGS_TRACE 16 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) =20 -static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; - if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; - } - if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; - } -} - void dump_mmu(CPUM68KState *env); =20 #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d511f22a55..6ad8643f2e 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -419,14 +419,6 @@ static inline bool mb_cpu_is_big_endian(CPUState *cs) return !cpu->cfg.endi; } =20 -static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); -} - #if !defined(CONFIG_USER_ONLY) bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d16f9a7220..5cd4c6c818 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1366,15 +1366,6 @@ void cpu_mips_clock_init(MIPSCPU *cpu); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); =20 -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); -} - /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 569819bfb0..f4bcf00b07 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -349,16 +349,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, = int i, uint32_t val) env->shadow_gpr[0][i] =3D val; } =20 -static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3c02f7f7d4..13f4b7f8e0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2755,19 +2755,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xe= r); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) =20 -#ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); -#else -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D env->hflags; -} -#endif - G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exceptio= n, uint32_t error_code, uintptr_t radd= r); =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 167909c89b..c66ac3bc27 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -802,9 +802,6 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, u= int32_t vsew, return vlen >> (vsew + 3 - lmul); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 5c19c83219..ba5761b647 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -153,15 +153,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, = int rte); #define RX_CPU_IRQ 0 #define RX_CPU_FIR 1 =20 -static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index ee59039879..f97d024b74 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -411,15 +411,6 @@ static inline int s390x_env_mmu_index(CPUS390XState *e= nv, bool ifetch) #endif } =20 -#ifdef CONFIG_TCG - -#include "tcg/tcg_s390x.h" - -void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - -#endif /* CONFIG_TCG */ - /* PER bits from control register 9 */ #define PER_CR9_EVENT_BRANCH 0x80000000 #define PER_CR9_EVENT_IFETCH 0x40000000 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 906f99ddf0..c41ab70dd7 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -380,19 +380,4 @@ static inline void cpu_write_sr(CPUSH4State *env, targ= et_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 -static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags - | (env->fpscr & TB_FLAG_FPSCR_MASK) - | (env->sr & TB_FLAG_SR_MASK) - | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ -#ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #endif /* SH4_CPU_H */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 83ac818933..5958f5671b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -744,9 +744,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_FSR_QNE (1 << 8) #define TB_FLAG_ASI_SHIFT 24 =20 -void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - static inline bool tb_fpu_enabled(int tb_flags) { #if defined(CONFIG_USER_ONLY) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c76e65f818..82085fbc32 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -258,18 +258,6 @@ void tricore_tcg_init(void); void tricore_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); =20 -static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; - - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; -} - #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU =20 /* helpers.c */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c03ed71c94..74122ebe15 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -733,74 +733,6 @@ static inline uint32_t xtensa_replicate_windowstart(CP= UXtensaState *env) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 =20 -static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); - if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { - target_ulong lend_dist =3D - env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); - - /* - * 0 in the csbase_lend field means that there may not be a loopba= ck - * for any instruction that starts inside this page. Any other val= ue - * means that an instruction that ends at this offset from the page - * start may loop back and will need loopback code to be generated. - * - * lend_dist is 0 when LEND points to the start of the page, but - * no instruction that starts inside this page may end at offset 0, - * so it's still correct. - * - * When an instruction ends at a page boundary it may only start in - * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE - * for the TB that contains this instruction. - */ - if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { - target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; - - *cs_base =3D lend_dist; - if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; - } - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && - (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; - } - if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && - (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { - uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> - (env->sregs[WINDOW_BASE] + 1); - uint32_t w =3D ctz32(windowstart | 0x8); - - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, - PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; - } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; - } - if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; - } -} - XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 9dc1c7242b..d1fddef1f4 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "exec/translation-block.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "fpu/softfloat.h" =20 =20 @@ -40,6 +41,17 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 +void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *pflags =3D env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void alpha_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -231,8 +243,6 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps alpha_tcg_ops =3D { /* Alpha processors have a weak memory model */ .guest_default_memory_order =3D 0, diff --git a/target/arm/helper.c b/target/arm/helper.c index 8de4eb2c1f..98adeb7086 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,6 +30,7 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG #include "accel/tcg/probe.h" +#include "accel/tcg/cpu-ops.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" diff --git a/target/avr/cpu.c b/target/avr/cpu.c index e50ebfd8f8..fac8954c39 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -27,6 +27,7 @@ #include "disas/dis-asm.h" #include "tcg/debug-assert.h" #include "hw/qdev-properties.h" +#include "accel/tcg/cpu-ops.h" =20 static void avr_cpu_set_pc(CPUState *cs, vaddr value) { @@ -53,6 +54,24 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 +void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags =3D 0; + + *pc =3D env->pc_w * 2; + *cs_base =3D 0; + + if (env->fullacc) { + flags |=3D TB_FLAGS_FULL_ACCESS; + } + if (env->skip) { + flags |=3D TB_FLAGS_SKIP; + } + + *pflags =3D flags; +} + static void avr_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -220,8 +239,6 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, }; =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps avr_tcg_ops =3D { .guest_default_memory_order =3D 0, .mttcg_supported =3D false, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 9f93c17009..e1a93ce24f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -25,6 +25,7 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" #include "exec/gdbstub.h" +#include "accel/tcg/cpu-ops.h" =20 static void hexagon_v66_cpu_init(Object *obj) { } static void hexagon_v67_cpu_init(Object *obj) { } @@ -254,6 +255,21 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 +void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t hex_flags =3D 0; + *pc =3D env->gpr[HEX_REG_PC]; + *cs_base =3D 0; + if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); + } + *flags =3D hex_flags; + if (*pc & PCALIGN_MASK) { + hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); + } +} + static void hexagon_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -321,8 +337,6 @@ static void hexagon_cpu_init(Object *obj) { } =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps hexagon_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 300c6b809f..24ca2d7175 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -29,6 +29,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg.h" #include "hw/hppa/hppa_hardware.h" +#include "accel/tcg/cpu-ops.h" =20 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { @@ -249,8 +250,6 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps hppa_tcg_ops =3D { /* PA-RISC 1.x processors have a strong memory model. */ /* diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 0184e308e6..cf9ce70139 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -24,6 +24,7 @@ #include "accel/accel-cpu-target.h" #include "exec/translation-block.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "tcg-cpu.h" =20 /* Frob eflags into and out of the CPU temporary format. */ @@ -47,6 +48,20 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 +void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *flags =3D env->hflags | + (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); + if (env->hflags & HF_CS64_MASK) { + *cs_base =3D 0; + *pc =3D env->eip; + } else { + *cs_base =3D env->segs[R_CS].base; + *pc =3D (uint32_t)(*cs_base + env->eip); + } +} + static void x86_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -131,8 +146,6 @@ static void x86_cpu_exec_reset(CPUState *cs) } #endif =20 -#include "accel/tcg/cpu-ops.h" - const TCGCPUOps x86_tcg_ops =3D { .mttcg_supported =3D true, .precise_smc =3D true, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 3cb7aa6039..db66a6bdeb 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -29,6 +29,7 @@ #endif #ifdef CONFIG_TCG #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" #endif #include "tcg/tcg_loongarch.h" @@ -335,6 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs,= int interrupt_request) } #endif =20 +void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; + *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; + *flags |=3D is_va32(env) * HW_FLAGS_VA32; +} + static void loongarch_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -861,8 +874,6 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) } =20 #ifdef CONFIG_TCG -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps loongarch_tcg_ops =3D { .guest_default_memory_order =3D 0, .mttcg_supported =3D true, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c8c1dbeac9..0fc3ed316d 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "fpu/softfloat.h" +#include "accel/tcg/cpu-ops.h" =20 static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { @@ -38,6 +39,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |=3D TB_FLAGS_MSR_S; + *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; + *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + } + if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { + *flags |=3D TB_FLAGS_TRACE; + } +} + static void m68k_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -586,8 +603,6 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { }; #endif /* !CONFIG_USER_ONLY */ =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps m68k_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6b14377819..a91844e4bf 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -31,6 +31,7 @@ #include "exec/gdbstub.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" =20 static const struct { @@ -94,6 +95,14 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); + *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); +} + static void mb_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -423,8 +432,6 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps mb_tcg_ops =3D { /* MicroBlaze is always in-order. */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 9f6441d7af..066dadc71b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,6 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) return mips_env_mmu_index(cpu_env(cs)); } =20 +void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->active_tc.PC; + *cs_base =3D 0; + *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR); +} + static const TCGCPUOps mips_tcg_ops =3D { .mttcg_supported =3D TARGET_LONG_BITS =3D=3D 32, .guest_default_memory_order =3D 0, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index ffdc011a44..cfb3f62663 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" =20 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -40,6 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); +} + static void openrisc_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -239,8 +250,6 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps openrisc_tcg_ops =3D { .guest_default_memory_order =3D 0, .mttcg_supported =3D true, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index f211bc9830..8d248bcbb9 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -27,6 +27,7 @@ #include "power8-pmu.h" #include "cpu-models.h" #include "spr_common.h" +#include "accel/tcg/cpu-ops.h" =20 /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -255,26 +256,25 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -#ifdef CONFIG_DEBUG_TCG void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { uint32_t hflags_current =3D env->hflags; - uint32_t hflags_rebuilt; =20 - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D hflags_current; - - hflags_rebuilt =3D hreg_compute_hflags_value(env); +#ifdef CONFIG_DEBUG_TCG + uint32_t hflags_rebuilt =3D hreg_compute_hflags_value(env); if (unlikely(hflags_current !=3D hflags_rebuilt)) { cpu_abort(env_cpu(env), "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", hflags_current, hflags_rebuilt); } -} #endif =20 + *pc =3D env->nip; + *cs_base =3D 0; + *flags =3D hflags_current; +} + void cpu_interrupt_exittb(CPUState *cs) { /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c9615f0655..f22737865e 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -28,6 +28,7 @@ #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" +#include "accel/tcg/cpu-ops.h" =20 static void rx_cpu_set_pc(CPUState *cs, vaddr value) { @@ -43,6 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); + *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); +} + static void rx_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -201,8 +211,6 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, }; =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps rx_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index f4289f9857..3ca3f880a7 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -302,6 +302,7 @@ static const Property s390x_cpu_properties[] =3D { =20 #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" +#include "tcg/tcg_s390x.h" =20 static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 2cafb56a23..adbd59cd68 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -26,6 +26,7 @@ #include "migration/vmstate.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" =20 static void superh_cpu_set_pc(CPUState *cs, vaddr value) @@ -42,6 +43,21 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + /* For a gUSA region, notice the end of the region. */ + *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; + *flags =3D env->flags + | (env->fpscr & TB_FLAG_FPSCR_MASK) + | (env->sr & TB_FLAG_SR_MASK) + | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void superh_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -258,8 +274,6 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps superh_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 36c82888e8..8538066114 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -23,6 +23,7 @@ #include "exec/translation-block.h" #include "qemu/error-report.h" #include "tcg/debug-assert.h" +#include "accel/tcg/cpu-ops.h" =20 static inline void set_feature(CPUTriCoreState *env, int feature) { @@ -44,6 +45,18 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 +void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t new_flags =3D 0; + *pc =3D env->PC; + *cs_base =3D 0; + + new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, + extract32(env->PSW, 10, 2)); + *flags =3D new_flags; +} + static void tricore_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -168,8 +181,6 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, }; =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps tricore_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a13f1f950a..fe974e90f7 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -35,6 +35,7 @@ #include "qemu/module.h" #include "migration/vmstate.h" #include "hw/qdev-clock.h" +#include "accel/tcg/cpu-ops.h" #ifndef CONFIG_USER_ONLY #include "system/memory.h" #endif @@ -54,6 +55,74 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 +void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D 0; + *flags |=3D xtensa_get_ring(env); + if (env->sregs[PS] & PS_EXCM) { + *flags |=3D XTENSA_TBFLAG_EXCM; + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { + target_ulong lend_dist =3D + env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); + + /* + * 0 in the csbase_lend field means that there may not be a loopba= ck + * for any instruction that starts inside this page. Any other val= ue + * means that an instruction that ends at this offset from the page + * start may loop back and will need loopback code to be generated. + * + * lend_dist is 0 when LEND points to the start of the page, but + * no instruction that starts inside this page may end at offset 0, + * so it's still correct. + * + * When an instruction ends at a page boundary it may only start in + * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE + * for the TB that contains this instruction. + */ + if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { + target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; + + *cs_base =3D lend_dist; + if (lbeg_off < 256) { + *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + } + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |=3D XTENSA_TBFLAG_LITBASE; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + *flags |=3D XTENSA_TBFLAG_DEBUG; + } + if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + *flags |=3D XTENSA_TBFLAG_ICOUNT; + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { + *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && + (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { + uint32_t windowstart =3D xtensa_replicate_windowstart(env) >> + (env->sregs[WINDOW_BASE] + 1); + uint32_t w =3D ctz32(windowstart | 0x8); + + *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; + } else { + *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + } + if (env->yield_needed) { + *flags |=3D XTENSA_TBFLAG_YIELD; + } +} + static void xtensa_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -229,8 +298,6 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { }; #endif =20 -#include "accel/tcg/cpu-ops.h" - static const TCGCPUOps xtensa_tcg_ops =3D { /* Xtensa processors have a weak memory model */ .guest_default_memory_order =3D 0, --=20 2.43.0 From nobody Sat Nov 15 23:38:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745871136; cv=none; d=zohomail.com; s=zohoarc; b=dpwamiA9cD7kpJHCg1XcWwGaI3x4ubC46KH4MZH13qSDn5djoeaHG2MkMu2XKV0c2wbT4Q4eMBSDVIrJ3J8B7utMSV9WxE2b6jSJhU9w2xRGX87vzjAFXuqN173iauYIVcGhmYKUjl6kBUjTJbaLwr1zxiPSdpTb6nEaal+eAxw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745871136; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nj/KkQHJ+XNFYfBYngAfvob8GBlvpvqFFYAf7mtabnU=; b=T5a6Fj828+etv0eNCcUEwDY5Kc9EQCbzG2rfpv2v2odDql62yATnb+EA70MGx+1GjwxnbGqtn1Bv+VW1LjRQf7K1RK/RxChJ5hTnJiKagXlbNRcQkITfXuV5EjEPxgtz4UXd4+zMWYoCKem9GnS9Pa4mv7Xrg7Oc4fYKVDaf3k8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745871136549659.0072424873097; Mon, 28 Apr 2025 13:12:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9UoM-0005A7-EX; Mon, 28 Apr 2025 16:10:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9UoI-00058j-Dz for qemu-devel@nongnu.org; Mon, 28 Apr 2025 16:10:38 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9UoG-0000cq-7F for qemu-devel@nongnu.org; Mon, 28 Apr 2025 16:10:38 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-73bf1cef6ceso5293135b3a.0 for ; Mon, 28 Apr 2025 13:10:35 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25912fb9sm8469976b3a.34.2025.04.28.13.10.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 13:10:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745871034; x=1746475834; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nj/KkQHJ+XNFYfBYngAfvob8GBlvpvqFFYAf7mtabnU=; b=L6Yjn2MVA1J9oaq3OFeHgURQor6NTB6LrHKCFj/iIYnqfu7lb4ySxkR/P+fm3+nJNq tt3g20gLFSuaDBWKRMUXtKpEQUcQoZ1nt3caYi4pRWEzxB9PPGLRh5YH4rY3DK4RBWZK hGB4ElbO90OFIMVNPZX668V/444pb34VI/Jw361SazuHMS6cfTMSV8HK+m8lkWVjLHd/ vV2+riDrN76DggmE/yu8IBloJc3bfX6JzRKGYx8r4Qn6ar7fTb0bIp+E+UazOY7XMcNc ig5vbZgn7SXx6utN+FIL2KHxwVc5z+pxWF/+TQ6KJw6SFyCFZqcpAQuwkKaMjlMnbyJi Dfnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745871034; x=1746475834; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nj/KkQHJ+XNFYfBYngAfvob8GBlvpvqFFYAf7mtabnU=; b=Xp0EiyKMliqPoqay8WfxSPRE/TS+8QMnZlvJk4rXU0wgwhNq6fQGyqQE671tYoh7AF qtDik6qU85+zgevZ6TQG7Vi46eZkwKq/uUy7RUZLzVlYZ+U1weexCfBP5qbhaCNCAlkU UvsUIMQjVrDMUcBMrzhY4Pi4MzQyi3MJw8FpMgopE7r512Jr/6Vo0whRrK7ZLhviDskn Nxzw/r1dKxp+2nG3gn6t/P/gCHWghnHGg1XqoB//dn1zLgjVQ7lyatmpyUhDeAYSdQvV mQl1Vb63vmRv0qv5mbZW2p4xdiZuLS9rYZ5JykveZhGC5JZNq2ffE+gfHsaRHlsSk+p1 LcDA== X-Gm-Message-State: AOJu0Yym+MOY93wF3qrIcToYDfzj9vOfz7XIW6Xa34RPATjom3QKw2y4 FEfz/0J/kA61vrZIEquBitxN+XDLEYyx1+/PfLWIJ117jx8IyT7yBlpw5CmMZZGV2BpY3esufpL M X-Gm-Gg: ASbGncvAoT/nOjjwSWJUobqeurXoHv/0wAwdi5Tng66hGR7cZLQg8UnYmh4NPpAPd2U ZQEpfSTIonUoSKFDHeVl7F4rd+8253NxpVLKrpdCKk+zmKUg8e2vIlfEK25t9eKh+nWYlPDC5sJ jNY2AizmVRWttQNBunti1sGsm92PRv3r9VJG5Nd2bi3t7cU9klNRk/iABxJ0U9vNieiWpCIhNYS cXamw+v84nGCiWjO7kkfkK9f32m9wXBLd8aIX9Iy0WCBYUCRQ76N8LB6cwcggtJofEMkML0Ns6K kp5AoT1ZVGVuij/Pk+A0JBOhEslPBJLcQ1fEZA0LOO/5j6dTo8APigsTweF0ntjnFwtTqlLTEpP XPPkfa/aeQQ== X-Google-Smtp-Source: AGHT+IHnhl/SXBPuV+Teh2onhSMDZZRSjqgEBJhNx8fQi22TSLVw/o4y42POuk8xy668uBRrxuyThQ== X-Received: by 2002:a05:6a00:a28:b0:736:5725:59b4 with SMTP id d2e1a72fcca58-73ff7255d50mr14179829b3a.3.1745871034415; Mon, 28 Apr 2025 13:10:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 06/10] target/riscv: Move cpu_get_tb_cpu_state to tcg-cpu.c Date: Mon, 28 Apr 2025 13:10:24 -0700 Message-ID: <20250428201028.1699157-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250428201028.1699157-1-richard.henderson@linaro.org> References: <20250428201028.1699157-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745871138790019000 Content-Type: text/plain; charset="utf-8" This function is only relevant to tcg. Move it to a tcg-specific file. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/riscv/cpu_helper.c | 97 ------------------------------------- target/riscv/tcg/tcg-cpu.c | 98 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+), 97 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f2e90a9889..d5039f69a9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -135,103 +135,6 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *en= v, bool virt) #endif } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - RISCVCPU *cpu =3D env_archcpu(env); - RISCVExtStatus fs, vs; - uint32_t flags =3D 0; - bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); - - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - - if (cpu->cfg.ext_zve32x) { - /* - * If env->vl equals to VLMAX, we can use generic vector operation - * expanders (GVEC) to accerlate the vector operations. - * However, as LMUL could be a fractional number. The maximum - * vector size can be operated might be less than 8 bytes, - * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue - * only when maxsz >=3D 8 bytes. - */ - - /* lmul encoded as in DisasContext::lmul */ - int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); - uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); - uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); - uint32_t maxsz =3D vlmax << vsew; - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && - (maxsz >=3D 8); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); - flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, - FIELD_EX64(env->vtype, VTYPE, VTA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, - FIELD_EX64(env->vtype, VTYPE, VMA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); - } else { - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - - if (cpu_get_fcfien(env)) { - /* - * For Forward CFI, only the expectation of a lpad at - * the start of the block is tracked via env->elp. env->elp - * is turned on during jalr translation. - */ - flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); - flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); - } - - if (cpu_get_bcfien(env)) { - flags =3D FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); - } - -#ifdef CONFIG_USER_ONLY - fs =3D EXT_STATUS_DIRTY; - vs =3D EXT_STATUS_DIRTY; -#else - flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); - - flags |=3D riscv_env_mmu_index(env, 0); - fs =3D get_field(env->mstatus, MSTATUS_FS); - vs =3D get_field(env->mstatus, MSTATUS_VS); - - if (env->virt_enabled) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } - - /* With Zfinx, floating point is enabled/disabled by Smstateen. */ - if (!riscv_has_ext(env, RVF)) { - fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) - ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; - } - - if (cpu->cfg.debug && !icount_enabled()) { - flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); - } -#endif - - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); - flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); - - *pflags =3D flags; -} - RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e3e7fea66a..f2cacef5e5 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "system/tcg.h" +#include "exec/icount.h" #endif =20 /* Hash that stores user set extensions */ @@ -97,6 +98,103 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetc= h) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 +void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + RISCVCPU *cpu =3D env_archcpu(env); + RISCVExtStatus fs, vs; + uint32_t flags =3D 0; + bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); + + *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; + *cs_base =3D 0; + + if (cpu->cfg.ext_zve32x) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ + + /* lmul encoded as in DisasContext::lmul */ + int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); + uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); + uint32_t maxsz =3D vlmax << vsew; + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && + (maxsz >=3D 8); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, vsew); + flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, + FIELD_EX64(env->vtype, VTYPE, VTA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); + } else { + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + + if (cpu_get_fcfien(env)) { + /* + * For Forward CFI, only the expectation of a lpad at + * the start of the block is tracked via env->elp. env->elp + * is turned on during jalr translation. + */ + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); + } + + if (cpu_get_bcfien(env)) { + flags =3D FIELD_DP32(flags, TB_FLAGS, BCFI_ENABLED, 1); + } + +#ifdef CONFIG_USER_ONLY + fs =3D EXT_STATUS_DIRTY; + vs =3D EXT_STATUS_DIRTY; +#else + flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); + + flags |=3D riscv_env_mmu_index(env, 0); + fs =3D get_field(env->mstatus, MSTATUS_FS); + vs =3D get_field(env->mstatus, MSTATUS_VS); + + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } + + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ + if (!riscv_has_ext(env, RVF)) { + fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; + } + + if (cpu->cfg.debug && !icount_enabled()) { + flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); + } +#endif + + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); + + *pflags =3D flags; +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { --=20 2.43.0 From nobody Sat Nov 15 23:38:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745871149; cv=none; d=zohomail.com; s=zohoarc; b=EWqTEP48zUFUI9sgXt+Uweq+hK03SdOt8nb7Ugf40Bgx6e79WYrfgarqW3K4x0FVQ2zjybpFPXnruLIKK7YxV9IteCOXBxoIAUaVU34ItDsgowbbidjEhXVi72ESUB7zaT3WhQW36VIgkIuxUML1K+PJXDf0WOIYu+HUaVTJqD4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745871149; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Euuw7vRLlECbRToI2wToD7v5PcT3Tt4xvVhWvmexFBc=; b=TGC5Os91MrEPmEgGDdf+LCkkEUoU6feyYAmNe3kOwN+dHXgG62NbtjBArmO2AKRjhnD3KdZ3kfxLOVdwOUXNUg3J1hXCe5Z+48xinUfV8XQZGLObwCL9Agr/I83o8hS1bJWrKJRIlOA2gWcGEcZ8Ug/XPaWu923zJCdf7nyjhuY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745871149691653.8189804823053; Mon, 28 Apr 2025 13:12:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u9UoM-0005AJ-Ov; Mon, 28 Apr 2025 16:10:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u9UoK-000597-7c for qemu-devel@nongnu.org; Mon, 28 Apr 2025 16:10:40 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u9UoG-0000d8-MS for qemu-devel@nongnu.org; Mon, 28 Apr 2025 16:10:39 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-7369ce5d323so4342174b3a.1 for ; Mon, 28 Apr 2025 13:10:36 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/internal-common.h | 6 +++++ include/accel/tcg/cpu-ops.h | 9 +++++-- include/qemu/typedefs.h | 1 + accel/tcg/cpu-exec.c | 48 +++++++++++++++---------------------- accel/tcg/translate-all.c | 8 ++----- target/alpha/cpu.c | 13 +++++----- target/arm/helper.c | 16 ++++++++----- target/avr/cpu.c | 9 +++---- target/hexagon/cpu.c | 15 ++++++------ target/hppa/cpu.c | 10 ++++---- target/i386/tcg/tcg-cpu.c | 19 +++++++++------ target/loongarch/cpu.c | 20 +++++++++------- target/m68k/cpu.c | 20 +++++++++------- target/microblaze/cpu.c | 13 ++++++---- target/mips/cpu.c | 14 ++++++----- target/openrisc/cpu.c | 16 +++++++------ target/ppc/helper_regs.c | 8 +++---- target/riscv/tcg/tcg-cpu.c | 12 +++++----- target/rx/cpu.c | 14 ++++++----- target/s390x/cpu.c | 14 ++++++----- target/sh4/cpu.c | 22 +++++++++++------ target/sparc/cpu.c | 17 +++++++------ target/tricore/cpu.c | 14 +++++------ target/xtensa/cpu.c | 36 +++++++++++++++------------- 24 files changed, 202 insertions(+), 172 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 98c702422f..3ff4c1cb54 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -12,6 +12,7 @@ #include "exec/cpu-common.h" #include "exec/translation-block.h" #include "exec/mmap-lock.h" +#include "accel/tcg/cpu-ops.h" =20 extern int64_t max_delay; extern int64_t max_advance; @@ -56,6 +57,11 @@ TranslationBlock *tb_link_page(TranslationBlock *tb); void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc); =20 +static inline TCGTBCPUState get_tb_cpu_state(CPUState *cs) +{ + return cpu_get_tb_cpu_state(cs); +} + /** * tlb_init - initialize a CPU's TLB * @cpu: CPU whose TLB should be initialized diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f5e5746976..8dbe79ea7c 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -18,8 +18,13 @@ #include "exec/vaddr.h" #include "tcg/tcg-mo.h" =20 -void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); +struct TCGTBCPUState { + vaddr pc; + uint32_t flags; + uint64_t flags2; +}; + +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); =20 struct TCGCPUOps { /** diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 507f0814d5..551239ca61 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -114,6 +114,7 @@ typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; typedef struct TCGCPUOps TCGCPUOps; typedef struct TCGHelperInfo TCGHelperInfo; +typedef struct TCGTBCPUState TCGTBCPUState; typedef struct TaskState TaskState; typedef struct TranslationBlock TranslationBlock; typedef struct VirtIODevice VirtIODevice; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c21c5d202d..a48df5f291 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -385,9 +385,6 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; =20 /* * By definition we've just finished a TB, so I/O is OK. @@ -397,20 +394,21 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) * The next TB, if we chain to it, will clear the flag again. */ cpu->neg.can_do_io =3D true; - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 - cflags =3D curr_cflags(cpu); - if (check_for_breakpoints(cpu, pc, &cflags)) { + TCGTBCPUState s =3D get_tb_cpu_state(cpu); + uint32_t cflags =3D curr_cflags(cpu); + + if (check_for_breakpoints(cpu, s.pc, &cflags)) { cpu_loop_exit(cpu); } =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.flags2, s.flags, cflags); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } =20 if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) { - log_cpu_exec(pc, cpu, tb); + log_cpu_exec(s.pc, cpu, tb); } =20 return tb->tc.ptr; @@ -560,11 +558,7 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu) =20 void cpu_exec_step_atomic(CPUState *cpu) { - CPUArchState *env =3D cpu_env(cpu); TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; int tb_exit; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { @@ -573,9 +567,9 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running =3D true; =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + TCGTBCPUState s =3D get_tb_cpu_state(cpu); + uint32_t cflags =3D curr_cflags(cpu); =20 - cflags =3D curr_cflags(cpu); /* Execute in a serial context. */ cflags &=3D ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ @@ -587,16 +581,16 @@ void cpu_exec_step_atomic(CPUState *cpu) * Any breakpoint for this insn will have been recognized earlier. */ =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.flags2, s.flags, cflags); if (tb =3D=3D NULL) { mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_gen_code(cpu, s.pc, s.flags2, s.flags, cflags); mmap_unlock(); } =20 cpu_exec_enter(cpu); /* execute the generated code */ - trace_exec_tb(tb, pc); + trace_exec_tb(tb, s.pc); cpu_tb_exec(cpu, tb, &tb_exit); cpu_exec_exit(cpu); } else { @@ -941,11 +935,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { TranslationBlock *tb; - vaddr pc; - uint64_t cs_base; - uint32_t flags, cflags; - - cpu_get_tb_cpu_state(cpu_env(cpu), &pc, &cs_base, &flags); + TCGTBCPUState s =3D get_tb_cpu_state(cpu); + uint32_t cflags =3D cpu->cflags_next_tb; =20 /* * When requested, use an exact setting for cflags for the next @@ -954,33 +945,32 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) * have CF_INVALID set, -1 is a convenient invalid value that * does not require tcg headers for cpu_common_reset. */ - cflags =3D cpu->cflags_next_tb; if (cflags =3D=3D -1) { cflags =3D curr_cflags(cpu); } else { cpu->cflags_next_tb =3D -1; } =20 - if (check_for_breakpoints(cpu, pc, &cflags)) { + if (check_for_breakpoints(cpu, s.pc, &cflags)) { break; } =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + tb =3D tb_lookup(cpu, s.pc, s.flags2, s.flags, cflags); if (tb =3D=3D NULL) { CPUJumpCache *jc; uint32_t h; =20 mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb =3D tb_gen_code(cpu, s.pc, s.flags2, s.flags, cflags); mmap_unlock(); =20 /* * We add the TB in the virtual pc hash table * for the fast lookup */ - h =3D tb_jmp_cache_hash_func(pc); + h =3D tb_jmp_cache_hash_func(s.pc); jc =3D cpu->tb_jmp_cache; - jc->array[h].pc =3D pc; + jc->array[h].pc =3D s.pc; qatomic_set(&jc->array[h].tb, tb); } =20 @@ -1000,7 +990,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) tb_add_jump(last_tb, tb_exit, tb); } =20 - cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit); + cpu_loop_exec_tb(cpu, tb, s.pc, &last_tb, &tb_exit); =20 /* Try to align the host and virtual clocks if the guest is in advance */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 31c7f9927f..759ae77559 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -590,13 +590,9 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t reta= ddr) /* The exception probably happened in a helper. The CPU state sho= uld have been saved before calling it. Fetch the PC from there. */ CPUArchState *env =3D cpu_env(cpu); - vaddr pc; - uint64_t cs_base; - tb_page_addr_t addr; - uint32_t flags; + TCGTBCPUState s =3D get_tb_cpu_state(cpu); + tb_page_addr_t addr =3D get_page_addr_code(env, s.pc); =20 - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - addr =3D get_page_addr_code(env, pc); if (addr !=3D -1) { tb_invalidate_phys_range(cpu, addr, addr); } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index d1fddef1f4..6efaa71543 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -41,15 +41,16 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 -void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *pflags =3D env->flags & ENV_FLAG_TB_MASK; + CPUAlphaState *env =3D cpu_env(cs); + uint32_t flags =3D env->flags & ENV_FLAG_TB_MASK; + #ifdef CONFIG_USER_ONLY - *pflags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |=3D TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void alpha_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/arm/helper.c b/target/arm/helper.c index 98adeb7086..aa887af50f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11453,21 +11453,22 @@ static bool mve_no_pred(CPUARMState *env) return true; } =20 -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUARMState *env =3D cpu_env(cs); CPUARMTBFlags flags; + vaddr pc; =20 assert_hflags_rebuild_correctly(env); flags =3D env->hflags; =20 if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { - *pc =3D env->pc; + pc =3D env->pc; if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { DP_TBFLAG_A64(flags, BTYPE, env->btype); } } else { - *pc =3D env->regs[15]; + pc =3D env->regs[15]; =20 if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY) && @@ -11529,8 +11530,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, vaddr = *pc, DP_TBFLAG_ANY(flags, PSTATE__SS, 1); } =20 - *pflags =3D flags.flags; - *cs_base =3D flags.flags2; + return (TCGTBCPUState){ + .pc =3D pc, + .flags =3D flags.flags, + .flags2 =3D flags.flags2, + }; } =20 #ifdef TARGET_AARCH64 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index fac8954c39..88a4b970df 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,14 +54,11 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 -void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUAVRState *env =3D cpu_env(cs); uint32_t flags =3D 0; =20 - *pc =3D env->pc_w * 2; - *cs_base =3D 0; - if (env->fullacc) { flags |=3D TB_FLAGS_FULL_ACCESS; } @@ -69,7 +66,7 @@ void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, flags |=3D TB_FLAGS_SKIP; } =20 - *pflags =3D flags; + return (TCGTBCPUState){ .pc =3D env->pc_w * 2, .flags =3D flags }; } =20 static void avr_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index e1a93ce24f..08c9aef55e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -255,19 +255,20 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 -void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHexagonState *env =3D cpu_env(cs); + vaddr pc =3D env->gpr[HEX_REG_PC]; uint32_t hex_flags =3D 0; - *pc =3D env->gpr[HEX_REG_PC]; - *cs_base =3D 0; - if (*pc =3D=3D env->gpr[HEX_REG_SA0]) { + + if (pc =3D=3D env->gpr[HEX_REG_SA0]) { hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); } - *flags =3D hex_flags; - if (*pc & PCALIGN_MASK) { + if (pc & PCALIGN_MASK) { hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); } + + return (TCGTBCPUState){ .pc =3D pc, .flags =3D hex_flags }; } =20 static void hexagon_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 24ca2d7175..7270b0a2a7 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -51,11 +51,12 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) env->iaoq_f & -4); } =20 -void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *pcsbase, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUHPPAState *env =3D cpu_env(cs); uint32_t flags =3D 0; uint64_t cs_base =3D 0; + vaddr pc; =20 /* * TB lookup assumes that PC contains the complete virtual address. @@ -63,7 +64,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, * incomplete virtual address. This also means that we must separate * out current cpu privilege from the low bits of IAOQ_F. */ - *pc =3D hppa_cpu_get_pc(env_cpu(env)); + pc =3D hppa_cpu_get_pc(env_cpu(env)); flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; =20 /* @@ -99,8 +100,7 @@ void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, } #endif =20 - *pcsbase =3D cs_base; - *pflags =3D flags; + return (TCGTBCPUState){ .pc =3D pc, .flags =3D flags, .flags2 =3D cs_b= ase }; } =20 static void hppa_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index cf9ce70139..950b3bfa76 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -48,18 +48,23 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 -void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *flags =3D env->hflags | + CPUX86State *env =3D cpu_env(cs); + uint32_t flags, cs_base; + vaddr pc; + + flags =3D env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)= ); if (env->hflags & HF_CS64_MASK) { - *cs_base =3D 0; - *pc =3D env->eip; + cs_base =3D 0; + pc =3D env->eip; } else { - *cs_base =3D env->segs[R_CS].base; - *pc =3D (uint32_t)(*cs_base + env->eip); + cs_base =3D env->segs[R_CS].base; + pc =3D (uint32_t)(cs_base + env->eip); } + + return (TCGTBCPUState){ .pc =3D pc, .flags =3D flags, .flags2 =3D cs_b= ase }; } =20 static void x86_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index db66a6bdeb..1691fe1d9f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,16 +336,18 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs= , int interrupt_request) } #endif =20 -void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_F= PE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_S= XE; - *flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_= ASXE; - *flags |=3D is_va32(env) * HW_FLAGS_VA32; + CPULoongArchState *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FP= E; + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SX= E; + flags |=3D FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_A= SXE; + flags |=3D is_va32(env) * HW_FLAGS_VA32; + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void loongarch_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 0fc3ed316d..1786d9e0ce 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -39,20 +39,22 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; + CPUM68KState *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D (env->macsr >> 4) & TB_FLAGS_MACSR; if (env->sr & SR_S) { - *flags |=3D TB_FLAGS_MSR_S; - *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; - *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; + flags |=3D TB_FLAGS_MSR_S; + flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; + flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; } if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { - *flags |=3D TB_FLAGS_TRACE; + flags |=3D TB_FLAGS_TRACE; } + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void m68k_restore_state_to_opc(CPUState *cs, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index a91844e4bf..91e77a4e53 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -95,12 +95,15 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base =3D (*flags & IMM_FLAG ? env->imm : 0); + CPUMBState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MAS= K), + .flags2 =3D (env->iflags & IMM_FLAG ? env->imm : 0), + }; } =20 static void mb_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 066dadc71b..c514202fbc 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,13 +549,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifun= c) return mips_env_mmu_index(cpu_env(cs)); } =20 -void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->active_tc.PC; - *cs_base =3D 0; - *flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); + CPUMIPSState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->active_tc.PC, + .flags =3D env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR), + }; } =20 static const TCGCPUOps mips_tcg_ops =3D { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cfb3f62663..6b31f9c80e 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,14 +41,16 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); + CPUOpenRISCState *env =3D cpu_env(cs); + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D ((env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE))), + }; } =20 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 8d248bcbb9..ccaf2b0343 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -256,9 +256,9 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUPPCState *env =3D cpu_env(cs); uint32_t hflags_current =3D env->hflags; =20 #ifdef CONFIG_DEBUG_TCG @@ -270,9 +270,7 @@ void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, } #endif =20 - *pc =3D env->nip; - *cs_base =3D 0; - *flags =3D hflags_current; + return (TCGTBCPUState){ .pc =3D env->nip, .flags =3D hflags_current }; } =20 void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f2cacef5e5..461b8c97b4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -98,17 +98,14 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetc= h) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPURISCVState *env =3D cpu_env(cs); RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); =20 - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - if (cpu->cfg.ext_zve32x) { /* * If env->vl equals to VLMAX, we can use generic vector operation @@ -192,7 +189,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 - *pflags =3D flags; + return (TCGTBCPUState){ + .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, + .flags =3D flags + }; } =20 static void riscv_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index f22737865e..b8bba1a0c7 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,13 +44,15 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags =3D FIELD_DP32(*flags, PSW, U, env->psw_u); + CPURXState *env =3D cpu_env(cs); + uint32_t flags =3D 0; + + flags =3D FIELD_DP32(flags, PSW, PM, env->psw_pm); + flags =3D FIELD_DP32(flags, PSW, U, env->psw_u); + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags }; } =20 static void rx_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 3ca3f880a7..127574c085 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,9 +309,9 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetc= h) return s390x_env_mmu_index(cpu_env(cs), ifetch); } =20 -void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { + CPUS390XState *env =3D cpu_env(cs); uint32_t flags; =20 if (env->psw.addr & 1) { @@ -323,9 +323,6 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); } =20 - *pc =3D env->psw.addr; - *cs_base =3D env->ex_value; - flags =3D (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; if (env->psw.mask & PSW_MASK_PER) { flags |=3D env->cregs[9] & (FLAG_MASK_PER_BRANCH | @@ -342,7 +339,12 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *p= c, if (env->cregs[0] & CR0_VECTOR) { flags |=3D FLAG_MASK_VECTOR; } - *pflags =3D flags; + + return (TCGTBCPUState){ + .pc =3D env->psw.addr, + .flags =3D flags, + .flags2 =3D env->ex_value + }; } =20 static const TCGCPUOps s390_tcg_ops =3D { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index adbd59cd68..320cb8ddcc 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,19 +43,27 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base =3D env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags =3D env->flags + CPUSH4State *env =3D cpu_env(cs); + uint32_t flags; + + flags =3D env->flags | (env->fpscr & TB_FLAG_FPSCR_MASK) | (env->sr & TB_FLAG_SR_MASK) | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ #ifdef CONFIG_USER_ONLY - *flags |=3D TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; + flags |=3D TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus; #endif + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, +#ifdef CONFIG_USER_ONLY + /* For a gUSA region, notice the end of the region. */ + .flags2 =3D flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0, +#endif + }; } =20 static void superh_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 5a1f5b7915..77591e84ba 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -716,13 +716,11 @@ static void sparc_cpu_synchronize_from_tb(CPUState *c= s, cpu->env.npc =3D tb->cs_base; } =20 -void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t flags; - *pc =3D env->pc; - *cs_base =3D env->npc; - flags =3D cpu_mmu_index(env_cpu(env), false); + CPUSPARCState *env =3D cpu_env(cs); + uint32_t flags =3D cpu_mmu_index(cs, false); + #ifndef CONFIG_USER_ONLY if (cpu_supervisor_mode(env)) { flags |=3D TB_FLAG_SUPER; @@ -751,7 +749,12 @@ void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *p= c, } #endif /* !CONFIG_USER_ONLY */ #endif /* TARGET_SPARC64 */ - *pflags =3D flags; + + return (TCGTBCPUState){ + .pc =3D env->pc, + .flags =3D flags, + .flags2 =3D env->npc, + }; } =20 static void sparc_restore_state_to_opc(CPUState *cs, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8538066114..fdc2012d16 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -45,16 +45,14 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 -void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - uint32_t new_flags =3D 0; - *pc =3D env->PC; - *cs_base =3D 0; + CPUTriCoreState *env =3D cpu_env(cs); =20 - new_flags |=3D FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags =3D new_flags; + return (TCGTBCPUState){ + .pc =3D env->PC, + .flags =3D FIELD_DP32(0, TB_FLAGS, PRIV, extract32(env->PSW, 10, 2= )), + }; } =20 static void tricore_cpu_synchronize_from_tb(CPUState *cs, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index fe974e90f7..4a8de9f42c 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -55,15 +55,15 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) +TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) { - *pc =3D env->pc; - *cs_base =3D 0; - *flags =3D 0; - *flags |=3D xtensa_get_ring(env); + CPUXtensaState *env =3D cpu_env(cs); + uint32_t flags =3D 0; + target_ulong cs_base =3D 0; + + flags |=3D xtensa_get_ring(env); if (env->sregs[PS] & PS_EXCM) { - *flags |=3D XTENSA_TBFLAG_EXCM; + flags |=3D XTENSA_TBFLAG_EXCM; } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { target_ulong lend_dist =3D env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); @@ -85,26 +85,26 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *p= c, if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_s= ize) { target_ulong lbeg_off =3D env->sregs[LEND] - env->sregs[LBEG]; =20 - *cs_base =3D lend_dist; + cs_base =3D lend_dist; if (lbeg_off < 256) { - *cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + cs_base |=3D lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; } } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && (env->sregs[LITBASE] & 1)) { - *flags |=3D XTENSA_TBFLAG_LITBASE; + flags |=3D XTENSA_TBFLAG_LITBASE; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |=3D XTENSA_TBFLAG_DEBUG; + flags |=3D XTENSA_TBFLAG_DEBUG; } if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |=3D XTENSA_TBFLAG_ICOUNT; + flags |=3D XTENSA_TBFLAG_ICOUNT; } } if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + flags |=3D env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; } if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER= ) && (env->sregs[PS] & (PS_WOE | PS_EXCM)) =3D=3D PS_WOE) { @@ -112,15 +112,17 @@ void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr = *pc, (env->sregs[WINDOW_BASE] + 1); uint32_t w =3D ctz32(windowstart | 0x8); =20 - *flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, + flags |=3D (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + flags |=3D extract32(env->sregs[PS], PS_CALLINC_SHIFT, PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; } else { - *flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + flags |=3D 3 << XTENSA_TBFLAG_WINDOW_SHIFT; } if (env->yield_needed) { - *flags |=3D XTENSA_TBFLAG_YIELD; + flags |=3D XTENSA_TBFLAG_YIELD; } + + return (TCGTBCPUState){ .pc =3D env->pc, .flags =3D flags, .flags2 =3D= cs_base }; } =20 static void xtensa_restore_state_to_opc(CPUState *cs, --=20 2.43.0 From nobody Sat Nov 15 23:38:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/internal-common.h | 2 +- include/accel/tcg/cpu-ops.h | 8 ++++++-- target/arm/internals.h | 1 + target/ppc/internal.h | 2 ++ accel/tcg/cpu-exec.c | 1 + target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 1 + target/arm/helper.c | 2 +- target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 3 ++- target/hexagon/cpu.c | 3 ++- target/hppa/cpu.c | 3 ++- target/i386/tcg/tcg-cpu.c | 3 ++- target/loongarch/cpu.c | 3 ++- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 3 ++- target/openrisc/cpu.c | 3 ++- target/ppc/cpu_init.c | 2 +- target/ppc/helper_regs.c | 3 ++- target/riscv/tcg/tcg-cpu.c | 3 ++- target/rx/cpu.c | 3 ++- target/s390x/cpu.c | 3 ++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 3 ++- target/tricore/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- 27 files changed, 51 insertions(+), 23 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 3ff4c1cb54..130af3098c 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -59,7 +59,7 @@ void cpu_restore_state_from_tb(CPUState *cpu, Translation= Block *tb, =20 static inline TCGTBCPUState get_tb_cpu_state(CPUState *cs) { - return cpu_get_tb_cpu_state(cs); + return cs->cc->tcg_ops->get_tb_cpu_state(cs); } =20 /** diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 8dbe79ea7c..25986a351a 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -24,8 +24,6 @@ struct TCGTBCPUState { uint64_t flags2; }; =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); - struct TCGCPUOps { /** * mttcg_supported: multi-threaded TCG is supported @@ -68,6 +66,12 @@ struct TCGCPUOps { */ void (*translate_code)(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); + /** + * @get_tb_cpu_state: Extract CPU state for a TCG #TranslationBlock + * + * Fill in all data required to select or compile a TranslationBlock. + */ + TCGTBCPUState (*get_tb_cpu_state)(CPUState *cs); /** * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock * diff --git a/target/arm/internals.h b/target/arm/internals.h index d24acdd672..10f523873a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -370,6 +370,7 @@ void arm_restore_state_to_opc(CPUState *cs, const uint64_t *data); =20 #ifdef CONFIG_TCG +TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); =20 /* Our implementation of TCGCPUOps::cpu_exec_halt */ diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 9012d3809c..681d522c2e 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -308,4 +308,6 @@ static inline int ger_pack_masks(int pmsk, int ymsk, in= t xmsk) return msk; } =20 +TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs); + #endif /* PPC_INTERNAL_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index a48df5f291..a10a2c5f29 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1052,6 +1052,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_reset); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); + assert(tcg_ops->get_tb_cpu_state); assert(tcg_ops->mmu_index); tcg_ops->initialize(); tcg_target_initialized =3D true; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 6efaa71543..695e6f42a6 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -41,7 +41,7 @@ static vaddr alpha_cpu_get_pc(CPUState *cs) return env->pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState alpha_get_tb_cpu_state(CPUState *cs) { CPUAlphaState *env =3D cpu_env(cs); uint32_t flags =3D env->flags & ENV_FLAG_TB_MASK; @@ -251,6 +251,7 @@ static const TCGCPUOps alpha_tcg_ops =3D { =20 .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, + .get_tb_cpu_state =3D alpha_get_tb_cpu_state, .synchronize_from_tb =3D alpha_cpu_synchronize_from_tb, .restore_state_to_opc =3D alpha_restore_state_to_opc, .mmu_index =3D alpha_cpu_mmu_index, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9e74d7bc07..c401f0455b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2676,6 +2676,7 @@ static const TCGCPUOps arm_tcg_ops =3D { =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, + .get_tb_cpu_state =3D arm_get_tb_cpu_state, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, .restore_state_to_opc =3D arm_restore_state_to_opc, diff --git a/target/arm/helper.c b/target/arm/helper.c index aa887af50f..84f1d963c2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11453,7 +11453,7 @@ static bool mve_no_pred(CPUARMState *env) return true; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs) { CPUARMState *env =3D cpu_env(cs); CPUARMTBFlags flags; diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 57ed3f3a06..ef7e16dfcd 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -238,6 +238,7 @@ static const TCGCPUOps arm_v7m_tcg_ops =3D { =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, + .get_tb_cpu_state =3D arm_get_tb_cpu_state, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, .restore_state_to_opc =3D arm_restore_state_to_opc, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 88a4b970df..47b5334906 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -54,7 +54,7 @@ static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState avr_get_tb_cpu_state(CPUState *cs) { CPUAVRState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -241,6 +241,7 @@ static const TCGCPUOps avr_tcg_ops =3D { .mttcg_supported =3D false, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, + .get_tb_cpu_state =3D avr_get_tb_cpu_state, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .restore_state_to_opc =3D avr_restore_state_to_opc, .mmu_index =3D avr_cpu_mmu_index, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 08c9aef55e..9beb6a2dc2 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -255,7 +255,7 @@ static vaddr hexagon_cpu_get_pc(CPUState *cs) return cpu_env(cs)->gpr[HEX_REG_PC]; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs) { CPUHexagonState *env =3D cpu_env(cs); vaddr pc =3D env->gpr[HEX_REG_PC]; @@ -344,6 +344,7 @@ static const TCGCPUOps hexagon_tcg_ops =3D { .mttcg_supported =3D false, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, + .get_tb_cpu_state =3D hexagon_get_tb_cpu_state, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, .restore_state_to_opc =3D hexagon_restore_state_to_opc, .mmu_index =3D hexagon_cpu_mmu_index, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7270b0a2a7..58566d9897 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -51,7 +51,7 @@ static vaddr hppa_cpu_get_pc(CPUState *cs) env->iaoq_f & -4); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState hppa_get_tb_cpu_state(CPUState *cs) { CPUHPPAState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -262,6 +262,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { =20 .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, + .get_tb_cpu_state =3D hppa_get_tb_cpu_state, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, .restore_state_to_opc =3D hppa_restore_state_to_opc, .mmu_index =3D hppa_cpu_mmu_index, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 950b3bfa76..2845e5b0cc 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -48,7 +48,7 @@ static void x86_cpu_exec_exit(CPUState *cs) env->eflags =3D cpu_compute_eflags(env); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState x86_get_tb_cpu_state(CPUState *cs) { CPUX86State *env =3D cpu_env(cs); uint32_t flags, cs_base; @@ -160,6 +160,7 @@ const TCGCPUOps x86_tcg_ops =3D { .guest_default_memory_order =3D TCG_MO_ALL & ~TCG_MO_ST_LD, .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, + .get_tb_cpu_state =3D x86_get_tb_cpu_state, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .restore_state_to_opc =3D x86_restore_state_to_opc, .mmu_index =3D x86_cpu_mmu_index, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 1691fe1d9f..4ea17a288b 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -336,7 +336,7 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, = int interrupt_request) } #endif =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState loongarch_get_tb_cpu_state(CPUState *cs) { CPULoongArchState *env =3D cpu_env(cs); uint32_t flags; @@ -882,6 +882,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { =20 .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, + .get_tb_cpu_state =3D loongarch_get_tb_cpu_state, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, .restore_state_to_opc =3D loongarch_restore_state_to_opc, .mmu_index =3D loongarch_cpu_mmu_index, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1786d9e0ce..75a860cf6f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -39,7 +39,7 @@ static vaddr m68k_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState m68k_get_tb_cpu_state(CPUState *cs) { CPUM68KState *env =3D cpu_env(cs); uint32_t flags; @@ -612,6 +612,7 @@ static const TCGCPUOps m68k_tcg_ops =3D { =20 .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, + .get_tb_cpu_state =3D m68k_get_tb_cpu_state, .restore_state_to_opc =3D m68k_restore_state_to_opc, .mmu_index =3D m68k_cpu_mmu_index, =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 91e77a4e53..6a4f93e99c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -95,7 +95,7 @@ static vaddr mb_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState mb_get_tb_cpu_state(CPUState *cs) { CPUMBState *env =3D cpu_env(cs); =20 @@ -442,6 +442,7 @@ static const TCGCPUOps mb_tcg_ops =3D { =20 .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, + .get_tb_cpu_state =3D mb_get_tb_cpu_state, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, .restore_state_to_opc =3D mb_restore_state_to_opc, .mmu_index =3D mb_cpu_mmu_index, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c514202fbc..a47a96f060 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -549,7 +549,7 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) return mips_env_mmu_index(cpu_env(cs)); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs) { CPUMIPSState *env =3D cpu_env(cs); =20 @@ -566,6 +566,7 @@ static const TCGCPUOps mips_tcg_ops =3D { =20 .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, + .get_tb_cpu_state =3D mips_get_tb_cpu_state, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, .restore_state_to_opc =3D mips_restore_state_to_opc, .mmu_index =3D mips_cpu_mmu_index, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 6b31f9c80e..c0cd279b1e 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -41,7 +41,7 @@ static vaddr openrisc_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState openrisc_get_tb_cpu_state(CPUState *cs) { CPUOpenRISCState *env =3D cpu_env(cs); =20 @@ -258,6 +258,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { =20 .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, + .get_tb_cpu_state =3D openrisc_get_tb_cpu_state, .synchronize_from_tb =3D openrisc_cpu_synchronize_from_tb, .restore_state_to_opc =3D openrisc_restore_state_to_opc, .mmu_index =3D openrisc_cpu_mmu_index, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 5981f607d2..fcd96e369e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -45,7 +45,6 @@ #include "internal.h" #include "spr_common.h" #include "power8-pmu.h" - #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "hw/intc/intc.h" @@ -7483,6 +7482,7 @@ static const TCGCPUOps ppc_tcg_ops =3D { .guest_default_memory_order =3D 0, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, + .get_tb_cpu_state =3D ppc_get_tb_cpu_state, .restore_state_to_opc =3D ppc_restore_state_to_opc, .mmu_index =3D ppc_cpu_mmu_index, =20 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index ccaf2b0343..7e5726871e 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -28,6 +28,7 @@ #include "cpu-models.h" #include "spr_common.h" #include "accel/tcg/cpu-ops.h" +#include "internal.h" =20 /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -256,7 +257,7 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |=3D hreg_compute_pmu_hflags_value(env); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +TCGTBCPUState ppc_get_tb_cpu_state(CPUState *cs) { CPUPPCState *env =3D cpu_env(cs); uint32_t hflags_current =3D env->hflags; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 461b8c97b4..4ab8f021eb 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -98,7 +98,7 @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) return riscv_env_mmu_index(cpu_env(cs), ifetch); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs) { CPURISCVState *env =3D cpu_env(cs); RISCVCPU *cpu =3D env_archcpu(env); @@ -243,6 +243,7 @@ const TCGCPUOps riscv_tcg_ops =3D { =20 .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, + .get_tb_cpu_state =3D riscv_get_tb_cpu_state, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .restore_state_to_opc =3D riscv_restore_state_to_opc, .mmu_index =3D riscv_cpu_mmu_index, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index b8bba1a0c7..786c9d3031 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -44,7 +44,7 @@ static vaddr rx_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState rx_get_tb_cpu_state(CPUState *cs) { CPURXState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -220,6 +220,7 @@ static const TCGCPUOps rx_tcg_ops =3D { =20 .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, + .get_tb_cpu_state =3D rx_get_tb_cpu_state, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, .restore_state_to_opc =3D rx_restore_state_to_opc, .mmu_index =3D rx_cpu_mmu_index, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 127574c085..65330d8ae5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,7 +309,7 @@ static int s390x_cpu_mmu_index(CPUState *cs, bool ifetc= h) return s390x_env_mmu_index(cpu_env(cs), ifetch); } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState s390x_get_tb_cpu_state(CPUState *cs) { CPUS390XState *env =3D cpu_env(cs); uint32_t flags; @@ -358,6 +358,7 @@ static const TCGCPUOps s390_tcg_ops =3D { =20 .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, + .get_tb_cpu_state =3D s390x_get_tb_cpu_state, .restore_state_to_opc =3D s390x_restore_state_to_opc, .mmu_index =3D s390x_cpu_mmu_index, =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 320cb8ddcc..20969037d1 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -43,7 +43,7 @@ static vaddr superh_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState superh_get_tb_cpu_state(CPUState *cs) { CPUSH4State *env =3D cpu_env(cs); uint32_t flags; @@ -289,6 +289,7 @@ static const TCGCPUOps superh_tcg_ops =3D { =20 .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, + .get_tb_cpu_state =3D superh_get_tb_cpu_state, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, .restore_state_to_opc =3D superh_restore_state_to_opc, .mmu_index =3D sh4_cpu_mmu_index, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 77591e84ba..05805ee127 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -716,7 +716,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, cpu->env.npc =3D tb->cs_base; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState sparc_get_tb_cpu_state(CPUState *cs) { CPUSPARCState *env =3D cpu_env(cs); uint32_t flags =3D cpu_mmu_index(cs, false); @@ -1029,6 +1029,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { =20 .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, + .get_tb_cpu_state =3D sparc_get_tb_cpu_state, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, .restore_state_to_opc =3D sparc_restore_state_to_opc, .mmu_index =3D sparc_cpu_mmu_index, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index fdc2012d16..15e9d0eb1a 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -45,7 +45,7 @@ static vaddr tricore_cpu_get_pc(CPUState *cs) return cpu_env(cs)->PC; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState tricore_get_tb_cpu_state(CPUState *cs) { CPUTriCoreState *env =3D cpu_env(cs); =20 @@ -185,6 +185,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .mttcg_supported =3D false, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, + .get_tb_cpu_state =3D tricore_get_tb_cpu_state, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .restore_state_to_opc =3D tricore_restore_state_to_opc, .mmu_index =3D tricore_cpu_mmu_index, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 4a8de9f42c..6850a0e508 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -55,7 +55,7 @@ static vaddr xtensa_cpu_get_pc(CPUState *cs) return cpu->env.pc; } =20 -TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs) +static TCGTBCPUState xtensa_get_tb_cpu_state(CPUState *cs) { CPUXtensaState *env =3D cpu_env(cs); uint32_t flags =3D 0; @@ -308,6 +308,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, .debug_excp_handler =3D xtensa_breakpoint_handler, + .get_tb_cpu_state =3D xtensa_get_tb_cpu_state, .restore_state_to_opc =3D xtensa_restore_state_to_opc, .mmu_index =3D xtensa_cpu_mmu_index, =20 --=20 2.43.0 From nobody Sat Nov 15 23:38:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/accel/tcg/cpu-ldst.h | 34 ----------------------- include/accel/tcg/helper-retaddr.h | 43 ++++++++++++++++++++++++++++++ accel/tcg/cpu-exec.c | 1 + accel/tcg/user-exec.c | 1 + target/arm/tcg/helper-a64.c | 1 + target/arm/tcg/sme_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/ppc/mem_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + 9 files changed, 50 insertions(+), 34 deletions(-) create mode 100644 include/accel/tcg/helper-retaddr.h diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h index f97a730703..44a62b54da 100644 --- a/include/accel/tcg/cpu-ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -526,38 +526,4 @@ void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, MMUAccessType access_type, int mmu_idx); #endif =20 -/* - * For user-only, helpers that use guest to host address translation - * must protect the actual host memory access by recording 'retaddr' - * for the signal handler. This is required for a race condition in - * which another thread unmaps the page between a probe and the - * actual access. - */ -#ifdef CONFIG_USER_ONLY -extern __thread uintptr_t helper_retaddr; - -static inline void set_helper_retaddr(uintptr_t ra) -{ - helper_retaddr =3D ra; - /* - * Ensure that this write is visible to the SIGSEGV handler that - * may be invoked due to a subsequent invalid memory operation. - */ - signal_barrier(); -} - -static inline void clear_helper_retaddr(void) -{ - /* - * Ensure that previous memory operations have succeeded before - * removing the data visible to the signal handler. - */ - signal_barrier(); - helper_retaddr =3D 0; -} -#else -#define set_helper_retaddr(ra) do { } while (0) -#define clear_helper_retaddr() do { } while (0) -#endif - #endif /* ACCEL_TCG_CPU_LDST_H */ diff --git a/include/accel/tcg/helper-retaddr.h b/include/accel/tcg/helper-= retaddr.h new file mode 100644 index 0000000000..037fda2b83 --- /dev/null +++ b/include/accel/tcg/helper-retaddr.h @@ -0,0 +1,43 @@ +/* + * Get user helper pc for memory unwinding. + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_HELPER_RETADDR_H +#define ACCEL_TCG_HELPER_RETADDR_H + +/* + * For user-only, helpers that use guest to host address translation + * must protect the actual host memory access by recording 'retaddr' + * for the signal handler. This is required for a race condition in + * which another thread unmaps the page between a probe and the + * actual access. + */ +#ifdef CONFIG_USER_ONLY +extern __thread uintptr_t helper_retaddr; + +static inline void set_helper_retaddr(uintptr_t ra) +{ + helper_retaddr =3D ra; + /* + * Ensure that this write is visible to the SIGSEGV handler that + * may be invoked due to a subsequent invalid memory operation. + */ + signal_barrier(); +} + +static inline void clear_helper_retaddr(void) +{ + /* + * Ensure that previous memory operations have succeeded before + * removing the data visible to the signal handler. + */ + signal_barrier(); + helper_retaddr =3D 0; +} +#else +#define set_helper_retaddr(ra) do { } while (0) +#define clear_helper_retaddr() do { } while (0) +#endif + +#endif /* ACCEL_TCG_HELPER_RETADDR_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index a10a2c5f29..985abb1269 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -24,6 +24,7 @@ #include "hw/core/cpu.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/helper-retaddr.h" #include "trace.h" #include "disas/disas.h" #include "exec/cpu-common.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 70feee8df9..68e01fc584 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -26,6 +26,7 @@ #include "qemu/bitops.h" #include "qemu/rcu.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "user/cpu_loop.h" #include "qemu/main-loop.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 9cffda07cd..4f618ae390 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -30,6 +30,7 @@ #include "qemu/crc32c.h" #include "exec/cpu-common.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 3226895cae..de0c6e54d4 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -23,6 +23,7 @@ #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" #include "fpu/softfloat.h" #include "vec_internal.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 9f20ecb51d..a2c363a4e1 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -30,6 +30,7 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/probe.h" #ifdef CONFIG_USER_ONLY diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index aa1af44d22..6ab71a6fcb 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/helper-retaddr.h" #include "accel/tcg/probe.h" #include "internal.h" #include "qemu/atomic128.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 857005b120..a03609a140 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -32,6 +32,7 @@ #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" #include "qemu/atomic128.h" =20 --=20 2.43.0 From nobody Sat Nov 15 23:38:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 13:10:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org Subject: [PATCH 10/10] accel/tcg: Compile cpu-exec.c twice Date: Mon, 28 Apr 2025 13:10:28 -0700 Message-ID: <20250428201028.1699157-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250428201028.1699157-1-richard.henderson@linaro.org> References: <20250428201028.1699157-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745871127807019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cpu-exec.c | 2 -- accel/tcg/meson.build | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 985abb1269..47c34cdbd6 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,7 +22,6 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/cpu.h" -#include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" #include "accel/tcg/helper-retaddr.h" #include "trace.h" @@ -37,7 +36,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#include "cpu.h" #include "exec/icount.h" #include "exec/replay-core.h" #include "system/tcg.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 3f7b127130..0bb089299b 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -5,6 +5,7 @@ endif tcg_ss =3D ss.source_set() =20 tcg_ss.add(files( + 'cpu-exec.c', 'cpu-exec-common.c', 'tcg-runtime.c', 'tcg-runtime-gvec.c', @@ -21,7 +22,6 @@ libsystem_ss.add_all(tcg_ss) tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', - 'cpu-exec.c', 'translate-all.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) --=20 2.43.0