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([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4db99d3sm87300565ad.53.2025.04.28.12.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 12:23:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745868231; x=1746473031; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R37KMDljb4CsAfrDdBRy5Wnf5bfrROiq1X3f4Wy4iUE=; b=IzQ59fGdE/d5oa05R0PMcREMp8mPGfA76bg0wDaFdI4ireD6iTW2M5Gn93FEaRCa5z 3850mxt7UdMHVySOZeliOn4fSFw4jHDTGYmDNaFZ/9z874QZYcIAwsNPfnDCdenAn/M2 Cb6d3SAB0lZcnKH+nDbWV2RqK742TvCOIwWs9HxHb0ssZUKrLMqqnJqAKqNzo3EZ0F3h G+pgaRiJi0bNlkZMA1eryhJUbtmmDq9KYia8p07aCD5hadC7QMkZ7PRD1hiks9Sw8fjg tuG58NjBu5A1pluN+3lD07CUNTJoa4H0ohSvAm0ewItUZyKxrZlFfcYH1mbDs5ayrdrq xVew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745868231; x=1746473031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R37KMDljb4CsAfrDdBRy5Wnf5bfrROiq1X3f4Wy4iUE=; b=YGvR6MZLSBVXdIcuT7EJejPLs2KnqV+gjuqgRlnzjVmqv4+y9O3g13OGv3nY9Ko35H mVOtdoCKcMEdLtkjOz8cwy40sVtN4I6CvLmntOeLTc3jittJ7bUwcmPZjoQ2+O+3ObGz OorC4jRQe9tss2DPdXswWHvU5kRv5q+kVRgempSJQlP4e4XmUijnqS+1KdUCj4d11qd3 d++BYdc/FIQz4cs9xHCUPtG1amwFcQk5w9PzIyFdL8ppiog3z9XdDs1zjlmVFKFTANPW nfpjm+ebCldss8SPDJU5ky8+w6RUBIP5t0zBtylEaNNG3HLjzKlXRlmV3ubKDFlk/+D+ irEw== X-Gm-Message-State: AOJu0Yx4daSI5/169PSganCYYjQ8wfCjBxSE0wePbP9tH7Kl9Rv3spa1 HiDHkMoOipVYiM+HNDgIV913F4GP2Q6fe9H2GQq1h7xeZ784Wsz8rs9zl19+mS4U8zndnfdFXIG t+/k= X-Gm-Gg: ASbGncvilUGLXqKxHw9wTz+nRSkPKD6ifFDwOSL4hSs2QhXYPO2x1qLxRnWYHVapQ3+ zsHLKflzFVbvQn4/ckCXJF6h2RVXHn1sQbevq+Hdx5hscMVUh1fjWbALZTr7Kl7Ig/bWPEZvIHp sjwmbxpO/xB12EiL2z92eml3+UeOaIcKdT9coC9PddJZfjNi9izyROncP7+iDyAf+DDwUzKM1Rd dj07iHfNgxO6jH+K8kQG3IZW+BKMFlLiI23g6mlgi5yGAgv3wptfSc0uMu1VeV7VlpaYvnoHBQA Xgr5wrbsnphQ9MvlhSXMPXO3ss6QL30YfKxjGCkR5wYc X-Google-Smtp-Source: AGHT+IFeaHEcx3TWpvR3XoC2fzWGJ6Sk3aag6oxrNz9DFxJU1pISjQzp7baIpRib4Nzf/8jZrY6rTw== X-Received: by 2002:a17:90a:c2c7:b0:309:e351:2e3d with SMTP id 98e67ed59e1d1-30a23dd992dmr15592a91.12.1745868231247; Mon, 28 Apr 2025 12:23:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza , Andrea Bolognani Subject: [PATCH v4 6/9] target/riscv/kvm: do not read unavailable CSRs Date: Mon, 28 Apr 2025 16:23:20 -0300 Message-ID: <20250428192323.84992-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428192323.84992-1-dbarboza@ventanamicro.com> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745868404072019100 Content-Type: text/plain; charset="utf-8" [1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6. This happens because the kernel does not know 'senvcfg', making it unable to boot because QEMU is reading/wriiting it without any checks. After converting the CSRs to do "automated" get/put reg procedures in the previous patch we can now scan for availability. Two functions are created: - kvm_riscv_read_csr_cfg_legacy() will check if the CSR exists by brute forcing KVM_GET_ONE_REG in each one of them, interpreting an EINVAL return as indication that the CSR isn't available. This will be use in absence of KVM_GET_REG_LIST; - kvm_riscv_read_csr_cfg() will use the existing result of get_reg_list to check if the CSRs ids are present. kvm_riscv_init_multiext_cfg() is now kvm_riscv_init_cfg() to reflect that the function is also dealing with CSRs. [1] https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBL= bLKhfv=3D+jb0SYAw@mail.gmail.com/ Fixes: 4db19d5b21 ("target/riscv/kvm: add missing KVM CSRs") Reported-by: Andrea Bolognani Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 62 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 3 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index f881e7eb5d..1ce747d047 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -636,6 +636,10 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; =20 + if (!csr_cfg->supported) { + continue; + } + ret =3D kvm_get_one_reg(cs, csr_cfg->kvm_reg_id, ®); if (ret) { return ret; @@ -662,6 +666,10 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; =20 + if (!csr_cfg->supported) { + continue; + } + if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { reg =3D kvm_cpu_csr_get_u32(cpu, csr_cfg); } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint64_= t)) { @@ -1090,6 +1098,32 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU = *cpu, } } =20 +static void kvm_riscv_read_csr_cfg_legacy(KVMScratchCPU *kvmcpu) +{ + uint64_t val; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; + struct kvm_one_reg reg; + + reg.id =3D csr_cfg->kvm_reg_id; + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + if (errno =3D=3D EINVAL) { + csr_cfg->supported =3D false; + } else { + error_report("Unable to read KVM CSR %s: %s", + csr_cfg->name, strerror(errno)); + exit(EXIT_FAILURE); + } + } else { + csr_cfg->supported =3D true; + } + } +} + static int uint64_cmp(const void *a, const void *b) { uint64_t val1 =3D *(const uint64_t *)a; @@ -1146,7 +1180,26 @@ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMS= cratchCPU *kvmcpu, } } =20 -static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmc= pu) +static void kvm_riscv_read_csr_cfg(struct kvm_reg_list *reglist) +{ + struct kvm_reg_list *reg_search; + uint64_t reg_id; + + for (int i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; + + reg_id =3D csr_cfg->kvm_reg_id; + reg_search =3D bsearch(®_id, reglist->reg, reglist->n, + sizeof(uint64_t), uint64_cmp); + if (!reg_search) { + continue; + } + + csr_cfg->supported =3D true; + } +} + +static void kvm_riscv_init_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) { g_autofree struct kvm_reg_list *reglist =3D NULL; KVMCPUConfig *multi_ext_cfg; @@ -1163,7 +1216,9 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) * (EINVAL). Use read_legacy() in this case. */ if (errno =3D=3D EINVAL) { - return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); + kvm_riscv_read_multiext_legacy(cpu, kvmcpu); + kvm_riscv_read_csr_cfg_legacy(kvmcpu); + return; } else if (errno !=3D E2BIG) { /* * E2BIG is an expected error message for the API since we @@ -1226,6 +1281,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) } =20 kvm_riscv_check_sbi_dbcn_support(cpu, reglist); + kvm_riscv_read_csr_cfg(reglist); } =20 static void riscv_init_kvm_registers(Object *cpu_obj) @@ -1239,7 +1295,7 @@ static void riscv_init_kvm_registers(Object *cpu_obj) =20 kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); - kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); + kvm_riscv_init_cfg(cpu, &kvmcpu); =20 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); } --=20 2.49.0