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([2804:7f0:bcc0:906e:57d5:dca2:1ab3:20de]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4db99d3sm87300565ad.53.2025.04.28.12.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 12:23:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745868221; x=1746473021; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TOeCBxmoJl3fpGbBgDl7Mncm5lacwWUBmOxyjJ4Qi9g=; b=kDD3IM+cS9wW6EtObfpQpWo8igB1mm3qbo6wSosJCwEApK3bWcH6xo4fP8lvcUtaWP cDVGZ6ii8WyRwRnvlumWlPiVIe7+E18cb0crncpgtwi9iiTju9p3e/0TcYwsvmfcU0GB QcFk5woUjWIKJdthrL1vKmaQU5dBs82gmN2ZM3bjC+RUHK+9IFnKQ1hHoESr9AeRTCch 8/JfwaEIAzg/ThtqErJUEAQSNzbqiWAjn8YVdEBsLIJLiHFjHD/yyFCQCrjac+gYQ8Gh 1tgDO1E79KyduU4pCpLzhw7LZo0MhMWhKgVHE9q5zwHgG/Z5B0illZquiyMp2HZM16LZ eyGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745868221; x=1746473021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TOeCBxmoJl3fpGbBgDl7Mncm5lacwWUBmOxyjJ4Qi9g=; b=ozL7WJfmdkruZNxZkQUo9FqayUTkDibP8B7zeY+lp8IX04DIotF6vf5EngeuMfoZoq g40dEUSHGvODOaf/10B/ZlBfR7qaSoo0NPMUWFoUYecHO2fvbobagFlV4P0R5xkhHTzU pssL8ocBVUC67g5fc8xNLbMWkIG8+8yZXHJnKt5nc6LnPrV1MhfjiQjfxB6V12IEJCdG nyoLUHs8WTjzRfmN3Dku/u2r02XPieC6Mzpmne0PAvEIQmAT5vJo8pxEW3yqfKc6Wc0R 2S+5IEI1iHEcjWA3wc7NsRDgMRpx4EwxHWn530+wsnSfoSgpC1GtMC95OET4m//8++Y6 XlBQ== X-Gm-Message-State: AOJu0Yy2BfGhOzsYx350jWcQFRcSJ7QIrd+NGu8nu/84f7PGDnHRecmE su7Q/zackrQK7e6RxcN+f/Y2423GiDnIMFCu5bJ8xc3v9Uut2yapk2fF9uYrUew7rWIJphjEzcp aUg4= X-Gm-Gg: ASbGncvNQetG4jQ4wDjMAjaJqLJqMcCrg3x0jXzA3IgfU8tLJWojPx9dEpGGL7l77K0 yWfnObsAYP8L6gptjKkXVc3nJQFKjSEV0j0lmiVJI4tqrXYJfZJmpwBO4lw71nwYxXT3dF+2Acd CkAAFscz/T5sJdNIKxb+GXtTCmKnlBThMDHZCBJD66aRRg3GHHo2t+5chEaWgQl3lJNp2CPvLnM jZKGX4djumrlFq1Q1pJdmkdY/751gETTqxoQaC8e7owruolkPwGvsSd/jbKVH1zr5lha9K7NyM2 W85PbX+lZ2IVwaUiAnlGbOBq/77RctOP4e87dD8qg0bY X-Google-Smtp-Source: AGHT+IGvGt+ZA76bXf7rA/QgT+NlkWA2ckxJ+it9GwjuYhdgSwXMR52EmKApbVF3P37+7TL3nz+Xrw== X-Received: by 2002:a17:902:da88:b0:224:5a8:ba2c with SMTP id d9443c01a7336-22de703cff0mr3185845ad.52.1745868221642; Mon, 28 Apr 2025 12:23:41 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v4 3/9] target/riscv/kvm: turn u32/u64 reg functions into macros Date: Mon, 28 Apr 2025 16:23:17 -0300 Message-ID: <20250428192323.84992-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428192323.84992-1-dbarboza@ventanamicro.com> References: <20250428192323.84992-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745868349915019100 Content-Type: text/plain; charset="utf-8" This change is motivated by a future change w.r.t CSRs management. We want to handle them the same way as KVM extensions, i.e. a static array with KVMCPUConfig objs that will be read/write during init and so on. But to do that properly we must be able to declare a static array that hold KVM regs. C does not allow to init static arrays and use functions as initializers, e.g. we can't do: .kvm_reg_id =3D kvm_riscv_reg_id_ulong(...) When instantiating the array. We can do that with macros though, so our goal is turn kvm_riscv_reg_ulong() in a macro. It is cleaner to turn every other reg_id_*() function in macros, and ulong will end up using the macros for u32 and u64, so we'll start with them. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 6ba122f360..c91ecdfe59 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -58,6 +58,12 @@ void riscv_kvm_aplic_request(void *opaque, int irq, int = level) =20 static bool cap_has_mp_state; =20 +#define KVM_RISCV_REG_ID_U32(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U32 = | \ + type | idx) + +#define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 = | \ + type | idx) + static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, uint64_t idx) { @@ -76,16 +82,6 @@ static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *en= v, uint64_t type, return id; } =20 -static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) -{ - return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; -} - -static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) -{ - return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; -} - static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) { uint64_t size_ctz =3D __builtin_ctz(size_b); @@ -119,12 +115,12 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ KVM_REG_RISCV_CONFIG_REG(name)) =20 -#define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ +#define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ KVM_REG_RISCV_TIMER_REG(name)) =20 -#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) +#define RISCV_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx) =20 -#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) +#define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) =20 #define RISCV_VECTOR_CSR_REG(env, name) \ kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ --=20 2.49.0