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Mon, 28 Apr 2025 00:34:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHJnMm0x3WHtNnXoq140Kf2vkGMwKwlMhT+PD7yS8UiJgCHX71a5XMFQlFD2rUdivfGj7obJg== X-Received: by 2002:a05:6000:144b:b0:3a0:7c88:8f02 with SMTP id ffacd0b85a97d-3a07c888f61mr6024669f8f.1.1745825693849; Mon, 28 Apr 2025 00:34:53 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 04/26] target/riscv: update max_satp_mode based on QOM properties Date: Mon, 28 Apr 2025 09:34:19 +0200 Message-ID: <20250428073442.315770-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745825748054019000 Content-Type: text/plain; charset="utf-8" Almost all users of cpu->cfg.satp_mode care about the "max" value satp_mode_max_from_map(cpu->cfg.satp_mode.map). Convert the QOM properties back into it. For TCG, deduce the bitmap of supported modes from valid_vm[]. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 1 - hw/riscv/virt-acpi-build.c | 14 +++++--------- hw/riscv/virt.c | 5 ++--- target/riscv/cpu.c | 27 ++++++++++----------------- target/riscv/csr.c | 9 +++++++-- 5 files changed, 24 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 167909c89bc..4f3668012de 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -931,7 +931,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs); target_ulong riscv_new_csr_seed(target_ulong new_value, target_ulong write_mask); =20 -uint8_t satp_mode_max_from_map(uint32_t map); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); =20 /* Implemented in th_csr.c */ diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 2b374ebacbf..1a92a84207d 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -261,7 +261,6 @@ static void build_rhct(GArray *table_data, uint32_t isa_offset, num_rhct_nodes, cmo_offset =3D 0; RISCVCPU *cpu =3D &s->soc[0].harts[0]; uint32_t mmu_offset =3D 0; - uint8_t satp_mode_max; bool rv32 =3D riscv_cpu_is_32bit(cpu); g_autofree char *isa =3D NULL; =20 @@ -282,8 +281,7 @@ static void build_rhct(GArray *table_data, num_rhct_nodes++; } =20 - if (!rv32 && cpu->cfg.satp_mode.supported !=3D 0 && - (cpu->cfg.satp_mode.map & ~(1 << VM_1_10_MBARE))) { + if (!rv32 && cpu->cfg.max_satp_mode >=3D VM_1_10_SV39) { num_rhct_nodes++; } =20 @@ -343,20 +341,18 @@ static void build_rhct(GArray *table_data, } =20 /* MMU node structure */ - if (!rv32 && cpu->cfg.satp_mode.supported !=3D 0 && - (cpu->cfg.satp_mode.map & ~(1 << VM_1_10_MBARE))) { - satp_mode_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); + if (!rv32 && cpu->cfg.max_satp_mode >=3D VM_1_10_SV39) { mmu_offset =3D table_data->len - table.table_offset; build_append_int_noprefix(table_data, 2, 2); /* Type */ build_append_int_noprefix(table_data, 8, 2); /* Length */ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ /* MMU Type */ - if (satp_mode_max =3D=3D VM_1_10_SV57) { + if (cpu->cfg.max_satp_mode =3D=3D VM_1_10_SV57) { build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ - } else if (satp_mode_max =3D=3D VM_1_10_SV48) { + } else if (cpu->cfg.max_satp_mode =3D=3D VM_1_10_SV48) { build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ - } else if (satp_mode_max =3D=3D VM_1_10_SV39) { + } else if (cpu->cfg.max_satp_mode =3D=3D VM_1_10_SV39) { build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ } else { g_assert_not_reached(); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index be1bf0f6468..719365a95e0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -237,10 +237,10 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,= int socket, uint32_t cpu_phandle; MachineState *ms =3D MACHINE(s); bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); - uint8_t satp_mode_max; =20 for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { RISCVCPU *cpu_ptr =3D &s->soc[socket].harts[cpu]; + int8_t satp_mode_max =3D cpu_ptr->cfg.max_satp_mode; g_autofree char *cpu_name =3D NULL; g_autofree char *core_name =3D NULL; g_autofree char *intc_name =3D NULL; @@ -252,8 +252,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, i= nt socket, s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(ms->fdt, cpu_name); =20 - if (cpu_ptr->cfg.satp_mode.supported !=3D 0) { - satp_mode_max =3D satp_mode_max_from_map(cpu_ptr->cfg.satp_mod= e.map); + if (satp_mode_max !=3D -1) { sv_name =3D g_strdup_printf("riscv,%s", satp_mode_str(satp_mode_max, is_32_b= it)); qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name= ); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7ba57685a66..33a36a24737 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -390,7 +390,7 @@ static uint8_t satp_mode_from_str(const char *satp_mode= _str) g_assert_not_reached(); } =20 -uint8_t satp_mode_max_from_map(uint32_t map) +static uint8_t satp_mode_max_from_map(uint32_t map) { /* * 'map =3D 0' will make us return (31 - 32), which C will @@ -456,15 +456,13 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) /* * Bare CPUs do not default to the max available. * Users must set a valid satp_mode in the command - * line. + * line. Otherwise, leave the existing max_satp_mode + * in place. */ if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_BARE_CPU) !=3D NULL) { warn_report("No satp mode set. Defaulting to 'bare'"); - cpu->cfg.satp_mode.map =3D (1 << VM_1_10_MBARE); - return; + cpu->cfg.max_satp_mode =3D VM_1_10_MBARE; } - - cpu->cfg.satp_mode.map =3D cpu->cfg.satp_mode.supported; } #endif =20 @@ -1176,8 +1174,8 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) bool rv32 =3D riscv_cpu_is_32bit(cpu); uint8_t satp_mode_map_max; =20 - /* The CPU wants the OS to decide which satp mode to use */ - if (cpu->cfg.satp_mode.supported =3D=3D 0) { + if (cpu->cfg.max_satp_mode =3D=3D -1) { + /* The CPU wants the hypervisor to decide which satp mode to allow= */ return; } =20 @@ -1196,14 +1194,14 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *= cpu, Error **errp) (cpu->cfg.satp_mode.supported & (1 << i))) { for (int j =3D i - 1; j >=3D 0; --j) { if (cpu->cfg.satp_mode.supported & (1 << j)) { - cpu->cfg.satp_mode.map |=3D (1 << j); - break; + cpu->cfg.max_satp_mode =3D j; + return; } } - break; } } } + return; } =20 satp_mode_map_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); @@ -1233,12 +1231,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *c= pu, Error **errp) } } =20 - /* Finally expand the map so that all valid modes are set */ - for (int i =3D satp_mode_map_max - 1; i >=3D 0; --i) { - if (cpu->cfg.satp_mode.supported & (1 << i)) { - cpu->cfg.satp_mode.map |=3D (1 << i); - } - } + cpu->cfg.max_satp_mode =3D satp_mode_map_max; } #endif =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c52c87faaea..038be009c82 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1906,8 +1906,13 @@ static RISCVException read_mstatus(CPURISCVState *en= v, int csrno, =20 static bool validate_vm(CPURISCVState *env, target_ulong vm) { - uint64_t mode_supported =3D riscv_cpu_cfg(env)->satp_mode.map; - return get_field(mode_supported, (1 << vm)); + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + RISCVCPU *cpu =3D env_archcpu(env); + int satp_mode_supported_max =3D cpu->cfg.max_satp_mode; + const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + + assert(satp_mode_supported_max >=3D 0); + return vm <=3D satp_mode_supported_max && valid_vm[vm]; } =20 static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xat= p, --=20 2.49.0