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Mon, 28 Apr 2025 00:35:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGZsw+qjimAYNtW9HD0kljb/W6caZ+A/vrXcPNCi3ul1UrqhJKFVJoj+V+/Nvr2Fe8ncn96uQ== X-Received: by 2002:adf:ec87:0:b0:39c:1257:c96f with SMTP id ffacd0b85a97d-3a07adb1766mr4206226f8f.59.1745825715603; Mon, 28 Apr 2025 00:35:15 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 12/26] target/riscv: add more RISCVCPUDef fields Date: Mon, 28 Apr 2025 09:34:27 +0200 Message-ID: <20250428073442.315770-13-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826105370019100 Content-Type: text/plain; charset="utf-8" Allow using RISCVCPUDef to replicate all the logic of custom .instance_init functions. To simulate inheritance, merge the child's RISCVCPUDef with the parent and then finally move it to the CPUState at the end of TYPE_RISCV_CPU's own instance_init function. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 42 +++++++++++++++++++++++++++++++++++++- target/riscv/kvm/kvm-cpu.c | 6 ++++++ 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 842c9d3f194..5015763b7f4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -539,6 +539,10 @@ struct ArchCPU { =20 typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + uint32_t misa_ext; + int priv_spec; + int32_t vext_spec; + RISCVCPUConfig cfg; } RISCVCPUDef; =20 /** diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0beaed2f340..de831c8004d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -74,6 +74,13 @@ bool riscv_cpu_option_set(const char *optname) return g_hash_table_contains(general_user_opts, optname); } =20 +static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig= *src) +{ +#define BOOL_FIELD(x) dest->x |=3D src->x; +#define TYPED_FIELD(type, x, default_) if (src->x !=3D default_) dest->x = =3D src->x; +#include "cpu_cfg_fields.h.inc" +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -435,7 +442,7 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32= _bit) } =20 static void set_satp_mode_max_supported(RISCVCPU *cpu, - uint8_t satp_mode) + int satp_mode) { bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; @@ -1480,6 +1487,16 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cboz_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; cpu->cfg.max_satp_mode =3D -1; + + env->misa_ext_mask =3D env->misa_ext =3D mcc->def->misa_ext; + riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); + + if (mcc->def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + cpu->env.priv_ver =3D mcc->def->priv_spec; + } + if (mcc->def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + cpu->env.vext_ver =3D mcc->def->vext_spec; + } } =20 static void riscv_bare_cpu_init(Object *obj) @@ -3088,6 +3105,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; } + if (def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + assert(def->priv_spec <=3D PRIV_VERSION_LATEST); + mcc->def->priv_spec =3D def->priv_spec; + } + if (def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + assert(def->vext_spec !=3D 0); + mcc->def->vext_spec =3D def->vext_spec; + } + mcc->def->misa_ext |=3D def->misa_ext; + + riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg); } =20 if (!object_class_is_abstract(c)) { @@ -3194,6 +3222,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .instance_init =3D (initfn), \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode =3D -1, \ }), \ } =20 @@ -3204,6 +3235,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .instance_init =3D (initfn), \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode =3D -1, \ }), \ } =20 @@ -3214,6 +3248,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .instance_init =3D (initfn), \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode =3D -1, \ }), \ } =20 @@ -3224,6 +3261,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .instance_init =3D (initfn), \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode =3D -1, \ }), \ } =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 41b6f34552a..644b05988af 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -2004,10 +2004,16 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = =3D { #if defined(TARGET_RISCV32) .class_data =3D &((const RISCVCPUDef) { .misa_mxl_max =3D MXL_RV32, + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, + .cfg.max_satp_mode =3D -1, }, #elif defined(TARGET_RISCV64) .class_data =3D &((const RISCVCPUDef) { .misa_mxl_max =3D MXL_RV64, + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, + .cfg.max_satp_mode =3D -1, }, #endif } --=20 2.49.0