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Mon, 28 Apr 2025 00:34:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEsGwq+yLShN/RkC60H2fSjCcnflEJXOa5pd07yiFstPDm8dXEgKVAFVT8kHx7zlsv8FhAn8A== X-Received: by 2002:a05:6000:1787:b0:3a0:7fcf:1f41 with SMTP id ffacd0b85a97d-3a07fcf1facmr4419510f8f.47.1745825686870; Mon, 28 Apr 2025 00:34:46 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 01/26] hw/riscv: acpi: only create RHCT MMU entry for supported types Date: Mon, 28 Apr 2025 09:34:16 +0200 Message-ID: <20250428073442.315770-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745825748759019100 Content-Type: text/plain; charset="utf-8" Do not create the RHCT MMU type entry for RV32 CPUs, since it only has definitions for SV39/SV48/SV57. Likewise, check that satp_mode_max_from_map() will actually return a valid value, skipping the MMU type entry if all MMU types were disabled on the command line. Acked-by: Alistair Francis Signed-off-by: Paolo Bonzini --- hw/riscv/virt-acpi-build.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 1ad68005085..2b374ebacbf 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -262,6 +262,7 @@ static void build_rhct(GArray *table_data, RISCVCPU *cpu =3D &s->soc[0].harts[0]; uint32_t mmu_offset =3D 0; uint8_t satp_mode_max; + bool rv32 =3D riscv_cpu_is_32bit(cpu); g_autofree char *isa =3D NULL; =20 AcpiTable table =3D { .sig =3D "RHCT", .rev =3D 1, .oem_id =3D s->oem_= id, @@ -281,7 +282,8 @@ static void build_rhct(GArray *table_data, num_rhct_nodes++; } =20 - if (cpu->cfg.satp_mode.supported !=3D 0) { + if (!rv32 && cpu->cfg.satp_mode.supported !=3D 0 && + (cpu->cfg.satp_mode.map & ~(1 << VM_1_10_MBARE))) { num_rhct_nodes++; } =20 @@ -341,7 +343,8 @@ static void build_rhct(GArray *table_data, } =20 /* MMU node structure */ - if (cpu->cfg.satp_mode.supported !=3D 0) { + if (!rv32 && cpu->cfg.satp_mode.supported !=3D 0 && + (cpu->cfg.satp_mode.map & ~(1 << VM_1_10_MBARE))) { satp_mode_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); mmu_offset =3D table_data->len - table.table_offset; build_append_int_noprefix(table_data, 2, 2); /* Type */ @@ -356,7 +359,7 @@ static void build_rhct(GArray *table_data, } else if (satp_mode_max =3D=3D VM_1_10_SV39) { build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ } else { - assert(1); + g_assert_not_reached(); } } =20 --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1745825746; cv=none; d=zohomail.com; s=zohoarc; b=f4jOQ/uLlP+LY/AV7OzmFpYI5OPaBKEL1rHDaKH3KmY9pMV20FG0UvB/s5U/UlYX6vCmeZaJRX/lxTcaopwlEFvdnDbnbNaxWoE0YZ8eMREniuJ5LrNRFSa4aEquGMu0LzTWYsQhY7zOppK4WHcPsHuQJAdZ2QTivH2I9OUCRmw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Mon, 28 Apr 2025 00:34:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFCbhDcYVjq266H6xnfPTnegEg1cNRv0W4LrRnB+jtT/ymIF+lKZ7QnlcbVZE/zq991gLduNw== X-Received: by 2002:a05:6000:659:20b0:390:ee01:68fa with SMTP id ffacd0b85a97d-3a074e2f5f4mr5412450f8f.24.1745825688952; Mon, 28 Apr 2025 00:34:48 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 02/26] target/riscv: assert argument to set_satp_mode_max_supported is valid Date: Mon, 28 Apr 2025 09:34:17 +0200 Message-ID: <20250428073442.315770-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745825748742019100 Content-Type: text/plain; charset="utf-8" Check that the argument to set_satp_mode_max_supported is valid for the MXL value of the CPU. It would be a bug in the CPU definition if it weren't. In fact, there is such a bug in riscv_bare_cpu_init(): not just SV64 is not a valid VM mode for 32-bit CPUs, SV64 is not a valid VM mode at all, not yet at least. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e0604f4c78b..e0e70a2227f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -445,6 +445,8 @@ static void set_satp_mode_max_supported(RISCVCPU *cpu, cpu->cfg.satp_mode.supported |=3D (1 << i); } } + + assert(cpu->cfg.satp_mode.supported & (1 << satp_mode)); } =20 /* Set the satp mode to the max supported */ @@ -1498,7 +1500,9 @@ static void riscv_bare_cpu_init(Object *obj) * satp_mode manually (see set_satp_mode_default()). */ #ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV64); + set_satp_mode_max_supported(RISCV_CPU(obj), + riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? + VM_1_10_SV32 : VM_1_10_SV57); #endif } =20 --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 28 Apr 2025 00:34:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFWN3J9G7TSB7NtoROv4fcqLQsONrvW5mGFDe6PWcGc8at66IXoA0dyokNKuQXwcxUATVgQTQ== X-Received: by 2002:adf:fb0d:0:b0:38d:d371:e04d with SMTP id ffacd0b85a97d-3a074e6a9d6mr6880362f8f.34.1745825690958; Mon, 28 Apr 2025 00:34:50 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 03/26] target/riscv: cpu: store max SATP mode as a single integer Date: Mon, 28 Apr 2025 09:34:18 +0200 Message-ID: <20250428073442.315770-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826047978019000 Content-Type: text/plain; charset="utf-8" The maximum available SATP mode implies all the shorter virtual address siz= es. Store it in RISCVCPUConfig and avoid recomputing it via satp_mode_max_from_= map. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 11 +++++------ target/riscv/tcg/tcg-cpu.c | 3 ++- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index cfe371b829d..c8ea5cdc870 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -196,6 +196,7 @@ struct RISCVCPUConfig { =20 bool short_isa_string; =20 + int8_t max_satp_mode; RISCVSATPMap satp_mode; }; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e0e70a2227f..7ba57685a66 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -447,6 +447,7 @@ static void set_satp_mode_max_supported(RISCVCPU *cpu, } =20 assert(cpu->cfg.satp_mode.supported & (1 << satp_mode)); + cpu->cfg.max_satp_mode =3D satp_mode; } =20 /* Set the satp mode to the max supported */ @@ -1173,16 +1174,13 @@ static void riscv_cpu_disas_set_info(CPUState *s, d= isassemble_info *info) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 =3D riscv_cpu_is_32bit(cpu); - uint8_t satp_mode_map_max, satp_mode_supported_max; + uint8_t satp_mode_map_max; =20 /* The CPU wants the OS to decide which satp mode to use */ if (cpu->cfg.satp_mode.supported =3D=3D 0) { return; } =20 - satp_mode_supported_max =3D - satp_mode_max_from_map(cpu->cfg.satp_mode.supported); - if (cpu->cfg.satp_mode.map =3D=3D 0) { if (cpu->cfg.satp_mode.init =3D=3D 0) { /* If unset by the user, we fallback to the default satp mode.= */ @@ -1211,10 +1209,10 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *= cpu, Error **errp) satp_mode_map_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); =20 /* Make sure the user asked for a supported configuration (HW and qemu= ) */ - if (satp_mode_map_max > satp_mode_supported_max) { + if (satp_mode_map_max > cpu->cfg.max_satp_mode) { error_setg(errp, "satp_mode %s is higher than hw max capability %s= ", satp_mode_str(satp_mode_map_max, rv32), - satp_mode_str(satp_mode_supported_max, rv32)); + satp_mode_str(cpu->cfg.max_satp_mode, rv32)); return; } =20 @@ -1474,6 +1472,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; + cpu->cfg.max_satp_mode =3D -1; } =20 static void riscv_bare_cpu_init(Object *obj) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 54ac54f2e15..1192b4e1545 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -717,8 +717,9 @@ static bool riscv_cpu_validate_profile_satp(RISCVCPU *c= pu, RISCVCPUProfile *profile, bool send_warn) { - int satp_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.supported); + int satp_max =3D cpu->cfg.max_satp_mode; =20 + assert(satp_max >=3D 0); if (profile->satp_mode > satp_max) { if (send_warn) { bool is_32bit =3D riscv_cpu_is_32bit(cpu); --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 28 Apr 2025 00:34:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHJnMm0x3WHtNnXoq140Kf2vkGMwKwlMhT+PD7yS8UiJgCHX71a5XMFQlFD2rUdivfGj7obJg== X-Received: by 2002:a05:6000:144b:b0:3a0:7c88:8f02 with SMTP id ffacd0b85a97d-3a07c888f61mr6024669f8f.1.1745825693849; Mon, 28 Apr 2025 00:34:53 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 04/26] target/riscv: update max_satp_mode based on QOM properties Date: Mon, 28 Apr 2025 09:34:19 +0200 Message-ID: <20250428073442.315770-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745825748054019000 Content-Type: text/plain; charset="utf-8" Almost all users of cpu->cfg.satp_mode care about the "max" value satp_mode_max_from_map(cpu->cfg.satp_mode.map). Convert the QOM properties back into it. For TCG, deduce the bitmap of supported modes from valid_vm[]. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 1 - hw/riscv/virt-acpi-build.c | 14 +++++--------- hw/riscv/virt.c | 5 ++--- target/riscv/cpu.c | 27 ++++++++++----------------- target/riscv/csr.c | 9 +++++++-- 5 files changed, 24 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 167909c89bc..4f3668012de 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -931,7 +931,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs); target_ulong riscv_new_csr_seed(target_ulong new_value, target_ulong write_mask); =20 -uint8_t satp_mode_max_from_map(uint32_t map); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); =20 /* Implemented in th_csr.c */ diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 2b374ebacbf..1a92a84207d 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -261,7 +261,6 @@ static void build_rhct(GArray *table_data, uint32_t isa_offset, num_rhct_nodes, cmo_offset =3D 0; RISCVCPU *cpu =3D &s->soc[0].harts[0]; uint32_t mmu_offset =3D 0; - uint8_t satp_mode_max; bool rv32 =3D riscv_cpu_is_32bit(cpu); g_autofree char *isa =3D NULL; =20 @@ -282,8 +281,7 @@ static void build_rhct(GArray *table_data, num_rhct_nodes++; } =20 - if (!rv32 && cpu->cfg.satp_mode.supported !=3D 0 && - (cpu->cfg.satp_mode.map & ~(1 << VM_1_10_MBARE))) { + if (!rv32 && cpu->cfg.max_satp_mode >=3D VM_1_10_SV39) { num_rhct_nodes++; } =20 @@ -343,20 +341,18 @@ static void build_rhct(GArray *table_data, } =20 /* MMU node structure */ - if (!rv32 && cpu->cfg.satp_mode.supported !=3D 0 && - (cpu->cfg.satp_mode.map & ~(1 << VM_1_10_MBARE))) { - satp_mode_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); + if (!rv32 && cpu->cfg.max_satp_mode >=3D VM_1_10_SV39) { mmu_offset =3D table_data->len - table.table_offset; build_append_int_noprefix(table_data, 2, 2); /* Type */ build_append_int_noprefix(table_data, 8, 2); /* Length */ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ /* MMU Type */ - if (satp_mode_max =3D=3D VM_1_10_SV57) { + if (cpu->cfg.max_satp_mode =3D=3D VM_1_10_SV57) { build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ - } else if (satp_mode_max =3D=3D VM_1_10_SV48) { + } else if (cpu->cfg.max_satp_mode =3D=3D VM_1_10_SV48) { build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ - } else if (satp_mode_max =3D=3D VM_1_10_SV39) { + } else if (cpu->cfg.max_satp_mode =3D=3D VM_1_10_SV39) { build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ } else { g_assert_not_reached(); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index be1bf0f6468..719365a95e0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -237,10 +237,10 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,= int socket, uint32_t cpu_phandle; MachineState *ms =3D MACHINE(s); bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); - uint8_t satp_mode_max; =20 for (cpu =3D s->soc[socket].num_harts - 1; cpu >=3D 0; cpu--) { RISCVCPU *cpu_ptr =3D &s->soc[socket].harts[cpu]; + int8_t satp_mode_max =3D cpu_ptr->cfg.max_satp_mode; g_autofree char *cpu_name =3D NULL; g_autofree char *core_name =3D NULL; g_autofree char *intc_name =3D NULL; @@ -252,8 +252,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, i= nt socket, s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(ms->fdt, cpu_name); =20 - if (cpu_ptr->cfg.satp_mode.supported !=3D 0) { - satp_mode_max =3D satp_mode_max_from_map(cpu_ptr->cfg.satp_mod= e.map); + if (satp_mode_max !=3D -1) { sv_name =3D g_strdup_printf("riscv,%s", satp_mode_str(satp_mode_max, is_32_b= it)); qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name= ); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7ba57685a66..33a36a24737 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -390,7 +390,7 @@ static uint8_t satp_mode_from_str(const char *satp_mode= _str) g_assert_not_reached(); } =20 -uint8_t satp_mode_max_from_map(uint32_t map) +static uint8_t satp_mode_max_from_map(uint32_t map) { /* * 'map =3D 0' will make us return (31 - 32), which C will @@ -456,15 +456,13 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) /* * Bare CPUs do not default to the max available. * Users must set a valid satp_mode in the command - * line. + * line. Otherwise, leave the existing max_satp_mode + * in place. */ if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_BARE_CPU) !=3D NULL) { warn_report("No satp mode set. Defaulting to 'bare'"); - cpu->cfg.satp_mode.map =3D (1 << VM_1_10_MBARE); - return; + cpu->cfg.max_satp_mode =3D VM_1_10_MBARE; } - - cpu->cfg.satp_mode.map =3D cpu->cfg.satp_mode.supported; } #endif =20 @@ -1176,8 +1174,8 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) bool rv32 =3D riscv_cpu_is_32bit(cpu); uint8_t satp_mode_map_max; =20 - /* The CPU wants the OS to decide which satp mode to use */ - if (cpu->cfg.satp_mode.supported =3D=3D 0) { + if (cpu->cfg.max_satp_mode =3D=3D -1) { + /* The CPU wants the hypervisor to decide which satp mode to allow= */ return; } =20 @@ -1196,14 +1194,14 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *= cpu, Error **errp) (cpu->cfg.satp_mode.supported & (1 << i))) { for (int j =3D i - 1; j >=3D 0; --j) { if (cpu->cfg.satp_mode.supported & (1 << j)) { - cpu->cfg.satp_mode.map |=3D (1 << j); - break; + cpu->cfg.max_satp_mode =3D j; + return; } } - break; } } } + return; } =20 satp_mode_map_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); @@ -1233,12 +1231,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *c= pu, Error **errp) } } =20 - /* Finally expand the map so that all valid modes are set */ - for (int i =3D satp_mode_map_max - 1; i >=3D 0; --i) { - if (cpu->cfg.satp_mode.supported & (1 << i)) { - cpu->cfg.satp_mode.map |=3D (1 << i); - } - } + cpu->cfg.max_satp_mode =3D satp_mode_map_max; } #endif =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c52c87faaea..038be009c82 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1906,8 +1906,13 @@ static RISCVException read_mstatus(CPURISCVState *en= v, int csrno, =20 static bool validate_vm(CPURISCVState *env, target_ulong vm) { - uint64_t mode_supported =3D riscv_cpu_cfg(env)->satp_mode.map; - return get_field(mode_supported, (1 << vm)); + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32; + RISCVCPU *cpu =3D env_archcpu(env); + int satp_mode_supported_max =3D cpu->cfg.max_satp_mode; + const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + + assert(satp_mode_supported_max >=3D 0); + return vm <=3D satp_mode_supported_max && valid_vm[vm]; } =20 static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xat= p, --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1745826063; cv=none; d=zohomail.com; s=zohoarc; b=bhhbuF3i+LQLcxA+CDHywZKyB1qUmg/aVN/Rl1qbfcahYFngKbAAqrW+oPZAmit085NodyRtq67QO739XXTAGKWjYCCMYEXU12RDdMvNNpR3FEWzixQG0wPSlyl0v6oQVnxlspNVjuiv+QUBwJnqi+qkJM20152Vl+LXlpNiKDQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745826063; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 28 Apr 2025 00:34:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHKiWxzddEAI6XUocOgwYpnc41ztCxQpe+7vU+nj4jeihXHC4TrmUz++8GAjRt2Ie4Oijg08Q== X-Received: by 2002:a5d:5f8f:0:b0:39c:1efd:ed8f with SMTP id ffacd0b85a97d-3a074f66b39mr7043155f8f.50.1745825696812; Mon, 28 Apr 2025 00:34:56 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 05/26] target/riscv: remove supported from RISCVSATPMap Date: Mon, 28 Apr 2025 09:34:20 +0200 Message-ID: <20250428073442.315770-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826064087019000 Content-Type: text/plain; charset="utf-8" "supported" can be computed on the fly based on the max_satp_mode. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h | 4 +--- target/riscv/cpu.c | 34 ++++++++++++++++++++++++---------- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index c8ea5cdc870..8b80e03c9ab 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -29,11 +29,9 @@ * * init is a 16-bit bitmap used to make sure the user selected a correct * configuration as per the specification. - * - * supported is a 16-bit bitmap used to reflect the hw capabilities. */ typedef struct { - uint16_t map, init, supported; + uint16_t map, init; } RISCVSATPMap; =20 struct RISCVCPUConfig { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 33a36a24737..43ccea72e8d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -440,14 +440,27 @@ static void set_satp_mode_max_supported(RISCVCPU *cpu, bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; =20 - for (int i =3D 0; i <=3D satp_mode; ++i) { - if (valid_vm[i]) { - cpu->cfg.satp_mode.supported |=3D (1 << i); - } + assert(valid_vm[satp_mode]); + cpu->cfg.max_satp_mode =3D satp_mode; +} + +static bool get_satp_mode_supported(RISCVCPU *cpu, uint16_t *supported) +{ + bool rv32 =3D riscv_cpu_is_32bit(cpu); + const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + int satp_mode =3D cpu->cfg.max_satp_mode; + + if (satp_mode =3D=3D -1) { + return false; } =20 - assert(cpu->cfg.satp_mode.supported & (1 << satp_mode)); - cpu->cfg.max_satp_mode =3D satp_mode; + *supported =3D 0; + for (int i =3D 0; i <=3D satp_mode; ++i) { + if (valid_vm[i]) { + *supported |=3D (1 << i); + } + } + return true; } =20 /* Set the satp mode to the max supported */ @@ -1172,9 +1185,10 @@ static void riscv_cpu_disas_set_info(CPUState *s, di= sassemble_info *info) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 =3D riscv_cpu_is_32bit(cpu); + uint16_t supported; uint8_t satp_mode_map_max; =20 - if (cpu->cfg.max_satp_mode =3D=3D -1) { + if (!get_satp_mode_supported(cpu, &supported)) { /* The CPU wants the hypervisor to decide which satp mode to allow= */ return; } @@ -1191,9 +1205,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) */ for (int i =3D 1; i < 16; ++i) { if ((cpu->cfg.satp_mode.init & (1 << i)) && - (cpu->cfg.satp_mode.supported & (1 << i))) { + supported & (1 << i)) { for (int j =3D i - 1; j >=3D 0; --j) { - if (cpu->cfg.satp_mode.supported & (1 << j)) { + if (supported & (1 << j)) { cpu->cfg.max_satp_mode =3D j; return; } @@ -1222,7 +1236,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) for (int i =3D satp_mode_map_max - 1; i >=3D 0; --i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - (cpu->cfg.satp_mode.supported & (1 << i))) { + (supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), satp_mode_str(satp_mode_map_max, false)); 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Mon, 28 Apr 2025 00:34:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEnT/KhmWjOxZivM9GeBU+LCLFSK6yzJ8+S5P86UeLyJqhCGBMUZ8aVRBiylSy5bYpP3mUYaQ== X-Received: by 2002:a05:6000:40c7:b0:39f:d13:32a with SMTP id ffacd0b85a97d-3a074d4f2c9mr7541128f8f.29.1745825699142; Mon, 28 Apr 2025 00:34:59 -0700 (PDT) To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 06/26] target/riscv: move satp_mode.{map, init} out of CPUConfig Date: Mon, 28 Apr 2025 09:34:21 +0200 Message-ID: <20250428073442.315770-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Paolo Bonzini From: Paolo Bonzini via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1745826083349019100 Content-Type: text/plain; charset="utf-8" They are used to provide the nice QOM properties for svNN, but the canonical source of the CPU configuration is now cpu->cfg.max_satp_mode. Store them in the ArchCPU struct. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 14 ++++++++++++++ target/riscv/cpu_cfg.h | 14 -------------- target/riscv/cpu.c | 32 ++++++++++++++++---------------- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4f3668012de..97dc3ba7811 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,6 +498,19 @@ struct CPUArchState { uint64_t rnmi_excpvec; }; =20 +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maxi= mum + * satp mode that is supported. It may be chosen by the user and must resp= ect + * what qemu implements (valid_1_10_32/64) and what the hw is capable of + * (supported bitmap below). + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPModes; + /* * RISCVCPU: * @env: #CPURISCVState @@ -514,6 +527,7 @@ struct ArchCPU { =20 /* Configuration Settings */ RISCVCPUConfig cfg; + RISCVSATPModes satp_modes; =20 QEMUTimer *pmu_timer; /* A bitmask of Available programmable counters */ diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 8b80e03c9ab..8fa73c8a07d 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -21,19 +21,6 @@ #ifndef RISCV_CPU_CFG_H #define RISCV_CPU_CFG_H =20 -/* - * map is a 16-bit bitmap: the most significant set bit in map is the maxi= mum - * satp mode that is supported. It may be chosen by the user and must resp= ect - * what qemu implements (valid_1_10_32/64) and what the hw is capable of - * (supported bitmap below). - * - * init is a 16-bit bitmap used to make sure the user selected a correct - * configuration as per the specification. - */ -typedef struct { - uint16_t map, init; -} RISCVSATPMap; - struct RISCVCPUConfig { bool ext_zba; bool ext_zbb; @@ -195,7 +182,6 @@ struct RISCVCPUConfig { bool short_isa_string; =20 int8_t max_satp_mode; - RISCVSATPMap satp_mode; }; =20 typedef struct RISCVCPUConfig RISCVCPUConfig; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 43ccea72e8d..ab6ee39d304 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1193,8 +1193,8 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) return; } =20 - if (cpu->cfg.satp_mode.map =3D=3D 0) { - if (cpu->cfg.satp_mode.init =3D=3D 0) { + if (cpu->satp_modes.map =3D=3D 0) { + if (cpu->satp_modes.init =3D=3D 0) { /* If unset by the user, we fallback to the default satp mode.= */ set_satp_mode_default_map(cpu); } else { @@ -1204,7 +1204,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) * valid_vm_1_10_32/64. */ for (int i =3D 1; i < 16; ++i) { - if ((cpu->cfg.satp_mode.init & (1 << i)) && + if ((cpu->satp_modes.init & (1 << i)) && supported & (1 << i)) { for (int j =3D i - 1; j >=3D 0; --j) { if (supported & (1 << j)) { @@ -1218,7 +1218,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) return; } =20 - satp_mode_map_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); + satp_mode_map_max =3D satp_mode_max_from_map(cpu->satp_modes.map); =20 /* Make sure the user asked for a supported configuration (HW and qemu= ) */ if (satp_mode_map_max > cpu->cfg.max_satp_mode) { @@ -1234,8 +1234,8 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) */ if (!rv32) { for (int i =3D satp_mode_map_max - 1; i >=3D 0; --i) { - if (!(cpu->cfg.satp_mode.map & (1 << i)) && - (cpu->cfg.satp_mode.init & (1 << i)) && + if (!(cpu->satp_modes.map & (1 << i)) && + (cpu->satp_modes.init & (1 << i)) && (supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), @@ -1323,11 +1323,11 @@ bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu) static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - RISCVSATPMap *satp_map =3D opaque; + RISCVSATPModes *satp_modes =3D opaque; uint8_t satp =3D satp_mode_from_str(name); bool value; =20 - value =3D satp_map->map & (1 << satp); + value =3D satp_modes->map & (1 << satp); =20 visit_type_bool(v, name, &value, errp); } @@ -1335,7 +1335,7 @@ static void cpu_riscv_get_satp(Object *obj, Visitor *= v, const char *name, static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - RISCVSATPMap *satp_map =3D opaque; + RISCVSATPModes *satp_modes =3D opaque; uint8_t satp =3D satp_mode_from_str(name); bool value; =20 @@ -1343,8 +1343,8 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *= v, const char *name, return; } =20 - satp_map->map =3D deposit32(satp_map->map, satp, 1, value); - satp_map->init |=3D 1 << satp; + satp_modes->map =3D deposit32(satp_modes->map, satp, 1, value); + satp_modes->init |=3D 1 << satp; } =20 void riscv_add_satp_mode_properties(Object *obj) @@ -1353,16 +1353,16 @@ void riscv_add_satp_mode_properties(Object *obj) =20 if (cpu->env.misa_mxl =3D=3D MXL_RV32) { object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); } else { object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, - cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + cpu_riscv_set_satp, NULL, &cpu->satp_modes); } } =20 --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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Mon, 28 Apr 2025 00:35:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHoZYpKyKXQO3ty2aokjOl7KorbPq4HOTB0XCyztA4KbJ3SdqYEe7/rZvcEi3+Qk6VkATTIqA== X-Received: by 2002:a05:6000:2905:b0:390:e7c1:59c4 with SMTP id ffacd0b85a97d-3a07aa690bamr5589005f8f.13.1745825702027; Mon, 28 Apr 2025 00:35:02 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 07/26] target/riscv: introduce RISCVCPUDef Date: Mon, 28 Apr 2025 09:34:22 +0200 Message-ID: <20250428073442.315770-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826218737019100 Content-Type: text/plain; charset="utf-8" Start putting all the CPU definitions in a struct. Later this will replace instance_init functions with declarative code, for now just remove the ugly cast of class_data. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 27 ++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97dc3ba7811..62e303f0635 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -537,6 +537,10 @@ struct ArchCPU { const GPtrArray *decoders; }; =20 +typedef struct RISCVCPUDef { + RISCVMXL misa_mxl_max; /* max mxl for this cpu */ +} RISCVCPUDef; + /** * RISCVCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ab6ee39d304..f30cf1b532b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3074,8 +3074,9 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, const void *data) static void riscv_cpu_class_init(ObjectClass *c, const void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + const RISCVCPUDef *def =3D data; =20 - mcc->misa_mxl_max =3D (RISCVMXL)GPOINTER_TO_UINT(data); + mcc->misa_mxl_max =3D def->misa_mxl_max; riscv_cpu_validate_misa_mxl(mcc); } =20 @@ -3171,40 +3172,48 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) } #endif =20 -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ + .class_data =3D &((const RISCVCPUDef) { \ + .misa_mxl_max =3D (misa_mxl_max_), \ + }), \ } =20 -#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ .parent =3D TYPE_RISCV_VENDOR_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ + .class_data =3D &((const RISCVCPUDef) { \ + .misa_mxl_max =3D (misa_mxl_max_), \ + }), \ } =20 -#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ + .class_data =3D &((const RISCVCPUDef) { \ + .misa_mxl_max =3D (misa_mxl_max_), \ + }), \ } =20 -#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ .class_init =3D riscv_cpu_class_init, \ - .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ + .class_data =3D &((const RISCVCPUDef) { \ + .misa_mxl_max =3D (misa_mxl_max_), \ + }), \ } =20 static const TypeInfo riscv_cpu_type_infos[] =3D { --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826041701019100 Content-Type: text/plain; charset="utf-8" Prepare for adding more fields to RISCVCPUDef and reading them in riscv_cpu_init: instead of storing the misa_mxl_max field in RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct and go through it. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 2 +- hw/riscv/boot.c | 2 +- target/riscv/cpu.c | 23 ++++++++++++++++++----- target/riscv/gdbstub.c | 6 +++--- target/riscv/kvm/kvm-cpu.c | 21 +++++++++------------ target/riscv/machine.c | 2 +- target/riscv/tcg/tcg-cpu.c | 10 +++++----- target/riscv/translate.c | 2 +- 8 files changed, 39 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 62e303f0635..842c9d3f194 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -553,7 +553,7 @@ struct RISCVCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; - RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + RISCVCPUDef *def; }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 765b9e2b1ab..828a867be39 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -37,7 +37,7 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(&harts->harts[0]); - return mcc->misa_mxl_max =3D=3D MXL_RV32; + return mcc->def->misa_mxl_max =3D=3D MXL_RV32; } =20 /* diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f30cf1b532b..d8c189d596b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -357,7 +357,7 @@ void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_= t ext) =20 int riscv_cpu_max_xlen(RISCVCPUClass *mcc) { - return 16 << mcc->misa_mxl_max; + return 16 << mcc->def->misa_mxl_max; } =20 #ifndef CONFIG_USER_ONLY @@ -1048,7 +1048,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy= pe type) mcc->parent_phases.hold(obj, type); } #ifndef CONFIG_USER_ONLY - env->misa_mxl =3D mcc->misa_mxl_max; + env->misa_mxl =3D mcc->def->misa_mxl_max; env->priv =3D PRV_M; env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { @@ -1450,7 +1450,7 @@ static void riscv_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; =20 - env->misa_mxl =3D mcc->misa_mxl_max; + env->misa_mxl =3D mcc->def->misa_mxl_max; =20 #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, @@ -1544,7 +1544,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass= *mcc) CPUClass *cc =3D CPU_CLASS(mcc); =20 /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: case MXL_RV128: @@ -3071,12 +3071,24 @@ static void riscv_cpu_common_class_init(ObjectClass= *c, const void *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +static void riscv_cpu_class_base_init(ObjectClass *c, const void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + RISCVCPUClass *pcc =3D RISCV_CPU_CLASS(object_class_get_parent(c)); + + if (pcc->def) { + mcc->def =3D g_memdup2(pcc->def, sizeof(*pcc->def)); + } else { + mcc->def =3D g_new0(RISCVCPUDef, 1); + } +} + static void riscv_cpu_class_init(ObjectClass *c, const void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); const RISCVCPUDef *def =3D data; =20 - mcc->misa_mxl_max =3D def->misa_mxl_max; + mcc->def->misa_mxl_max =3D def->misa_mxl_max; riscv_cpu_validate_misa_mxl(mcc); } =20 @@ -3227,6 +3239,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_common_class_init, + .class_base_init =3D riscv_cpu_class_base_init, }, { .name =3D TYPE_RISCV_DYNAMIC_CPU, diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 18e88f416af..1934f919c01 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -62,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) return 0; } =20 - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: @@ -82,7 +82,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) int length =3D 0; target_ulong tmp; =20 - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: tmp =3D (int32_t)ldl_p(mem_buf); length =3D 4; @@ -359,7 +359,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs), 0); } - switch (mcc->misa_mxl_max) { + switch (mcc->def->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 75724b6af4f..41b6f34552a 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1997,22 +1997,19 @@ static void kvm_cpu_accel_register_types(void) } type_init(kvm_cpu_accel_register_types); =20 -static void riscv_host_cpu_class_init(ObjectClass *c, const void *data) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); - -#if defined(TARGET_RISCV32) - mcc->misa_mxl_max =3D MXL_RV32; -#elif defined(TARGET_RISCV64) - mcc->misa_mxl_max =3D MXL_RV64; -#endif -} - static const TypeInfo riscv_kvm_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU_HOST, .parent =3D TYPE_RISCV_CPU, - .class_init =3D riscv_host_cpu_class_init, +#if defined(TARGET_RISCV32) + .class_data =3D &((const RISCVCPUDef) { + .misa_mxl_max =3D MXL_RV32, + }, +#elif defined(TARGET_RISCV64) + .class_data =3D &((const RISCVCPUDef) { + .misa_mxl_max =3D MXL_RV64, + }, +#endif } }; =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index a1f70cc9556..c97e9ce9df1 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -170,7 +170,7 @@ static bool rv128_needed(void *opaque) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(opaque); =20 - return mcc->misa_mxl_max =3D=3D MXL_RV128; + return mcc->def->misa_mxl_max =3D=3D MXL_RV128; } =20 static const VMStateDescription vmstate_rv128 =3D { diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 1192b4e1545..f3ca61103c4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -592,7 +592,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) return; } =20 - if (mcc->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + if (mcc->def->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return; } @@ -689,7 +689,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) return; } =20 - if (mcc->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) { + if (mcc->def->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) { error_setg(errp, "svukte is not supported for RV32"); return; } @@ -927,7 +927,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); =20 - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max =3D=3D MXL_R= V32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } @@ -936,7 +936,7 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); =20 - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max =3D=3D MXL_R= V32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } =20 @@ -1062,7 +1062,7 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) #ifndef CONFIG_USER_ONLY RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); =20 - if (mcc->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled()) { + if (mcc->def->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled())= { /* Missing 128-bit aligned atomics */ error_setg(errp, "128-bit RISC-V currently does not work with Multi " diff --git a/target/riscv/translate.c b/target/riscv/translate.c index cef61b5b290..26ac7cdcaa1 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1282,7 +1282,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; ctx->vstart_eq_zero =3D FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); - ctx->misa_mxl_max =3D mcc->misa_mxl_max; + ctx->misa_mxl_max =3D mcc->def->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); 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Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826053460019100 Content-Type: text/plain; charset="utf-8" Since all TYPE_RISCV_CPU subclasses support a class_data of type RISCVCPUDef, process it even before calling the .class_init function for the subclasses. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d8c189d596b..0beaed2f340 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3081,15 +3081,18 @@ static void riscv_cpu_class_base_init(ObjectClass *= c, const void *data) } else { mcc->def =3D g_new0(RISCVCPUDef, 1); } -} =20 -static void riscv_cpu_class_init(ObjectClass *c, const void *data) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); - const RISCVCPUDef *def =3D data; + if (data) { + const RISCVCPUDef *def =3D data; + if (def->misa_mxl_max) { + assert(def->misa_mxl_max <=3D MXL_RV128); + mcc->def->misa_mxl_max =3D def->misa_mxl_max; + } + } =20 - mcc->def->misa_mxl_max =3D def->misa_mxl_max; - riscv_cpu_validate_misa_mxl(mcc); + if (!object_class_is_abstract(c)) { + riscv_cpu_validate_misa_mxl(mcc); + } } =20 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, @@ -3189,7 +3192,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ @@ -3200,7 +3202,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_VENDOR_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ @@ -3211,7 +3212,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ @@ -3222,7 +3222,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .name =3D (type_name), \ .parent =3D TYPE_RISCV_BARE_CPU, \ .instance_init =3D (initfn), \ - .class_init =3D riscv_cpu_class_init, \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ }), \ --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826049573019100 Content-Type: text/plain; charset="utf-8" To support merging a subclass's RISCVCPUDef into the superclass, a list of all the CPU features is needed. Put them into a header file that can be included multiple times, expanding the macros BOOL_FIELD and TYPE_FIELD to different operations. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h | 163 +--------------------------- target/riscv/cpu_cfg_fields.h.inc | 170 ++++++++++++++++++++++++++++++ 2 files changed, 173 insertions(+), 160 deletions(-) create mode 100644 target/riscv/cpu_cfg_fields.h.inc diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 8fa73c8a07d..e9bf75730a6 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -22,166 +22,9 @@ #define RISCV_CPU_CFG_H =20 struct RISCVCPUConfig { - bool ext_zba; - bool ext_zbb; - bool ext_zbc; - bool ext_zbkb; - bool ext_zbkc; - bool ext_zbkx; - bool ext_zbs; - bool ext_zca; - bool ext_zcb; - bool ext_zcd; - bool ext_zce; - bool ext_zcf; - bool ext_zcmp; - bool ext_zcmt; - bool ext_zk; - bool ext_zkn; - bool ext_zknd; - bool ext_zkne; - bool ext_zknh; - bool ext_zkr; - bool ext_zks; - bool ext_zksed; - bool ext_zksh; - bool ext_zkt; - bool ext_zifencei; - bool ext_zicntr; - bool ext_zicsr; - bool ext_zicbom; - bool ext_zicbop; - bool ext_zicboz; - bool ext_zicfilp; - bool ext_zicfiss; - bool ext_zicond; - bool ext_zihintntl; - bool ext_zihintpause; - bool ext_zihpm; - bool ext_zimop; - bool ext_zcmop; - bool ext_ztso; - bool ext_smstateen; - bool ext_sstc; - bool ext_smcdeleg; - bool ext_ssccfg; - bool ext_smcntrpmf; - bool ext_smcsrind; - bool ext_sscsrind; - bool ext_ssdbltrp; - bool ext_smdbltrp; - bool ext_svadu; - bool ext_svinval; - bool ext_svnapot; - bool ext_svpbmt; - bool ext_svvptc; - bool ext_svukte; - bool ext_zdinx; - bool ext_zaamo; - bool ext_zacas; - bool ext_zama16b; - bool ext_zabha; - bool ext_zalrsc; - bool ext_zawrs; - bool ext_zfa; - bool ext_zfbfmin; - bool ext_zfh; - bool ext_zfhmin; - bool ext_zfinx; - bool ext_zhinx; - bool ext_zhinxmin; - bool ext_zve32f; - bool ext_zve32x; - bool ext_zve64f; - bool ext_zve64d; - bool ext_zve64x; - bool ext_zvbb; - bool ext_zvbc; - bool ext_zvkb; - bool ext_zvkg; - bool ext_zvkned; - bool ext_zvknha; - bool ext_zvknhb; - bool ext_zvksed; - bool ext_zvksh; - bool ext_zvkt; - bool ext_zvkn; - bool ext_zvknc; - bool ext_zvkng; - bool ext_zvks; - bool ext_zvksc; - bool ext_zvksg; - bool ext_zmmul; - bool ext_zvfbfmin; - bool ext_zvfbfwma; - bool ext_zvfh; - bool ext_zvfhmin; - bool ext_smaia; - bool ext_ssaia; - bool ext_smctr; - bool ext_ssctr; - bool ext_sscofpmf; - bool ext_smepmp; - bool ext_smrnmi; - bool ext_ssnpm; - bool ext_smnpm; - bool ext_smmpm; - bool ext_sspm; - bool ext_supm; - bool rvv_ta_all_1s; - bool rvv_ma_all_1s; - bool rvv_vl_half_avl; - - uint32_t mvendorid; - uint64_t marchid; - uint64_t mimpid; - - /* Named features */ - bool ext_svade; - bool ext_zic64b; - bool ext_ssstateen; - bool ext_sha; - - /* - * Always 'true' booleans for named features - * TCG always implement/can't be user disabled, - * based on spec version. - */ - bool has_priv_1_13; - bool has_priv_1_12; - bool has_priv_1_11; - - /* Always enabled for TCG if has_priv_1_11 */ - bool ext_ziccrse; - - /* Vendor-specific custom extensions */ - bool ext_xtheadba; - bool ext_xtheadbb; - bool ext_xtheadbs; - bool ext_xtheadcmo; - bool ext_xtheadcondmov; - bool ext_xtheadfmemidx; - bool ext_xtheadfmv; - bool ext_xtheadmac; - bool ext_xtheadmemidx; - bool ext_xtheadmempair; - bool ext_xtheadsync; - bool ext_XVentanaCondOps; - - uint32_t pmu_mask; - uint16_t vlenb; - uint16_t elen; - uint16_t cbom_blocksize; - uint16_t cbop_blocksize; - uint16_t cboz_blocksize; - bool mmu; - bool pmp; - bool debug; - bool misa_w; - - bool short_isa_string; - - int8_t max_satp_mode; +#define BOOL_FIELD(x) bool x; +#define TYPED_FIELD(type, x) type x; +#include "cpu_cfg_fields.h.inc" }; =20 typedef struct RISCVCPUConfig RISCVCPUConfig; diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc new file mode 100644 index 00000000000..cb86bfc5dc3 --- /dev/null +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -0,0 +1,170 @@ +/* + * Required definitions before including this file: + * + * #define BOOL_FIELD(x) + * #define TYPED_FIELD(type, x) + */ + +BOOL_FIELD(ext_zba) +BOOL_FIELD(ext_zbb) +BOOL_FIELD(ext_zbc) +BOOL_FIELD(ext_zbkb) +BOOL_FIELD(ext_zbkc) +BOOL_FIELD(ext_zbkx) +BOOL_FIELD(ext_zbs) +BOOL_FIELD(ext_zca) +BOOL_FIELD(ext_zcb) +BOOL_FIELD(ext_zcd) +BOOL_FIELD(ext_zce) +BOOL_FIELD(ext_zcf) +BOOL_FIELD(ext_zcmp) +BOOL_FIELD(ext_zcmt) +BOOL_FIELD(ext_zk) +BOOL_FIELD(ext_zkn) +BOOL_FIELD(ext_zknd) +BOOL_FIELD(ext_zkne) +BOOL_FIELD(ext_zknh) +BOOL_FIELD(ext_zkr) +BOOL_FIELD(ext_zks) +BOOL_FIELD(ext_zksed) +BOOL_FIELD(ext_zksh) +BOOL_FIELD(ext_zkt) +BOOL_FIELD(ext_zifencei) +BOOL_FIELD(ext_zicntr) +BOOL_FIELD(ext_zicsr) +BOOL_FIELD(ext_zicbom) +BOOL_FIELD(ext_zicbop) +BOOL_FIELD(ext_zicboz) +BOOL_FIELD(ext_zicfilp) +BOOL_FIELD(ext_zicfiss) +BOOL_FIELD(ext_zicond) +BOOL_FIELD(ext_zihintntl) +BOOL_FIELD(ext_zihintpause) +BOOL_FIELD(ext_zihpm) +BOOL_FIELD(ext_zimop) +BOOL_FIELD(ext_zcmop) +BOOL_FIELD(ext_ztso) +BOOL_FIELD(ext_smstateen) +BOOL_FIELD(ext_sstc) +BOOL_FIELD(ext_smcdeleg) +BOOL_FIELD(ext_ssccfg) +BOOL_FIELD(ext_smcntrpmf) +BOOL_FIELD(ext_smcsrind) +BOOL_FIELD(ext_sscsrind) +BOOL_FIELD(ext_ssdbltrp) +BOOL_FIELD(ext_smdbltrp) +BOOL_FIELD(ext_svadu) +BOOL_FIELD(ext_svinval) +BOOL_FIELD(ext_svnapot) +BOOL_FIELD(ext_svpbmt) +BOOL_FIELD(ext_svvptc) +BOOL_FIELD(ext_svukte) +BOOL_FIELD(ext_zdinx) +BOOL_FIELD(ext_zaamo) +BOOL_FIELD(ext_zacas) +BOOL_FIELD(ext_zama16b) +BOOL_FIELD(ext_zabha) +BOOL_FIELD(ext_zalrsc) +BOOL_FIELD(ext_zawrs) +BOOL_FIELD(ext_zfa) +BOOL_FIELD(ext_zfbfmin) +BOOL_FIELD(ext_zfh) +BOOL_FIELD(ext_zfhmin) +BOOL_FIELD(ext_zfinx) +BOOL_FIELD(ext_zhinx) +BOOL_FIELD(ext_zhinxmin) +BOOL_FIELD(ext_zve32f) +BOOL_FIELD(ext_zve32x) +BOOL_FIELD(ext_zve64f) +BOOL_FIELD(ext_zve64d) +BOOL_FIELD(ext_zve64x) +BOOL_FIELD(ext_zvbb) +BOOL_FIELD(ext_zvbc) +BOOL_FIELD(ext_zvkb) +BOOL_FIELD(ext_zvkg) +BOOL_FIELD(ext_zvkned) +BOOL_FIELD(ext_zvknha) +BOOL_FIELD(ext_zvknhb) +BOOL_FIELD(ext_zvksed) +BOOL_FIELD(ext_zvksh) +BOOL_FIELD(ext_zvkt) +BOOL_FIELD(ext_zvkn) +BOOL_FIELD(ext_zvknc) +BOOL_FIELD(ext_zvkng) +BOOL_FIELD(ext_zvks) +BOOL_FIELD(ext_zvksc) +BOOL_FIELD(ext_zvksg) +BOOL_FIELD(ext_zmmul) +BOOL_FIELD(ext_zvfbfmin) +BOOL_FIELD(ext_zvfbfwma) +BOOL_FIELD(ext_zvfh) +BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_smaia) +BOOL_FIELD(ext_ssaia) +BOOL_FIELD(ext_smctr) +BOOL_FIELD(ext_ssctr) +BOOL_FIELD(ext_sscofpmf) +BOOL_FIELD(ext_smepmp) +BOOL_FIELD(ext_smrnmi) +BOOL_FIELD(ext_ssnpm) +BOOL_FIELD(ext_smnpm) +BOOL_FIELD(ext_smmpm) +BOOL_FIELD(ext_sspm) +BOOL_FIELD(ext_supm) +BOOL_FIELD(rvv_ta_all_1s) +BOOL_FIELD(rvv_ma_all_1s) +BOOL_FIELD(rvv_vl_half_avl) +/* Named features */ +BOOL_FIELD(ext_svade) +BOOL_FIELD(ext_zic64b) +BOOL_FIELD(ext_ssstateen) +BOOL_FIELD(ext_sha) + +/* + * Always 'true' booleans for named features + * TCG always implement/can't be user disabled, + * based on spec version. + */ +BOOL_FIELD(has_priv_1_13) +BOOL_FIELD(has_priv_1_12) +BOOL_FIELD(has_priv_1_11) + +/* Always enabled for TCG if has_priv_1_11 */ +BOOL_FIELD(ext_ziccrse) + +/* Vendor-specific custom extensions */ +BOOL_FIELD(ext_xtheadba) +BOOL_FIELD(ext_xtheadbb) +BOOL_FIELD(ext_xtheadbs) +BOOL_FIELD(ext_xtheadcmo) +BOOL_FIELD(ext_xtheadcondmov) +BOOL_FIELD(ext_xtheadfmemidx) +BOOL_FIELD(ext_xtheadfmv) +BOOL_FIELD(ext_xtheadmac) +BOOL_FIELD(ext_xtheadmemidx) +BOOL_FIELD(ext_xtheadmempair) +BOOL_FIELD(ext_xtheadsync) +BOOL_FIELD(ext_XVentanaCondOps) + +BOOL_FIELD(mmu) +BOOL_FIELD(pmp) +BOOL_FIELD(debug) +BOOL_FIELD(misa_w) + +BOOL_FIELD(short_isa_string) + +TYPED_FIELD(uint32_t, mvendorid) +TYPED_FIELD(uint64_t, marchid) +TYPED_FIELD(uint64_t, mimpid) + +TYPED_FIELD(uint32_t, pmu_mask) +TYPED_FIELD(uint16_t, vlenb) +TYPED_FIELD(uint16_t, elen) +TYPED_FIELD(uint16_t, cbom_blocksize) +TYPED_FIELD(uint16_t, cbop_blocksize) +TYPED_FIELD(uint16_t, cboz_blocksize) + +TYPED_FIELD(int8_t, max_satp_mode) + +#undef BOOL_FIELD +#undef TYPED_FIELD --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHTDHYQ2MZ5xlceN1dB7LsC3biw6dPnhpqstppnsYYv8rz6yoLgnmm3zyVeAylu+I9xyBiCqg== X-Received: by 2002:a05:600c:524a:b0:43c:fae1:5151 with SMTP id 5b1f17b1804b1-440ab8480b4mr60251785e9.25.1745825713616; Mon, 28 Apr 2025 00:35:13 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 11/26] target/riscv: include default value in cpu_cfg_fields.h.inc Date: Mon, 28 Apr 2025 09:34:26 +0200 Message-ID: <20250428073442.315770-12-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745825967533019000 Content-Type: text/plain; charset="utf-8" In preparation for adding a function to merge two RISCVCPUConfigs (pulling values from the parent if they are not overridden) annotate cpu_cfg_fields.h.inc with the default value of the fields. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu_cfg.h | 2 +- target/riscv/cpu_cfg_fields.h.inc | 22 +++++++++++----------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e9bf75730a6..aa28dc8d7e6 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -23,7 +23,7 @@ =20 struct RISCVCPUConfig { #define BOOL_FIELD(x) bool x; -#define TYPED_FIELD(type, x) type x; +#define TYPED_FIELD(type, x, default) type x; #include "cpu_cfg_fields.h.inc" }; =20 diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index cb86bfc5dc3..59f134a4192 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -2,7 +2,7 @@ * Required definitions before including this file: * * #define BOOL_FIELD(x) - * #define TYPED_FIELD(type, x) + * #define TYPED_FIELD(type, x, default) */ =20 BOOL_FIELD(ext_zba) @@ -153,18 +153,18 @@ BOOL_FIELD(misa_w) =20 BOOL_FIELD(short_isa_string) =20 -TYPED_FIELD(uint32_t, mvendorid) -TYPED_FIELD(uint64_t, marchid) -TYPED_FIELD(uint64_t, mimpid) +TYPED_FIELD(uint32_t, mvendorid, 0) +TYPED_FIELD(uint64_t, marchid, 0) +TYPED_FIELD(uint64_t, mimpid, 0) =20 -TYPED_FIELD(uint32_t, pmu_mask) -TYPED_FIELD(uint16_t, vlenb) -TYPED_FIELD(uint16_t, elen) -TYPED_FIELD(uint16_t, cbom_blocksize) -TYPED_FIELD(uint16_t, cbop_blocksize) -TYPED_FIELD(uint16_t, cboz_blocksize) +TYPED_FIELD(uint32_t, pmu_mask, 0) +TYPED_FIELD(uint16_t, vlenb, 0) +TYPED_FIELD(uint16_t, elen, 0) +TYPED_FIELD(uint16_t, cbom_blocksize, 0) +TYPED_FIELD(uint16_t, cbop_blocksize, 0) +TYPED_FIELD(uint16_t, cboz_blocksize, 0) =20 -TYPED_FIELD(int8_t, max_satp_mode) +TYPED_FIELD(int8_t, max_satp_mode, -1) =20 #undef BOOL_FIELD #undef TYPED_FIELD --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGZsw+qjimAYNtW9HD0kljb/W6caZ+A/vrXcPNCi3ul1UrqhJKFVJoj+V+/Nvr2Fe8ncn96uQ== X-Received: by 2002:adf:ec87:0:b0:39c:1257:c96f with SMTP id ffacd0b85a97d-3a07adb1766mr4206226f8f.59.1745825715603; Mon, 28 Apr 2025 00:35:15 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 12/26] target/riscv: add more RISCVCPUDef fields Date: Mon, 28 Apr 2025 09:34:27 +0200 Message-ID: <20250428073442.315770-13-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826105370019100 Content-Type: text/plain; charset="utf-8" Allow using RISCVCPUDef to replicate all the logic of custom .instance_init functions. To simulate inheritance, merge the child's RISCVCPUDef with the parent and then finally move it to the CPUState at the end of TYPE_RISCV_CPU's own instance_init function. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 42 +++++++++++++++++++++++++++++++++++++- target/riscv/kvm/kvm-cpu.c | 6 ++++++ 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 842c9d3f194..5015763b7f4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -539,6 +539,10 @@ struct ArchCPU { =20 typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + uint32_t misa_ext; + int priv_spec; + int32_t vext_spec; + RISCVCPUConfig cfg; } RISCVCPUDef; =20 /** diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0beaed2f340..de831c8004d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -74,6 +74,13 @@ bool riscv_cpu_option_set(const char *optname) return g_hash_table_contains(general_user_opts, optname); } =20 +static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConfig= *src) +{ +#define BOOL_FIELD(x) dest->x |=3D src->x; +#define TYPED_FIELD(type, x, default_) if (src->x !=3D default_) dest->x = =3D src->x; +#include "cpu_cfg_fields.h.inc" +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -435,7 +442,7 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32= _bit) } =20 static void set_satp_mode_max_supported(RISCVCPU *cpu, - uint8_t satp_mode) + int satp_mode) { bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; @@ -1480,6 +1487,16 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cboz_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; cpu->cfg.max_satp_mode =3D -1; + + env->misa_ext_mask =3D env->misa_ext =3D mcc->def->misa_ext; + riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); + + if (mcc->def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + cpu->env.priv_ver =3D mcc->def->priv_spec; + } + if (mcc->def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + cpu->env.vext_ver =3D mcc->def->vext_spec; + } } =20 static void riscv_bare_cpu_init(Object *obj) @@ -3088,6 +3105,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; } + if (def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + assert(def->priv_spec <=3D PRIV_VERSION_LATEST); + mcc->def->priv_spec =3D def->priv_spec; + } + if (def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { + assert(def->vext_spec !=3D 0); + mcc->def->vext_spec =3D def->vext_spec; + } + mcc->def->misa_ext |=3D def->misa_ext; + + riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg); } =20 if (!object_class_is_abstract(c)) { @@ -3194,6 +3222,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .instance_init =3D (initfn), \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode =3D -1, \ }), \ } =20 @@ -3204,6 +3235,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .instance_init =3D (initfn), \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode =3D -1, \ }), \ } =20 @@ -3214,6 +3248,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .instance_init =3D (initfn), \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode =3D -1, \ }), \ } =20 @@ -3224,6 +3261,9 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, ch= ar *nodename) .instance_init =3D (initfn), \ .class_data =3D &((const RISCVCPUDef) { \ .misa_mxl_max =3D (misa_mxl_max_), \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode =3D -1, \ }), \ } =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 41b6f34552a..644b05988af 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -2004,10 +2004,16 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = =3D { #if defined(TARGET_RISCV32) .class_data =3D &((const RISCVCPUDef) { .misa_mxl_max =3D MXL_RV32, + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, + .cfg.max_satp_mode =3D -1, }, #elif defined(TARGET_RISCV64) .class_data =3D &((const RISCVCPUDef) { .misa_mxl_max =3D MXL_RV64, + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, + .cfg.max_satp_mode =3D -1, }, #endif } --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IERw9boEc2ptjITRbuQEqSI8VEJ9VpNYIQnG41q7rly483+1g5+/fkaWW0Jw5V9UMv8dSGmCQ== X-Received: by 2002:a05:600c:3111:b0:43c:ee3f:2c3 with SMTP id 5b1f17b1804b1-440a64c179emr90664155e9.7.1745825717808; Mon, 28 Apr 2025 00:35:17 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 13/26] target/riscv: convert abstract CPU classes to RISCVCPUDef Date: Mon, 28 Apr 2025 09:34:28 +0200 Message-ID: <20250428073442.315770-14-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826055365019100 Content-Type: text/plain; charset="utf-8" Start from the top of the hierarchy: dynamic and vendor CPUs are just markers, whereas bare CPUs can have their instance_init function replaced by RISCVCPUDef. The only difference is that the maximum supported SATP mode has to be specified separately for 32-bit and 64-bit modes. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 93 ++++++++++++++++++++++------------------------ 2 files changed, 46 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5015763b7f4..b2744b66030 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -543,6 +543,7 @@ typedef struct RISCVCPUDef { int priv_spec; int32_t vext_spec; RISCVCPUConfig cfg; + bool bare; } RISCVCPUDef; =20 /** diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index de831c8004d..0876b8a959c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1475,8 +1475,8 @@ static void riscv_cpu_init(Object *obj) * for all CPUs. Each accelerator will decide what to do when * users disable them. */ - RISCV_CPU(obj)->cfg.ext_zicntr =3D true; - RISCV_CPU(obj)->cfg.ext_zihpm =3D true; + RISCV_CPU(obj)->cfg.ext_zicntr =3D !mcc->def->bare; + RISCV_CPU(obj)->cfg.ext_zihpm =3D !mcc->def->bare; =20 /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); @@ -1499,36 +1499,6 @@ static void riscv_cpu_init(Object *obj) } } =20 -static void riscv_bare_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - - /* - * Bare CPUs do not inherit the timer and performance - * counters from the parent class (see riscv_cpu_init() - * for info on why the parent enables them). - * - * Users have to explicitly enable these counters for - * bare CPUs. - */ - cpu->cfg.ext_zicntr =3D false; - cpu->cfg.ext_zihpm =3D false; - - /* Set to QEMU's first supported priv version */ - cpu->env.priv_ver =3D PRIV_VERSION_1_10_0; - - /* - * Support all available satp_mode settings. The default - * value will be set to MBARE if the user doesn't set - * satp_mode manually (see set_satp_mode_default()). - */ -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), - riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); -#endif -} - typedef struct misa_ext_info { const char *name; const char *description; @@ -3101,6 +3071,7 @@ static void riscv_cpu_class_base_init(ObjectClass *c,= const void *data) =20 if (data) { const RISCVCPUDef *def =3D data; + mcc->def->bare |=3D def->bare; if (def->misa_mxl_max) { assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; @@ -3254,6 +3225,19 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) }), \ } =20 +#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ + { \ + .name =3D (type_name), \ + .parent =3D (parent_type_name), \ + .abstract =3D true, \ + .class_data =3D &((const RISCVCPUDef) { \ + .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ + .cfg.max_satp_mode =3D -1, \ + __VA_ARGS__ \ + }), \ + } + #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ @@ -3280,22 +3264,35 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_init =3D riscv_cpu_common_class_init, .class_base_init =3D riscv_cpu_class_base_init, }, - { - .name =3D TYPE_RISCV_DYNAMIC_CPU, - .parent =3D TYPE_RISCV_CPU, - .abstract =3D true, - }, - { - .name =3D TYPE_RISCV_VENDOR_CPU, - .parent =3D TYPE_RISCV_CPU, - .abstract =3D true, - }, - { - .name =3D TYPE_RISCV_BARE_CPU, - .parent =3D TYPE_RISCV_CPU, - .instance_init =3D riscv_bare_cpu_init, - .abstract =3D true, - }, + + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU, + /* + * Bare CPUs do not inherit the timer and performance + * counters from the parent class (see riscv_cpu_init() + * for info on why the parent enables them). + * + * Users have to explicitly enable these counters for + * bare CPUs. + */ + .bare =3D true, + + /* Set to QEMU's first supported priv version */ + .priv_spec =3D PRIV_VERSION_1_10_0, + + /* + * Support all available satp_mode settings. By default + * only MBARE will be available if the user doesn't enable + * a mode manually (see riscv_cpu_satp_mode_finalize()). + */ +#ifdef TARGET_RISCV32 + .cfg.max_satp_mode =3D VM_1_10_SV32, +#else + .cfg.max_satp_mode =3D VM_1_10_SV57, +#endif + ), + #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_= init), #elif defined(TARGET_RISCV64) --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1745826071; cv=none; d=zohomail.com; s=zohoarc; b=fsAyWwig3jce9HXE3bmUJ9Q1FGuG/vUZ6NRr4gIkkUWxQLRlpfkq0QrG+tBBUxATkyAxjKU+VoxwHDjyX3PU3bnEWMfl2BY9y0BRwWtEAMxYDdEhQOSysphXOslEBvg3HQ8mrVjbJnh/7XBCvNGh6dQ/ahCB04df91gdMArbboM= ARC-Message-Signature: i=1; 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Mon, 28 Apr 2025 00:35:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE+prVP/unTuBqXIsRPRxO9fECe6oI2LgCbCm10u5E5Eas2pfUnn9xM2Xrc8f45Y3J7PsJCXg== X-Received: by 2002:a05:6000:2504:b0:391:3f4f:a17f with SMTP id ffacd0b85a97d-3a074f397demr7074723f8f.42.1745825720299; Mon, 28 Apr 2025 00:35:20 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 14/26] target/riscv: convert profile CPU models to RISCVCPUDef Date: Mon, 28 Apr 2025 09:34:29 +0200 Message-ID: <20250428073442.315770-15-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826073290019100 Content-Type: text/plain; charset="utf-8" Profile CPUs reuse the instance_init function for bare CPUs; make them proper subclasses instead. Enabling a profile is now done based on the RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef, subclasses check that the parent class's profile is enabled through the parent profile mechanism. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 85 +++++++++++++++++++++++++--------------------- 2 files changed, 48 insertions(+), 38 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b2744b66030..38fd667aba6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -539,6 +539,7 @@ struct ArchCPU { =20 typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ + RISCVCPUProfile *profile; uint32_t misa_ext; int priv_spec; int32_t vext_spec; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0876b8a959c..c07ce5ddb9b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1488,6 +1488,10 @@ static void riscv_cpu_init(Object *obj) cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; cpu->cfg.max_satp_mode =3D -1; =20 + if (mcc->def->profile) { + mcc->def->profile->enabled =3D true; + } + env->misa_ext_mask =3D env->misa_ext =3D mcc->def->misa_ext; riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg); =20 @@ -2960,36 +2964,6 @@ static const Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), }; =20 -#if defined(TARGET_RISCV64) -static void rva22u64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA22U64.enabled =3D true; -} - -static void rva22s64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA22S64.enabled =3D true; -} - -static void rva23u64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA23U64.enabled =3D true; -} - -static void rva23s64_profile_cpu_init(Object *obj) -{ - rv64i_bare_cpu_init(obj); - - RVA23S64.enabled =3D true; -} -#endif - static const gchar *riscv_gdb_arch_name(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -3058,6 +3032,32 @@ static void riscv_cpu_common_class_init(ObjectClass = *c, const void *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +static bool profile_extends(RISCVCPUProfile *trial, RISCVCPUProfile *paren= t) +{ + RISCVCPUProfile *curr; + if (!parent) { + return true; + } + + curr =3D trial; + while (curr) { + if (curr =3D=3D parent) { + return true; + } + curr =3D curr->u_parent; + } + + curr =3D trial; + while (curr) { + if (curr =3D=3D parent) { + return true; + } + curr =3D curr->s_parent; + } + + return false; +} + static void riscv_cpu_class_base_init(ObjectClass *c, const void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -3072,6 +3072,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) if (data) { const RISCVCPUDef *def =3D data; mcc->def->bare |=3D def->bare; + if (def->profile) { + assert(profile_extends(def->profile, mcc->def->profile)); + assert(mcc->def->bare); + mcc->def->profile =3D def->profile; + } if (def->misa_mxl_max) { assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; @@ -3238,19 +3243,22 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) }), \ } =20 -#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ +#define DEFINE_RISCV_CPU(type_name, parent_type_name, ...) \ { \ .name =3D (type_name), \ - .parent =3D TYPE_RISCV_BARE_CPU, \ - .instance_init =3D (initfn), \ + .parent =3D (parent_type_name), \ .class_data =3D &((const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ .cfg.max_satp_mode =3D -1, \ + __VA_ARGS__ \ }), \ } =20 +#define DEFINE_PROFILE_CPU(type_name, parent_type_name, profile_) \ + DEFINE_RISCV_CPU(type_name, parent_type_name, \ + .profile =3D &(profile_)) + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -3329,10 +3337,11 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu= _init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profi= le_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profi= le_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, MXL_RV64, rva23s64_profi= le_cpu_init), + + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RV= A22U64), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RV= A22S64), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, TYPE_RISCV_CPU_RV64I, RV= A23U64), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, TYPE_RISCV_CPU_RV64I, RV= A23S64), #endif /* TARGET_RISCV64 */ }; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826031208019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 58 ++++++++++++++-------------------------------- 1 file changed, 17 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c07ce5ddb9b..93992be6c4d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -733,18 +733,6 @@ static void rv128_base_cpu_init(Object *obj) } #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 -static void rv64i_bare_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - riscv_cpu_set_misa_ext(env, RVI); -} - -static void rv64e_bare_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - riscv_cpu_set_misa_ext(env, RVE); -} - #endif /* !TARGET_RISCV64 */ =20 #if defined(TARGET_RISCV32) || \ @@ -837,18 +825,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) cpu->cfg.ext_zicsr =3D true; cpu->cfg.pmp =3D true; } - -static void rv32i_bare_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - riscv_cpu_set_misa_ext(env, RVI); -} - -static void rv32e_bare_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - riscv_cpu_set_misa_ext(env, RVE); -} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -3217,19 +3193,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) }), \ } =20 -#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \ - { \ - .name =3D (type_name), \ - .parent =3D TYPE_RISCV_BARE_CPU, \ - .instance_init =3D (initfn), \ - .class_data =3D &((const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ - .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ - .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ - .cfg.max_satp_mode =3D -1, \ - }), \ - } - #define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ { \ .name =3D (type_name), \ @@ -3314,8 +3277,15 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_no= mmu_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_= cpu_init), - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu= _init), - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu= _init), + + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU, + .misa_mxl_max =3D MXL_RV32, + .misa_ext =3D RVI + ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU, + .misa_mxl_max =3D MXL_RV32, + .misa_ext =3D RVE + ), #endif =20 #if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) @@ -3335,8 +3305,14 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu= _init), - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVI + ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVE + ), =20 DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, RV= A22U64), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, RV= A22S64), --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745825853279019000 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 113 +++++++++++++-------------------------------- 1 file changed, 31 insertions(+), 82 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 93992be6c4d..56f292a3616 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -486,38 +486,7 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 -static void riscv_max_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), - riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); -#endif -} - #if defined(TARGET_RISCV64) -static void rv64_base_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); -#endif -} - static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -718,41 +687,11 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj) #endif } =20 -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) -static void rv128_base_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_LATEST; - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); -} -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ - #endif /* !TARGET_RISCV64 */ =20 #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) =20 -static void rv32_base_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - - /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); -#endif -} - static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -3167,19 +3106,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) } #endif =20 -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \ - { \ - .name =3D (type_name), \ - .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ - .instance_init =3D (initfn), \ - .class_data =3D &((const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ - .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ - .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ - .cfg.max_satp_mode =3D -1, \ - }), \ - } - #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name =3D (type_name), \ @@ -3236,7 +3162,12 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_base_init =3D riscv_cpu_class_base_init, }, =20 - DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_DYNAMIC_CPU, TYPE_RISCV_CPU, + .cfg.mmu =3D true, + .cfg.pmp =3D true, + .priv_spec =3D PRIV_VERSION_LATEST, + ), + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_VENDOR_CPU, TYPE_RISCV_CPU), DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_BARE_CPU, TYPE_RISCV_CPU, /* @@ -3264,15 +3195,23 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX, TYPE_RISCV_DYNAMIC_CPU, #if defined(TARGET_RISCV32) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_= init), + .misa_mxl_max =3D MXL_RV32, + .cfg.max_satp_mode =3D VM_1_10_SV32, #elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_= init), + .misa_mxl_max =3D MXL_RV64, + .cfg.max_satp_mode =3D VM_1_10_SV57, #endif + ), =20 #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV32, + .misa_mxl_max =3D MXL_RV32, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_no= mmu_cpu_init), @@ -3289,11 +3228,18 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif =20 #if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_MAX32, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV32, + .misa_mxl_max =3D MXL_RV32, + ), #endif =20 #if defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV57, + .misa_mxl_max =3D MXL_RV64, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), @@ -3303,8 +3249,11 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, + .cfg.max_satp_mode =3D VM_1_10_SV57, + .misa_mxl_max =3D MXL_RV128, + ), +#endif /* CONFIG_TCG */ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU, .misa_mxl_max =3D MXL_RV64, .misa_ext =3D RVI --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IErLykpvcE+rTPzvix421zI3DhygvOnBCz6y1HoZL8j3uBIKK0Kx4kOfmLMla6hf/BJQn/GVA== X-Received: by 2002:a5d:5f8f:0:b0:38d:b325:471f with SMTP id ffacd0b85a97d-3a074e23241mr7857749f8f.15.1745825727937; Mon, 28 Apr 2025 00:35:27 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 17/26] target/riscv: convert SiFive E CPU models to RISCVCPUDef Date: Mon, 28 Apr 2025 09:34:32 +0200 Message-ID: <20250428073442.315770-18-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826057265019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 74 ++++++++++++------------------------------ 2 files changed, 21 insertions(+), 54 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 4cfdb74891e..0f9be15e47b 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -44,6 +44,7 @@ #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") +#define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 56f292a3616..5b4ffc285da 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -504,23 +504,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) cpu->cfg.pmp =3D true; } =20 -static void rv64_sifive_e_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_MBARE); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; -} - static void rv64_thead_c906_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -709,23 +692,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) cpu->cfg.pmp =3D true; } =20 -static void rv32_sifive_e_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_MBARE); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; -} - static void rv32_ibex_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -747,23 +713,6 @@ static void rv32_ibex_cpu_init(Object *obj) cpu->cfg.ext_zbc =3D true; cpu->cfg.ext_zbs =3D true; } - -static void rv32_imafcu_nommu_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_MBARE); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; -} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -3205,6 +3154,15 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E, TYPE_RISCV_VENDOR_C= PU, + .misa_ext =3D RVI | RVM | RVA | RVC | RVU, + .priv_spec =3D PRIV_VERSION_1_10_0, + .cfg.max_satp_mode =3D VM_1_10_MBARE, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.pmp =3D true + ), + #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, @@ -3213,8 +3171,14 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { ), =20 DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_no= mmu_cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E, + .misa_mxl_max =3D MXL_RV32 + ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E34, TYPE_RISCV_CPU_SIFIVE_E, + .misa_mxl_max =3D MXL_RV32, + .misa_ext =3D RVF, /* IMAFCU */ + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_= cpu_init), =20 DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU, @@ -3240,7 +3204,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_mxl_max =3D MXL_RV64, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E, + .misa_mxl_max =3D MXL_RV64 + ), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90= 6_cpu_init), --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFx38+L21r/+GEBmBnJ5X2/aCYEYBoqtF1ct4+8YCieECdi6MZwi9PizceCv0NS3k+90frSNg== X-Received: by 2002:a05:6000:1868:b0:39e:e438:8e4b with SMTP id ffacd0b85a97d-3a074f792b4mr8154573f8f.50.1745825730145; Mon, 28 Apr 2025 00:35:30 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 18/26] target/riscv: convert ibex CPU models to RISCVCPUDef Date: Mon, 28 Apr 2025 09:34:33 +0200 Message-ID: <20250428073442.315770-19-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745825971263019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 39 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5b4ffc285da..4f531711655 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -691,28 +691,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; } - -static void rv32_ibex_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU); - env->priv_ver =3D PRIV_VERSION_1_12_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_MBARE); -#endif - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; - cpu->cfg.ext_smepmp =3D true; - - cpu->cfg.ext_zba =3D true; - cpu->cfg.ext_zbb =3D true; - cpu->cfg.ext_zbc =3D true; - cpu->cfg.ext_zbs =3D true; -} #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -3170,7 +3148,22 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_mxl_max =3D MXL_RV32, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV32, + .misa_ext =3D RVI | RVM | RVC | RVU, + .priv_spec =3D PRIV_VERSION_1_12_0, + .cfg.max_satp_mode =3D VM_1_10_MBARE, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.pmp =3D true, + .cfg.ext_smepmp =3D true, + + .cfg.ext_zba =3D true, + .cfg.ext_zbb =3D true, + .cfg.ext_zbc =3D true, + .cfg.ext_zbs =3D true + ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E, .misa_mxl_max =3D MXL_RV32 ), --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826242620019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 79 +++++++++++++++++++----------------------- 2 files changed, 37 insertions(+), 43 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 0f9be15e47b..1ee05eb393d 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -48,6 +48,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") +#define TYPE_RISCV_CPU_SIFIVE_U RISCV_CPU_TYPE_NAME("sifive-u") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4f531711655..9a28f590c45 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -441,8 +441,8 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32= _bit) g_assert_not_reached(); } =20 -static void set_satp_mode_max_supported(RISCVCPU *cpu, - int satp_mode) +static void __attribute__((unused)) +set_satp_mode_max_supported(RISCVCPU *cpu, int satp_mode) { bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; @@ -487,23 +487,6 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) #endif =20 #if defined(TARGET_RISCV64) -static void rv64_sifive_u_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; -} - static void rv64_thead_c906_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -672,27 +655,6 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj) =20 #endif /* !TARGET_RISCV64 */ =20 -#if defined(TARGET_RISCV32) || \ - (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) - -static void rv32_sifive_u_cpu_init(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); - env->priv_ver =3D PRIV_VERSION_1_10_0; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; -} -#endif - static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -2922,6 +2884,17 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) if (def->misa_mxl_max) { assert(def->misa_mxl_max <=3D MXL_RV128); mcc->def->misa_mxl_max =3D def->misa_mxl_max; + +#ifndef CONFIG_USER_ONLY + /* + * Hack to simplify CPU class hierarchies that include both 32= - and + * 64-bit models: reduce SV39/48/57/64 to SV32 for 32-bit mode= ls. + */ + if (mcc->def->misa_mxl_max =3D=3D MXL_RV32 && + !valid_vm_1_10_32[mcc->def->cfg.max_satp_mode]) { + mcc->def->cfg.max_satp_mode =3D VM_1_10_SV32; + } +#endif } if (def->priv_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { assert(def->priv_spec <=3D PRIV_VERSION_LATEST); @@ -3141,6 +3114,17 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.pmp =3D true ), =20 + DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U, TYPE_RISCV_VENDOR_C= PU, + .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU, + .priv_spec =3D PRIV_VERSION_1_10_0, + + .cfg.max_satp_mode =3D VM_1_10_SV39, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.mmu =3D true, + .cfg.pmp =3D true + ), + #if defined(TARGET_RISCV32) || \ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU, @@ -3172,7 +3156,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_ext =3D RVF, /* IMAFCU */ ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_= cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U34, TYPE_RISCV_CPU_SIFIVE_U, + .misa_mxl_max =3D MXL_RV32, + ), =20 DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU, .misa_mxl_max =3D MXL_RV32, @@ -3200,8 +3186,15 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E, .misa_mxl_max =3D MXL_RV64 ), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), + + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U54, TYPE_RISCV_CPU_SIFIVE_U, + .misa_mxl_max =3D MXL_RV64, + ), + + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SHAKTI_C, TYPE_RISCV_CPU_SIFIVE_U, + .misa_mxl_max =3D MXL_RV64, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90= 6_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo= n_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEsgg2c45KIzdjb//p8F4NcdZJkmEEbAN/XL0QZHdqNH9Otv0Tth1ekIO5tkatzobSnkvLi+w== X-Received: by 2002:a05:6000:2207:b0:3a0:839b:f52c with SMTP id ffacd0b85a97d-3a0839bf543mr2116738f8f.0.1745825734514; Mon, 28 Apr 2025 00:35:34 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 20/26] target/riscv: th: make CSR insertion test a bit more intuitive Date: Mon, 28 Apr 2025 09:34:35 +0200 Message-ID: <20250428073442.315770-21-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826073984019000 Content-Type: text/plain; charset="utf-8" In preparation for generalizing the custom CSR functionality, make the test return bool instead of int. Make the insertion_test optional, too. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/th_csr.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c index 6c970d4e813..969a9fe3c80 100644 --- a/target/riscv/th_csr.c +++ b/target/riscv/th_csr.c @@ -29,7 +29,7 @@ =20 typedef struct { int csrno; - int (*insertion_test)(RISCVCPU *cpu); + bool (*insertion_test)(RISCVCPU *cpu); riscv_csr_operations csr_ops; } riscv_csr; =20 @@ -42,13 +42,9 @@ static RISCVException smode(CPURISCVState *env, int csrn= o) return RISCV_EXCP_ILLEGAL_INST; } =20 -static int test_thead_mvendorid(RISCVCPU *cpu) +static bool test_thead_mvendorid(RISCVCPU *cpu) { - if (cpu->cfg.mvendorid !=3D THEAD_VENDOR_ID) { - return -1; - } - - return 0; + return cpu->cfg.mvendorid =3D=3D THEAD_VENDOR_ID; } =20 static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno, @@ -66,13 +62,12 @@ static riscv_csr th_csr_list[] =3D { .csr_ops =3D { "th.sxstatus", smode, read_th_sxstatus } } }; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745825771757019000 Content-Type: text/plain; charset="utf-8" While at it, constify it so that the RISCVCSR array in RISCVCPUDef can also be const. Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.h | 15 ++++++++++++--- target/riscv/cpu.c | 25 ++++++++++++++++++++++++- target/riscv/csr.c | 2 +- target/riscv/th_csr.c | 21 +++------------------ 4 files changed, 40 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 38fd667aba6..238687c635c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -537,6 +537,8 @@ struct ArchCPU { const GPtrArray *decoders; }; =20 +typedef struct RISCVCSR RISCVCSR; + typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ RISCVCPUProfile *profile; @@ -545,6 +547,7 @@ typedef struct RISCVCPUDef { int32_t vext_spec; RISCVCPUConfig cfg; bool bare; + const RISCVCSR *custom_csrs; } RISCVCPUDef; =20 /** @@ -894,6 +897,12 @@ typedef struct { uint32_t min_priv_ver; } riscv_csr_operations; =20 +struct RISCVCSR { + int csrno; + bool (*insertion_test)(RISCVCPU *cpu); + riscv_csr_operations csr_ops; +}; + /* CSR function table constants */ enum { CSR_TABLE_SIZE =3D 0x1000 @@ -948,7 +957,7 @@ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; =20 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); -void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); +void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 @@ -957,8 +966,8 @@ target_ulong riscv_new_csr_seed(target_ulong new_value, =20 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); =20 -/* Implemented in th_csr.c */ -void th_register_custom_csrs(RISCVCPU *cpu); +/* In th_csr.c */ +extern const RISCVCSR th_csr_list[]; =20 const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9a28f590c45..5045ebc0b70 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -486,6 +486,19 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 +#ifndef CONFIG_USER_ONLY +static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_= list) +{ + for (size_t i =3D 0; csr_list[i].csr_ops.name; i++) { + int csrno =3D csr_list[i].csrno; + const riscv_csr_operations *csr_ops =3D &csr_list[i].csr_ops; + if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)= ) { + riscv_set_csr_ops(csrno, csr_ops); + } + } +} +#endif + #if defined(TARGET_RISCV64) static void rv64_thead_c906_cpu_init(Object *obj) { @@ -512,7 +525,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); - th_register_custom_csrs(cpu); + riscv_register_custom_csrs(cpu, th_csr_list); #endif =20 /* inherited from parent obj via riscv_cpu_init() */ @@ -1305,6 +1318,11 @@ static void riscv_cpu_init(Object *obj) if (mcc->def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { cpu->env.vext_ver =3D mcc->def->vext_spec; } +#ifndef CONFIG_USER_ONLY + if (mcc->def->custom_csrs) { + riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); + } +#endif } =20 typedef struct misa_ext_info { @@ -2907,6 +2925,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) mcc->def->misa_ext |=3D def->misa_ext; =20 riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg); + + if (def->custom_csrs) { + assert(!mcc->def->custom_csrs); + mcc->def->custom_csrs =3D def->custom_csrs; + } } =20 if (!object_class_is_abstract(c)) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 038be009c82..e85b3aedf6e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -38,7 +38,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operations *o= ps) *ops =3D csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; } =20 -void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) +void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops) { csr_ops[csrno & (CSR_TABLE_SIZE - 1)] =3D *ops; } diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c index 969a9fe3c80..49eb7bbab5f 100644 --- a/target/riscv/th_csr.c +++ b/target/riscv/th_csr.c @@ -27,12 +27,6 @@ #define TH_SXSTATUS_MAEE BIT(21) #define TH_SXSTATUS_THEADISAEE BIT(22) =20 -typedef struct { - int csrno; - bool (*insertion_test)(RISCVCPU *cpu); - riscv_csr_operations csr_ops; -} riscv_csr; - static RISCVException smode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS)) { @@ -55,20 +49,11 @@ static RISCVException read_th_sxstatus(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 -static riscv_csr th_csr_list[] =3D { +const RISCVCSR th_csr_list[] =3D { { .csrno =3D CSR_TH_SXSTATUS, .insertion_test =3D test_thead_mvendorid, .csr_ops =3D { "th.sxstatus", smode, read_th_sxstatus } - } + }, + { } }; -void th_register_custom_csrs(RISCVCPU *cpu) -{ - for (size_t i =3D 0; i < ARRAY_SIZE(th_csr_list); i++) { - int csrno =3D th_csr_list[i].csrno; - riscv_csr_operations *csr_ops =3D &th_csr_list[i].csr_ops; - if (!th_csr_list[i].insertion_test || th_csr_list[i].insertion_tes= t(cpu)) { - riscv_set_csr_ops(csrno, csr_ops); - } - } -} --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 28 Apr 2025 00:35:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHHPLP5Osvhw2u8Qn2QSqnWmojUDqfuPIMO4IbPwvgW5wfMhymVOD5pNqmmj/D8ZtDPb1UVvw== X-Received: by 2002:a05:600c:1e29:b0:440:6a1a:d8a0 with SMTP id 5b1f17b1804b1-440ab7827f3mr60986515e9.7.1745825738770; Mon, 28 Apr 2025 00:35:38 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 22/26] target/riscv: convert TT C906 to RISCVCPUDef Date: Mon, 28 Apr 2025 09:34:37 +0200 Message-ID: <20250428073442.315770-23-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826037218019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 61 +++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5045ebc0b70..f3af9643af4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -500,38 +500,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, = const RISCVCSR *csr_list) #endif =20 #if defined(TARGET_RISCV64) -static void rv64_thead_c906_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); - env->priv_ver =3D PRIV_VERSION_1_11_0; - - cpu->cfg.ext_zfa =3D true; - cpu->cfg.ext_zfh =3D true; - cpu->cfg.mmu =3D true; - cpu->cfg.ext_xtheadba =3D true; - cpu->cfg.ext_xtheadbb =3D true; - cpu->cfg.ext_xtheadbs =3D true; - cpu->cfg.ext_xtheadcmo =3D true; - cpu->cfg.ext_xtheadcondmov =3D true; - cpu->cfg.ext_xtheadfmemidx =3D true; - cpu->cfg.ext_xtheadmac =3D true; - cpu->cfg.ext_xtheadmemidx =3D true; - cpu->cfg.ext_xtheadmempair =3D true; - cpu->cfg.ext_xtheadsync =3D true; - - cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV39); - riscv_register_custom_csrs(cpu, th_csr_list); -#endif - - /* inherited from parent obj via riscv_cpu_init() */ - cpu->cfg.pmp =3D true; -} - static void rv64_veyron_v1_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -3218,7 +3186,34 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .misa_mxl_max =3D MXL_RV64, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90= 6_cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVS | RVU, + .priv_spec =3D PRIV_VERSION_1_11_0, + + .cfg.ext_zfa =3D true, + .cfg.ext_zfh =3D true, + .cfg.mmu =3D true, + .cfg.ext_xtheadba =3D true, + .cfg.ext_xtheadbb =3D true, + .cfg.ext_xtheadbs =3D true, + .cfg.ext_xtheadcmo =3D true, + .cfg.ext_xtheadcondmov =3D true, + .cfg.ext_xtheadfmemidx =3D true, + .cfg.ext_xtheadmac =3D true, + .cfg.ext_xtheadmemidx =3D true, + .cfg.ext_xtheadmempair =3D true, + .cfg.ext_xtheadsync =3D true, + .cfg.pmp =3D true, + + .cfg.mvendorid =3D THEAD_VENDOR_ID, + + .cfg.max_satp_mode =3D VM_1_10_SV39, +#ifndef CONFIG_USER_ONLY + .custom_csrs =3D th_csr_list, +#endif + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo= n_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGgO3y1iXtYMhGCUn4xi/pez3JYaVXblbISeXiqZ8hHkZbkg16wPBvYReN/pIQwIlRaj6cxJA== X-Received: by 2002:a5d:4c82:0:b0:391:4095:49b7 with SMTP id ffacd0b85a97d-3a07aa6c501mr4687591f8f.25.1745825741115; Mon, 28 Apr 2025 00:35:41 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 23/26] target/riscv: convert TT Ascalon to RISCVCPUDef Date: Mon, 28 Apr 2025 09:34:38 +0200 Message-ID: <20250428073442.315770-24-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826029428019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 127 +++++++++++++++++++++------------------------ 1 file changed, 60 insertions(+), 67 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f3af9643af4..20a68ba43c4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -540,72 +540,6 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } =20 -/* Tenstorrent Ascalon */ -static void rv64_tt_ascalon_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); - env->priv_ver =3D PRIV_VERSION_1_13_0; - - /* Enable ISA extensions */ - cpu->cfg.mmu =3D true; - cpu->cfg.vlenb =3D 256 >> 3; - cpu->cfg.elen =3D 64; - cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; - cpu->cfg.rvv_ma_all_1s =3D true; - cpu->cfg.rvv_ta_all_1s =3D true; - cpu->cfg.misa_w =3D true; - cpu->cfg.pmp =3D true; - cpu->cfg.cbom_blocksize =3D 64; - cpu->cfg.cbop_blocksize =3D 64; - cpu->cfg.cboz_blocksize =3D 64; - cpu->cfg.ext_zic64b =3D true; - cpu->cfg.ext_zicbom =3D true; - cpu->cfg.ext_zicbop =3D true; - cpu->cfg.ext_zicboz =3D true; - cpu->cfg.ext_zicntr =3D true; - cpu->cfg.ext_zicond =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zihintntl =3D true; - cpu->cfg.ext_zihintpause =3D true; - cpu->cfg.ext_zihpm =3D true; - cpu->cfg.ext_zimop =3D true; - cpu->cfg.ext_zawrs =3D true; - cpu->cfg.ext_zfa =3D true; - cpu->cfg.ext_zfbfmin =3D true; - cpu->cfg.ext_zfh =3D true; - cpu->cfg.ext_zfhmin =3D true; - cpu->cfg.ext_zcb =3D true; - cpu->cfg.ext_zcmop =3D true; - cpu->cfg.ext_zba =3D true; - cpu->cfg.ext_zbb =3D true; - cpu->cfg.ext_zbs =3D true; - cpu->cfg.ext_zkt =3D true; - cpu->cfg.ext_zvbb =3D true; - cpu->cfg.ext_zvbc =3D true; - cpu->cfg.ext_zvfbfmin =3D true; - cpu->cfg.ext_zvfbfwma =3D true; - cpu->cfg.ext_zvfh =3D true; - cpu->cfg.ext_zvfhmin =3D true; - cpu->cfg.ext_zvkng =3D true; - cpu->cfg.ext_smaia =3D true; - cpu->cfg.ext_smstateen =3D true; - cpu->cfg.ext_ssaia =3D true; - cpu->cfg.ext_sscofpmf =3D true; - cpu->cfg.ext_sstc =3D true; - cpu->cfg.ext_svade =3D true; - cpu->cfg.ext_svinval =3D true; - cpu->cfg.ext_svnapot =3D true; - cpu->cfg.ext_svpbmt =3D true; - -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV57); -#endif -} - static void rv64_xiangshan_nanhu_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -3214,7 +3148,66 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { #endif ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo= n_cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_TT_ASCALON, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVS | RVU | RVH | RVV, + .priv_spec =3D PRIV_VERSION_1_13_0, + .vext_spec =3D VEXT_VERSION_1_00_0, + + /* ISA extensions */ + .cfg.mmu =3D true, + .cfg.vlenb =3D 256 >> 3, + .cfg.elen =3D 64, + .cfg.rvv_ma_all_1s =3D true, + .cfg.rvv_ta_all_1s =3D true, + .cfg.misa_w =3D true, + .cfg.pmp =3D true, + .cfg.cbom_blocksize =3D 64, + .cfg.cbop_blocksize =3D 64, + .cfg.cboz_blocksize =3D 64, + .cfg.ext_zic64b =3D true, + .cfg.ext_zicbom =3D true, + .cfg.ext_zicbop =3D true, + .cfg.ext_zicboz =3D true, + .cfg.ext_zicntr =3D true, + .cfg.ext_zicond =3D true, + .cfg.ext_zicsr =3D true, + .cfg.ext_zifencei =3D true, + .cfg.ext_zihintntl =3D true, + .cfg.ext_zihintpause =3D true, + .cfg.ext_zihpm =3D true, + .cfg.ext_zimop =3D true, + .cfg.ext_zawrs =3D true, + .cfg.ext_zfa =3D true, + .cfg.ext_zfbfmin =3D true, + .cfg.ext_zfh =3D true, + .cfg.ext_zfhmin =3D true, + .cfg.ext_zcb =3D true, + .cfg.ext_zcmop =3D true, + .cfg.ext_zba =3D true, + .cfg.ext_zbb =3D true, + .cfg.ext_zbs =3D true, + .cfg.ext_zkt =3D true, + .cfg.ext_zvbb =3D true, + .cfg.ext_zvbc =3D true, + .cfg.ext_zvfbfmin =3D true, + .cfg.ext_zvfbfwma =3D true, + .cfg.ext_zvfh =3D true, + .cfg.ext_zvfhmin =3D true, + .cfg.ext_zvkng =3D true, + .cfg.ext_smaia =3D true, + .cfg.ext_smstateen =3D true, + .cfg.ext_ssaia =3D true, + .cfg.ext_sscofpmf =3D true, + .cfg.ext_sstc =3D true, + .cfg.ext_svade =3D true, + .cfg.ext_svinval =3D true, + .cfg.ext_svnapot =3D true, + .cfg.ext_svpbmt =3D true, + + .cfg.max_satp_mode =3D VM_1_10_SV57, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEP8WblTwwTZbG1Miq+fD+3ircDLvms5Xj+7/Oy8ykj+yt//6iHA+re8BkYzwsCophV7N2mlQ== X-Received: by 2002:a05:600c:34ca:b0:43e:a7c9:8d2b with SMTP id 5b1f17b1804b1-440a66aaf1bmr84848705e9.24.1745825743316; Mon, 28 Apr 2025 00:35:43 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 24/26] target/riscv: convert Ventana V1 to RISCVCPUDef Date: Mon, 28 Apr 2025 09:34:39 +0200 Message-ID: <20250428073442.315770-25-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826047978019001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 75 ++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 40 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 20a68ba43c4..6cdb92c8a4c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -500,45 +500,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, = const RISCVCSR *csr_list) #endif =20 #if defined(TARGET_RISCV64) -static void rv64_veyron_v1_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); - env->priv_ver =3D PRIV_VERSION_1_12_0; - - /* Enable ISA extensions */ - cpu->cfg.mmu =3D true; - cpu->cfg.ext_zifencei =3D true; - cpu->cfg.ext_zicsr =3D true; - cpu->cfg.pmp =3D true; - cpu->cfg.ext_zicbom =3D true; - cpu->cfg.cbom_blocksize =3D 64; - cpu->cfg.cboz_blocksize =3D 64; - cpu->cfg.ext_zicboz =3D true; - cpu->cfg.ext_smaia =3D true; - cpu->cfg.ext_ssaia =3D true; - cpu->cfg.ext_sscofpmf =3D true; - cpu->cfg.ext_sstc =3D true; - cpu->cfg.ext_svinval =3D true; - cpu->cfg.ext_svnapot =3D true; - cpu->cfg.ext_svpbmt =3D true; - cpu->cfg.ext_smstateen =3D true; - cpu->cfg.ext_zba =3D true; - cpu->cfg.ext_zbb =3D true; - cpu->cfg.ext_zbc =3D true; - cpu->cfg.ext_zbs =3D true; - cpu->cfg.ext_XVentanaCondOps =3D true; - - cpu->cfg.mvendorid =3D VEYRON_V1_MVENDORID; - cpu->cfg.marchid =3D VEYRON_V1_MARCHID; - cpu->cfg.mimpid =3D VEYRON_V1_MIMPID; - -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV48); -#endif -} =20 static void rv64_xiangshan_nanhu_cpu_init(Object *obj) { @@ -3208,7 +3169,41 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.max_satp_mode =3D VM_1_10_SV57, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVS | RVU | RVH, + .priv_spec =3D PRIV_VERSION_1_12_0, + + /* ISA extensions */ + .cfg.mmu =3D true, + .cfg.ext_zifencei =3D true, + .cfg.ext_zicsr =3D true, + .cfg.pmp =3D true, + .cfg.ext_zicbom =3D true, + .cfg.cbom_blocksize =3D 64, + .cfg.cboz_blocksize =3D 64, + .cfg.ext_zicboz =3D true, + .cfg.ext_smaia =3D true, + .cfg.ext_ssaia =3D true, + .cfg.ext_sscofpmf =3D true, + .cfg.ext_sstc =3D true, + .cfg.ext_svinval =3D true, + .cfg.ext_svnapot =3D true, + .cfg.ext_svpbmt =3D true, + .cfg.ext_smstateen =3D true, + .cfg.ext_zba =3D true, + .cfg.ext_zbb =3D true, + .cfg.ext_zbc =3D true, + .cfg.ext_zbs =3D true, + .cfg.ext_XVentanaCondOps =3D true, + + .cfg.mvendorid =3D VEYRON_V1_MVENDORID, + .cfg.marchid =3D VEYRON_V1_MARCHID, + .cfg.mimpid =3D VEYRON_V1_MIMPID, + + .cfg.max_satp_mode =3D VM_1_10_SV48, + ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHitAI7cxo+5r54d1x6kI8r99LOCzmzBfmqs9z8ka16Utr8zzLLu3HiIS2N9dpMpmY+P4c2ag== X-Received: by 2002:a05:600c:5252:b0:43d:abd:ad1c with SMTP id 5b1f17b1804b1-440a65b6f77mr76467635e9.6.1745825745387; Mon, 28 Apr 2025 00:35:45 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 25/26] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef Date: Mon, 28 Apr 2025 09:34:40 +0200 Message-ID: <20250428073442.315770-26-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745825802735019100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 80 +++++++++++++--------------------------------- 1 file changed, 23 insertions(+), 57 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6cdb92c8a4c..e7e9e6bfe80 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -441,16 +441,6 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_3= 2_bit) g_assert_not_reached(); } =20 -static void __attribute__((unused)) -set_satp_mode_max_supported(RISCVCPU *cpu, int satp_mode) -{ - bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; - const bool *valid_vm =3D rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - - assert(valid_vm[satp_mode]); - cpu->cfg.max_satp_mode =3D satp_mode; -} - static bool get_satp_mode_supported(RISCVCPU *cpu, uint16_t *supported) { bool rv32 =3D riscv_cpu_is_32bit(cpu); @@ -499,38 +489,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, = const RISCVCSR *csr_list) } #endif =20 -#if defined(TARGET_RISCV64) - -static void rv64_xiangshan_nanhu_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; - RISCVCPU *cpu =3D RISCV_CPU(obj); - - riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU); - env->priv_ver =3D PRIV_VERSION_1_12_0; - - /* Enable ISA extensions */ - cpu->cfg.ext_zbc =3D true; - cpu->cfg.ext_zbkb =3D true; - cpu->cfg.ext_zbkc =3D true; - cpu->cfg.ext_zbkx =3D true; - cpu->cfg.ext_zknd =3D true; - cpu->cfg.ext_zkne =3D true; - cpu->cfg.ext_zknh =3D true; - cpu->cfg.ext_zksed =3D true; - cpu->cfg.ext_zksh =3D true; - cpu->cfg.ext_svinval =3D true; - - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(cpu, VM_1_10_SV39); -#endif -} - -#endif /* !TARGET_RISCV64 */ - static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -2892,19 +2850,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, c= har *nodename) } #endif =20 -#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \ - { \ - .name =3D (type_name), \ - .parent =3D TYPE_RISCV_VENDOR_CPU, \ - .instance_init =3D (initfn), \ - .class_data =3D &((const RISCVCPUDef) { \ - .misa_mxl_max =3D (misa_mxl_max_), \ - .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ - .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ - .cfg.max_satp_mode =3D -1, \ - }), \ - } - #define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ { \ .name =3D (type_name), \ @@ -3204,8 +3149,29 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .cfg.max_satp_mode =3D VM_1_10_SV48, ), =20 - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, - MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, TYPE_RISCV_VENDOR_CPU, + .misa_mxl_max =3D MXL_RV64, + .misa_ext =3D RVG | RVC | RVB | RVS | RVU, + .priv_spec =3D PRIV_VERSION_1_12_0, + + /* ISA extensions */ + .cfg.ext_zbc =3D true, + .cfg.ext_zbkb =3D true, + .cfg.ext_zbkc =3D true, + .cfg.ext_zbkx =3D true, + .cfg.ext_zknd =3D true, + .cfg.ext_zkne =3D true, + .cfg.ext_zknh =3D true, + .cfg.ext_zksed =3D true, + .cfg.ext_zksh =3D true, + .cfg.ext_svinval =3D true, + + .cfg.mmu =3D true, + .cfg.pmp =3D true, + + .cfg.max_satp_mode =3D VM_1_10_SV39, + ), + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode =3D VM_1_10_SV57, --=20 2.49.0 From nobody Tue Dec 16 03:26:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 28 Apr 2025 00:35:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHzsBDvUob5WPzLT77w8H2vOwIFoy2j7LvxRxEebVZakW+ZW+/gspR2r8rpITMbqGQnYyQ0Hg== X-Received: by 2002:adf:ec0d:0:b0:3a0:7a5d:96f6 with SMTP id ffacd0b85a97d-3a07a5d9bc6mr4902844f8f.38.1745825748449; Mon, 28 Apr 2025 00:35:48 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, dbarboza@ventanamicro.com Subject: [PATCH 26/26] target/riscv: remove .instance_post_init Date: Mon, 28 Apr 2025 09:34:41 +0200 Message-ID: <20250428073442.315770-27-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428073442.315770-1-pbonzini@redhat.com> References: <20250428073442.315770-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.492, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1745826073983019000 Content-Type: text/plain; charset="utf-8" Unlike other uses of .instance_post_init, accel_cpu_instance_init() *registers* properties, and therefore must be run before device_post_init() which sets them to their values from -global. In order to move all registration of properties to .instance_init, call accel_cpu_instance_init() at the end of riscv_cpu_init(). Reviewed-by: Alistair Francis Signed-off-by: Paolo Bonzini --- target/riscv/cpu.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e7e9e6bfe80..f1863344e8d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1084,11 +1084,6 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 -static void riscv_cpu_post_init(Object *obj) -{ - accel_cpu_instance_init(CPU(obj)); -} - static void riscv_cpu_init(Object *obj) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(obj); @@ -1144,6 +1139,8 @@ static void riscv_cpu_init(Object *obj) riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); } #endif + + accel_cpu_instance_init(CPU(obj)); } =20 typedef struct misa_ext_info { @@ -2886,7 +2883,6 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .instance_size =3D sizeof(RISCVCPU), .instance_align =3D __alignof(RISCVCPU), .instance_init =3D riscv_cpu_init, - .instance_post_init =3D riscv_cpu_post_init, .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_common_class_init, --=20 2.49.0