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Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic --- hw/intc/riscv_aclint.c | 24 ++++++++++++++++++++++-- hw/intc/riscv_aplic.c | 9 ++++++--- 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index db374a7c2d..403a889bf4 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -131,6 +131,8 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, = hwaddr addr, size_t hartid =3D mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); CPUState *cpu =3D cpu_by_arch_id(hartid); + if (cpu =3D=3D NULL) + return 0; CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -174,6 +176,8 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, size_t hartid =3D mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); CPUState *cpu =3D cpu_by_arch_id(hartid); + if (cpu =3D=3D NULL) + return; CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -233,6 +237,8 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, /* Check if timer interrupt is triggered for each hart. */ for (i =3D 0; i < mtimer->num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(mtimer->hartid_base + i); + if (cpu =3D=3D NULL) + continue; CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { continue; @@ -292,7 +298,10 @@ static void riscv_aclint_mtimer_realize(DeviceState *d= ev, Error **errp) s->timecmp =3D g_new0(uint64_t, s->num_harts); /* Claim timer interrupt bits */ for (i =3D 0; i < s->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(s->hartid_base + i)); + CPUState *temp =3D cpu_by_arch_id(s->hartid_base + i); + if (temp =3D=3D NULL) + continue; + RISCVCPU *cpu =3D RISCV_CPU(temp); if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) { error_report("MTIP already claimed"); exit(1); @@ -373,6 +382,8 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); + if (cpu =3D=3D NULL) + continue; RISCVCPU *rvcpu =3D RISCV_CPU(cpu); CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; riscv_aclint_mtimer_callback *cb =3D @@ -408,6 +419,8 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwa= ddr addr, if (addr < (swi->num_harts << 2)) { size_t hartid =3D swi->hartid_base + (addr >> 2); CPUState *cpu =3D cpu_by_arch_id(hartid); + if (cpu =3D=3D NULL) + return 0; CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -431,6 +444,8 @@ static void riscv_aclint_swi_write(void *opaque, hwaddr= addr, uint64_t value, if (addr < (swi->num_harts << 2)) { size_t hartid =3D swi->hartid_base + (addr >> 2); CPUState *cpu =3D cpu_by_arch_id(hartid); + if (cpu =3D=3D NULL) + return; CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, @@ -481,7 +496,10 @@ static void riscv_aclint_swi_realize(DeviceState *dev,= Error **errp) =20 /* Claim software interrupt bits */ for (i =3D 0; i < swi->num_harts; i++) { - RISCVCPU *cpu =3D RISCV_CPU(qemu_get_cpu(swi->hartid_base + i)); + CPUState *temp =3D cpu_by_arch_id(swi->hartid_base + i); + if (temp =3D=3D NULL) + continue; + RISCVCPU *cpu =3D RISCV_CPU(temp); /* We don't claim mip.SSIP because it is writable by software */ if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0)= { error_report("MSIP already claimed"); @@ -545,6 +563,8 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint3= 2_t hartid_base, =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); + if (cpu =3D=3D NULL) + continue; RISCVCPU *rvcpu =3D RISCV_CPU(cpu); =20 qdev_connect_gpio_out(dev, i, diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 5964cde7e0..be30579028 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -899,9 +899,10 @@ static void riscv_aplic_realize(DeviceState *dev, Erro= r **errp) if (!aplic->msimode) { /* Claim the CPU interrupt to be triggered by this APLIC */ for (i =3D 0; i < aplic->num_harts; i++) { - RISCVCPU *cpu; - - cpu =3D RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i)); + CPUState *temp =3D cpu_by_arch_id(aplic->hartid_base + i); + if (temp =3D=3D NULL) + continue; + RISCVCPU *cpu =3D RISCV_CPU(temp); if (riscv_cpu_claim_interrupts(cpu, (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { error_report("%s already claimed", @@ -1076,6 +1077,8 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr s= ize, if (!msimode) { for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); + if (cpu =3D=3D NULL) + continue; =20 qdev_connect_gpio_out_named(dev, NULL, i, qdev_get_gpio_in(DEVICE(cpu), --=20 2.34.1