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Fri, 25 Apr 2025 04:37:43 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 8/9] target/riscv: widen (m|s)counteren to target_ulong Date: Fri, 25 Apr 2025 08:37:04 -0300 Message-ID: <20250425113705.2741457-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425113705.2741457-1-dbarboza@ventanamicro.com> References: <20250425113705.2741457-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745581128695019000 Content-Type: text/plain; charset="utf-8" We want to support scounteren as a KVM CSR. The KVM UAPI defines every CSR size as target_ulong, and our env->scounteren is fixed at 32 bits. The other existing cases where the property size does not match the KVM reg size happens with uint64_t properties, like 'mstatus'. When running a 32 bit CPU we'll write a 32 bit 'sstatus' KVM reg into the 64 bit 'mstatus' field. As long as we're consistent, i.e. we're always reading/writing the same words, this is ok. For scounteren, a KVM guest running in a 64 bit CPU will end up writing a 64 bit reg in a 32 bit field. This will have all sort of funny side effects in the KVM guest that we would rather avoid. Increase scounteren to target_ulong to allow KVM to read/write the scounteren CSR without any surprises. 'mcounteren' is being changed to target_ulong for consistency. Aside from bumping the version of the RISCVCPU vmstate no other behavioral changes are expected. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 4 ++-- target/riscv/machine.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5a60d0c52..0623c3187b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -400,8 +400,8 @@ struct CPUArchState { */ bool two_stage_indirect_lookup; =20 - uint32_t scounteren; - uint32_t mcounteren; + target_ulong scounteren; + target_ulong mcounteren; =20 uint32_t scountinhibit; uint32_t mcountinhibit; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index df2d5bad8d..4b11b203fb 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -401,8 +401,8 @@ static const VMStateDescription vmstate_ssp =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 10, - .minimum_version_id =3D 10, + .version_id =3D 11, + .minimum_version_id =3D 11, .post_load =3D riscv_cpu_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -445,8 +445,8 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.mtval, RISCVCPU), VMSTATE_UINTTL(env.miselect, RISCVCPU), VMSTATE_UINTTL(env.siselect, RISCVCPU), - VMSTATE_UINT32(env.scounteren, RISCVCPU), - VMSTATE_UINT32(env.mcounteren, RISCVCPU), + VMSTATE_UINTTL(env.scounteren, RISCVCPU), + VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINT32(env.scountinhibit, RISCVCPU), VMSTATE_UINT32(env.mcountinhibit, RISCVCPU), VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, = 0, --=20 2.49.0