From nobody Sun Nov 16 01:00:02 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745581197; cv=none; d=zohomail.com; s=zohoarc; b=fsSOzP3PR3xWZu4do2EeHg+jkgfKp18mWd4fZDPkw4/lqV6S8sy1HJHaqCyEVpklsgbaPA4mwFAD2RDiTzHF9dCsqezT+0s963F0rj85IGpQ9AstPPQRvqje9FETVqa5cwgRrH0gDdDD2TduLlcmuPL4Um/vhShO/hjRNHXHYpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745581197; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5neQGzLPcsmIj+eh2EIpFmSDwCQhG6xSq9AiQ9ifoDM=; b=SSE2JGIFz56DRsSBRQF+qD05iRIPevOsGD08wpgP4a3LmwZiUpsKBKBkx40fu9LKD2qWwxpEiaKL8eta6BKXYUw+V1MnF+NpC2CMRE18ps++lYlH3fXTZQTY2/w6FZW3v6p8uWU3Ww2LOFs/yL5yQBeHD/rQ6oswNfIfZ3gD7NE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745581197216825.2286025319117; Fri, 25 Apr 2025 04:39:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u8HNL-0001Cw-BY; Fri, 25 Apr 2025 07:37:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u8HNH-0001Bb-W3 for qemu-devel@nongnu.org; Fri, 25 Apr 2025 07:37:44 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u8HNA-0006Wg-E9 for qemu-devel@nongnu.org; Fri, 25 Apr 2025 07:37:43 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2264aefc45dso33989085ad.0 for ; Fri, 25 Apr 2025 04:37:33 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([152.234.125.33]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db50e7a40sm29881055ad.147.2025.04.25.04.37.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 04:37:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1745581051; x=1746185851; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5neQGzLPcsmIj+eh2EIpFmSDwCQhG6xSq9AiQ9ifoDM=; b=kYaacMHDvK0JfDSwft12zqklR43i1lbXTpEOTIE8Nhg/96FiJrnBEMJ44AQN2M1EXF ju56R3DuyOt24dZBXzHVBC5gzD9QkZNjnc/52m5cTRTH6HUXmL6cTLXy79CzwjwZRfSl mjhaKWEbfDHcm6vvclxHM4M0jrO9Fg5WDm0QBK2SaUco/GUTa/f1W4j3Cmzfm64PcZQT E+lrZ8rBT5NvlpZCi4R7HLnJ5WGZaRyqjTI0805MzIwF2mrvcMVgs9tKHQtGyi7hmE+x SN0aaLx4H9ZA49OVW6RDk72E5PUPs+1/2Pjfc6v+xJQNhHh1CFNZGHxdABrW1VYYSLAw m8Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745581051; x=1746185851; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5neQGzLPcsmIj+eh2EIpFmSDwCQhG6xSq9AiQ9ifoDM=; b=js89Zce51UkNmdZVhyDjUaNk6eHBiJEno9A6NMm+8GzqisxbIPDqQ6XOh9gAvTDnyY dPS+aqxcmoqaY3UN1FUI+nzl2SDFhDJP/vcgb+Dh/VLkMYvn0GdcH1diPZwXgx6GR0iw vv2+g2LMgHwuhFEcGpkH7SUUB5S+YjA1B4u7pTeujOKV5uweOauiAjP3gIeblVjG6GLu 6+F4EJkLgGEnyUAtyPgJ8n8IZbUDE+LSxNqRxisiqTke1i4xvGkYjq+zrkGhTA9yOpNz 7avtpcuSEVzb5rXpbf+HEUMuuJr8rqLf3XgfueDzKhUD/6UpTPI2DbkBwRhoST5X+lhV ezBg== X-Gm-Message-State: AOJu0YxO6rzkIWP+JbeWCqSJlniSAQM+9wnCjJgCXtNkYd+bjkZzlYRC S8TjfuY98ofRsRAkRaKQBWapN3JZi53+h2NksTTTr0htbj1zYHtgLAozZDJIl2Wn9gRPt5KMuxe + X-Gm-Gg: ASbGncsYK7UYF3nmZL0H3BP00HFdcXU6u8UjNTt3kvv/I7Xh8Sh3yVHCgk+AtdGetJm FjpRTS/v87iNEDowiqCA7ckOvQ/uEMLmNY/MjTd8GR58wWDqzspqq8tiYxL1r22hMNzp1mLaEIW uAjMEqhR4ZpYfU1kwHnQOtf9pliuVJWPe3FCaY4qsmI2z4PvuVduqbwggkArXgtSG7EAjmXAZgJ RXWGrWH7NnD3U/PJoW1JDq8xS2v7S0l5uCqP47CXS92Wqy7QUdrv4n0GDChraBdG4EBdK5meq9k C8Y85BtbZHZv1ctL4DHacSneYgjIEsHO459t61Z7WWEhF52rGUzxnS67N/6BjTcXlf5QdOQA/15 ufaE= X-Google-Smtp-Source: AGHT+IE09FD0cMsBA13zqSe/F/Y43aUMRL01g/uuovEtGNz0oaczZm+0oMmgf5I5WHhOjP9AdOPPXw== X-Received: by 2002:a17:903:1c6:b0:224:192a:9154 with SMTP id d9443c01a7336-22dbf5fa834mr28954235ad.26.1745581051402; Fri, 25 Apr 2025 04:37:31 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() in a macro Date: Fri, 25 Apr 2025 08:37:00 -0300 Message-ID: <20250425113705.2741457-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425113705.2741457-1-dbarboza@ventanamicro.com> References: <20250425113705.2741457-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745581198535019100 Content-Type: text/plain; charset="utf-8" We need the reg_id_ulong() helper to be a macro to be able to create a static array of KVMCPUConfig that will hold CSR information. Despite the amount of changes all of them are tedious/trivial: - replace instances of "kvm_riscv_reg_id_ulong" with "KVM_RISCV_REG_ID_ULONG"; - RISCV_CORE_REG(), RISCV_CSR_REG(), RISCV_CONFIG_REG() and RISCV_VECTOR_CSR_REG() only receives one 'name' arg. Remove unneeded 'env' variables when applicable. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 99 ++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 58 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c91ecdfe59..fd66bc1759 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -64,23 +64,11 @@ static bool cap_has_mp_state; #define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 = | \ type | idx) =20 -static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, - uint64_t idx) -{ - uint64_t id =3D KVM_REG_RISCV | type | idx; - - switch (riscv_cpu_mxl(env)) { - case MXL_RV32: - id |=3D KVM_REG_SIZE_U32; - break; - case MXL_RV64: - id |=3D KVM_REG_SIZE_U64; - break; - default: - g_assert_not_reached(); - } - return id; -} +#if defined(TARGET_RISCV64) +#define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U64(type, idx) +#else +#define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U32(type, idx) +#endif =20 static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) { @@ -103,16 +91,16 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, return kvm_encode_reg_size_id(id, size_b); } =20 -#define RISCV_CORE_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ +#define RISCV_CORE_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, \ KVM_REG_RISCV_CORE_REG(name)) =20 -#define RISCV_CSR_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ +#define RISCV_CSR_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CSR, \ KVM_REG_RISCV_CSR_REG(name)) =20 -#define RISCV_CONFIG_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ +#define RISCV_CONFIG_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, \ KVM_REG_RISCV_CONFIG_REG(name)) =20 #define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ @@ -122,13 +110,13 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, =20 #define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) =20 -#define RISCV_VECTOR_CSR_REG(env, name) \ - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ +#define RISCV_VECTOR_CSR_REG(name) \ + KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ KVM_REG_RISCV_VECTOR_CSR_REG(name)) =20 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ do { \ - int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(csr), ®); \ if (_ret) { \ return _ret; \ } \ @@ -136,7 +124,7 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, =20 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ do { \ - int _ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + int _ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(csr), ®); \ if (_ret) { \ return _ret; \ } \ @@ -244,7 +232,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu= , CPUState *cs) =20 /* If we're here we're going to disable the MISA bit */ reg =3D 0; - id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, misa_cfg->kvm_reg_id); ret =3D kvm_set_one_reg(cs, id, ®); if (ret !=3D 0) { @@ -430,7 +418,6 @@ static KVMCPUConfig kvm_sbi_dbcn =3D { =20 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) { - CPURISCVState *env =3D &cpu->env; uint64_t id, reg; int i, ret; =20 @@ -441,7 +428,7 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *= cpu, CPUState *cs) continue; } =20 - id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, multi_ext_cfg->kvm_reg_id); reg =3D kvm_cpu_cfg_get(cpu, multi_ext_cfg); ret =3D kvm_set_one_reg(cs, id, ®); @@ -566,14 +553,14 @@ static int kvm_riscv_get_regs_core(CPUState *cs) target_ulong reg; CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 - ret =3D kvm_get_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); + ret =3D kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); if (ret) { return ret; } env->pc =3D reg; =20 for (i =3D 1; i < 32; i++) { - uint64_t id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); + uint64_t id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); ret =3D kvm_get_one_reg(cs, id, ®); if (ret) { return ret; @@ -592,13 +579,13 @@ static int kvm_riscv_put_regs_core(CPUState *cs) CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 reg =3D env->pc; - ret =3D kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®); + ret =3D kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); if (ret) { return ret; } =20 for (i =3D 1; i < 32; i++) { - uint64_t id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); + uint64_t id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); reg =3D env->gpr[i]; ret =3D kvm_set_one_reg(cs, id, ®); if (ret) { @@ -796,26 +783,26 @@ static int kvm_riscv_get_regs_vector(CPUState *cs) return 0; } =20 - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); if (ret) { return ret; } env->vstart =3D reg; =20 - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); if (ret) { return ret; } env->vl =3D reg; =20 - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); if (ret) { return ret; } env->vtype =3D reg; =20 if (kvm_v_vlenb.supported) { - ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®= ); + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); if (ret) { return ret; } @@ -853,26 +840,26 @@ static int kvm_riscv_put_regs_vector(CPUState *cs) } =20 reg =3D env->vstart; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); if (ret) { return ret; } =20 reg =3D env->vl; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); if (ret) { return ret; } =20 reg =3D env->vtype; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); if (ret) { return ret; } =20 if (kvm_v_vlenb.supported) { reg =3D cpu->cfg.vlenb; - ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vlenb), ®= ); + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); =20 for (int i =3D 0; i < 32; i++) { /* @@ -951,25 +938,24 @@ static void kvm_riscv_destroy_scratch_vcpu(KVMScratch= CPU *scratch) =20 static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcp= u) { - CPURISCVState *env =3D &cpu->env; struct kvm_one_reg reg; int ret; =20 - reg.id =3D RISCV_CONFIG_REG(env, mvendorid); + reg.id =3D RISCV_CONFIG_REG(mvendorid); reg.addr =3D (uint64_t)&cpu->cfg.mvendorid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { error_report("Unable to retrieve mvendorid from host, error %d", r= et); } =20 - reg.id =3D RISCV_CONFIG_REG(env, marchid); + reg.id =3D RISCV_CONFIG_REG(marchid); reg.addr =3D (uint64_t)&cpu->cfg.marchid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { error_report("Unable to retrieve marchid from host, error %d", ret= ); } =20 - reg.id =3D RISCV_CONFIG_REG(env, mimpid); + reg.id =3D RISCV_CONFIG_REG(mimpid); reg.addr =3D (uint64_t)&cpu->cfg.mimpid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { @@ -984,7 +970,7 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, struct kvm_one_reg reg; int ret; =20 - reg.id =3D RISCV_CONFIG_REG(env, isa); + reg.id =3D RISCV_CONFIG_REG(isa); reg.addr =3D (uint64_t)&env->misa_ext_mask; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); =20 @@ -1001,11 +987,10 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *c= pu, static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvm= cpu, KVMCPUConfig *cbomz_cfg) { - CPURISCVState *env =3D &cpu->env; struct kvm_one_reg reg; int ret; =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, cbomz_cfg->kvm_reg_id); reg.addr =3D (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); @@ -1019,7 +1004,6 @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cp= u, KVMScratchCPU *kvmcpu, static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) { - CPURISCVState *env =3D &cpu->env; uint64_t val; int i, ret; =20 @@ -1027,7 +1011,7 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *= cpu, KVMCPUConfig *multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; struct kvm_one_reg reg; =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, multi_ext_cfg->kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); @@ -1159,7 +1143,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu= , KVMScratchCPU *kvmcpu) =20 for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; - reg_id =3D kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, + reg_id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, multi_ext_cfg->kvm_reg_id); reg_search =3D bsearch(®_id, reglist->reg, reglist->n, sizeof(uint64_t), uint64_cmp); @@ -1338,12 +1322,11 @@ void kvm_arch_init_irq_routing(KVMState *s) =20 static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) { - CPURISCVState *env =3D &cpu->env; target_ulong reg; uint64_t id; int ret; =20 - id =3D RISCV_CONFIG_REG(env, mvendorid); + id =3D RISCV_CONFIG_REG(mvendorid); /* * cfg.mvendorid is an uint32 but a target_ulong will * be written. Assign it to a target_ulong var to avoid @@ -1355,13 +1338,13 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, = CPUState *cs) return ret; } =20 - id =3D RISCV_CONFIG_REG(env, marchid); + id =3D RISCV_CONFIG_REG(marchid); ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.marchid); if (ret !=3D 0) { return ret; } =20 - id =3D RISCV_CONFIG_REG(env, mimpid); + id =3D RISCV_CONFIG_REG(mimpid); ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); =20 return ret; @@ -1911,7 +1894,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, E= rror **errp) if (cpu->cfg.ext_zicbom && riscv_cpu_option_set(kvm_cbom_blocksize.name)) { =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, kvm_cbom_blocksize.kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); @@ -1930,7 +1913,7 @@ void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, E= rror **errp) if (cpu->cfg.ext_zicboz && riscv_cpu_option_set(kvm_cboz_blocksize.name)) { =20 - reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + reg.id =3D KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, kvm_cboz_blocksize.kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); --=20 2.49.0