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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440a538f691sm622195e9.37.2025.04.24.13.25.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 24 Apr 2025 13:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745526302; x=1746131102; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3ZaZUiVtvhip+YjUPzbukhiUty3aZRnPrZlaJVYneow=; b=l+AdB8HclIJLhxMv4eS5VDnF3VoSN689AljGoi6MUnHhtG5kaNcHX0UdCBK3HjPoqv EGIATutv6sJNSy5sH6Wl7zSTsF0E91eu5hkXf/RRQCOYbJWA71v0c3hCyqZE//dAbRAc HunPzEzQK6THvyZeWRatVcXwApRr6m0gdaQ1t63ldgj9o0bVjLfVaQQqYxKJqeQt+gaT CXaycBWQVyhAZpDLnYBIYLmQm+mbeJ5QCcSbce/ZIH7kxcI2GmIv9cdpCQzJpxCI2+CV lYvNYaMxy+Y6RH12oR+6qose6rnLkH3ZOfyua6MhrqdkyO/XWP3gX80gZS5BfLLlwlOA iZIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745526302; x=1746131102; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3ZaZUiVtvhip+YjUPzbukhiUty3aZRnPrZlaJVYneow=; b=UKhVG4ktq7lRMRGHjSJGVXa8z648Hf3BXPWW2TlCa4q7lgtGejbr9gOXeKNWAfwsWy 1Kkq7hjXfHay8ypOGiEu+o3BTv5oPxBMkHVBIG/IzGFDSHzJtIwzAoFNbblQs29z2M0N KrrTljMlTafPXI8K4FgJT0hMdR4hN9e/UdwqRPkORmXjB6f8CWAcA6jrcGbT1H2P0bGn xNaBLAudpNE/GD4S3NGn34OIf4HxJVRyrJhUMX2XalqdGrONP+5DDs4P+IhqPkBlZtlD ZY/gqmgR0DmHvadtlRxZFIIBA3wfygi3zUL7PhWPNFVxacOoQqq+bX8ZpWpcBY2ecfHa bDrQ== X-Forwarded-Encrypted: i=1; AJvYcCUfzkNSmZ2c1SNyLSs1ro6S/8oC/TxweadfKwvYLaGJcxERD1uZtUvomc5Z/hoLDss5O5m31jexiZqA@nongnu.org X-Gm-Message-State: AOJu0Yz9WAG4u+FRkUSfAdscaoj6/CgVGpT/S1mnMtPaDk4SgiMDf54G vh9RE7PJwF5OsPMADSiDPPBhtsTaPUZ2fj1uoQdVbh+LHE7dZzN/My8RaRk7BDU= X-Gm-Gg: ASbGncucNY2sd/mKfb/zoeGEF+WMS5KU9bt6hAToOi/+gwTYSZrFg0hvHW+87DnEX1C OdZ02zv8AjU0t74b0Fmf3pVZYucBnVmfrp0p63pAWjJOtBDTKYHJkHE+42jG2uIBoTOfexUjcif Zssz8mh3Py4Z+4urZwzL7HunBsfIEz+UIwDoBgUKk8iXyIZhozPeAzJKE7vTAG4xgStYwmkh13/ CeX2vaE9byNc80uY67fNAvWS9PFutXlvevdyEWDc2CxgbpLgNtdAaCm/J7SwCtCE8h8KubZAjDO At6lhCu7/gJK/EJSNdOTeVcBtBdcWGf8pXddmgrhnA23b1OgR13ZLlW8THBkSnBVtDozK42GEcY R/GcNhjWVc1w0Dso= X-Google-Smtp-Source: AGHT+IGtXw0XNrjlq7CWdnIXxs1DRrxI/a7YfhBBL17hb7NGrgIn0LtM9TXpOzmNpa7pBkWIcIG25A== X-Received: by 2002:a05:600c:510e:b0:43c:fee3:2bce with SMTP id 5b1f17b1804b1-440a3173a9fmr5815295e9.26.1745526302531; Thu, 24 Apr 2025 13:25:02 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: Paolo Bonzini , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland Subject: [PATCH v3 10/13] physmem: Move TCG IOTLB methods around Date: Thu, 24 Apr 2025 22:24:09 +0200 Message-ID: <20250424202412.91612-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250424202412.91612-1-philmd@linaro.org> References: <20250424202412.91612-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745526342982019000 The next commit will restrict TCG specific code in physmem.c using some #ifdef'ry. In order to keep it simple, move iotlb_to_section() and memory_region_section_get_iotlb() around close together. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Mark Cave-Ayland --- system/physmem.c | 50 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/system/physmem.c b/system/physmem.c index 637f2d85324..ccbeae241c4 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -746,6 +746,31 @@ translate_fail: return &d->map.sections[PHYS_SECTION_UNASSIGNED]; } =20 +MemoryRegionSection *iotlb_to_section(CPUState *cpu, + hwaddr index, MemTxAttrs attrs) +{ + int asidx =3D cpu_asidx_from_attrs(cpu, attrs); + CPUAddressSpace *cpuas =3D &cpu->cpu_ases[asidx]; + AddressSpaceDispatch *d =3D cpuas->memory_dispatch; + int section_index =3D index & ~TARGET_PAGE_MASK; + MemoryRegionSection *ret; + + assert(section_index < d->map.sections_nb); + ret =3D d->map.sections + section_index; + assert(ret->mr); + assert(ret->mr->ops); + + return ret; +} + +/* Called from RCU critical section */ +hwaddr memory_region_section_get_iotlb(CPUState *cpu, + MemoryRegionSection *section) +{ + AddressSpaceDispatch *d =3D flatview_to_dispatch(section->fv); + return section - d->map.sections; +} + void cpu_address_space_init(CPUState *cpu, int asidx, const char *prefix, MemoryRegion *mr) { @@ -1002,14 +1027,6 @@ bool cpu_physical_memory_snapshot_get_dirty(DirtyBit= mapSnapshot *snap, return false; } =20 -/* Called from RCU critical section */ -hwaddr memory_region_section_get_iotlb(CPUState *cpu, - MemoryRegionSection *section) -{ - AddressSpaceDispatch *d =3D flatview_to_dispatch(section->fv); - return section - d->map.sections; -} - static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end, uint16_t section); static subpage_t *subpage_init(FlatView *fv, hwaddr base); @@ -2669,23 +2686,6 @@ static uint16_t dummy_section(PhysPageMap *map, Flat= View *fv, MemoryRegion *mr) return phys_section_add(map, §ion); } =20 -MemoryRegionSection *iotlb_to_section(CPUState *cpu, - hwaddr index, MemTxAttrs attrs) -{ - int asidx =3D cpu_asidx_from_attrs(cpu, attrs); - CPUAddressSpace *cpuas =3D &cpu->cpu_ases[asidx]; - AddressSpaceDispatch *d =3D cpuas->memory_dispatch; - int section_index =3D index & ~TARGET_PAGE_MASK; - MemoryRegionSection *ret; - - assert(section_index < d->map.sections_nb); - ret =3D d->map.sections + section_index; - assert(ret->mr); - assert(ret->mr->ops); - - return ret; -} - static void io_mem_init(void) { memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, N= ULL, --=20 2.47.1