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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15fa907fcdsm119775a12.54.2025.04.23.17.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 17:56:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745456206; x=1746061006; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ggbOR76BAcyXgvavB4mZvfqZnt/5CtPguoo3NLh6PJU=; b=PV/XGtWiyd2WMWIm5EhWOQ5CHeKgMCNh3l27Bz+V2UucRYL7OAvUJtVqC+IR8XaXXC 5qc8UF34qSc4757c/5FvI+y0/uTXZ1J1RWAZfbMs7MTZYjc2DdqxGULca6rGXfGr/6h0 /vM4bTZPyyameQa+4Y/LD7zsoXnUKZnqr6V7ULFgcyRnP51ptpJEdsWhVXaaRTJciVGH 7pkNw3X099UMjnDq+8S3bI/Y4FgtyMqf8XUeriAqM6UH1Krki46Yhbhbtnh+4Vt2iWyt RjhbrYkmKPn4I7GjHsCmEQUqTNYOkGYkcMjWGBSxC1bqeT8+A2RkouLAIIkeEOw4vccQ r6TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745456206; x=1746061006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ggbOR76BAcyXgvavB4mZvfqZnt/5CtPguoo3NLh6PJU=; b=L5kXpdxmCJNViMWOLdhALbMVuQ3DuDOhaTek1p/1YmGthFxDsIia/VLC0XRqot8pMP 4SW5mMs1qNChD7AQraXe4/T3F1+K/9f52ps83FsTB72nuocGl2PuompZtPW+LEzxwxKD 1yUBeS79OQqM3WPBJlXJgXZ5JqUkBS+NU8YVRk2mswXu8A+7GPF97U0k7CuanVpdSjiB r81yO6jfZzNNkOZlszpQjj+0cEEK9grfGcEG2Qq5Lcr9Q8WsXsrDxtMC0Gnz998Gj2lL X2xWCq6guz1CDqzB7InD5DmfGE6cYu2EmGbWHg1VpKDYEvcq+bQuSOiL0Cg6ui/O6VLI ll/g== X-Gm-Message-State: AOJu0Yx1gxd54PsUsqqVIpcmLUpZwa4BJyyOSXywm+csOz0apKsW2+7G ZqTMX+IR08RBgeWAhtxRECmb6o7Yqegr7lRWroaWOX0I5zfu6eH/JCDTZySccaYIXuPRBuwQ4a0 X X-Gm-Gg: ASbGnctuHbVCzc0Rqh5C+CH9eO/2KgusR8DiDEXi4kPNtzveYx32i+UBC6bFG7YQ4OR qrcIH+FBN4UryaqAsgwD1WvIVSJ3+Uu4q6Zr3WJTWR7a27tyQEsiYVC0YzL2Hx9EkuQvt4lbxAM fTpylGiA9NaEHU0pDXd6retmhgQIUBZJnA8MHPKlOfE0bL/jV7vMU+cnvgD+aJbrzL6MMicnPOB yeoB/+T7wBH+WDAR+WMkaX6I8zckXdnPNFQRkY7t0ApH5KNcVS0tqEYVqnTZmgw1C938uPzeiEx 9pm72cnO1/X2K1QUhRkjo6HaPvJWC3jWh5tj3ZX7cSHZ8LhhEDVQjt5kwJfN5+7+aBDjj6WXiAM = X-Google-Smtp-Source: AGHT+IFt235Olki5BRT4tEwRUyNhF3lF204SSq/fPJsXxrNWJj/OifH9BzUldyCwGimC+8yTC1CW2w== X-Received: by 2002:a05:6a20:d706:b0:1f5:77bd:ecbc with SMTP id adf61e73a8af0-20444e9b3a8mr825739637.16.1745456206231; Wed, 23 Apr 2025 17:56:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 097/148] accel/tcg: Split out tlb-bounds.h Date: Wed, 23 Apr 2025 17:48:42 -0700 Message-ID: <20250424004934.598783-98-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250424004934.598783-1-richard.henderson@linaro.org> References: <20250424004934.598783-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745457378105019100 The CPU_TLB_DYN_{MIN,MAX}_BITS definitions are not required outside of cputlb.c and translate-all.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tb-internal.h | 27 --------------------------- accel/tcg/tlb-bounds.h | 32 ++++++++++++++++++++++++++++++++ accel/tcg/cputlb.c | 1 + accel/tcg/translate-all.c | 1 + 4 files changed, 34 insertions(+), 27 deletions(-) create mode 100644 accel/tcg/tlb-bounds.h diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index f9a06bcbab..08538e2896 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -22,33 +22,6 @@ */ #define GETPC_ADJ 2 =20 -#ifdef CONFIG_SOFTMMU - -#define CPU_TLB_DYN_MIN_BITS 6 -#define CPU_TLB_DYN_DEFAULT_BITS 8 - -# if HOST_LONG_BITS =3D=3D 32 -/* Make sure we do not require a double-word shift for the TLB load */ -# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) -# else /* HOST_LONG_BITS =3D=3D 64 */ -/* - * Assuming TARGET_PAGE_BITS=3D=3D12, with 2**22 entries we can cover 2**(= 22+12) =3D=3D - * 2**34 =3D=3D 16G of address space. This is roughly what one would expec= t a - * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel - * Skylake's Level-2 STLB has 16 1G entries. - * Also, make sure we do not size the TLB past the guest's address space. - */ -# ifdef TARGET_PAGE_BITS_VARY -# define CPU_TLB_DYN_MAX_BITS \ - MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# else -# define CPU_TLB_DYN_MAX_BITS \ - MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# endif -# endif - -#endif /* CONFIG_SOFTMMU */ - void tb_lock_page0(tb_page_addr_t); =20 #ifdef CONFIG_USER_ONLY diff --git a/accel/tcg/tlb-bounds.h b/accel/tcg/tlb-bounds.h new file mode 100644 index 0000000000..efd34d4793 --- /dev/null +++ b/accel/tcg/tlb-bounds.h @@ -0,0 +1,32 @@ +/* + * softmmu size bounds + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_TLB_BOUNDS_H +#define ACCEL_TCG_TLB_BOUNDS_H + +#define CPU_TLB_DYN_MIN_BITS 6 +#define CPU_TLB_DYN_DEFAULT_BITS 8 + +# if HOST_LONG_BITS =3D=3D 32 +/* Make sure we do not require a double-word shift for the TLB load */ +# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) +# else /* HOST_LONG_BITS =3D=3D 64 */ +/* + * Assuming TARGET_PAGE_BITS=3D=3D12, with 2**22 entries we can cover 2**(= 22+12) =3D=3D + * 2**34 =3D=3D 16G of address space. This is roughly what one would expec= t a + * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel + * Skylake's Level-2 STLB has 16 1G entries. + * Also, make sure we do not size the TLB past the guest's address space. + */ +# ifdef TARGET_PAGE_BITS_VARY +# define CPU_TLB_DYN_MAX_BITS \ + MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) +# else +# define CPU_TLB_DYN_MAX_BITS \ + MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) +# endif +# endif + +#endif /* ACCEL_TCG_TLB_BOUNDS_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 28c47d4872..a717f357d5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -41,6 +41,7 @@ #include "trace.h" #include "tb-hash.h" #include "tb-internal.h" +#include "tlb-bounds.h" #include "internal-common.h" #include "internal-target.h" #ifdef CONFIG_PLUGIN diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bb161ae61a..87fb6c51d3 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -47,6 +47,7 @@ #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "tb-internal.h" +#include "tlb-bounds.h" #include "exec/translator.h" #include "exec/tb-flush.h" #include "qemu/bitmap.h" --=20 2.43.0