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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f45c7sm129259a12.16.2025.04.23.18.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 18:00:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745456416; x=1746061216; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9MNvSRDi98aye64ClUWawrfGEwwTpHlnQYD/vV4dHwA=; b=khbK+y+qZHd+DpKSvbvQLeu1aRP1+YAVmCZhPnlg9p1hmtFxGQE/3dEXT/azWNHJlv fMj7sYqiHU9NKNqL3WbE7uInpfXJoFdFxxTDAysEfSlKIL7BU8dQjhDsN8hdj/V5DWiw /5Xgv0UhkqdTSJDQbPkq/C+KsACMo80fmsrBKkU1seoq1doo6RnMP0LcokcShFbL7KQk yfV5G2K9+eosKFk6csWLFvPQG8is+xilAaFBQlq2P+8oinka/hV5wsDYt5xykM6lnKJl I+7VMdmT2A4KscAhRbQMS86xJA4WLAwzPrNBBjhA0/ASaMn7AZ/E+YvCQI1twxK1fiZb 0nxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745456416; x=1746061216; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9MNvSRDi98aye64ClUWawrfGEwwTpHlnQYD/vV4dHwA=; b=xSjtcuS8X3lms0nRRPFdO5d/brkC4ryt3RGAAhafp6swgkSJI3dAbZoqDuEjnMGihV yGbdw1yrTAvq2VZgY2XJNYnDjOpIdjo1orKFhN1at1CJocaXtYS7gBeMHa9WVuErI4U/ /WpRLpdezXckHgN42sZc07aTg56uiZLr+EGK1gOm4MSvt1ZBJ49Dq2kq9IRYxEegnIOp drk/WwB2d1qM456tw/iCsvQoRRE6F2lrnLGs109/Cdf8x99c/27C/Nn290y2XcQgYtcT 2iYmfDd5pm73tLMkmHwQ0r4zvDkiV0eFm97PGHBVJjgSkdBRoZeWUQvQ/qCwMM7a9DVi wY6A== X-Gm-Message-State: AOJu0YxjiOY1s4NL86CJwxk+quZusjNYBwyK8zwcNOsV1NDVRq14j6FH muAhvBp6lkleht+273g1HUqhWvYH2WmYsf0WVdn0bhy+4Zfx9LX5oo4kbYq1hmFfo2plkLjhEj+ i X-Gm-Gg: ASbGncsdW/vPVSE0tC1BIJABCqY2kD3eUtSKnYgukrst8lQjq1rr786lW1dQ9JWsXO3 7h5Wk4htjfrYF1o8itES+jOEAv2pRnhrh1ptVvQZ0e1ekPV+Dvvg3FIvHFW6ofey5hQDQG7T+n6 8m3/l5TzWD0Z83kbUKmJ37AKZuinls2JCzEPz0Kk9MeC3oOTyKudJEWT71CGi1R2hpJPVIrW4Eg wXRH0ND07dRyNTMJNBfuiil+0VQAqWSzBbr5pyknn1ACMfgA2i+2mypsXxZtv7KfGXIwFnq+S7J ry6I2uIU1YvsZ7C0A5AYBtiYH/GWtFM6nLdYof4WdRc2TTl8i8R1tiuqp4MSpFz+B7O4dsfEJ8E = X-Google-Smtp-Source: AGHT+IEufZc5pe3VdLbKXe7a/Atl6hdRv9XUy9qoxGBe8Ii8Kch0EXmgQ5N7wUkMQCM/eK2uMJLt5g== X-Received: by 2002:a05:6a20:549c:b0:1f5:5807:13c7 with SMTP id adf61e73a8af0-20444e9c443mr862966637.17.1745456415731; Wed, 23 Apr 2025 18:00:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 137/148] tcg: Propagate CPUState argument to cpu_req_mo() Date: Wed, 23 Apr 2025 17:49:22 -0700 Message-ID: <20250424004934.598783-138-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250424004934.598783-1-richard.henderson@linaro.org> References: <20250424004934.598783-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745457285372019000 From: Philippe Mathieu-Daud=C3=A9 In preparation of having tcg_req_mo() access CPUState in the next commit, pass it to cpu_req_mo(), its single caller. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/internal-target.h | 3 ++- accel/tcg/cputlb.c | 20 ++++++++++---------- accel/tcg/user-exec.c | 20 ++++++++++---------- 3 files changed, 22 insertions(+), 21 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 1a46a7c87d..23aac39b57 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -59,12 +59,13 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); =20 /** * cpu_req_mo: + * @cpu: CPUState * @type: TCGBar * * If tcg_req_mo indicates a barrier for @type is required * for the guest memory model, issue a host memory barrier. */ -#define cpu_req_mo(type) \ +#define cpu_req_mo(cpu, type) \ do { \ if (tcg_req_mo(type)) { \ smp_mb(); \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2cafd38d2a..35b1ff03a5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2324,7 +2324,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); tcg_debug_assert(!crosspage); =20 @@ -2339,7 +2339,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2363,7 +2363,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint32_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2384,7 +2384,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint64_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2407,7 +2407,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, Int128 ret; int first; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { @@ -2735,7 +2735,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); tcg_debug_assert(!crosspage); =20 @@ -2749,7 +2749,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, bool crosspage; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2771,7 +2771,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2792,7 +2792,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2815,7 +2815,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, uint64_t a, b; int first; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1b878ead7a..3f4d682446 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1061,7 +1061,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, void *haddr; uint8_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, access_type); ret =3D ldub_p(haddr); clear_helper_retaddr(); @@ -1075,7 +1075,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_2(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1093,7 +1093,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint32_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_4(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1111,7 +1111,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint64_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_8(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1130,7 +1130,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr, MemOp mop =3D get_memop(oi); =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_LOAD); ret =3D load_atom_16(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1146,7 +1146,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, { void *haddr; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, MMU_DATA_STORE); stb_p(haddr, val); clear_helper_retaddr(); @@ -1158,7 +1158,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1174,7 +1174,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1190,7 +1190,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1206,7 +1206,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, void *haddr; MemOpIdx mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { --=20 2.43.0