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Wed, 23 Apr 2025 07:26:19 -0400 Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2025 04:26:14 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa003.jf.intel.com with ESMTP; 23 Apr 2025 04:26:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745407577; x=1776943577; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hFmCDh1g6jFUGO8m7NQhmZ+M7gV0kLnTguTu4AQJhYA=; b=ILm2u1j2aUjNZkAGGbAGYxnkVZuTrF2q8+d/8BzGLSNdp0DblD59N/m8 rI0RWsNCuda8YNYH8QyrrXk0Q9QcTgiPItaY0HToPFjW6qqitTAjZ8cuF b5AEG32qWcRswWwPmid2yI9lvhxYQBdRB5LJK5umM1z5Xc9N02qvX26tL UBphuCfbQaywn0ES3kuZUGKaLTmCh4V1dcCmvJZVw5w6Ux0lSCfhJUnw4 85k1BL2CulrN6omdJAVRViJUnAfG2oN1sDnEfzZ+kjTSD/KSEgx9nbx2c fLzVPE3htJQGusLs/HErcH4ybTpkjhmeZ6wjzz8E7gQYpiU8rJ53YeGCF g==; X-CSE-ConnectionGUID: 0tqkhLdeR6WSPtR5xXim4Q== X-CSE-MsgGUID: lIcY+OS6TmGZQLTEoie26w== X-IronPort-AV: E=McAfee;i="6700,10204,11411"; a="50825254" X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="50825254" X-CSE-ConnectionGUID: tsvDa8cqR0qLIgIGbl3vlA== X-CSE-MsgGUID: FVISKOKWSki5mLfx20fGug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="137150725" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Babu Moger , Ewan Hai , Xiaoyao Li , Tejus GK , Jason Zeng , Manish Mishra , Tao Su , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [RFC 01/10] i386/cpu: Mark CPUID[0x80000005] as reserved for Intel Date: Wed, 23 Apr 2025 19:46:53 +0800 Message-Id: <20250423114702.1529340-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423114702.1529340-1-zhao1.liu@intel.com> References: <20250423114702.1529340-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407629501019100 Content-Type: text/plain; charset="utf-8" Per SDM, 0x80000005 leaf is reserved for Intel CPU, and its current "assert" check blocks adding new cache model for non-AMD CPUs. Therefore, check the vendor and encode this leaf as all-0 for Intel CPU. And since Zhaoxin mostly follows Intel behavior, apply the vendor check for Zhaoxin as well. Note, for !vendor_cpuid_only case, non-AMD CPU would get the wrong information, i.e., get AMD's cache model for Intel or Zhaoxin CPUs. For this case, there is no need to tweak for non-AMD CPUs, because vendor_cpuid_only has been turned on by default since PC machine v6.1. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1b64ceaaba46..8fdafa8aedaf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7248,11 +7248,23 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *edx =3D env->cpuid_model[(index - 0x80000002) * 4 + 3]; break; case 0x80000005: - /* cache info (L1 cache) */ - if (cpu->cache_info_passthrough) { + /* + * cache info (L1 cache) + * + * For !vendor_cpuid_only case, non-AMD CPU would get the wrong + * information, i.e., get AMD's cache model. It doesn't matter, + * vendor_cpuid_only has been turned on by default since + * PC machine v6.1. + */ + if (cpu->vendor_cpuid_only && + (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } else if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; } + *eax =3D (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); *ebx =3D (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | --=20 2.34.1 From nobody Sat Nov 15 23:38:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1745407717; cv=none; d=zohomail.com; s=zohoarc; b=kBRhpuUDprNqw4GTTsJHw8F0bgwXLsILX6pzDvxQ3EKjM2JoKuE0oTzgEsj8IagKTJbLBSKJxth/ZVwJaMFBjjK0SjZzoiOZ87EbaORqVmWQ/I2CoCx646l/Q4Rzuyc058tvb29fAYWzkMAPL1cwvVkP+Rt9JhSWqBCdt7qJWF0= ARC-Message-Signature: i=1; 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bh=1ySg7f0MXv81a/sh1bBBvbxV263DWqo05jeGhcaGOgU=; b=hOGRjMEBAlVMpTSxyF4H0h6Enjk1PXpnAkyF450dORVBbyqYKzvo3VBV 88xEeemw+Kpu0PRBISEhbWi+oszxH4hwWD6IxYe2RbroKxBmyxWH5ooyR tXIiRqfKJrA9DsYsmvXfdamZ1lzF/3M20kFgXRjfdNdSVpqYuJ5QFw1e2 VdGHPBaF7zkgIvFKNqB2KBve9m5EJAPhq91dPwSwd4ma79i7Uzdf5PHCD 1Tvdt0lsMmV+jw0SsIvEavPGPh0j4pe+zpCDwSkkXu7rwiKr37pfAK3vZ cUJB6KA5TaHptTRfEUloqV1HGURbNgKOo/D5MlDVQpQbHOWlcmu9uVaU5 A==; X-CSE-ConnectionGUID: WFbaVZoPQzOixBMEDilUKg== X-CSE-MsgGUID: Kx6n0vXDRKONpr+BIEeSFg== X-IronPort-AV: E=McAfee;i="6700,10204,11411"; a="50825262" X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="50825262" X-CSE-ConnectionGUID: J/zQ7+W7SpG7028dkKk6iw== X-CSE-MsgGUID: 0bwUUFdxSS+gDtdPahEu6A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="137150732" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Babu Moger , Ewan Hai , Xiaoyao Li , Tejus GK , Jason Zeng , Manish Mishra , Tao Su , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [RFC 02/10] i386/cpu: Fix CPUID[0x80000006] for Intel CPU Date: Wed, 23 Apr 2025 19:46:54 +0800 Message-Id: <20250423114702.1529340-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423114702.1529340-1-zhao1.liu@intel.com> References: <20250423114702.1529340-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407719477019100 Content-Type: text/plain; charset="utf-8" Per SDM, Intel supports CPUID[0x80000006]. But only L2 information is encoded in ECX (note that L2 associativity field encodings rules consistent with AMD are used), all other fields are reserved. Therefore, make the following changes to CPUID[0x80000006]: * Rename AMD_ENC_ASSOC to X86_ENC_ASSOC since Intel also uses the same rules. (While there are some slight differences between the rules in AMD APM v4.07 no.40332 and those in the current QEMU, generally they are consistent.) * Check the vendor in CPUID[0x80000006] and just encode L2 to ECX for Intel. * Assert L2's lines_per_tag is not 0 for AMD, and assert it is 0 for Intel. * Apply the encoding change of Intel for Zhaoxin as well. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8fdafa8aedaf..5119d7aa4150 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -436,8 +436,8 @@ static uint32_t encode_cache_cpuid80000005(CPUCacheInfo= *cache) =20 #define ASSOC_FULL 0xFF =20 -/* AMD associativity encoding used on CPUID Leaf 0x80000006: */ -#define AMD_ENC_ASSOC(a) (a <=3D 1 ? a : \ +/* x86 associativity encoding used on CPUID Leaf 0x80000006: */ +#define X86_ENC_ASSOC(a) (a <=3D 1 ? a : \ a =3D=3D 2 ? 0x2 : \ a =3D=3D 4 ? 0x4 : \ a =3D=3D 8 ? 0x6 : \ @@ -460,19 +460,19 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *= l2, { assert(l2->size % 1024 =3D=3D 0); assert(l2->associativity > 0); - assert(l2->lines_per_tag > 0); assert(l2->line_size > 0); *ecx =3D ((l2->size / 1024) << 16) | - (AMD_ENC_ASSOC(l2->associativity) << 12) | + (X86_ENC_ASSOC(l2->associativity) << 12) | (l2->lines_per_tag << 8) | (l2->line_size); =20 + /* For Intel, EDX is reserved. */ if (l3) { assert(l3->size % (512 * 1024) =3D=3D 0); assert(l3->associativity > 0); assert(l3->lines_per_tag > 0); assert(l3->line_size > 0); *edx =3D ((l3->size / (512 * 1024)) << 18) | - (AMD_ENC_ASSOC(l3->associativity) << 12) | + (X86_ENC_ASSOC(l3->associativity) << 12) | (l3->lines_per_tag << 8) | (l3->line_size); } else { *edx =3D 0; @@ -7277,15 +7277,25 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; + } else if (cpu->vendor_cpuid_only && + (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { + *eax =3D *ebx =3D 0; + assert(env->cache_info_cpuid4.l2_cache->lines_per_tag =3D=3D 0= ); + encode_cache_cpuid80000006(env->cache_info_cpuid4.l2_cache, + NULL, ecx, edx); + break; } - *eax =3D (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | + + *eax =3D (X86_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | (L2_DTLB_2M_ENTRIES << 16) | - (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | + (X86_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | (L2_ITLB_2M_ENTRIES); - *ebx =3D (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | + *ebx =3D (X86_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | (L2_DTLB_4K_ENTRIES << 16) | - (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | + (X86_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | (L2_ITLB_4K_ENTRIES); + + assert(env->cache_info_amd.l2_cache->lines_per_tag > 0); encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, cpu->enable_l3_cache ? env->cache_info_amd.l3_cache : NULL, --=20 2.34.1 From nobody Sat Nov 15 23:38:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1745407766; cv=none; d=zohomail.com; s=zohoarc; b=OZ08/rBDxacuUYBVQT/E3bxtWjVrETjhIT1gdOy1omHjMQtStnmdmlSgcCqqi8/NC/N4TZ78iJdunwLe3Lj4tjgMyHUPpIre5VK23fiiLRiWfHvPa/QKBBGb+ykulxUO5OPTLTHV1y9y/Oh87ma5XrVqVUFfuFsNgb0jamwJPG4= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407769122019000 Add the cache model to SierraForest (v3) to better emulate its environment. The cache model is based on SierraForest-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x80 (128) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 128 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x7 (7) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x1000 (4096) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 4096 (size synth) =3D 4194304 (4 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1ff (511) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x24000 (147456) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 147456 (size synth) =3D 113246208 (108 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Signed-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5119d7aa4150..4f7ab6246e39 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2453,6 +2453,97 @@ static const CPUCaches epyc_genoa_cache_info =3D { }, }; =20 +static const CPUCaches xeon_srf_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x0.EAX + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + // CPUID 0x4.0x0.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + // CPUID 0x4.0x0.ECX + .sets =3D 64, + + // CPUID 0x4.0x0.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 32 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x1.EAX + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + // CPUID 0x4.0x1.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + // CPUID 0x4.0x1.ECX + .sets =3D 128, + + // CPUID 0x4.0x1.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 64 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x2.EAX + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + // CPUID 0x4.0x2.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + // CPUID 0x4.0x2.ECX + .sets =3D 4096, + + // CPUID 0x4.0x2.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 4 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_MODULE, + }, + .l3_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x3.EAX + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + // CPUID 0x4.0x3.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + // CPUID 0x4.0x3.ECX + .sets =3D 147456, + + // CPUID 0x4.0x3.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 108 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + /* The following VMX features are not supported by KVM and are left out in= the * CPU definitions: * @@ -4571,6 +4662,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 3, + .note =3D "with srf-sp cache model", + .cache_info =3D &xeon_srf_cache_info, + }, { /* end of list */ }, }, }, --=20 2.34.1 From nobody Sat Nov 15 23:38:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1745407705; cv=none; d=zohomail.com; s=zohoarc; b=QYTeKf/uIGWuaVvRxsFktwiTtAC1JGCu1hgmcn1yY+Y3jRZCYY+x/TGpsLhaaU+SrkHh+QVXcEGU4+CljuYVcAlZSAc1iS96iBtW3AsWdrPaYkaHjxw5U+IH9e8mqSBwTbgZVFMAgy9pE1YcLg0uluesFpQ2ZqkD5CxxAEqVW9g= ARC-Message-Signature: i=1; a=rsa-sha256; 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bh=ZACIexM/oE4FNN0LXsaQvogct46TsXFr8hAXTBqvlCM=; b=BqRhQiSL61tV5GoiQ3CxkUfIDPLy/v4hO1mCeH4A4datoPfwGbXVaS87 TU2PAabSpQSOZmenEX+nXsR/7sDIq1S8utIgpHninjsJ03tlkk+eGRE40 6+/M7p3ejqZmhBAeiyWZABAjxgXocheAVvAe0YNIbS96ON5JqL8+Deedz UcFO9DAoUdEkDF0BvFfm1JqF+MD14ZdCEyuqql7ykmn4kTdh7tcpe7Ute lwj3SeDRnIhuzding3fmGil2104whUJOmQqFD62NxkX5p3jpaShlNvFNw 43d5t0Ogto5Rk66V0oiSRniVcA4WOsF4GVoPgTnet1gRcHtYsjJPuC/FD w==; X-CSE-ConnectionGUID: MVQI8b3RQk6tl/eyRG8OYw== X-CSE-MsgGUID: jn7bHW8bQTu0tAIRPR8DWA== X-IronPort-AV: E=McAfee;i="6700,10204,11411"; a="50825276" X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="50825276" X-CSE-ConnectionGUID: gSa9HZhSRsyXUQ8/6Q7mhA== X-CSE-MsgGUID: AOj9NinMQG+cUDI4+oh1HA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="137150748" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Babu Moger , Ewan Hai , Xiaoyao Li , Tejus GK , Jason Zeng , Manish Mishra , Tao Su , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [RFC 04/10] i386/cpu: Introduce cache model for GraniteRapids Date: Wed, 23 Apr 2025 19:46:56 +0800 Message-Id: <20250423114702.1529340-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423114702.1529340-1-zhao1.liu@intel.com> References: <20250423114702.1529340-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407707464019100 Add the cache model to GraniteRapids (v3) to better emulate its environment. The cache model is based on GraniteRapids-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 49152 (48 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x800 (2048) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 2048 (size synth) =3D 2097152 (2 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0xff (255) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x48000 (294912) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 294912 (size synth) =3D 301989888 (288 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Signed-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4f7ab6246e39..00e4a8372c28 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2453,6 +2453,97 @@ static const CPUCaches epyc_genoa_cache_info =3D { }, }; =20 +static const CPUCaches xeon_gnr_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x0.EAX + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + // CPUID 0x4.0x0.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + // CPUID 0x4.0x0.ECX + .sets =3D 64, + + // CPUID 0x4.0x0.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 48 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x1.EAX + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + // CPUID 0x4.0x1.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + // CPUID 0x4.0x1.ECX + .sets =3D 64, + + // CPUID 0x4.0x1.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 64 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x2.EAX + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + // CPUID 0x4.0x2.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + // CPUID 0x4.0x2.ECX + .sets =3D 2048, + + // CPUID 0x4.0x2.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 2 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x3.EAX + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + // CPUID 0x4.0x3.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + // CPUID 0x4.0x3.ECX + .sets =3D 294912, + + // CPUID 0x4.0x3.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 288 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + static const CPUCaches xeon_srf_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { // CPUID 0x4.0x0.EAX @@ -4517,6 +4608,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 3, + .note =3D "with gnr-sp cache model", + .cache_info =3D &xeon_gnr_cache_info, + }, { /* end of list */ }, }, }, --=20 2.34.1 From nobody Sat Nov 15 23:38:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1745407637; cv=none; d=zohomail.com; s=zohoarc; b=PViV3cGd4KaIbGp/tWGqdoq6BuWSAG0CD0fHZuoWrVRnjgqJi2jDdr7wAGlhZlCCZ7PRnWDCCK3gHzhDrqjYo26SJ+RegZfM5LetkZ7I3oGrkrvh8myP4aRC4E1ili9at7ULbTjnUDtnDQq+NZetg8p0CE8VV41vDy4KEtnXOxk= ARC-Message-Signature: i=1; a=rsa-sha256; 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bh=EdOiRvpfaIrH24kzspKuhxR/NwlYqPkO66JzlNcO+rc=; b=GvReGvw3J9Igy8tupkRzXX0tgIrbXDfxSUwsvXXtbIxMtoX84ZhNdGAO gTBg6y5/9rO2sNi071N1CJ+zdUPrcdcccnv98dMsqWYQQwnyaKDn5LONx Ux8pozmn76JXI9iFoEKlC3Sr5q3z1MWSTNP5mfHaxDeFZEolUUqEABDHe lZxL7VozVq8VGr6ZFdlRNinInW/0O2AiQ7YymkjHzYbb15lDZz5nHULBv OaLvo4rzN8vQoEpGFFAWCeroSzXiN022tOzYA/U1x2P29nPTY5CdNbbZ9 LsKDA2Vefp5r3s2G2XJ+c9AYff3eY1rtNO52d0rEs0Xz9s2r7NUitkTO7 g==; X-CSE-ConnectionGUID: e453FKHYRFG39RhlvUwtbg== X-CSE-MsgGUID: 0Fza3vFdRDW0ehDDe/6ITQ== X-IronPort-AV: E=McAfee;i="6700,10204,11411"; a="50825288" X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="50825288" X-CSE-ConnectionGUID: C38RJhAtSU+00GWPFsrWww== X-CSE-MsgGUID: sBnRGwgDQUm0vpmg7/00Mg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="137150761" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Babu Moger , Ewan Hai , Xiaoyao Li , Tejus GK , Jason Zeng , Manish Mishra , Tao Su , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [RFC 05/10] i386/cpu: Introduce cache model for SapphireRapids Date: Wed, 23 Apr 2025 19:46:57 +0800 Message-Id: <20250423114702.1529340-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423114702.1529340-1-zhao1.liu@intel.com> References: <20250423114702.1529340-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407639379019100 Add the cache model to SapphireRapids (v4) to better emulate its environment. The cache model is based on SapphireRapids-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 49152 (48 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x800 (2048) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 2048 (size synth) =3D 2097152 (2 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x7f (127) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xf (15) number of sets =3D 0x10000 (65536) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 65536 (size synth) =3D 62914560 (60 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Signed-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 00e4a8372c28..d90e048d48f2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2453,6 +2453,97 @@ static const CPUCaches epyc_genoa_cache_info =3D { }, }; =20 +static const CPUCaches xeon_spr_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x0.EAX + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + // CPUID 0x4.0x0.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + // CPUID 0x4.0x0.ECX + .sets =3D 64, + + // CPUID 0x4.0x0.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 48 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x1.EAX + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + // CPUID 0x4.0x1.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + // CPUID 0x4.0x1.ECX + .sets =3D 64, + + // CPUID 0x4.0x1.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 32 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x2.EAX + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + // CPUID 0x4.0x2.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + // CPUID 0x4.0x2.ECX + .sets =3D 2048, + + // CPUID 0x4.0x2.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 2 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + // CPUID 0x4.0x3.EAX + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + // CPUID 0x4.0x3.EBX + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 15, + + // CPUID 0x4.0x3.ECX + .sets =3D 65536, + + // CPUID 0x4.0x3.EDX + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 60 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + static const CPUCaches xeon_gnr_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { // CPUID 0x4.0x0.EAX @@ -4455,6 +4546,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 4, + .note =3D "with spr-sp cache model", + .cache_info =3D &xeon_spr_cache_info, + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Sat Nov 15 23:38:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1745407668; cv=none; d=zohomail.com; s=zohoarc; b=JwBmd0oM2gSX2bddRmvHh11flOWOIbqXdgYlTN0aYfXuX33PsTyc0PMx5GfJ+f7EAeAVIeSRdGA3yw/F2Fr2MKMFFN/w849NiUArSz4QLvllrlausP+W/1UFwL0obGEtV9N5xv6V9RaIBjpcNe2GziwPOZYQ98wgQydCHve0L8U= ARC-Message-Signature: i=1; a=rsa-sha256; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407669813019000 Content-Type: text/plain; charset="utf-8" From: Xiaoyao Li Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e., when topology level that cannot be enumerated by leaf 0xB, e.g., die or module level, are configured for the guest, e.g., -smp xx,dies=3D2. However, TDX architecture forces to require CPUID 0x1f to configure CPU topology. Introduce a bool flag, enable_cpuid_0x1f, in CPU for the case that requires CPUID leaf 0x1f to be exposed to guest. Introduce a new function x86_has_cpuid_0x1f(), which is the warpper of cpu->enable_cpuid_0x1f and x86_has_extended_topo() to check if it needs to enable cpuid leaf 0x1f for the guest. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 4 ++-- target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 2 +- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d90e048d48f2..e0716dbe5934 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7292,7 +7292,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x1F: /* V2 Extended Topology Enumeration Leaf */ - if (!x86_has_extended_topo(env->avail_cpu_topo)) { + if (!x86_has_cpuid_0x1f(cpu)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } @@ -8178,7 +8178,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **err= p) * cpu->vendor_cpuid_only has been unset for compatibility with ol= der * machine types. */ - if (x86_has_extended_topo(env->avail_cpu_topo) && + if (x86_has_cpuid_0x1f(cpu) && (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 76f24446a55d..3910b488f775 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2251,6 +2251,9 @@ struct ArchCPU { /* Compatibility bits for old machine types: */ bool enable_cpuid_0xb; =20 + /* Force to enable cpuid 0x1f */ + bool enable_cpuid_0x1f; + /* Enable auto level-increase for all CPUID leaves */ bool full_cpuid_auto_level; =20 @@ -2513,6 +2516,12 @@ void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); bool cpu_has_x2apic_feature(CPUX86State *env); =20 +static inline bool x86_has_cpuid_0x1f(X86CPU *cpu) +{ + return cpu->enable_cpuid_0x1f || + x86_has_extended_topo(cpu->env.avail_cpu_topo); +} + /* helper.c */ void x86_cpu_set_a20(X86CPU *cpu, int a20_state); void cpu_sync_avx_hflag(CPUX86State *env); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6c749d4ee812..23b8de308525 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1863,7 +1863,7 @@ static uint32_t kvm_x86_build_cpuid(CPUX86State *env, break; } case 0x1f: - if (!x86_has_extended_topo(env->avail_cpu_topo)) { + if (!x86_has_cpuid_0x1f(env_archcpu(env))) { cpuid_i--; break; } --=20 2.34.1 From nobody Sat Nov 15 23:38:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="50825307" X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="50825307" X-CSE-ConnectionGUID: 9A6bHYTjSUiobgHkXuiizw== X-CSE-MsgGUID: bL+hEagfSoWySz+YUSAf0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,233,1739865600"; d="scan'208";a="137150786" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Babu Moger , Ewan Hai , Xiaoyao Li , Tejus GK , Jason Zeng , Manish Mishra , Tao Su , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [RFC 07/10] i386/cpu: Add a "cpuid-0x1f" property Date: Wed, 23 Apr 2025 19:46:59 +0800 Message-Id: <20250423114702.1529340-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423114702.1529340-1-zhao1.liu@intel.com> References: <20250423114702.1529340-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407673333019100 Content-Type: text/plain; charset="utf-8" From: Manish Mishra Add a "cpuid-0x1f" property so that CPU models can enable it and have 0x1f CPUID leaf natually as the Host CPU. The advantage is that when the CPU model's cache model is already consistent with the Host CPU, for example, SRF defaults to l2 per module & l3 per package, 0x1f can better help users identify the topology in the VM. Adding 0x1f for specific CPU models should not cause any trouble in principle. This property is only enabled for CPU models that already have 0x1f leaf on the Host, so software that originally runs normally on the Host won't encounter issues in the Guest with corresponding CPU model. Conversely, some software that relies on checking 0x1f might experience problems in the Guest due to the lack of 0x1f [*]. In summary, adding 0x1f is also intended to further emulate the Host CPU environment. Therefore, the "x-" prefix is not added to this property. [*]: https://lore.kernel.org/qemu-devel/PH0PR02MB738410511BF51B12DB09BE6CF6= AC2@PH0PR02MB7384.namprd02.prod.outlook.com/ Co-authored-by: Xiaoyao Li (Missing signed-off from Manish & Xiaoyao) Signed-off-by: Zhao Liu --- Note: This patch integrates the idea from 2 previous posted patches (ordered by post time)[1] [2]. Although the target cases are not exactly the same as this patch, add the authorship of previous authors. [1]: From Manish: https://lore.kernel.org/qemu-devel/20240722101859.47408-1= -manish.mishra@nutanix.com/ [2]: From Xiaoyao: https://lore.kernel.org/qemu-devel/20240813033145.279307= -1-xiaoyao.li@intel.com/ --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e0716dbe5934..26dc5b6a6a8c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9195,6 +9195,7 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, t= rue), + DEFINE_PROP_BOOL("cpuid-0x1f", X86CPU, enable_cpuid_0x1f, false), }; =20 #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Sat Nov 15 23:38:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="137150812" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Babu Moger , Ewan Hai , Xiaoyao Li , Tejus GK , Jason Zeng , Manish Mishra , Tao Su , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [RFC 08/10] i386/cpu: Enable 0x1f leaf for SierraForest by default Date: Wed, 23 Apr 2025 19:47:00 +0800 Message-Id: <20250423114702.1529340-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423114702.1529340-1-zhao1.liu@intel.com> References: <20250423114702.1529340-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407705907019000 Content-Type: text/plain; charset="utf-8" Host SierraForest CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 26dc5b6a6a8c..2a518b68e67a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4856,8 +4856,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 3, - .note =3D "with srf-sp cache model", + .note =3D "with srf-sp cache model and 0x1f leaf", .cache_info =3D &xeon_srf_cache_info, + .props =3D (PropValue[]) { + { "cpuid-0x1f", "on" }, + } }, { /* end of list */ }, }, --=20 2.34.1 From nobody Sat Nov 15 23:38:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1745407727; cv=none; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407729882019000 Content-Type: text/plain; charset="utf-8" Host GraniteRapids CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2a518b68e67a..38b330aaed4f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4706,8 +4706,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 3, - .note =3D "with gnr-sp cache model", + .note =3D "with gnr-sp cache model and 0x1f leaf", .cache_info =3D &xeon_gnr_cache_info, + .props =3D (PropValue[]) { + { "cpuid-0x1f", "on" }, + } }, { /* end of list */ }, }, --=20 2.34.1 From nobody Sat Nov 15 23:38:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1745407715; cv=none; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.294, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1745407717361019100 Content-Type: text/plain; charset="utf-8" Host SapphireRapids CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Signed-off-by: Zhao Liu --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 38b330aaed4f..5573a9fd6c61 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4548,8 +4548,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 4, - .note =3D "with spr-sp cache model", + .note =3D "with spr-sp cache model and 0x1f leaf", .cache_info =3D &xeon_spr_cache_info, + .props =3D (PropValue[]) { + { "cpuid-0x1f", "on" }, + } }, { /* end of list */ } } --=20 2.34.1