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Wed, 23 Apr 2025 04:06:46 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 2/9] hw/riscv/virt.c: remove trivial virt_memmap references Date: Wed, 23 Apr 2025 08:06:23 -0300 Message-ID: <20250423110630.2249904-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406552992019100 Content-Type: text/plain; charset="utf-8" We should use s->memmap instead of virt_memmap to be able to use an updated memmap when we start versioning the board. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6e3e34879f..fdf0318e15 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -166,8 +166,8 @@ static void virt_flash_map1(PFlashCFI01 *flash, static void virt_flash_map(RISCVVirtState *s, MemoryRegion *sysmem) { - hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; - hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; + hwaddr flashsize =3D s->memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D s->memmap[VIRT_FLASH].base; =20 virt_flash_map1(s->flash[0], flashbase, flashsize, sysmem); @@ -999,8 +999,8 @@ static void create_fdt_rtc(RISCVVirtState *s, const Mem= MapEntry *memmap, static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) { MachineState *ms =3D MACHINE(s); - hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; - hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; + hwaddr flashsize =3D s->memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D s->memmap[VIRT_FLASH].base; g_autofree char *name =3D g_strdup_printf("/flash@%" PRIx64, flashbase= ); =20 qemu_fdt_add_subnode(ms->fdt, name); @@ -1035,7 +1035,7 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s= , uint16_t bdf) g_autofree char *pci_node =3D NULL; =20 pci_node =3D g_strdup_printf("/soc/pci@%lx", - (long) virt_memmap[VIRT_PCIE_ECAM].base); + (long) s->memmap[VIRT_PCIE_ECAM].base); iommu_node =3D g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, PCI_SLOT(bdf), PCI_FUNC(bdf)); iommu_phandle =3D qemu_fdt_alloc_phandle(fdt); @@ -1104,7 +1104,7 @@ static void create_fdt_iommu(RISCVVirtState *s, uint1= 6_t bdf) g_autofree char *pci_node =3D NULL; =20 pci_node =3D g_strdup_printf("/soc/pci@%lx", - (long) virt_memmap[VIRT_PCIE_ECAM].base); + (long) s->memmap[VIRT_PCIE_ECAM].base); iommu_node =3D g_strdup_printf("%s/iommu@%x", pci_node, bdf); iommu_phandle =3D qemu_fdt_alloc_phandle(fdt); qemu_fdt_add_subnode(fdt, iommu_node); @@ -1126,24 +1126,24 @@ static void finalize_fdt(RISCVVirtState *s) uint32_t irq_pcie_phandle =3D 1, irq_virtio_phandle =3D 1; uint32_t iommu_sys_phandle =3D 1; =20 - create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, + create_fdt_sockets(s, s->memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, &msi_pcie_phandle); =20 - create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); + create_fdt_virtio(s, s->memmap, irq_virtio_phandle); =20 if (virt_is_iommu_sys_enabled(s)) { create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, &iommu_sys_phandle); } - create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle, + create_fdt_pcie(s, s->memmap, irq_pcie_phandle, msi_pcie_phandle, iommu_sys_phandle); =20 - create_fdt_reset(s, virt_memmap, &phandle); + create_fdt_reset(s, s->memmap, &phandle); =20 - create_fdt_uart(s, virt_memmap, irq_mmio_phandle); + create_fdt_uart(s, s->memmap, irq_mmio_phandle); =20 - create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); + create_fdt_rtc(s, s->memmap, irq_mmio_phandle); } =20 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) @@ -1366,14 +1366,13 @@ static void create_platform_bus(RISCVVirtState *s, = DeviceState *irqchip) { DeviceState *dev; SysBusDevice *sysbus; - const MemMapEntry *memmap =3D virt_memmap; int i; MemoryRegion *sysmem =3D get_system_memory(); =20 dev =3D qdev_new(TYPE_PLATFORM_BUS_DEVICE); dev->id =3D g_strdup(TYPE_PLATFORM_BUS_DEVICE); qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); - qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); + qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].si= ze); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); s->platform_bus_dev =3D dev; =20 @@ -1384,7 +1383,7 @@ static void create_platform_bus(RISCVVirtState *s, De= viceState *irqchip) } =20 memory_region_add_subregion(sysmem, - memmap[VIRT_PLATFORM_BUS].base, + s->memmap[VIRT_PLATFORM_BUS].base, sysbus_mmio_get_region(sysbus, 0)); } =20 --=20 2.49.0