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Wed, 23 Apr 2025 04:06:43 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 1/9] hw/riscv/virt.c: enforce s->memmap use in machine_init() Date: Wed, 23 Apr 2025 08:06:22 -0300 Message-ID: <20250423110630.2249904-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406573069019100 Content-Type: text/plain; charset="utf-8" Throughout the code we're accessing the board memmap, most of the time, by accessing it statically via 'virt_memmap'. This static map is also assigned in the machine state in s->memmap. We're also passing it as a variable to some fdt functions, which is unorthodox since we can spare a function argument by accessing it statically or via the machine state. All the current forms are valid but not all of the are scalable. In the future we will version this board, and then all this code will need rework because it should point to the updated memmap. In this case, we'll want to assign the adequate versioned memmap once during init, in s->memmap like it is being done today, and the rest of the code will access the updated map via s->memmap. We're also enforcing the pattern of using s->memmap instead of assigning it to a temp variable 'memmap'. Code is copy/pasted around all the time and being consistent is important. We'll start these rather mechanical changes with virt_machine_init(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Joel Stanley --- hw/riscv/virt.c | 54 ++++++++++++++++++++++++------------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c9d255d8a8..6e3e34879f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1527,7 +1527,6 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) =20 static void virt_machine_init(MachineState *machine) { - const MemMapEntry *memmap =3D virt_memmap; RISCVVirtState *s =3D RISCV_VIRT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); @@ -1535,6 +1534,8 @@ static void virt_machine_init(MachineState *machine) int i, base_hartid, hart_count; int socket_count =3D riscv_socket_count(machine); =20 + s->memmap =3D virt_memmap; + /* Check socket count limit */ if (VIRT_SOCKETS_MAX < socket_count) { error_report("number of sockets/nodes should be less than %d", @@ -1582,7 +1583,7 @@ static void virt_machine_init(MachineState *machine) if (virt_aclint_allowed() && s->have_aclint) { if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { /* Per-socket ACLINT MTIMER */ - riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, @@ -1591,28 +1592,28 @@ static void virt_machine_init(MachineState *machine) RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); } else { /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ - riscv_aclint_swi_create(memmap[VIRT_CLINT].base + - i * memmap[VIRT_CLINT].size, + riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base + + i * s->memmap[VIRT_CLINT].size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + - i * memmap[VIRT_CLINT].size + + riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); - riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + - i * memmap[VIRT_ACLINT_SSWI].size, + riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base + + i * s->memmap[VIRT_ACLINT_SSWI].size, base_hartid, hart_count, true); } } else if (tcg_enabled()) { /* Per-socket SiFive CLINT */ riscv_aclint_swi_create( - memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT]= .size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + - i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZ= E, + riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_co= unt, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MT= IME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); @@ -1620,11 +1621,11 @@ static void virt_machine_init(MachineState *machine) =20 /* Per-socket interrupt controller */ if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - s->irqchip[i] =3D virt_create_plic(memmap, i, + s->irqchip[i] =3D virt_create_plic(s->memmap, i, base_hartid, hart_count); } else { s->irqchip[i] =3D virt_create_aia(s->aia_type, s->aia_guests, - memmap, i, base_hartid, + s->memmap, i, base_hartid, hart_count); } =20 @@ -1646,8 +1647,8 @@ static void virt_machine_init(MachineState *machine) if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MS= IS, - memmap[VIRT_APLIC_S].base, - memmap[VIRT_IMSIC_S].base, + s->memmap[VIRT_APLIC_S].base, + s->memmap[VIRT_IMSIC_S].base, s->aia_guests); } =20 @@ -1663,21 +1664,20 @@ static void virt_machine_init(MachineState *machine) virt_high_pcie_memmap.size =3D VIRT32_HIGH_PCIE_MMIO_SIZE; } else { virt_high_pcie_memmap.size =3D VIRT64_HIGH_PCIE_MMIO_SIZE; - virt_high_pcie_memmap.base =3D memmap[VIRT_DRAM].base + machine->r= am_size; + virt_high_pcie_memmap.base =3D s->memmap[VIRT_DRAM].base + + machine->ram_size; virt_high_pcie_memmap.base =3D ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.siz= e); } =20 - s->memmap =3D virt_memmap; - /* register system main memory (actual RAM) */ - memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, - machine->ram); + memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, + machine->ram); =20 /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", - memmap[VIRT_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, + s->memmap[VIRT_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, s->memmap[VIRT_MROM].base, mask_rom); =20 /* @@ -1688,12 +1688,12 @@ static void virt_machine_init(MachineState *machine) rom_set_fw(s->fw_cfg); =20 /* SiFive Test MMIO device */ - sifive_test_create(memmap[VIRT_TEST].base); + sifive_test_create(s->memmap[VIRT_TEST].base); =20 /* VirtIO MMIO devices */ for (i =3D 0; i < VIRTIO_COUNT; i++) { sysbus_create_simple("virtio-mmio", - memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, + s->memmap[VIRT_VIRTIO].base + i * s->memmap[VIRT_VIRTIO].size, qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); } =20 @@ -1701,11 +1701,11 @@ static void virt_machine_init(MachineState *machine) =20 create_platform_bus(s, mmio_irqchip); =20 - serial_mm_init(system_memory, memmap[VIRT_UART0].base, + serial_mm_init(system_memory, s->memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 - sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, + sysbus_create_simple("goldfish_rtc", s->memmap[VIRT_RTC].base, qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); 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Wed, 23 Apr 2025 04:06:46 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 2/9] hw/riscv/virt.c: remove trivial virt_memmap references Date: Wed, 23 Apr 2025 08:06:23 -0300 Message-ID: <20250423110630.2249904-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406552992019100 Content-Type: text/plain; charset="utf-8" We should use s->memmap instead of virt_memmap to be able to use an updated memmap when we start versioning the board. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6e3e34879f..fdf0318e15 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -166,8 +166,8 @@ static void virt_flash_map1(PFlashCFI01 *flash, static void virt_flash_map(RISCVVirtState *s, MemoryRegion *sysmem) { - hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; - hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; + hwaddr flashsize =3D s->memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D s->memmap[VIRT_FLASH].base; =20 virt_flash_map1(s->flash[0], flashbase, flashsize, sysmem); @@ -999,8 +999,8 @@ static void create_fdt_rtc(RISCVVirtState *s, const Mem= MapEntry *memmap, static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) { MachineState *ms =3D MACHINE(s); - hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; - hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; + hwaddr flashsize =3D s->memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D s->memmap[VIRT_FLASH].base; g_autofree char *name =3D g_strdup_printf("/flash@%" PRIx64, flashbase= ); =20 qemu_fdt_add_subnode(ms->fdt, name); @@ -1035,7 +1035,7 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s= , uint16_t bdf) g_autofree char *pci_node =3D NULL; =20 pci_node =3D g_strdup_printf("/soc/pci@%lx", - (long) virt_memmap[VIRT_PCIE_ECAM].base); + (long) s->memmap[VIRT_PCIE_ECAM].base); iommu_node =3D g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, PCI_SLOT(bdf), PCI_FUNC(bdf)); iommu_phandle =3D qemu_fdt_alloc_phandle(fdt); @@ -1104,7 +1104,7 @@ static void create_fdt_iommu(RISCVVirtState *s, uint1= 6_t bdf) g_autofree char *pci_node =3D NULL; =20 pci_node =3D g_strdup_printf("/soc/pci@%lx", - (long) virt_memmap[VIRT_PCIE_ECAM].base); + (long) s->memmap[VIRT_PCIE_ECAM].base); iommu_node =3D g_strdup_printf("%s/iommu@%x", pci_node, bdf); iommu_phandle =3D qemu_fdt_alloc_phandle(fdt); qemu_fdt_add_subnode(fdt, iommu_node); @@ -1126,24 +1126,24 @@ static void finalize_fdt(RISCVVirtState *s) uint32_t irq_pcie_phandle =3D 1, irq_virtio_phandle =3D 1; uint32_t iommu_sys_phandle =3D 1; =20 - create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, + create_fdt_sockets(s, s->memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, &msi_pcie_phandle); =20 - create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); + create_fdt_virtio(s, s->memmap, irq_virtio_phandle); =20 if (virt_is_iommu_sys_enabled(s)) { create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, &iommu_sys_phandle); } - create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle, + create_fdt_pcie(s, s->memmap, irq_pcie_phandle, msi_pcie_phandle, iommu_sys_phandle); =20 - create_fdt_reset(s, virt_memmap, &phandle); + create_fdt_reset(s, s->memmap, &phandle); =20 - create_fdt_uart(s, virt_memmap, irq_mmio_phandle); + create_fdt_uart(s, s->memmap, irq_mmio_phandle); =20 - create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); + create_fdt_rtc(s, s->memmap, irq_mmio_phandle); } =20 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) @@ -1366,14 +1366,13 @@ static void create_platform_bus(RISCVVirtState *s, = DeviceState *irqchip) { DeviceState *dev; SysBusDevice *sysbus; - const MemMapEntry *memmap =3D virt_memmap; int i; MemoryRegion *sysmem =3D get_system_memory(); =20 dev =3D qdev_new(TYPE_PLATFORM_BUS_DEVICE); dev->id =3D g_strdup(TYPE_PLATFORM_BUS_DEVICE); qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); - qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); + qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].si= ze); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); s->platform_bus_dev =3D dev; =20 @@ -1384,7 +1383,7 @@ static void create_platform_bus(RISCVVirtState *s, De= viceState *irqchip) } =20 memory_region_add_subregion(sysmem, - memmap[VIRT_PLATFORM_BUS].base, + s->memmap[VIRT_PLATFORM_BUS].base, sysbus_mmio_get_region(sysbus, 0)); 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Wed, 23 Apr 2025 04:06:48 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 3/9] hw/riscv/virt.c: use s->memmap in virt_machine_done() Date: Wed, 23 Apr 2025 08:06:24 -0300 Message-ID: <20250423110630.2249904-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406496804019100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index fdf0318e15..473416bcf3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1430,9 +1430,8 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) { RISCVVirtState *s =3D container_of(notifier, RISCVVirtState, machine_done); - const MemMapEntry *memmap =3D virt_memmap; MachineState *machine =3D MACHINE(s); - hwaddr start_addr =3D memmap[VIRT_DRAM].base; + hwaddr start_addr =3D s->memmap[VIRT_DRAM].base; target_ulong firmware_end_addr, kernel_start_addr; const char *firmware_name =3D riscv_default_firmware_name(&s->soc[0]); uint64_t fdt_load_addr; @@ -1476,14 +1475,14 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) * let's overwrite the address we jump to after reset to * the base of the flash. */ - start_addr =3D virt_memmap[VIRT_FLASH].base; + start_addr =3D s->memmap[VIRT_FLASH].base; } else { /* * Pflash was supplied but either KVM guest or bios is not non= e. * In this case, base of the flash would contain S-mode payloa= d. */ riscv_setup_firmware_boot(machine); - kernel_entry =3D virt_memmap[VIRT_FLASH].base; + kernel_entry =3D s->memmap[VIRT_FLASH].base; } } =20 @@ -1497,15 +1496,15 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) kernel_entry =3D boot_info.image_low_addr; } =20 - fdt_load_addr =3D riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, - memmap[VIRT_DRAM].size, + fdt_load_addr =3D riscv_compute_fdt_addr(s->memmap[VIRT_DRAM].base, + s->memmap[VIRT_DRAM].size, machine, &boot_info); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, - virt_memmap[VIRT_MROM].base, - virt_memmap[VIRT_MROM].size, kernel_entry, + s->memmap[VIRT_MROM].base, + s->memmap[VIRT_MROM].size, kernel_entry, fdt_load_addr); =20 /* --=20 2.49.0 From nobody Sat Nov 15 23:41:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 23 Apr 2025 04:06:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 4/9] hw/riscv/virt.c: add 'base' arg in create_fw_cfg() Date: Wed, 23 Apr 2025 08:06:25 -0300 Message-ID: <20250423110630.2249904-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406485189019100 Content-Type: text/plain; charset="utf-8" The function can receive the value via s->memmap[VIRT_FW_CFG].base from the caller, avoiding the use of virt_memmap. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 473416bcf3..77ebb517f2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1262,9 +1262,8 @@ static inline DeviceState *gpex_pcie_init(MemoryRegio= n *sys_mem, return dev; } =20 -static FWCfgState *create_fw_cfg(const MachineState *ms) +static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) { - hwaddr base =3D virt_memmap[VIRT_FW_CFG].base; FWCfgState *fw_cfg; =20 fw_cfg =3D fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, @@ -1682,7 +1681,7 @@ static void virt_machine_init(MachineState *machine) * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the * device tree cannot be altered and we get FDT_ERR_NOSPACE. */ - s->fw_cfg =3D create_fw_cfg(machine); + s->fw_cfg =3D create_fw_cfg(machine, s->memmap[VIRT_FW_CFG].base); rom_set_fw(s->fw_cfg); =20 /* SiFive Test MMIO device */ --=20 2.49.0 From nobody Sat Nov 15 23:41:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745406581; cv=none; d=zohomail.com; s=zohoarc; b=WTTMVxJJtmZ+au3ACVBeNxcH0S3xFZuFq4CY29RTttVkdccsnG13hRJiRtg5OU3SaEXPtiECWl2eJsv9oCv9JyyRMUf3iRXHjk1Bh++G8125CkSe63ilbEALd0mpS5qVtZO6+CjKzs3RFHHY7oPttcR/dgcLu6iks/kYjTFHgeM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745406581; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 23 Apr 2025 04:06:54 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 5/9] hw/riscv/virt.c: use s->memmap in create_fdt() path Date: Wed, 23 Apr 2025 08:06:26 -0300 Message-ID: <20250423110630.2249904-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406583448019000 Content-Type: text/plain; charset="utf-8" create_fdt(), create_fdt_flash() and create_fdt_fw_cfg() can access the memmap via their RISCVVirtState pointers. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 77ebb517f2..02f3659d38 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -996,7 +996,7 @@ static void create_fdt_rtc(RISCVVirtState *s, const Mem= MapEntry *memmap, } } =20 -static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) +static void create_fdt_flash(RISCVVirtState *s) { MachineState *ms =3D MACHINE(s); hwaddr flashsize =3D s->memmap[VIRT_FLASH].size / 2; @@ -1011,11 +1011,11 @@ static void create_fdt_flash(RISCVVirtState *s, con= st MemMapEntry *memmap) qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); } =20 -static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) +static void create_fdt_fw_cfg(RISCVVirtState *s) { MachineState *ms =3D MACHINE(s); - hwaddr base =3D memmap[VIRT_FW_CFG].base; - hwaddr size =3D memmap[VIRT_FW_CFG].size; + hwaddr base =3D s->memmap[VIRT_FW_CFG].base; + hwaddr size =3D s->memmap[VIRT_FW_CFG].size; g_autofree char *nodename =3D g_strdup_printf("/fw-cfg@%" PRIx64, base= ); =20 qemu_fdt_add_subnode(ms->fdt, nodename); @@ -1146,7 +1146,7 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_rtc(s, s->memmap, irq_mmio_phandle); } =20 -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) +static void create_fdt(RISCVVirtState *s) { MachineState *ms =3D MACHINE(s); uint8_t rng_seed[32]; @@ -1173,7 +1173,8 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap) * The "/soc/pci@..." node is needed for PCIE hotplugs * that might happen before finalize_fdt(). */ - name =3D g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM]= .base); + name =3D g_strdup_printf("/soc/pci@%lx", + (long) s->memmap[VIRT_PCIE_ECAM].base); qemu_fdt_add_subnode(ms->fdt, name); =20 qemu_fdt_add_subnode(ms->fdt, "/chosen"); @@ -1185,8 +1186,8 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap) =20 qemu_fdt_add_subnode(ms->fdt, "/aliases"); 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Wed, 23 Apr 2025 04:06:57 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 6/9] hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path Date: Wed, 23 Apr 2025 08:06:27 -0300 Message-ID: <20250423110630.2249904-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_FILL_THIS_FORM_SHORT=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406537167019100 Content-Type: text/plain; charset="utf-8" create_fdt_sockets() and all its fdt helpers (create_fdt_socket_aplic(), create_fdt_imsic(), create_fdt_socket_plic(), create_fdt_socket_aclint() and create_fdt_socket_memory()) can use s->memmap from their RISCVVirtState pointer instead of having an extra memmap argument. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 89 ++++++++++++++++++++++++++----------------------- 1 file changed, 47 insertions(+), 42 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 02f3659d38..dcaf28d1a4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -301,14 +301,13 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,= int socket, } } =20 -static void create_fdt_socket_memory(RISCVVirtState *s, - const MemMapEntry *memmap, int socket) +static void create_fdt_socket_memory(RISCVVirtState *s, int socket) { g_autofree char *mem_name =3D NULL; uint64_t addr, size; MachineState *ms =3D MACHINE(s); =20 - addr =3D memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); + addr =3D s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socke= t); size =3D riscv_socket_mem_size(ms, socket); mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); qemu_fdt_add_subnode(ms->fdt, mem_name); @@ -319,7 +318,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, } =20 static void create_fdt_socket_clint(RISCVVirtState *s, - const MemMapEntry *memmap, int socket, + int socket, uint32_t *intc_phandles) { int cpu; @@ -340,21 +339,22 @@ static void create_fdt_socket_clint(RISCVVirtState *s, clint_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_M_TIMER); } =20 - clint_addr =3D memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * so= cket); + clint_addr =3D s->memmap[VIRT_CLINT].base + + (s->memmap[VIRT_CLINT].size * socket); clint_name =3D g_strdup_printf("/soc/clint@%lx", clint_addr); qemu_fdt_add_subnode(ms->fdt, clint_name); qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", (char **)&clint_compat, ARRAY_SIZE(clint_compat)); qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", - 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); + 0x0, clint_addr, 0x0, s->memmap[VIRT_CLINT].size); qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); riscv_socket_fdt_write_id(ms, clint_name, socket); } =20 static void create_fdt_socket_aclint(RISCVVirtState *s, - const MemMapEntry *memmap, int socket, + int socket, uint32_t *intc_phandles) { int cpu; @@ -381,8 +381,10 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, aclint_cells_size =3D s->soc[socket].num_harts * sizeof(uint32_t) * 2; =20 if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - addr =3D memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * sock= et); + addr =3D s->memmap[VIRT_CLINT].base + + (s->memmap[VIRT_CLINT].size * socket); name =3D g_strdup_printf("/soc/mswi@%lx", addr); + qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mswi"); @@ -397,13 +399,13 @@ static void create_fdt_socket_aclint(RISCVVirtState *= s, } =20 if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - addr =3D memmap[VIRT_CLINT].base + + addr =3D s->memmap[VIRT_CLINT].base + (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); size =3D RISCV_ACLINT_DEFAULT_MTIMER_SIZE; } else { - addr =3D memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + - (memmap[VIRT_CLINT].size * socket); - size =3D memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; + addr =3D s->memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + + (s->memmap[VIRT_CLINT].size * socket); + size =3D s->memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; } name =3D g_strdup_printf("/soc/mtimer@%lx", addr); qemu_fdt_add_subnode(ms->fdt, name); @@ -420,14 +422,15 @@ static void create_fdt_socket_aclint(RISCVVirtState *= s, g_free(name); =20 if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - addr =3D memmap[VIRT_ACLINT_SSWI].base + - (memmap[VIRT_ACLINT_SSWI].size * socket); + addr =3D s->memmap[VIRT_ACLINT_SSWI].base + + (s->memmap[VIRT_ACLINT_SSWI].size * socket); + name =3D g_strdup_printf("/soc/sswi@%lx", addr); qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-sswi"); qemu_fdt_setprop_cells(ms->fdt, name, "reg", - 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); + 0x0, addr, 0x0, s->memmap[VIRT_ACLINT_SSWI].size); qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_sswi_cells, aclint_cells_size); qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); @@ -438,7 +441,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, } =20 static void create_fdt_socket_plic(RISCVVirtState *s, - const MemMapEntry *memmap, int socket, + int socket, uint32_t *phandle, uint32_t *intc_phand= les, uint32_t *plic_phandles) { @@ -452,7 +455,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s, }; =20 plic_phandles[socket] =3D (*phandle)++; - plic_addr =3D memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socke= t); + plic_addr =3D s->memmap[VIRT_PLIC].base + + (s->memmap[VIRT_PLIC].size * socket); plic_name =3D g_strdup_printf("/soc/plic@%lx", plic_addr); qemu_fdt_add_subnode(ms->fdt, plic_name); qemu_fdt_setprop_cell(ms->fdt, plic_name, @@ -491,7 +495,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, } =20 qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", - 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); + 0x0, plic_addr, 0x0, s->memmap[VIRT_PLIC].size); qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); riscv_socket_fdt_write_id(ms, plic_name, socket); @@ -500,8 +504,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s, =20 if (!socket) { platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, - memmap[VIRT_PLATFORM_BUS].base, - memmap[VIRT_PLATFORM_BUS].size, + s->memmap[VIRT_PLATFORM_BUS].base, + s->memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); } } @@ -588,7 +592,7 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwa= ddr base_addr, qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); } =20 -static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, +static void create_fdt_imsic(RISCVVirtState *s, uint32_t *phandle, uint32_t *intc_phandles, uint32_t *msi_m_phandle, uint32_t *msi_s_phan= dle) { @@ -597,12 +601,12 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, =20 if (!kvm_enabled()) { /* M-level IMSIC node */ - create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, + create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_M].base, intc_phandle= s, *msi_m_phandle, true, 0); } =20 /* S-level IMSIC node */ - create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, + create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_S].base, intc_phandles, *msi_s_phandle, false, imsic_num_bits(s->aia_guests + 1)); =20 @@ -679,7 +683,7 @@ static void create_fdt_one_aplic(RISCVVirtState *s, int= socket, } =20 static void create_fdt_socket_aplic(RISCVVirtState *s, - const MemMapEntry *memmap, int socket, + int socket, uint32_t msi_m_phandle, uint32_t msi_s_phandle, uint32_t *phandle, @@ -696,18 +700,19 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, =20 if (!kvm_enabled()) { /* M-level APLIC node */ - aplic_addr =3D memmap[VIRT_APLIC_M].base + - (memmap[VIRT_APLIC_M].size * socket); - create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].s= ize, + aplic_addr =3D s->memmap[VIRT_APLIC_M].base + + (s->memmap[VIRT_APLIC_M].size * socket); + create_fdt_one_aplic(s, socket, aplic_addr, + s->memmap[VIRT_APLIC_M].size, msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, true, num_harts); } =20 /* S-level APLIC node */ - aplic_addr =3D memmap[VIRT_APLIC_S].base + - (memmap[VIRT_APLIC_S].size * socket); - create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, + aplic_addr =3D s->memmap[VIRT_APLIC_S].base + + (s->memmap[VIRT_APLIC_S].size * socket); + create_fdt_one_aplic(s, socket, aplic_addr, s->memmap[VIRT_APLIC_S].si= ze, msi_s_phandle, intc_phandles, aplic_s_phandle, 0, false, num_harts); @@ -715,8 +720,8 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, if (!socket) { g_autofree char *aplic_name =3D fdt_get_aplic_nodename(aplic_addr); platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, - memmap[VIRT_PLATFORM_BUS].base, - memmap[VIRT_PLATFORM_BUS].size, + s->memmap[VIRT_PLATFORM_BUS].base, + s->memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); } =20 @@ -734,7 +739,7 @@ static void create_fdt_pmu(RISCVVirtState *s) riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); } =20 -static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memma= p, +static void create_fdt_sockets(RISCVVirtState *s, uint32_t *phandle, uint32_t *irq_mmio_phandle, uint32_t *irq_pcie_phandle, @@ -770,20 +775,20 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, create_fdt_socket_cpus(s, socket, clust_name, phandle, &intc_phandles[phandle_pos]); =20 - create_fdt_socket_memory(s, memmap, socket); + create_fdt_socket_memory(s, socket); =20 if (virt_aclint_allowed() && s->have_aclint) { - create_fdt_socket_aclint(s, memmap, socket, + create_fdt_socket_aclint(s, socket, &intc_phandles[phandle_pos]); } else if (tcg_enabled()) { - create_fdt_socket_clint(s, memmap, socket, + create_fdt_socket_clint(s, socket, &intc_phandles[phandle_pos]); } } =20 if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { - create_fdt_imsic(s, memmap, phandle, intc_phandles, - &msi_m_phandle, &msi_s_phandle); + create_fdt_imsic(s, phandle, intc_phandles, + &msi_m_phandle, &msi_s_phandle); *msi_pcie_phandle =3D msi_s_phandle; } =20 @@ -792,7 +797,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, * mode, we'll use only one APLIC instance. */ if (!virt_use_emulated_aplic(s->aia_type)) { - create_fdt_socket_aplic(s, memmap, 0, + create_fdt_socket_aplic(s, 0, msi_m_phandle, msi_s_phandle, phandle, &intc_phandles[0], xplic_phandles, ms->smp.cpus); @@ -806,11 +811,11 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, phandle_pos -=3D s->soc[socket].num_harts; =20 if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - create_fdt_socket_plic(s, memmap, socket, phandle, + create_fdt_socket_plic(s, socket, phandle, &intc_phandles[phandle_pos], xplic_phandles); } else { - create_fdt_socket_aplic(s, memmap, socket, + create_fdt_socket_aplic(s, socket, msi_m_phandle, msi_s_phandle, phan= dle, &intc_phandles[phandle_pos], xplic_phandles, @@ -1126,7 +1131,7 @@ static void finalize_fdt(RISCVVirtState *s) uint32_t irq_pcie_phandle =3D 1, irq_virtio_phandle =3D 1; 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Wed, 23 Apr 2025 04:07:00 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 7/9] hw/riscv/virt.c: use s->memmap in create_fdt_virtio() Date: Wed, 23 Apr 2025 08:06:28 -0300 Message-ID: <20250423110630.2249904-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406593007019100 Content-Type: text/plain; charset="utf-8" create_fdt_virtio() can use s->memmap instead of having an extra argument for it. While we're at it rewrite it a little bit to avoid the clunky line in 'name' and code repetition: - declare 'virtio_base' out of the loop since it never changes; - declare a 'size' variable. Use it to calculate the address of the virtio device in an 'addr' variable; - use 'addr' in the 'name' g_strdup_printf(); - use 'addr' and 'size' when creating the 'reg' property. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index dcaf28d1a4..07ee8e144f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -842,21 +842,24 @@ static void create_fdt_sockets(RISCVVirtState *s, riscv_socket_fdt_write_distance_matrix(ms); } =20 -static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, - uint32_t irq_virtio_phandle) +static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phand= le) { int i; MachineState *ms =3D MACHINE(s); + hwaddr virtio_base =3D s->memmap[VIRT_VIRTIO].base; =20 for (i =3D 0; i < VIRTIO_COUNT; i++) { - g_autofree char *name =3D g_strdup_printf("/soc/virtio_mmio@%lx", - (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size= )); + g_autofree char *name =3D NULL; + uint64_t size =3D s->memmap[VIRT_VIRTIO].size; + hwaddr addr =3D virtio_base + i * size; + + name =3D g_strdup_printf("/soc/virtio_mmio@%"HWADDR_PRIx, addr); =20 qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"= ); qemu_fdt_setprop_cells(ms->fdt, name, "reg", - 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, - 0x0, memmap[VIRT_VIRTIO].size); + 0x0, addr, + 0x0, size); qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_virtio_phandle); if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { @@ -1135,7 +1138,7 @@ static void finalize_fdt(RISCVVirtState *s) &irq_pcie_phandle, &irq_virtio_phandle, &msi_pcie_phandle); =20 - create_fdt_virtio(s, s->memmap, irq_virtio_phandle); + create_fdt_virtio(s, irq_virtio_phandle); =20 if (virt_is_iommu_sys_enabled(s)) { create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, --=20 2.49.0 From nobody Sat Nov 15 23:41:49 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 23 Apr 2025 04:07:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 8/9] hw/riscv/virt.c: use s->memmap in finalize_fdt() functions Date: Wed, 23 Apr 2025 08:06:29 -0300 Message-ID: <20250423110630.2249904-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406536908019100 Content-Type: text/plain; charset="utf-8" Change create_fdt_pcie(), create_fdt_reset(), create_fdt_uart() and create_fdt_rtc() to use s->memmap in their logic. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 07ee8e144f..036a0a9bfb 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -872,7 +872,7 @@ static void create_fdt_virtio(RISCVVirtState *s, uint32= _t irq_virtio_phandle) } } =20 -static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, +static void create_fdt_pcie(RISCVVirtState *s, uint32_t irq_pcie_phandle, uint32_t msi_pcie_phandle, uint32_t iommu_sys_phandle) @@ -881,7 +881,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const Me= mMapEntry *memmap, MachineState *ms =3D MACHINE(s); =20 name =3D g_strdup_printf("/soc/pci@%lx", - (long) memmap[VIRT_PCIE_ECAM].base); + (long) s->memmap[VIRT_PCIE_ECAM].base); qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", @@ -892,19 +892,19 @@ static void create_fdt_pcie(RISCVVirtState *s, const = MemMapEntry *memmap, qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, - memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); + s->memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandl= e); } qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, - memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); + s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size); qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, - 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, + 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, - 2, memmap[VIRT_PCIE_MMIO].base, - 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, + 2, s->memmap[VIRT_PCIE_MMIO].base, + 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].si= ze, 1, FDT_PCI_RANGE_MMIO_64BIT, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); @@ -918,8 +918,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const Me= mMapEntry *memmap, create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); } =20 -static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, - uint32_t *phandle) +static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle) { char *name; uint32_t test_phandle; @@ -927,7 +926,7 @@ static void create_fdt_reset(RISCVVirtState *s, const M= emMapEntry *memmap, =20 test_phandle =3D (*phandle)++; name =3D g_strdup_printf("/soc/test@%lx", - (long)memmap[VIRT_TEST].base); + (long)s->memmap[VIRT_TEST].base); qemu_fdt_add_subnode(ms->fdt, name); { static const char * const compat[3] =3D { @@ -937,7 +936,7 @@ static void create_fdt_reset(RISCVVirtState *s, const M= emMapEntry *memmap, (char **)&compat, ARRAY_SIZE(compat)= ); } qemu_fdt_setprop_cells(ms->fdt, name, "reg", - 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); + 0x0, s->memmap[VIRT_TEST].base, 0x0, s->memmap[VIRT_TEST].size); qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); test_phandle =3D qemu_fdt_get_phandle(ms->fdt, name); g_free(name); @@ -959,18 +958,19 @@ static void create_fdt_reset(RISCVVirtState *s, const= MemMapEntry *memmap, g_free(name); } =20 -static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, +static void create_fdt_uart(RISCVVirtState *s, uint32_t irq_mmio_phandle) { g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); =20 - name =3D g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].b= ase); + name =3D g_strdup_printf("/soc/serial@%lx", + (long)s->memmap[VIRT_UART0].base); qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); qemu_fdt_setprop_cells(ms->fdt, name, "reg", - 0x0, memmap[VIRT_UART0].base, - 0x0, memmap[VIRT_UART0].size); + 0x0, s->memmap[VIRT_UART0].base, + 0x0, s->memmap[VIRT_UART0].size); qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phan= dle); if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { @@ -983,18 +983,18 @@ static void create_fdt_uart(RISCVVirtState *s, const = MemMapEntry *memmap, qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); } =20 -static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, +static void create_fdt_rtc(RISCVVirtState *s, uint32_t irq_mmio_phandle) { g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); =20 - name =3D g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); + name =3D g_strdup_printf("/soc/rtc@%lx", (long)s->memmap[VIRT_RTC].bas= e); qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "google,goldfish-rtc"); qemu_fdt_setprop_cells(ms->fdt, name, "reg", - 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); + 0x0, s->memmap[VIRT_RTC].base, 0x0, s->memmap[VIRT_RTC].size); qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { @@ -1144,14 +1144,14 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, &iommu_sys_phandle); } - create_fdt_pcie(s, s->memmap, irq_pcie_phandle, msi_pcie_phandle, + create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, iommu_sys_phandle); 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Wed, 23 Apr 2025 04:07:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 9/9] hw/riscv/virt.c: remove 'long' casts in fmt strings Date: Wed, 23 Apr 2025 08:06:30 -0300 Message-ID: <20250423110630.2249904-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250423110630.2249904-1-dbarboza@ventanamicro.com> References: <20250423110630.2249904-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1745406585469019000 Content-Type: text/plain; charset="utf-8" We can avoid the 'long' casts by using PRIx64 and HWADDR_PRIx on the fmt strings for uint64_t and hwaddr types. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/virt.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 036a0a9bfb..075c035f25 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -309,7 +309,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s,= int socket) =20 addr =3D s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socke= t); size =3D riscv_socket_mem_size(ms, socket); - mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); + mem_name =3D g_strdup_printf("/memory@%"PRIx64, addr); qemu_fdt_add_subnode(ms->fdt, mem_name); qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); @@ -880,8 +880,8 @@ static void create_fdt_pcie(RISCVVirtState *s, g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); =20 - name =3D g_strdup_printf("/soc/pci@%lx", - (long) s->memmap[VIRT_PCIE_ECAM].base); + name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, + s->memmap[VIRT_PCIE_ECAM].base); qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", @@ -925,8 +925,8 @@ static void create_fdt_reset(RISCVVirtState *s, uint32_= t *phandle) MachineState *ms =3D MACHINE(s); =20 test_phandle =3D (*phandle)++; - name =3D g_strdup_printf("/soc/test@%lx", - (long)s->memmap[VIRT_TEST].base); + name =3D g_strdup_printf("/soc/test@%"HWADDR_PRIx, + s->memmap[VIRT_TEST].base); qemu_fdt_add_subnode(ms->fdt, name); { static const char * const compat[3] =3D { @@ -964,8 +964,8 @@ static void create_fdt_uart(RISCVVirtState *s, g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); =20 - name =3D g_strdup_printf("/soc/serial@%lx", - (long)s->memmap[VIRT_UART0].base); + name =3D g_strdup_printf("/soc/serial@%"HWADDR_PRIx, + s->memmap[VIRT_UART0].base); qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); qemu_fdt_setprop_cells(ms->fdt, name, "reg", @@ -989,7 +989,8 @@ static void create_fdt_rtc(RISCVVirtState *s, g_autofree char *name =3D NULL; MachineState *ms =3D MACHINE(s); =20 - name =3D g_strdup_printf("/soc/rtc@%lx", (long)s->memmap[VIRT_RTC].bas= e); + name =3D g_strdup_printf("/soc/rtc@%"HWADDR_PRIx, + s->memmap[VIRT_RTC].base); qemu_fdt_add_subnode(ms->fdt, name); qemu_fdt_setprop_string(ms->fdt, name, "compatible", "google,goldfish-rtc"); @@ -1042,8 +1043,8 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s= , uint16_t bdf) g_autofree char *iommu_node =3D NULL; g_autofree char *pci_node =3D NULL; =20 - pci_node =3D g_strdup_printf("/soc/pci@%lx", - (long) s->memmap[VIRT_PCIE_ECAM].base); + pci_node =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, + s->memmap[VIRT_PCIE_ECAM].base); iommu_node =3D g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, PCI_SLOT(bdf), PCI_FUNC(bdf)); iommu_phandle =3D qemu_fdt_alloc_phandle(fdt); @@ -1111,8 +1112,8 @@ static void create_fdt_iommu(RISCVVirtState *s, uint1= 6_t bdf) g_autofree char *iommu_node =3D NULL; g_autofree char *pci_node =3D NULL; =20 - pci_node =3D g_strdup_printf("/soc/pci@%lx", - (long) s->memmap[VIRT_PCIE_ECAM].base); + pci_node =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, + s->memmap[VIRT_PCIE_ECAM].base); iommu_node =3D g_strdup_printf("%s/iommu@%x", pci_node, bdf); iommu_phandle =3D qemu_fdt_alloc_phandle(fdt); qemu_fdt_add_subnode(fdt, iommu_node); @@ -1181,8 +1182,8 @@ static void create_fdt(RISCVVirtState *s) * The "/soc/pci@..." node is needed for PCIE hotplugs * that might happen before finalize_fdt(). */ - name =3D g_strdup_printf("/soc/pci@%lx", - (long) s->memmap[VIRT_PCIE_ECAM].base); + name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIx, + s->memmap[VIRT_PCIE_ECAM].base); qemu_fdt_add_subnode(ms->fdt, name); =20 qemu_fdt_add_subnode(ms->fdt, "/chosen"); --=20 2.49.0