From nobody Sun Nov 16 00:58:33 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1745377103; cv=none; d=zohomail.com; s=zohoarc; b=YyTknQQxIF7Drmo/qTv5x95n37bNHgEpuEXZjoAs+vVu16yp0HXy92qy7iP0o2TSNJINdua9udSonS/NpZaEUvM3C7TxK/cyam4CyyFJ6luHxOXs267uS+RGk1mF1A5bEdQsgIkO4AYafiGyw+WngIS1u0sthjPDmvKIUTxESU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745377103; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=bUjj155XiSLYxlUcyB10Xn0j4Ei6lEwpy/78j8RI4OU=; b=OLwA1FVtuZelG+Zm3dEhbKGFrk+YP8NRYkWvn6SsR4wIVZdv6ZdylKgJ9m/mAgAeJi0oZNdlGi9oQ1XO50VAHQy13bLMYA/U1CqkqUPuZYOwJQNzilAMpan8S4EbdA0Lc/+L9uNQjsNXhOnXhRlXN0x+qXzhz4tDu2zLlh9/fdg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745377103889633.2885381603681; Tue, 22 Apr 2025 19:58:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7QIb-0007HC-QR; Tue, 22 Apr 2025 22:57:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7QIV-0007Dd-CT; Tue, 22 Apr 2025 22:57:15 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7QIT-00043I-9V; Tue, 22 Apr 2025 22:57:15 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 23 Apr 2025 10:56:52 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Wed, 23 Apr 2025 10:56:52 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v3 3/3] hw/arm: Integrate Aspeed OTP memory into AST10x0 and AST2600 SoCs Date: Wed, 23 Apr 2025 10:56:51 +0800 Message-ID: <20250423025651.189702-4-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423025651.189702-1-kane_chen@aspeedtech.com> References: <20250423025651.189702-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1745377108300019100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS This patch wires up the OTP memory device (`aspeed.otpmem`) into the AST1030 and AST2600 SoC models. The device is initialized, attached to a backing block drive (`-drive id=3Dotpmem`) and linked to the SBC controller via a QOM link. The default OTP memory image can be generated using the following command. ```bash for i in $(seq 1 2048); do printf '\x00\x00\x00\x00\xff\xff\xff\xff' done > otpmem.img ``` To load the OTP memory image into the guest, use: ```bash ./qemu-system-arm \ -drive id=3Dotpmem,file=3Dotpmem.img,if=3Dnone,format=3Draw \ ... ``` Note: Do not use the -snapshot option, or OTP data writes will not persist to the image file. Signed-off-by: Kane-Chen-AS --- hw/arm/aspeed_ast10x0.c | 19 +++++++++++++++++++ hw/arm/aspeed_ast2600.c | 19 +++++++++++++++++++ include/hw/arm/aspeed_soc.h | 2 ++ 3 files changed, 40 insertions(+) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index ec329f4991..eaa70feb9f 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -15,6 +15,7 @@ #include "system/system.h" #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" +#include "system/block-backend-global-state.h" #include "hw/arm/aspeed_soc.h" =20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 @@ -156,6 +157,8 @@ static void aspeed_soc_ast1030_init(Object *obj) =20 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); =20 + object_initialize_child(obj, "otpmem", &s->otpmem, TYPE_ASPEED_OTPMEM); + for (i =3D 0; i < sc->wdts_num; i++) { snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); @@ -194,6 +197,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) Error *err =3D NULL; int i; g_autofree char *sram_name =3D NULL; + BlockBackend *blk; =20 if (!clock_has_source(s->sysclk)) { error_setg(errp, "sysclk clock must be wired up by the board code"= ); @@ -359,6 +363,21 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_bas= e); } =20 + /* OTP memory */ + blk =3D blk_by_name(ASPEED_OTPMEM_DRIVE); + if (blk) { + blk_set_perm(blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, + 0, &error_fatal); + qdev_prop_set_drive(DEVICE(&s->otpmem), "drive", blk); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->otpmem), errp)) { + return; + } + /* Assign OTP memory to SBC */ + object_property_set_link(OBJECT(&s->sbc), "otpmem", + OBJECT(&s->otpmem), &error_abort); + } + /* Secure Boot Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { return; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 1f994ba26c..9fe3eeeb0e 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/misc/unimp.h" +#include "system/block-backend-global-state.h" #include "hw/arm/aspeed_soc.h" #include "qemu/module.h" #include "qemu/error-report.h" @@ -263,6 +264,8 @@ static void aspeed_soc_ast2600_init(Object *obj) =20 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); =20 + object_initialize_child(obj, "otpmem", &s->otpmem, TYPE_ASPEED_OTPMEM); + object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DE= VICE); object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DE= VICE); object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DE= VICE); @@ -293,6 +296,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); qemu_irq irq; g_autofree char *sram_name =3D NULL; + BlockBackend *blk; =20 /* Default boot region (SPI memory or ROMs) */ memory_region_init(&s->spi_boot_container, OBJECT(s), @@ -628,6 +632,21 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); } =20 + /* OTP memory */ + blk =3D blk_by_name(ASPEED_OTPMEM_DRIVE); + if (blk) { + blk_set_perm(blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, + 0, &error_fatal); + qdev_prop_set_drive(DEVICE(&s->otpmem), "drive", blk); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->otpmem), errp)) { + return; + } + /* Assign OTP memory to SBC */ + object_property_set_link(OBJECT(&s->sbc), "otpmem", + OBJECT(&s->otpmem), &error_abort); + } + /* Secure Boot Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { return; diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index f069d17d16..2d15c6047a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -36,6 +36,7 @@ #include "hw/usb/hcd-ehci.h" #include "qom/object.h" #include "hw/misc/aspeed_lpc.h" +#include "hw/misc/aspeed_otpmem.h" #include "hw/misc/unimp.h" #include "hw/misc/aspeed_peci.h" #include "hw/fsi/aspeed_apb2opb.h" @@ -73,6 +74,7 @@ struct AspeedSoCState { AspeedSMCState spi[ASPEED_SPIS_NUM]; EHCISysBusState ehci[ASPEED_EHCIS_NUM]; AspeedSBCState sbc; + AspeedOTPMemState otpmem; AspeedSLIState sli; AspeedSLIState sliio; MemoryRegion secsram; --=20 2.43.0