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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745356286; x=1745961086; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BEoa5+P2s+dvjQMF6oUGcAe5STudghf85RD71OkQiHw=; b=Xv9+55YKv+AuK92hJXPNdVqnAd0rZdHvsIzoKjl+wFX9FHssTIZyyeank8gH+RchYB ehwkHbt9QVF2ciS8P/e5N5nM1JoGiOeKRYTt9v5JjSDDDe5B+Dr2s7CuQkuBhntnfi2R ULNDwMx/PklfuHL2JcJ9TDMBDGFeUbwn7oU8fyPPu55duKIDNOA98mSplWrD1NR9Gwp8 6dpOscMEW8lr/b5okWBx3KVltEQ2jarcI94reDE1Nunw7e9q2JypAeIYjMXcgPT4knGA hQ/aZY+//YssRiiIrWjiNn3DPOwTOAYe/gNxJDYOe67j3/TxPUn2obrMNkVxrBN9167l ypvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745356286; x=1745961086; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BEoa5+P2s+dvjQMF6oUGcAe5STudghf85RD71OkQiHw=; b=ixw+JJD4SgsmRAHj+PyAowQd4Zg5+lvstWVw5n3BgCiBNLULcQs1GKEtyx+254XFUJ OasDEQdENafRjwfTPq1e5DqQnm23kR3Nkrk4rjewKzNFZAm4gQtQqko246jiOWbkJm/U 3BDo2Mpmsfs0YDMR2tYMCeKwaFQnzxfIO3Mo1YDOOWB9ofXqrAyqfm7wiredsyOy56Cp soRHDBaKNl3zw+tu6QNYfiaZ0Byc5cmVI3XBpany+Kw0LqgJVtRMvEd++j3ZfS+7ytrp Yf2QyujQR6683ciEEEaGM6gppCgIieg7jJwKurDh6J84iBayIwpoQEjMZBBHEETunedB HBcQ== X-Gm-Message-State: AOJu0Yy5wvpTUHPbPP46WkrKJC6A9H6MIXoq9XWzYVEhWq0M117Hb+HC i+VZVOQAYe7c6wx9d4o1vfFn1jOFyjkKY84NhNJ3IUX8VxhJXMu8uK/1HiU9gKtccNSGotuvSgx u X-Gm-Gg: ASbGncua8onEBToQHPLXarC8E0WEQqNYv3g0RuzuEjHtZ8m9hkaO1j0XMwmwWTqR2UK x2tGu9UGIM8TullWNIMtHscp9We/r6XNTzvglx8izpgG0+FGANmivixYBGdHBvG3qXamUckcYwx w+PPJAYveqLghB9sB7y1e4ZcTnZP0qMqUX6BB2d/w7r8dtsI+TGKdBp2jgOg6FTdghcN0+eSorT JrsiIEdfiYxyUmwkfeV120CTHIgG1aNKHZRmZDRAYmMZiZ/P5THaY6xZNMN/kKMi0lloH7/dh5u fZ/Ijgixy4LVDSocla+muwlJsQA3CJdwxodZ8Rvuj4lXMoK7MdD0Quf0Ajab+CyCPActlmMAfC8 = X-Google-Smtp-Source: AGHT+IH85Xbb6fHERhvGrN7qw1qb234RqITajeWO4p5kIJQXuT523MIGes66o7BG7UfwabqrYNQgRQ== X-Received: by 2002:a05:6a00:884:b0:730:97a6:f04 with SMTP id d2e1a72fcca58-73dc1494019mr24972876b3a.7.1745356286115; Tue, 22 Apr 2025 14:11:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Pierrick Bouvier Subject: [PULL 1/9] target/avr: Improve decode of LDS, STS Date: Tue, 22 Apr 2025 14:11:16 -0700 Message-ID: <20250422211124.305724-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745356365933019000 Content-Type: text/plain; charset="utf-8" The comment about not being able to define a field with zero bits is out of date since 94597b6146f3 ("decodetree: Allow !function with no input bits"). This fixes the missing load of imm in the disassembler. Cc: qemu-stable@nongnu.org Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling via option '= -d in_asm'") Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/translate.c | 2 -- target/avr/insn.decode | 7 ++----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 4ab71d8138..e7f8ced9b3 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1578,7 +1578,6 @@ static bool trans_LDS(DisasContext *ctx, arg_LDS *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D tcg_temp_new_i32(); TCGv H =3D cpu_rampD; - a->imm =3D next_word(ctx); =20 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */ tcg_gen_shli_tl(addr, addr, 16); @@ -1783,7 +1782,6 @@ static bool trans_STS(DisasContext *ctx, arg_STS *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D tcg_temp_new_i32(); TCGv H =3D cpu_rampD; - a->imm =3D next_word(ctx); =20 tcg_gen_mov_tl(addr, H); /* addr =3D H:M:L */ tcg_gen_shli_tl(addr, addr, 16); diff --git a/target/avr/insn.decode b/target/avr/insn.decode index 482c23ad0c..cc302249db 100644 --- a/target/avr/insn.decode +++ b/target/avr/insn.decode @@ -118,11 +118,8 @@ BRBC 1111 01 ....... ... @op_bit_imm @io_rd_imm .... . .. ..... .... &rd_imm rd=3D%rd imm=3D%io= _imm @ldst_d .. . . .. . rd:5 . ... &rd_imm imm=3D%ldst_d_imm =20 -# The 16-bit immediate is completely in the next word. -# Fields cannot be defined with no bits, so we cannot play -# the same trick and append to a zero-bit value. -# Defer reading the immediate until trans_{LDS,STS}. -@ldst_s .... ... rd:5 .... imm=3D0 +%ldst_imm !function=3Dnext_word +@ldst_s .... ... rd:5 .... imm=3D%ldst_imm =20 MOV 0010 11 . ..... .... @op_rd_rr MOVW 0000 0001 .... .... &rd_rr rd=3D%rd_d rr=3D%r= r_d --=20 2.43.0 From nobody Sat Nov 15 23:38:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745356311; cv=none; d=zohomail.com; s=zohoarc; b=Csvo7HMT6TMGOifHp3LRadwlqTAGMVSXjeo5z+W4fEpNC55LAqe/xaNUVuDeIrSyJdaR4x/3Y3AcLtSxMik4WMECQm11jpTzwhjTA3iSJiTelqpup9oKoa6713RwN4sx0hC07JY1G5ABfEyi+0ACXzvJP3741L1/rNOIKwW10Ew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745356311; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=whE4tOIG14eY8JQ2gptqlrplDWnqt4RDL3Ybv6G0d7s=; b=SAAQI8VB/287beDYjD16Es3aFB+WAlM9+EqJwLwUQ7onkf+m4MvAUDSffxtUC4GWPXk8u4MnhcH3vE9rk79+YBSpNPJi+Glnh6J+CEj/Y9DQ+Rk1qxegYBfR6DYzvlVydPpYWqG+vGSiHAvwjNr7BBDyEvLMXUKUqS/loGBA8ts= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745356311280876.84767922766; Tue, 22 Apr 2025 14:11:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7Ku9-00017m-93; Tue, 22 Apr 2025 17:11:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7Ktu-0000zL-5I for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:33 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7Kts-0000PP-Cg for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:29 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-73c17c770a7so7281633b3a.2 for ; Tue, 22 Apr 2025 14:11:27 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu.h | 2 -- target/avr/helper.c | 3 +-- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 06f5ae4d1b..84a8f5cc8c 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -60,8 +60,6 @@ #define OFFSET_CODE 0x00000000 /* CPU registers, IO registers, and SRAM */ #define OFFSET_DATA 0x00800000 -/* CPU registers specifically, these are mapped at the start of data */ -#define OFFSET_CPU_REGISTERS OFFSET_DATA /* * IO registers, including status register, stack pointer, and memory * mapped peripherals, mapped just after CPU registers diff --git a/target/avr/helper.c b/target/avr/helper.c index 3412312ad5..e5bf16c6b7 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -340,8 +340,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uin= t32_t addr) env->fullacc =3D false; =20 /* Following logic assumes this: */ - assert(OFFSET_CPU_REGISTERS =3D=3D OFFSET_DATA); - assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_CPU_REGISTERS + + assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_DATA + NUMBER_OF_CPU_REGISTERS); =20 if (addr < NUMBER_OF_CPU_REGISTERS) { --=20 2.43.0 From nobody Sat Nov 15 23:38:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745356329; cv=none; d=zohomail.com; s=zohoarc; b=bsG1v7zD7UQe6wmKsw8uQxcNt6sdtOvCihm1mUrl5zz05HK1+lCsba24VEDVA+E6Jl9ahhJ0JVqGALSJCpPXFLe2hioZH0Bh28K+4s8mf1/SHDZYo75+JDJfAkoAFi2COkMxXmkBwKrF693v9KQ69XcaoCka97OCR72naSQz7uU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745356329; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=X7HP2zbvSkDBMLOLYhU6UsrfPqpzWt02XJu5z93nvtA=; b=OxBIBV77FmZRcQchwoy6w3qQmxqrfsVApUWDA3kEVR0mqfrsdnhU+BxCLH8wsOvelSg5Wh/VJ5oaiS+F4wASuB9o4d3yzr6U2gc9OGTCbjrNEr/VFlqZ+baxWEAcQ7v/XTeqQMmbfbIPQ70Ge40myGpRnK26nLC0mr9CER/PH8A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745356328991950.6042615410931; Tue, 22 Apr 2025 14:12:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7KuB-0001Fp-OC; Tue, 22 Apr 2025 17:11:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7Ktv-0000zq-OH for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:33 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7Ktt-0000Pa-Ai for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:31 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-73972a54919so5826919b3a.3 for ; Tue, 22 Apr 2025 14:11:28 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 14:11:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 3/9] target/avr: Add defines for i/o port registers Date: Tue, 22 Apr 2025 14:11:18 -0700 Message-ID: <20250422211124.305724-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745356329742019000 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu.h | 10 ++++++++++ target/avr/helper.c | 36 ++++++++++++++++++------------------ 2 files changed, 28 insertions(+), 18 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 84a8f5cc8c..1a5a5b8e3e 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -47,6 +47,16 @@ /* Number of IO registers accessible by ld/st/in/out */ #define NUMBER_OF_IO_REGISTERS 64 =20 +/* CPU registers mapped into i/o ports 0x38-0x3f. */ +#define REG_38_RAMPD 0 +#define REG_38_RAMPX 1 +#define REG_38_RAMPY 2 +#define REG_38_RAMPZ 3 +#define REG_38_EIDN 4 +#define REG_38_SPL 5 +#define REG_38_SPH 6 +#define REG_38_SREG 7 + /* * Offsets of AVR memory regions in host memory space. * diff --git a/target/avr/helper.c b/target/avr/helper.c index e5bf16c6b7..f8ada8b106 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -216,29 +216,29 @@ target_ulong helper_inb(CPUAVRState *env, uint32_t po= rt) { target_ulong data =3D 0; =20 - switch (port) { - case 0x38: /* RAMPD */ + switch (port - 0x38) { + case REG_38_RAMPD: data =3D 0xff & (env->rampD >> 16); break; - case 0x39: /* RAMPX */ + case REG_38_RAMPX: data =3D 0xff & (env->rampX >> 16); break; - case 0x3a: /* RAMPY */ + case REG_38_RAMPY: data =3D 0xff & (env->rampY >> 16); break; - case 0x3b: /* RAMPZ */ + case REG_38_RAMPZ: data =3D 0xff & (env->rampZ >> 16); break; - case 0x3c: /* EIND */ + case REG_38_EIDN: data =3D 0xff & (env->eind >> 16); break; - case 0x3d: /* SPL */ + case REG_38_SPL: data =3D env->sp & 0x00ff; break; - case 0x3e: /* SPH */ + case REG_38_SPH: data =3D env->sp >> 8; break; - case 0x3f: /* SREG */ + case REG_38_SREG: data =3D cpu_get_sreg(env); break; default: @@ -265,39 +265,39 @@ void helper_outb(CPUAVRState *env, uint32_t port, uin= t32_t data) { data &=3D 0x000000ff; =20 - switch (port) { - case 0x38: /* RAMPD */ + switch (port - 0x38) { + case REG_38_RAMPD: if (avr_feature(env, AVR_FEATURE_RAMPD)) { env->rampD =3D (data & 0xff) << 16; } break; - case 0x39: /* RAMPX */ + case REG_38_RAMPX: if (avr_feature(env, AVR_FEATURE_RAMPX)) { env->rampX =3D (data & 0xff) << 16; } break; - case 0x3a: /* RAMPY */ + case REG_38_RAMPY: if (avr_feature(env, AVR_FEATURE_RAMPY)) { env->rampY =3D (data & 0xff) << 16; } break; - case 0x3b: /* RAMPZ */ + case REG_38_RAMPZ: if (avr_feature(env, AVR_FEATURE_RAMPZ)) { env->rampZ =3D (data & 0xff) << 16; } break; - case 0x3c: /* EIDN */ + case REG_38_EIDN: env->eind =3D (data & 0xff) << 16; break; - case 0x3d: /* SPL */ + case REG_38_SPL: env->sp =3D (env->sp & 0xff00) | (data); break; - case 0x3e: /* SPH */ + case REG_38_SPH: if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { env->sp =3D (env->sp & 0x00ff) | (data << 8); } break; - case 0x3f: /* SREG */ + case REG_38_SREG: cpu_set_sreg(env, data); break; default: --=20 2.43.0 From nobody Sat Nov 15 23:38:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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We no longer need to trap accesses to the first page within avr_cpu_tlb_fill but can wait until a write occurs. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu.h | 7 ++ target/avr/helper.h | 3 - target/avr/cpu.c | 16 +++ target/avr/helper.c | 223 +++++++++++++++++------------------------ target/avr/translate.c | 42 ++++---- 5 files changed, 138 insertions(+), 153 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 1a5a5b8e3e..6f68060ab0 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memory.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" @@ -152,6 +153,9 @@ struct ArchCPU { =20 CPUAVRState env; =20 + MemoryRegion cpu_reg1; + MemoryRegion cpu_reg2; + /* Initial value of stack pointer */ uint32_t init_sp; }; @@ -252,6 +256,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 +extern const MemoryRegionOps avr_cpu_reg1; +extern const MemoryRegionOps avr_cpu_reg2; + #include "exec/cpu-all.h" =20 #endif /* QEMU_AVR_CPU_H */ diff --git a/target/avr/helper.h b/target/avr/helper.h index 4d02e648fa..e8d13e925f 100644 --- a/target/avr/helper.h +++ b/target/avr/helper.h @@ -23,7 +23,4 @@ DEF_HELPER_1(debug, noreturn, env) DEF_HELPER_1(break, noreturn, env) DEF_HELPER_1(sleep, noreturn, env) DEF_HELPER_1(unsupported, noreturn, env) -DEF_HELPER_3(outb, void, env, i32, i32) -DEF_HELPER_2(inb, tl, env, i32) DEF_HELPER_3(fullwr, void, env, i32, i32) -DEF_HELPER_2(fullrd, tl, env, i32) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 834c7082aa..0b14b36c17 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/exec-all.h" #include "exec/translation-block.h" +#include "exec/address-spaces.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -110,6 +111,8 @@ static void avr_cpu_disas_set_info(CPUState *cpu, disas= semble_info *info) static void avr_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + CPUAVRState *env =3D cpu_env(cs); + AVRCPU *cpu =3D env_archcpu(env); AVRCPUClass *mcc =3D AVR_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 @@ -122,6 +125,19 @@ static void avr_cpu_realizefn(DeviceState *dev, Error = **errp) cpu_reset(cs); =20 mcc->parent_realize(dev, errp); + + /* + * Two blocks in the low data space loop back into cpu registers. + */ + memory_region_init_io(&cpu->cpu_reg1, OBJECT(cpu), &avr_cpu_reg1, env, + "avr-cpu-reg1", 32); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA, &cpu->cpu_reg1); + + memory_region_init_io(&cpu->cpu_reg2, OBJECT(cpu), &avr_cpu_reg2, env, + "avr-cpu-reg2", 8); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + 0x58, &cpu->cpu_reg2); } =20 static void avr_cpu_set_int(void *opaque, int irq, int level) diff --git a/target/avr/helper.c b/target/avr/helper.c index f8ada8b106..d0e86f5614 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -108,7 +108,7 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - int prot, page_size =3D TARGET_PAGE_SIZE; + int prot; uint32_t paddr; =20 address &=3D TARGET_PAGE_MASK; @@ -133,23 +133,9 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, /* Access to memory. */ paddr =3D OFFSET_DATA + address; prot =3D PAGE_READ | PAGE_WRITE; - if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* - * Access to CPU registers, exit and rebuilt this TB to use - * full access in case it touches specially handled registers - * like SREG or SP. For probing, set page_size =3D 1, in order - * to force tlb_fill to be called for the next access. - */ - if (probe) { - page_size =3D 1; - } else { - cpu_env(cs)->fullacc =3D 1; - cpu_loop_exit_restore(cs, retaddr); - } - } } =20 - tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); + tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); return true; } =20 @@ -203,134 +189,78 @@ void helper_wdr(CPUAVRState *env) } =20 /* - * This function implements IN instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is read and returned - * b. otherwise io address is translated to mem address and physical memo= ry - * is read. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation - * + * The first 32 bytes of the data space are mapped to the cpu regs. + * We cannot write these from normal store operations because TCG + * does not expect global temps to be modified -- a global may be + * live in a host cpu register across the store. We can however + * read these, as TCG does make sure the global temps are saved + * in case the load operation traps. */ -target_ulong helper_inb(CPUAVRState *env, uint32_t port) + +static uint64_t avr_cpu_reg1_read(void *opaque, hwaddr addr, unsigned size) { - target_ulong data =3D 0; + CPUAVRState *env =3D opaque; =20 - switch (port - 0x38) { - case REG_38_RAMPD: - data =3D 0xff & (env->rampD >> 16); - break; - case REG_38_RAMPX: - data =3D 0xff & (env->rampX >> 16); - break; - case REG_38_RAMPY: - data =3D 0xff & (env->rampY >> 16); - break; - case REG_38_RAMPZ: - data =3D 0xff & (env->rampZ >> 16); - break; - case REG_38_EIDN: - data =3D 0xff & (env->eind >> 16); - break; - case REG_38_SPL: - data =3D env->sp & 0x00ff; - break; - case REG_38_SPH: - data =3D env->sp >> 8; - break; - case REG_38_SREG: - data =3D cpu_get_sreg(env); - break; - default: - /* not a special register, pass to normal memory access */ - data =3D address_space_ldub(&address_space_memory, - OFFSET_IO_REGISTERS + port, - MEMTXATTRS_UNSPECIFIED, NULL); - } - - return data; + assert(addr < 32); + return env->r[addr]; } =20 /* - * This function implements OUT instruction - * - * It does the following - * a. if an IO register belongs to CPU, its value is written into the re= gister - * b. otherwise io address is translated to mem address and physical mem= ory - * is written. - * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementati= on - * + * The range 0x38-0x3f of the i/o space is mapped to cpu regs. + * As above, we cannot write these from normal store operations. */ -void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data) -{ - data &=3D 0x000000ff; =20 - switch (port - 0x38) { +static uint64_t avr_cpu_reg2_read(void *opaque, hwaddr addr, unsigned size) +{ + CPUAVRState *env =3D opaque; + + switch (addr) { case REG_38_RAMPD: - if (avr_feature(env, AVR_FEATURE_RAMPD)) { - env->rampD =3D (data & 0xff) << 16; - } - break; + return 0xff & (env->rampD >> 16); case REG_38_RAMPX: - if (avr_feature(env, AVR_FEATURE_RAMPX)) { - env->rampX =3D (data & 0xff) << 16; - } - break; + return 0xff & (env->rampX >> 16); case REG_38_RAMPY: - if (avr_feature(env, AVR_FEATURE_RAMPY)) { - env->rampY =3D (data & 0xff) << 16; - } - break; + return 0xff & (env->rampY >> 16); case REG_38_RAMPZ: - if (avr_feature(env, AVR_FEATURE_RAMPZ)) { - env->rampZ =3D (data & 0xff) << 16; - } - break; + return 0xff & (env->rampZ >> 16); case REG_38_EIDN: - env->eind =3D (data & 0xff) << 16; - break; + return 0xff & (env->eind >> 16); case REG_38_SPL: - env->sp =3D (env->sp & 0xff00) | (data); - break; + return env->sp & 0x00ff; case REG_38_SPH: - if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { - env->sp =3D (env->sp & 0x00ff) | (data << 8); - } - break; + return 0xff & (env->sp >> 8); case REG_38_SREG: - cpu_set_sreg(env, data); - break; - default: - /* not a special register, pass to normal memory access */ - address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + por= t, - data, MEMTXATTRS_UNSPECIFIED, NULL); + return cpu_get_sreg(env); } + g_assert_not_reached(); } =20 -/* - * this function implements LD instruction when there is a possibility to= read - * from a CPU register - */ -target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) +static void avr_cpu_trap_write(void *opaque, hwaddr addr, + uint64_t data64, unsigned size) { - uint8_t data; + CPUAVRState *env =3D opaque; + CPUState *cs =3D env_cpu(env); =20 - env->fullacc =3D false; - - if (addr < NUMBER_OF_CPU_REGISTERS) { - /* CPU registers */ - data =3D env->r[addr]; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - data =3D helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS); - } else { - /* memory */ - data =3D address_space_ldub(&address_space_memory, OFFSET_DATA + a= ddr, - MEMTXATTRS_UNSPECIFIED, NULL); - } - return data; + env->fullacc =3D true; + cpu_loop_exit_restore(cs, cs->mem_io_pc); } =20 +const MemoryRegionOps avr_cpu_reg1 =3D { + .read =3D avr_cpu_reg1_read, + .write =3D avr_cpu_trap_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + +const MemoryRegionOps avr_cpu_reg2 =3D { + .read =3D avr_cpu_reg2_read, + .write =3D avr_cpu_trap_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 1, +}; + /* * this function implements ST instruction when there is a possibility to= write * into a CPU register @@ -339,19 +269,50 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, u= int32_t addr) { env->fullacc =3D false; =20 - /* Following logic assumes this: */ - assert(OFFSET_IO_REGISTERS =3D=3D OFFSET_DATA + - NUMBER_OF_CPU_REGISTERS); - - if (addr < NUMBER_OF_CPU_REGISTERS) { + switch (addr) { + case 0 ... 31: /* CPU registers */ env->r[addr] =3D data; - } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { - /* IO registers */ - helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data); - } else { - /* memory */ + break; + + case REG_38_RAMPD + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPD)) { + env->rampD =3D data << 16; + } + break; + case REG_38_RAMPX + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPX)) { + env->rampX =3D data << 16; + } + break; + case REG_38_RAMPY + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPY)) { + env->rampY =3D data << 16; + } + break; + case REG_38_RAMPZ + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_RAMPZ)) { + env->rampZ =3D data << 16; + } + break; + case REG_38_EIDN + 0x38 + NUMBER_OF_CPU_REGISTERS: + env->eind =3D data << 16; + break; + case REG_38_SPL + 0x38 + NUMBER_OF_CPU_REGISTERS: + env->sp =3D (env->sp & 0xff00) | data; + break; + case REG_38_SPH + 0x38 + NUMBER_OF_CPU_REGISTERS: + if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) { + env->sp =3D (env->sp & 0x00ff) | (data << 8); + } + break; + case REG_38_SREG + 0x38 + NUMBER_OF_CPU_REGISTERS: + cpu_set_sreg(env, data); + break; + + default: address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, MEMTXATTRS_UNSPECIFIED, NULL); + break; } } diff --git a/target/avr/translate.c b/target/avr/translate.c index e7f8ced9b3..0490936cd5 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -194,6 +194,9 @@ static bool avr_have_feature(DisasContext *ctx, int fea= ture) static bool decode_insn(DisasContext *ctx, uint16_t insn); #include "decode-insn.c.inc" =20 +static void gen_inb(DisasContext *ctx, TCGv data, int port); +static void gen_outb(DisasContext *ctx, TCGv data, int port); + /* * Arithmetic Instructions */ @@ -1293,9 +1296,8 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_EQ; ctx->skip_var0 =3D data; @@ -1311,9 +1313,8 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_NE; ctx->skip_var0 =3D data; @@ -1502,11 +1503,18 @@ static void gen_data_store(DisasContext *ctx, TCGv = data, TCGv addr) =20 static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { - if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { - gen_helper_fullrd(data, tcg_env, addr); - } else { - tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); - } + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); +} + +static void gen_inb(DisasContext *ctx, TCGv data, int port) +{ + gen_data_load(ctx, data, tcg_constant_i32(port + NUMBER_OF_CPU_REGISTE= RS)); +} + +static void gen_outb(DisasContext *ctx, TCGv data, int port) +{ + gen_helper_fullwr(tcg_env, data, + tcg_constant_i32(port + NUMBER_OF_CPU_REGISTERS)); } =20 /* @@ -2126,9 +2134,8 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a) static bool trans_IN(DisasContext *ctx, arg_IN *a) { TCGv Rd =3D cpu_r[a->rd]; - TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_inb(Rd, tcg_env, port); + gen_inb(ctx, Rd, a->imm); return true; } =20 @@ -2139,9 +2146,8 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) static bool trans_OUT(DisasContext *ctx, arg_OUT *a) { TCGv Rd =3D cpu_r[a->rd]; - TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_outb(tcg_env, port, Rd); + gen_outb(ctx, Rd, a->imm); return true; } =20 @@ -2407,11 +2413,10 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP = *a) static bool trans_SBI(DisasContext *ctx, arg_SBI *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_ori_tl(data, data, 1 << a->bit); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } =20 @@ -2422,11 +2427,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) static bool trans_CBI(DisasContext *ctx, arg_CBI *a) { TCGv data =3D tcg_temp_new_i32(); - TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, tcg_env, port); + gen_inb(ctx, data, a->reg); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); - gen_helper_outb(tcg_env, port, data); + gen_outb(ctx, data, a->reg); return true; } =20 --=20 2.43.0 From nobody Sat Nov 15 23:38:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745356317; cv=none; d=zohomail.com; s=zohoarc; b=B9nl8AxA+Cw9kQEGscOyIFHqMcfu78TzpPYRt/Yme2/YPoq0Nb/F5c+ki8ngxBHUOa13jP7yd7pj9aw+pumif8e1h6YuIre0HY41WQ25SDh7WrULsTCNxC4xGmQeBqcL0m8+ezODWQr4ysq4W5tZhe1Ubgm+/U9MfI9yTDBjXlU= ARC-Message-Signature: i=1; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 6f68060ab0..9862705c6a 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -45,8 +45,6 @@ =20 /* Number of CPU registers */ #define NUMBER_OF_CPU_REGISTERS 32 -/* Number of IO registers accessible by ld/st/in/out */ -#define NUMBER_OF_IO_REGISTERS 64 =20 /* CPU registers mapped into i/o ports 0x38-0x3f. */ #define REG_38_RAMPD 0 --=20 2.43.0 From nobody Sat Nov 15 23:38:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745356395; cv=none; d=zohomail.com; s=zohoarc; b=Wedh+sdKSt9Fe6uoubm/6SsaqudzZM7CGBnyAnsPijZK44UXD6Y2yLLS7xYUaLQKNNBDBZjj0d5NWMuFIYWDvH0tP1Rc8h21Ri2urchZIbUty7XiXh/0r30Vek/4R5ZDhss2SfpR587LbbUjxoz2EQ1WamEdJULo3MKsB4q3hOU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745356395; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=p5VV71JY8goeor4xQCwdYnut93y9ysd8cImiGLe4Oic=; b=nxAluXOg0BKsvI1i0o3aP2IJnqaHfd7OWo11x9CTTZdORPmEjXgqJNY4tliU/5+EVCqnbZmeT+nScCU5K/gH7Y4CmHgInh1piTUw5hHC/bKlvOaDZBEUd1LvwFCWI1aXKztdc011XlNUkN9ea/c9/wJACg2Fcc1dWLumkcGnxok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745356395862760.0593752977684; Tue, 22 Apr 2025 14:13:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7KuD-0001IM-8y; Tue, 22 Apr 2025 17:11:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7Ktx-000104-Ds for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:35 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7Ktu-0000Px-U3 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:33 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-7376e311086so7939001b3a.3 for ; Tue, 22 Apr 2025 14:11:30 -0700 (PDT) Received: from stoup.. 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Make use of the softmmu cache of the i/o page. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/helper.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index d0e86f5614..7d6954ec26 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,10 +23,10 @@ #include "qemu/error-report.h" #include "cpu.h" #include "accel/tcg/cpu-ops.h" +#include "accel/tcg/getpc.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" -#include "exec/address-spaces.h" #include "exec/helper-proto.h" =20 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -67,6 +67,11 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_= request) return false; } =20 +static void do_stb(CPUAVRState *env, uint32_t addr, uint8_t data, uintptr_= t ra) +{ + cpu_stb_mmuidx_ra(env, addr, data, MMU_DATA_IDX, ra); +} + void avr_cpu_do_interrupt(CPUState *cs) { CPUAVRState *env =3D cpu_env(cs); @@ -311,8 +316,7 @@ void helper_fullwr(CPUAVRState *env, uint32_t data, uin= t32_t addr) break; =20 default: - address_space_stb(&address_space_memory, OFFSET_DATA + addr, data, - MEMTXATTRS_UNSPECIFIED, NULL); + do_stb(env, addr, data, GETPC()); break; } } --=20 2.43.0 From nobody Sat Nov 15 23:38:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745356359; cv=none; d=zohomail.com; s=zohoarc; b=P7HSq5Rtqe/PBeFAMtJc9BhnAfC1ox8gC5ngf30GanJPFhd8Ou497jhGowvsrKQK6u3BQssf2NYldjRKr/UDiWTJ5TXr+CEBHZVSJg/Ruo60ujq98jbYP0pdsloVzv50jMVaAUKeCEvwXMnyaxp8Zm/rO43qeTxhnopOgoiGMo4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745356359; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DUF+4Y4/PqO50T2IhlnvWA6B/DIxYokH9Y5du5vjVAo=; b=Nwmo6RdppJl4kc5iWZfh6+ORRBeSGqeIyHr5OY6/+ha3JFnrrsv+SMV3+3LdJ0wfwGjW5qSXFaORAN/vYBpgU+FGhbQoh+5yxz6OLim7vwl2oe86BKUDjr85pDpcS5pxMyi/jb9/N0a/0wdONe7YlFeh8EMbxrD2QJHSsu2aE8k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745356359016981.8948903868932; Tue, 22 Apr 2025 14:12:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7KuF-0001NT-AK; Tue, 22 Apr 2025 17:11:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7Ku5-00013D-4L for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:41 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7Ktx-0000QC-4C for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:34 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-2260c91576aso49569305ad.3 for ; Tue, 22 Apr 2025 14:11:31 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 14:11:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 7/9] target/avr: Use do_stb in avr_cpu_do_interrupt Date: Tue, 22 Apr 2025 14:11:22 -0700 Message-ID: <20250422211124.305724-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745356360073019000 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index 7d6954ec26..f23fa3e8ba 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -88,14 +88,14 @@ void avr_cpu_do_interrupt(CPUState *cs) } =20 if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); - cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); + do_stb(env, env->sp--, ret >> 16, 0); } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); - cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8); + do_stb(env, env->sp--, ret, 0); + do_stb(env, env->sp--, ret >> 8, 0); } else { - cpu_stb_data(env, env->sp--, (ret & 0x0000ff)); + do_stb(env, env->sp--, ret, 0); } =20 env->pc_w =3D base + vector * size; --=20 2.43.0 From nobody Sat Nov 15 23:38:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745356387; cv=none; d=zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745356291; x=1745961091; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HNdVjawedf7L7sOM+y7tXhWt3e7lZuKafuAKLevf0NY=; b=tVbcbr8iGqYvQ9OpZmtHTg62Kk4RvN42uKsbdo7FAtyLPMCqboNbYLGqlh2aaI5QgY CLJPNSVgFzGgoj0mPNdEf7F8FI/UYK8Wu0m+5zVMGkZKmRHfA/OtObd3j9RzoW8uUtTi CeBstWq4utYH/f6eUrnXrDJmB8luBcpvdh1WUZ5+tey6j9CucjTkXz2NzFLvsI1of+kM WSCyhwI7JZxGR+53YXv3NO0mmisM0Y+TWE6MJcGSAOLaek0Bk0w+gBImmM6APqhK6gw2 HBH1YW7GmhD5p+2x4nUqd7CfT0pRYVNZ6PVrQjK+Xu8W0gnTQXjyNVMRLV7ppmYUm51G uViw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745356291; x=1745961091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HNdVjawedf7L7sOM+y7tXhWt3e7lZuKafuAKLevf0NY=; b=rk8okG7zfHwRMuxWDyfHKE0ZnG/w2FHypQsqAM8/CuC93+0EKiCrXEXRpxO2UqR3L5 4VOb0aPz231dMDVtVuensWu+sqdM572adnPO9TgYZSNRajjuZvqKXq+NZK9u9lffjoya bVyXVCKj6ehlNY+CXBhGVQLDXfWNFf9hudyI2xW5ZyEVfrBXCayEw663S9HEHpbuaoaa 0gt3qHDmHsOrmFmLBhn76LqDaFdv+kB4IYY0gLYc8jTTPjy98TihUnAYhfRYHbYH9SJO DDbQe/cYfmiPq83/Q/ooYzeI5uQPs2OFG53gW6QuQjSJUddzLLdhY5ryXjHLN50/6O/A Satw== X-Gm-Message-State: AOJu0YwjFf42BpWcKAbIIplbdlkY3k0PYeJSkiRWhPGFWEx8junxxW0S WkLycOdSN+pCe4ArbWuhzvUwIm5+imSZ8IgzD8k73jwY8WcfuZ/d+np+6i4Co4wYhius4zMNKTG U X-Gm-Gg: ASbGnctZ+ETYMQflwVlQSyYbt3uH/Vmm6l5RI0fg2x1TOloqSYOuTHRQvgw7pz+COeO kvBRDk6cqikqj/sdyOWMOD7HfTOJ0PV2WVAL0SpMICOp+tjlGHXq7c1Kb5yYSMqQstq4g6FLwas 4zciesOXCIRC6jdKeyZQ8FPFWWPRUpXobuAoqPPVZSczYeqr+1cadS7uVZGt8H8KtDPzac9eg/j ayi98uEbTcMMTSfJL6lUmkg2gTwyL3Pk3Aa07ymb6CPNmn/8aNLfNMbvNGDBGjjqESBAEFBZp8L VOeQwWYm2848TkYGq17soo/lue4SHTCjvbYEHbPjj/FY/Pj0WQKakbZyPC98JILdnwJvUAMb6NQ = X-Google-Smtp-Source: AGHT+IHcumkpvNE/XWu6bm9XfY/7pnpL9WUWOw/5Dos5eoRJioLqTtY4r5a2zSB3KHkKo4llHU4RoA== X-Received: by 2002:a17:903:1cf:b0:223:669f:ca2d with SMTP id d9443c01a7336-22c53611146mr274231935ad.35.1745356290776; Tue, 22 Apr 2025 14:11:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 8/9] hw/avr: Prepare for TARGET_PAGE_SIZE > 256 Date: Tue, 22 Apr 2025 14:11:23 -0700 Message-ID: <20250422211124.305724-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745356388005019000 Content-Type: text/plain; charset="utf-8" If i/o does not cover the entire first page, allocate a portion of ram as an i/o device, so that the entire first page is i/o. While memory_region_init_ram_device_ptr is happy to allocate the RAMBlock, it does not register the ram for migration. Do this by hand. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- hw/avr/atmega.h | 1 + hw/avr/atmega.c | 39 ++++++++++++++++++++++++++++++++------- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h index a99ee15c7e..9ac4678231 100644 --- a/hw/avr/atmega.h +++ b/hw/avr/atmega.h @@ -41,6 +41,7 @@ struct AtmegaMcuState { MemoryRegion flash; MemoryRegion eeprom; MemoryRegion sram; + MemoryRegion sram_io; DeviceState *io; AVRMaskState pwr[POWER_MAX]; AVRUsartState usart[USART_MAX]; diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index f6844bf118..11fab184de 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -19,6 +19,7 @@ #include "hw/sysbus.h" #include "qom/object.h" #include "hw/misc/unimp.h" +#include "migration/vmstate.h" #include "atmega.h" =20 enum AtmegaPeripheral { @@ -224,8 +225,6 @@ static void atmega_realize(DeviceState *dev, Error **er= rp) char *devname; size_t i; =20 - assert(mc->io_size <=3D 0x200); - if (!s->xtal_freq_hz) { error_setg(errp, "\"xtal-frequency-hz\" property must be provided.= "); return; @@ -240,11 +239,37 @@ static void atmega_realize(DeviceState *dev, Error **= errp) qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev =3D DEVICE(&s->cpu); =20 - /* SRAM */ - memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size, - &error_abort); - memory_region_add_subregion(get_system_memory(), - OFFSET_DATA + mc->io_size, &s->sram); + /* + * SRAM + * + * Softmmu is not able mix i/o and ram on the same page. + * Therefore in all cases, the first page exclusively contains i/o. + * + * If the MCU's i/o region matches the page size, then we can simply + * allocate all ram starting at the second page. Otherwise, we must + * allocate some ram as i/o to complete the first page. + */ + assert(mc->io_size =3D=3D 0x100 || mc->io_size =3D=3D 0x200); + if (mc->io_size >=3D TARGET_PAGE_SIZE) { + memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_siz= e, + &error_abort); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + mc->io_size, &s->sram); + } else { + int sram_io_size =3D TARGET_PAGE_SIZE - mc->io_size; + void *sram_io_mem =3D g_malloc0(sram_io_size); + + memory_region_init_ram_device_ptr(&s->sram_io, OBJECT(dev), "sram-= as-io", + sram_io_size, sram_io_mem); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + mc->io_size, &s->sram_io= ); + vmstate_register_ram(&s->sram_io, dev); + + memory_region_init_ram(&s->sram, OBJECT(dev), "sram", + mc->sram_size - sram_io_size, &error_abort); + memory_region_add_subregion(get_system_memory(), + OFFSET_DATA + TARGET_PAGE_SIZE, &s->sr= am); + } =20 /* Flash */ memory_region_init_rom(&s->flash, OBJECT(dev), --=20 2.43.0 From nobody Sat Nov 15 23:38:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745356313; cv=none; d=zohomail.com; s=zohoarc; b=dzkwp95XH5Uex1rmZ7KkKlb53Q1ZIzKYgBmCY4MPAKmHRG1RGPlrLke32QTNO/Z8xIuOTCpfEaSVAvWEkb8em4rb+b/FFzNLR1kh8+GIkXN6NwflIcDQYJDWyNyttvb5MvNXUsX0o9clcuq5QNbF+w2DMccpXFo8d8eI+KTCgfU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745356313; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=E4x0j7WHmS5PoiJFKXF/CXQYHRcuf16x9CbNw0mWO8Y=; b=MW/4n9CCJwJib6mocIx2ztIFuStsP+junSQclOLClaY7a3LoXhS6rL7XfX+oPtdd6sa8TH/iwizIOVtqvyD5JHZIqBSPbhcm5/3jQ4U7komUqlNKFOip4YdmhXsQupZ3si9W2yX7keLVOszQ/VPkzmsLmv2OdHVAZFWiSt/dOj4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745356313777266.05572748155635; Tue, 22 Apr 2025 14:11:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7Ku9-00019p-PV; Tue, 22 Apr 2025 17:11:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7Ku5-00013C-4j for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:41 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7Ktx-0000Qd-4P for qemu-devel@nongnu.org; Tue, 22 Apr 2025 17:11:35 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-736ab1c43c4so5956035b3a.1 for ; Tue, 22 Apr 2025 14:11:32 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbf8e4932sm9448160b3a.55.2025.04.22.14.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 14:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745356291; x=1745961091; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E4x0j7WHmS5PoiJFKXF/CXQYHRcuf16x9CbNw0mWO8Y=; b=gfBJvrFJ4d3TyZeSofUAzwSD7Mdna1/+Vow4oVuezXtYOxHYAbW74haUsbwjwWv5Kj grAJXq5yK+I3Y66aox9jXGAFOU1H1jG8cSJAS4q0zIjxEFLOxaeUlCdxVLR8yPdN54Et ECAlYdsHIAi6i4PwkJh7/rXQWkDz3VwszSeIDdnG+21pcXyTkw2r66IdtXGKr9pfn+88 qked+9+3wFGWKJDF6Fn4o6+H+rXIcNOcznc3usqA6FdnigpatJ4wBSOXXA6PwSAr2Pnf nSI/0kpwrSYroWUf7mXmOclbD+g4aEVi/TAJ2BjFtWLUSO+c8gZ3UGESruZD74+N3x0P hrjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745356291; x=1745961091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E4x0j7WHmS5PoiJFKXF/CXQYHRcuf16x9CbNw0mWO8Y=; b=SML7KotKShkAIWffEv6zWUdwcFD6XqcdkD3febPZICfk5dF/aZWTrAOWN5bbC5ZKLA CuLiG9BLIh+27FmBa5ii1XQi4LzRoDr4N6FVtT2KUAgS/JnMXSMRG/e/VhCdkOKzeQsr bXCwsRYGA3sp818mG1R1YBKTHitJE5AJolLy33BB6qtTEKwBHE2mRjwbggS8ipDHuEoN px2VwxP/Jh+fSuBUE6VCv7IqNmkjDFhvdZTGtA+NwrY0mWxpL7wqmaJCRWZ6BtlJ3eFQ 6mcjdRBcfGUWoikWXRABNDzlryS52FqXBUvXQf4F7tAetSEICIaQPbqQ1LZn2JaZ7oth C34w== X-Gm-Message-State: AOJu0Yx1RQM7MPcmMXMJIPXpYkm43jsDkPR7hChXD5A/YgO7Z7T4T4n4 2kw03FhEYoniOc1S5uRKrZL6PaDO0NDcE5pyeodrDQeJ7SUPC4Q+KTrqLYLkmQB831tg+ipHIYp p X-Gm-Gg: ASbGncs+7p5FBBkTyAkHF5i1D+RKJhbPmYCCXt0i+fl2x7gknAddJJ1chLZ/wftZqEB 11zxvf0s4Qg3pP0weLil8FXe/DX/euq7e5tddduofRaFf+YSTR8OLGD0JgzuCeVwYFLW6eQhS9J 6NGp16c4MXf1vOE/bBvWu5hQmaBi01RAtSOtqU9CqCz6XhWtrUdX4p6CIxA0MoEfpB1m9t/e9Qx Y9+PaF7SH5UuHx5wTVoTokUZ5NWstbxTr4rwgHAX3h9NPgg0Xe9gx/uVRINk0mherq3iWJkD31T SfuZuTOhaIXUgguNRHzEsVzNDOmmRDTJWxLXobkoAla/atluto6nDUMV8xCRENpKDKJvqQ3qx2M = X-Google-Smtp-Source: AGHT+IGYnyUFNSdjvJkc0VIW3yuJtg5aiz0NyZ+LALBqUDcckNurq4l2e7uGpiJrXW6vpO/DZ00KKA== X-Received: by 2002:a05:6a21:3305:b0:1f5:8e94:2e7f with SMTP id adf61e73a8af0-203cbd0bba0mr25055381637.33.1745356291350; Tue, 22 Apr 2025 14:11:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PULL 9/9] target/avr: Increase TARGET_PAGE_BITS to 10 Date: Tue, 22 Apr 2025 14:11:24 -0700 Message-ID: <20250422211124.305724-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422211124.305724-1-richard.henderson@linaro.org> References: <20250422211124.305724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745356315716019000 Content-Type: text/plain; charset="utf-8" Now that we can handle the MCU allocating only a portion of the first page to i/o, increase the page size. Choose 10 as larger than the i/o on every MCU, just so that this path is tested. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/avr/cpu-param.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 81f3f49ee1..f5248ce9e7 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -21,13 +21,7 @@ #ifndef AVR_CPU_PARAM_H #define AVR_CPU_PARAM_H =20 -/* - * TARGET_PAGE_BITS cannot be more than 8 bits because - * 1. all IO registers occupy [0x0000 .. 0x00ff] address range, and they - * should be implemented as a device and not memory - * 2. SRAM starts at the address 0x0100 - */ -#define TARGET_PAGE_BITS 8 +#define TARGET_PAGE_BITS 10 #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 --=20 2.43.0