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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350737; x=1745955537; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TW4N3ReYmKveN3DtkTRFhUmPoxz9JDSNytNFvFcor3s=; b=ltj6Rp4PuGgS1vYQe7Q1ica0xDvbxsNvFGUjeYwi59ukvKceSaNefi59UHP9agYH/V /qdy4jsHi+hdaXyVDIEweBsGbMuOmdxoqe7yXHlJWPc7912360tV8Q2lD3L/eo3wOUIC XI2wQp+XIHoUx63FdLdBbPH85q0MoFRkuqB+IeeZj9TUTTIJXDIo+Shu5tGvz8sZYAzS MlnDEYaQJWTI7fKfJltXZuvwwaEPZ3RtC6Yw13y6tSHktUdx+Zz0C4VbcKngcwuoh3uh 6mC1sj6WO/S9qlY9zt/QfoFkxp4Rk8Za5yzjfyc/KRTwkmqIus3vG0rhWSZQGdOFeEIz TRoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350737; x=1745955537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TW4N3ReYmKveN3DtkTRFhUmPoxz9JDSNytNFvFcor3s=; b=FrsZprrkcfdMjF+WajURaKV4EWEYg6qrBv9JWubq0tTQOyXLiLQzRfFUwLEH2UEsDJ 41Pw7+R6wb4KEHKksdSKzUA8pV8o+2LdDgr6Oi64BKDInYfI0kYhfrRZuSQAHS9UdC4E DVvpUsYwbiIJqRuVSJRuwcPW7QMHq9sqppWPILAiQUlGdZ6rr0q4MrqCRCwCIxm+kCK9 A15k1VzKJYDIub1C7sACy5UIgnvSJnpLmK6pIU5acNo3Gkkf6i2Feu2NaYUZNC3eISqj TzjASLIve2q6exxbjYZyk8Y/185KV88rcYGWSyGVLyKP/tMODULGBltfdyah3hcB+rTo Dsjw== X-Gm-Message-State: AOJu0YyvSpZ93aev7F7oTWnWepNVMHBLH4Q90bKDynbWxN0bEdIaGytY RhrFSHpV6NjSACtTyrMF1iROGRDLVpf4fIuTKWdM3MBgf7hQ/EdX+IUQsh9r8mtnrP8IEhwjev6 X X-Gm-Gg: ASbGncuhSS3Elk4nwExYYOkqzgV2Qpila3acvB/61+BEOCvYCSKabNXrMBJXCIYbycI RAGx088/vCfagEk7nLSdwl8pbGSya04uWK8GpLxxu6RZa06tK+XFks7+YluQeii193W/LKJ0Ifv Nj4e1Cr+WyXiKcEVC2wrUWy5GlC89z100LgWr/iY66GBV7vB+JiMmFSm3ssTBxWRp6C/5NSYCoA +nSsZ5btVmhBkdfxFYjdCcir9ZoxPQUkOr86BGQyM31VueXaI9gF0DtoSt7YqCkk0pOhRh9rFjm i0mbVinVvXoxZloA0e0nzZyqQLITH1wlSM9Dqtf2VMR13D1WDDt6eAsVHfI14LoEgUhIYBGnbXb 1kwOC51xgTw== X-Google-Smtp-Source: AGHT+IFBP8BXSno0ocNf5zHGzoEvSQ8K01g8QYaLPu6p5KMfevvtuWHn+qmG3jzCGBcThPldjCz1jg== X-Received: by 2002:a17:903:11c5:b0:221:85:f384 with SMTP id d9443c01a7336-22c5359c36cmr229258785ad.16.1745350737383; Tue, 22 Apr 2025 12:38:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 146/147] target/i386: Remove AccelCPUClass::cpu_class_init need Date: Tue, 22 Apr 2025 12:28:15 -0700 Message-ID: <20250422192819.302784-147-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351278265019000 From: Philippe Mathieu-Daud=C3=A9 Expose x86_tcg_ops symbol, then directly set it as CPUClass::tcg_ops in TYPE_X86_CPU's class_init(), using CONFIG_TCG #ifdef'ry. No need for the AccelCPUClass::cpu_class_init() handler anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20250405161320.76854-3-philmd@linaro.org> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/i386/tcg/tcg-cpu.h | 4 ++++ target/i386/cpu.c | 4 ++++ target/i386/tcg/tcg-cpu.c | 14 +------------- 3 files changed, 9 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h index 7580f8afb4..85bcd61678 100644 --- a/target/i386/tcg/tcg-cpu.h +++ b/target/i386/tcg/tcg-cpu.h @@ -19,6 +19,8 @@ #ifndef TCG_CPU_H #define TCG_CPU_H =20 +#include "cpu.h" + #define XSAVE_FCW_FSW_OFFSET 0x000 #define XSAVE_FTW_FOP_OFFSET 0x004 #define XSAVE_CWD_RIP_OFFSET 0x008 @@ -76,6 +78,8 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state)= !=3D XSAVE_ZMM_HI256_OFF QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) !=3D XSAVE_HI16_Z= MM_OFFSET); QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=3D XSAVE_PKRU_OFFSE= T); =20 +extern const TCGCPUOps x86_tcg_ops; + bool tcg_cpu_realizefn(CPUState *cs, Error **errp); =20 int x86_mmu_index_pl(CPUX86State *env, unsigned pl); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d930ebd262..31487f4b28 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -43,6 +43,7 @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "tcg/tcg-cpu.h" =20 #include "disas/capstone.h" #include "cpu-internal.h" @@ -8903,6 +8904,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ +#ifdef CONFIG_TCG + cc->tcg_ops =3D &x86_tcg_ops; +#endif /* CONFIG_TCG */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; #ifdef TARGET_X86_64 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d941df0956..e13d0f6f86 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -124,7 +124,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) =20 #include "accel/tcg/cpu-ops.h" =20 -static const TCGCPUOps x86_tcg_ops =3D { +const TCGCPUOps x86_tcg_ops =3D { /* * The x86 has a strong memory model with some store-after-load re-ord= ering */ @@ -152,17 +152,6 @@ static const TCGCPUOps x86_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 -static void x86_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) -{ - /* for x86, all cpus use the same set of operations */ - cc->tcg_ops =3D &x86_tcg_ops; -} - -static void x86_tcg_cpu_class_init(CPUClass *cc) -{ - cc->init_accel_cpu =3D x86_tcg_cpu_init_ops; -} - static void x86_tcg_cpu_xsave_init(void) { #define XO(bit, field) \ @@ -211,7 +200,6 @@ static void x86_tcg_cpu_accel_class_init(ObjectClass *o= c, void *data) acc->cpu_target_realize =3D tcg_cpu_realizefn; #endif /* CONFIG_USER_ONLY */ =20 - acc->cpu_class_init =3D x86_tcg_cpu_class_init; acc->cpu_instance_init =3D x86_tcg_cpu_instance_init; } static const TypeInfo x86_tcg_cpu_accel_type_info =3D { --=20 2.43.0