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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350737; x=1745955537; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kCb0nI+2CCy6xbgQ0QUcGLa1ZUmAGxVEjmnQDdUz4pI=; b=t1jd2P++avcm45conNuRd0V9gBEOm2yuhTiMJpRNl2J/TLGBZwdBpIlkYOhYxbDVLD 6zVHhbXsaQN4zJLTn88B6keg5xxtqKB7vGbzbR2VNHdD3H3JJC9V8D7GQ7DTrm/mEYMV hpmaEyLdN7kSySzxYxRcLi4vuPM20+tGXGSkxI5OBa3dVJDt6uHBqJol8TFUFLuWZBBG yqLBhqt3jOi5BC3PVc+ptOwHa2T1UqIK3ICcdEq3OMvNFMBlJP5i734wKobA4WQPVT/J 5F9NRyW8gMhd80qv68RJEm+qK3Zv4VxefrvFAJKEqiFX6f5a+4m/XmIVWM6ota+wiY/k 9/+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350737; x=1745955537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kCb0nI+2CCy6xbgQ0QUcGLa1ZUmAGxVEjmnQDdUz4pI=; b=JVR3G+Hgum23qoCaS6hpDSESne6efxup6+xCbfmEC6qtW0nGSFZRM8/kZmmQ4Jz3Tl g7007BgURwzHgR54UFJKwoEOMlwMUyOc58Fu5Y4Awb8eWfxY52TMpzfw5Tg5imWgw52A aZS5Oul5ehOzcpUF25d+vi2JDVsjFEemdacccqlr0QULGk0uf7qiE/02DKNiL79OyIw3 dXRR7XVRLy00JX2VOwN6kTvxhc2XMCSoIEhurNe+/diK8KlxdiGn6ew0LaWZH4UZedg4 iJz9XpC/UFOXfQZAOinGz3QdP4rrYCzlcLOuZppQ6S2VxhZm37lLKzYT+85OmCvCopfe f6SQ== X-Gm-Message-State: AOJu0YwSB7l2BsxrIag6ViKKSxJK82FbSpj7Z/8nYEMSWVsOEVy5i9RX FxVxisnZUwiYBkR7pc7i8JOn+QefcUFPQnxBvk8LMmoJRIHAw+H/LHohSumGq0LGr1KpQGgfDk/ B X-Gm-Gg: ASbGncsmgJjKMy4FvbE5hQeQ93lqP4eNodYXNRMZGpTt6ZasUjT9NI4VkqcfJY2IgpT Q+6O69aCqzsliy5Z3p/dhXYh2H0IQFRDyGDk/Mqv3nsup5fdeTCESyw/5v0a1Gpgp7MnEjJepDU XW0jrUb7U4VjCSVbeT8SRRbYc+ot4se+ITmXF0vLh8OHi2UhpbGpNOh6NcMXG3tQZ89D+bJ/EfV mM+3vwwOifIzbgsyIIzBFpyHX7U5MlyiASgO/0T+ReOl5Xu2ZrYsGp6adSSE7WN+gPrFOMrTT/M Zkg10luffN8/s5X0vyESdG2Hulv2oCVqN1ihDJ3askmgZNlxuROsX/ir48yqjCBvCSQ33Jo3BjA = X-Google-Smtp-Source: AGHT+IEJoOituXy0/PTNSMRaXHdmEJwDzZVsh54EDpKftpM6BdXek50eQDExtZ/2P1RfKmAS/wAE2w== X-Received: by 2002:a17:902:cec8:b0:215:a179:14ca with SMTP id d9443c01a7336-22c5357a118mr233458515ad.2.1745350736728; Tue, 22 Apr 2025 12:38:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 145/147] target/riscv: Remove AccelCPUClass::cpu_class_init need Date: Tue, 22 Apr 2025 12:28:14 -0700 Message-ID: <20250422192819.302784-146-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351453467019100 From: Philippe Mathieu-Daud=C3=A9 Expose riscv_tcg_ops symbol, then directly set it as CPUClass::tcg_ops in TYPE_RISCV_CPU's class_init(), using CONFIG_TCG #ifdef'ry. No need for the AccelCPUClass::cpu_class_init() handler anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20250405161320.76854-2-philmd@linaro.org> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/riscv/tcg/tcg-cpu.h | 2 ++ target/riscv/cpu.c | 3 +++ target/riscv/tcg/tcg-cpu.c | 16 +--------------- 3 files changed, 6 insertions(+), 15 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h index ce94253fe4..a23716a5ac 100644 --- a/target/riscv/tcg/tcg-cpu.h +++ b/target/riscv/tcg/tcg-cpu.h @@ -26,6 +26,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Err= or **errp); void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp); bool riscv_cpu_tcg_compatible(RISCVCPU *cpu); =20 +extern const TCGCPUOps riscv_tcg_ops; + struct DisasContext; struct RISCVCPUConfig; typedef struct RISCVDecoder { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ad534cee51..2b830b3317 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3054,6 +3054,9 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, void *data) cc->get_arch_id =3D riscv_get_arch_id; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; +#ifdef CONFIG_TCG + cc->tcg_ops =3D &riscv_tcg_ops; +#endif /* CONFIG_TCG */ =20 device_class_set_props(dc, riscv_cpu_properties); } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 88f7cdb887..44fdf6c4cf 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,7 +140,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->excp_uw2 =3D data[2]; } =20 -static const TCGCPUOps riscv_tcg_ops =3D { +const TCGCPUOps riscv_tcg_ops =3D { .guest_default_memory_order =3D 0, =20 .initialize =3D riscv_translate_init, @@ -1527,24 +1527,10 @@ static void riscv_tcg_cpu_instance_init(CPUState *c= s) } } =20 -static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) -{ - /* - * All cpus use the same set of operations. - */ - cc->tcg_ops =3D &riscv_tcg_ops; -} - -static void riscv_tcg_cpu_class_init(CPUClass *cc) -{ - cc->init_accel_cpu =3D riscv_tcg_cpu_init_ops; -} - static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 - acc->cpu_class_init =3D riscv_tcg_cpu_class_init; acc->cpu_instance_init =3D riscv_tcg_cpu_instance_init; acc->cpu_target_realize =3D riscv_tcg_cpu_realize; } --=20 2.43.0