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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350101; x=1745954901; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sOXb/HC4BV8O7xeI6J7gLNVlc4Uon6AIhH5cPrLF7Cw=; b=MrZQUbE9Hy8vGPPpwsQ65SKZ6qPNgijIZnXow720adB+/weHMEHEBV3cSHCpWkmgxi DoQ1MaC//9j61ts8Nyw+Zt4ODwlK7PAQUug5tCk70v7a8bmx82ga2fHcNHH+CMFjckDt 80+nMUkUpL65P4+/lSC5hV4hOY8HF/6UKWcNRIF7x91xXwjv3Y48n4uawbmtI0/RWT67 fvQNp9WSxV4Z1WsSt6oWivdmjB6N+bVhpX/WqkThR//JUWrDP1+N8kVjfK+mRybnO1Rx A9kmm5zD1K4VM+jolDx+JmmE3M7ChNmmuIwETQcXqROjhcJDc0QcbAOoOPyuP9shdjpO GCvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350101; x=1745954901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sOXb/HC4BV8O7xeI6J7gLNVlc4Uon6AIhH5cPrLF7Cw=; b=S2p8o9FpvF8eEQTIITuyqEdkSxCIjlcIQbsSlJn3P0qKoWoNPs7H/04ZKv4R5QF6z5 qk/EQsRfffeUMrI+EYZzc81hVtIbGKsChYnYyfbYbrqdX8aIpK4GqdxNEC3jGsATYQmm Sr60aX/1KEFFAubvIsEeA0HoYbVqlA+aBtsBydUyKGHsGE2TNvFh5f259+uVW13g1UKO foGqdAMRL1OfjG740LhbS1LY+tTMb4EhHSuRnSffuiVffn+26AAeYz975EyrRuko2uO6 5MXN7JBDaBYe+X1MSZ4lSj0oYmyAEBnEcw1JZGhVGOqqWN7bOGF8jpnAuuQqsBLPUG8D gW0A== X-Gm-Message-State: AOJu0Yw98DBNLrdr4wBDKW+wtMhipP4jJzVw9z9l2ap5uQWKwNR0SoTV IRPFGzUA8PRpPG5G9BhhQUtSDtH2zKa+e+ERcgfvuhHDKP8+oD5HgpTkP9BbtcdAhimE+XDReqN h X-Gm-Gg: ASbGnctDDQelXxZMo1CComBiTQehP8GU5fd9xrNHI0yf0fIv99OWEPICgJpIJFvWaL/ B1tivphQXmrDY8ITXhDPpsxdKj6mxurTyt2Rub0evu+ktU5gTaIdix12lW3sR2VX49gTOkEiQgP DsrLzDmrIU7qe61/K4eWRvXTkUeFhvxQ6U6OXPkgJ+oX2YGrMUPezkW6SyLDsS42I6etJXwOk8q ltlP4mBosXfZ69UHdB7YCiVMXRqhtgl6nGg1mtlg+5vy1XzmGlyCmF3DrrzcYIbIhZ1o+y81gNO tF1RFE7HRKaJ2WZCfPr2hAGMV6uCAqj/NlSoOtEh5aq2xNvNkrUigPKZC6xwFUUy/q+pBopc0xs = X-Google-Smtp-Source: AGHT+IG+JqAivi5FuRZlxNM8RB0hycSEQHQMnDsgUXG9HEUEXLSERihRdceNl0ZUZVen3UTrUI6kcw== X-Received: by 2002:a17:90b:5646:b0:2ee:f80c:6889 with SMTP id 98e67ed59e1d1-3087bcc8a9dmr27042451a91.33.1745350101084; Tue, 22 Apr 2025 12:28:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 001/147] exec/tswap: target code can use TARGET_BIG_ENDIAN instead of target_words_bigendian() Date: Tue, 22 Apr 2025 12:25:50 -0700 Message-ID: <20250422192819.302784-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350196506019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-2-pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/tswap.h | 11 ++++++----- cpu-target.c | 1 + 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/exec/tswap.h b/include/exec/tswap.h index ecd4faef01..2683da0adb 100644 --- a/include/exec/tswap.h +++ b/include/exec/tswap.h @@ -13,13 +13,14 @@ /** * target_words_bigendian: * Returns true if the (default) endianness of the target is big endian, - * false otherwise. Note that in target-specific code, you can use - * TARGET_BIG_ENDIAN directly instead. On the other hand, common - * code should normally never need to know about the endianness of the - * target, so please do *not* use this function unless you know very well - * what you are doing! + * false otherwise. Common code should normally never need to know about t= he + * endianness of the target, so please do *not* use this function unless y= ou + * know very well what you are doing! */ bool target_words_bigendian(void); +#ifdef COMPILING_PER_TARGET +#define target_words_bigendian() TARGET_BIG_ENDIAN +#endif =20 /* * If we're in target-specific code, we can hard-code the swapping diff --git a/cpu-target.c b/cpu-target.c index cae77374b3..519b0f8900 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -155,6 +155,7 @@ void cpu_abort(CPUState *cpu, const char *fmt, ...) abort(); } =20 +#undef target_words_bigendian bool target_words_bigendian(void) { return TARGET_BIG_ENDIAN; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350220809265.7622782323874; Tue, 22 Apr 2025 12:30:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JID-0002NB-0G; Tue, 22 Apr 2025 15:28:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIA-0002MJ-ED for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:26 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JI7-000694-93 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:26 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-af59c920d32so3797969a12.0 for ; Tue, 22 Apr 2025 12:28:22 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350102; x=1745954902; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7uAMrxInIp+C0jH/wHKgggSAeCetsGjpX7/pWD8kiro=; b=y9D5gy0dDTn+N2sI5/VTQFDkq2Hf9UuEf45+Cxe8ZUCQwPIGZBUKHeEsJ/0/bpVZ7b cR2GkLcyu/uznmkMILGwCqByqzfzEiLcs8Y/ReV5LxdN9+7CTdwSRPsIfVJeeUtoLuOG DcA2ciL5M9Phuls+7Vy2qKTche4KelmgOfMFWPPnRa+IaeK+35An2iZ6Gg3TGU019V33 z8UEgocmKQStHB9I9eMoz0DN+Sdt6K3Jjl6EDgBJ8lPS80fTtPYHuNO8+J12bDqy59aG G9q60XczcKcoelMztPfetC5UEoVb4eKj/l3NqI+P6V361KrvD5POUPfVaIB8D7GUaayl xaNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350102; x=1745954902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7uAMrxInIp+C0jH/wHKgggSAeCetsGjpX7/pWD8kiro=; b=EHyQIEL7YB3AqpSQi/oR8MOs6r+TCaeVej6lwOukQq0YNMa7s7fJxa+uJg2LSud3kr S4uO1OGQX8NcqIgMq2ILC6yPXAupXJsyoycpgGHkF8MGSDn0tr86i0nIE0nPQyRCyD9L peD/HP2PZyoK623Edufq7E2BlzSEupMv/eHLLhGmhzIQUY70eduC0mJgql2CrQkGxKw6 IUtjmmqA/dJbuVtNN/D+TnXakqS7zRgCp+UlSu9X3HEgk5qR/JhobPVSyFSTvwwRvFew kX9L9+I9DaqMYqvsWMjYuc3mheAxQCnR1h1maov4aaIZ++gwv9k67C40m01N6vBY+0Ul OE/g== X-Gm-Message-State: AOJu0YwsRf04g4CIOZzRgZk+h3q/DNUPqNxN+52rA0CMb/9uTCLvmuDv EFz5AUzD6x/UEECtC4ac2YqQEuG1YEcFWB7ZbZg2DvoI7KcNIzoFKtZiSZsDLzrDZApu28ZcqGC t X-Gm-Gg: ASbGncs1SS3pDdqFHI49NwZi+AstSjsNHya2om7AhH54cfZAFKGs5+rTB3UKJkr57hf S79QjOuImUoQLlq9nytRQg6tv/Evd+KEYlsPmMODWRcWzpy+WLTCC+VAYgqYVjFA2GOBDE+ngLW PhTSjEpEIMOSc2F9ikZOb04ikYJL7/LLaSEDJtGH/MOGKprfU2hLdqUh5UoCDLfa/n7bNVSZWe5 IYwOS78sjX6IkSBRSBsQjUAIfquxWOkqqZGXCYWbGhYTnIPe8WXU0ObGhTg/5eI8x81gDDwh2Pi LGnNwz51QyeiihTzNU/h4rZdRfhsDkp9KCM+18eMbUc++dJxUeRhNKordldstUjlmy/pWQU0zwo = X-Google-Smtp-Source: AGHT+IFZ1QdC+BGWztzMsPshQ6NV1rtCruXr5mh/Sc/PPv499dYasfpvM5NOWL6Yw5SGPw4CNvr9yA== X-Received: by 2002:a17:90b:2807:b0:2ee:ee5e:42fb with SMTP id 98e67ed59e1d1-3087bb4d0bbmr26115087a91.13.1745350101704; Tue, 22 Apr 2025 12:28:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 002/147] exec/tswap: implement {ld, st}.*_p as functions instead of macros Date: Tue, 22 Apr 2025 12:25:51 -0700 Message-ID: <20250422192819.302784-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1745350222581019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Defining functions allows to use them from common code, by not depending on TARGET_BIG_ENDIAN. Remove previous macros from exec/cpu-all.h. By moving them out of cpu-all.h, we'll be able to break dependency on cpu.h for memory related functions coming in next commits. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-3-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 25 --------------- include/exec/tswap.h | 70 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 47b14446b8..d000fe4871 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -26,31 +26,6 @@ #include "exec/tswap.h" #include "hw/core/cpu.h" =20 -/* Target-endianness CPU memory access functions. These fit into the - * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. - */ -#if TARGET_BIG_ENDIAN -#define lduw_p(p) lduw_be_p(p) -#define ldsw_p(p) ldsw_be_p(p) -#define ldl_p(p) ldl_be_p(p) -#define ldq_p(p) ldq_be_p(p) -#define stw_p(p, v) stw_be_p(p, v) -#define stl_p(p, v) stl_be_p(p, v) -#define stq_p(p, v) stq_be_p(p, v) -#define ldn_p(p, sz) ldn_be_p(p, sz) -#define stn_p(p, sz, v) stn_be_p(p, sz, v) -#else -#define lduw_p(p) lduw_le_p(p) -#define ldsw_p(p) ldsw_le_p(p) -#define ldl_p(p) ldl_le_p(p) -#define ldq_p(p) ldq_le_p(p) -#define stw_p(p, v) stw_le_p(p, v) -#define stl_p(p, v) stl_le_p(p, v) -#define stq_p(p, v) stq_le_p(p, v) -#define ldn_p(p, sz) ldn_le_p(p, sz) -#define stn_p(p, sz, v) stn_le_p(p, sz, v) -#endif - /* MMU memory access macros */ =20 #if !defined(CONFIG_USER_ONLY) diff --git a/include/exec/tswap.h b/include/exec/tswap.h index 2683da0adb..84060a4999 100644 --- a/include/exec/tswap.h +++ b/include/exec/tswap.h @@ -80,4 +80,74 @@ static inline void tswap64s(uint64_t *s) } } =20 +/* Return ld{word}_{le,be}_p following target endianness. */ +#define LOAD_IMPL(word, args...) \ +do { \ + if (target_words_bigendian()) { \ + return glue(glue(ld, word), _be_p)(args); \ + } else { \ + return glue(glue(ld, word), _le_p)(args); \ + } \ +} while (0) + +static inline int lduw_p(const void *ptr) +{ + LOAD_IMPL(uw, ptr); +} + +static inline int ldsw_p(const void *ptr) +{ + LOAD_IMPL(sw, ptr); +} + +static inline int ldl_p(const void *ptr) +{ + LOAD_IMPL(l, ptr); +} + +static inline uint64_t ldq_p(const void *ptr) +{ + LOAD_IMPL(q, ptr); +} + +static inline uint64_t ldn_p(const void *ptr, int sz) +{ + LOAD_IMPL(n, ptr, sz); +} + +#undef LOAD_IMPL + +/* Call st{word}_{le,be}_p following target endianness. */ +#define STORE_IMPL(word, args...) \ +do { \ + if (target_words_bigendian()) { \ + glue(glue(st, word), _be_p)(args); \ + } else { \ + glue(glue(st, word), _le_p)(args); \ + } \ +} while (0) + + +static inline void stw_p(void *ptr, uint16_t v) +{ + STORE_IMPL(w, ptr, v); +} + +static inline void stl_p(void *ptr, uint32_t v) +{ + STORE_IMPL(l, ptr, v); +} + +static inline void stq_p(void *ptr, uint64_t v) +{ + STORE_IMPL(q, ptr, v); +} + +static inline void stn_p(void *ptr, int sz, uint64_t v) +{ + STORE_IMPL(n, ptr, sz, v); +} + +#undef STORE_IMPL + #endif /* TSWAP_H */ --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350314; cv=none; d=zohomail.com; s=zohoarc; b=f+catDtN3gnOi3QxPxJvZ+54b2UZMqfvUQ9jTUGNSKDzzZXuQ3Suu27khmzQAAENi9YrEKuivVwVGlvS7qt/yay/63ntpqbXaydXfr6TtZhevPbgIVv4s/viacvcCmS7PQGlKRg2IwsAKe2jteCCNb/voDRgylQvyGCLBzYGeVw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350314; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=a3Pmx2FLEZ9kjbt+cSL6Q/1nXndHvzQCpATDx6amJMg=; b=SdXNqfNB2uYPDt2QznzvXPkZNF3lH2puhZeLD+uflifMz7n/RoBQE1O5onL9exZWjdV5SRnmFI0r5NQbNQn8qU9EsDIU8X7nf3Vqi2dOL9mZjW4zyvI63t2iu1mtPJDC3jTTpqjmcOWH5/NtDREDMuoHDRKiWGOUCxjUsTiDH6o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174535031467288.38990743305146; Tue, 22 Apr 2025 12:31:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JID-0002NW-0v; Tue, 22 Apr 2025 15:28:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIA-0002MU-OU for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:27 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JI8-000698-DW for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:26 -0400 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-2ff85fec403so219927a91.1 for ; Tue, 22 Apr 2025 12:28:23 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350102; x=1745954902; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a3Pmx2FLEZ9kjbt+cSL6Q/1nXndHvzQCpATDx6amJMg=; b=s7ZfK3hwLZl+LA55jW4RO4i8KWsGOnotfmEWADQovEvXcj1hiV7utepQGjsl7Ue01o FPMSMVXD8PgvKvc3hlnhTRmzizscK2g+X988WuL2kqniwYRU/rwoHFVgAFJfdyHOjHF4 vccCWKo971b9IafxmAzHnxb3X33mItfKtNj5SnOxUcN5+S42obo5qbnJhtUnrwfwL5p6 ST3nf2j5F2v3hbR8HXQo5mCl+iWHWCt5njWRz5/UrwvDqY1T7pp286GtkhfYpBDD3Qen aA8Os7pS840i4pF94nIAblmutO56wGuwvO/nO75IGahgtMlHLfcj4MMEbbqL4Hp2Lnum r6oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350102; x=1745954902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a3Pmx2FLEZ9kjbt+cSL6Q/1nXndHvzQCpATDx6amJMg=; b=vNetFSFXcc+CFS3q0y5O8D+qhXGZG8grje757S01ZGTUuQKwOW3VCRaka6nge6pvcP aRoS2Kl50L40J1HDOq8Dgl0Ag8aMHvrM5mCMLgOw1QGBHnd/cZMTgUMxWV80CUpip2Bx cTlZpR2RoH0ziUwG//SAsRcxbB7iEopBouEQwUXjg9B/DrtzTNfVEn3tTpesdEj0BaFT nKNn4gkcSjHWtz4tnJFwQ1LFQbRGlyyt5dCGDXrcoYsWPz5/AdLFSN17HUE4wtJb6yrG h3BJz2bsLINrb4pMSWsYTeCMrAEqqzLS2gDLHxG+PdhN/C4On4TfKAkY6s+2ng4dLFO0 9KnA== X-Gm-Message-State: AOJu0YzWi4RZe5PNDabECKlfLTpkW1u6w9sqUnxyP/E22GqH6KsjHNL7 88zS8FsDYFp2uFe/wOWAyTpWFijq6LfjXhgOM8DIy/p6elJxkgyfHKWtYHZGyjGjGv8uyAL8kbx o X-Gm-Gg: ASbGncspKEEqgcg+bn2DsEKgYM5Yj9DEL0yFuXzEaWuC/qi48s469alf4NI9s5JLVL2 JuCuoCVbHXnOXGS3WTi46xU2NeBetQX+y9ZgxTBzMWe2YtMmr0P9PkwgbjMz7K+fcfsV25/crb0 2Lu628Oja33IgMPOShlipZb83kUPpliQWCjaF0TV02BMJKqWzW2iaNP3dmQIgaVtcfUeMdhO8/n NYmb0HstTSOU6qFKMPo+R/Et2MRX5Q83gXNBEm2Nrxv9OclFcl3jSXsYRW5pTXI3MUBgylbvzDk PGtCB5TMFd0FFTI7y8bT/4IKATjF/jiJWX0UPQJiA2WzHdVFMz/6SiPuqm5eUto2E7Bp2X4pc08 = X-Google-Smtp-Source: AGHT+IHyiBOi3NRLf4QBAXSg4pfZlKe1+JGNmVfHG6XvMzJGDIYOKIBKWl64Z+qaWVw8z+0NF8NV6A== X-Received: by 2002:a17:90b:3a44:b0:2fa:1c09:3cee with SMTP id 98e67ed59e1d1-309df0f2f8fmr255863a91.9.1745350102502; Tue, 22 Apr 2025 12:28:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 003/147] exec/memory_ldst: extract memory_ldst declarations from cpu-all.h Date: Tue, 22 Apr 2025 12:25:52 -0700 Message-ID: <20250422192819.302784-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350316705019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier They are now accessible through exec/memory.h instead, and we make sure all variants are available for common or target dependent code. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-4-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 12 ------------ include/exec/memory_ldst.h.inc | 4 ---- 2 files changed, 16 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index d000fe4871..7e8d66de31 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -32,18 +32,6 @@ =20 #include "exec/hwaddr.h" =20 -#define SUFFIX -#define ARG1 as -#define ARG1_DECL AddressSpace *as -#define TARGET_ENDIANNESS -#include "exec/memory_ldst.h.inc" - -#define SUFFIX _cached_slow -#define ARG1 cache -#define ARG1_DECL MemoryRegionCache *cache -#define TARGET_ENDIANNESS -#include "exec/memory_ldst.h.inc" - static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32= _t val) { address_space_stl_notdirty(as, addr, val, diff --git a/include/exec/memory_ldst.h.inc b/include/exec/memory_ldst.h.inc index 92ad74e956..7270235c60 100644 --- a/include/exec/memory_ldst.h.inc +++ b/include/exec/memory_ldst.h.inc @@ -19,7 +19,6 @@ * License along with this library; if not, see . */ =20 -#ifdef TARGET_ENDIANNESS uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, @@ -34,7 +33,6 @@ void glue(address_space_stl, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); void glue(address_space_stq, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); -#else uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, @@ -63,9 +61,7 @@ void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); -#endif =20 #undef ARG1_DECL #undef ARG1 #undef SUFFIX -#undef TARGET_ENDIANNESS --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350145; cv=none; d=zohomail.com; s=zohoarc; b=gOYYoKnnitLWkA9s5JYDOKjZ+J0C7jHMi2+sW8uxsk1+CqjiFjH0gbxlWxlppFXuVKxVWhAaqGDTpmERA3k1ufE0u7kihzGmkiJeSxhgbjVR2PUqMXMwj2qpt2p+Nv8FedIFgqYZILZKws+Mlk7CwqZIdhMvZaFksBC4EoWSweo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350145; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gWWqDQpkYSHDISmeC6TzU4TbRuBzp7ZNAHRWv+UuIFE=; b=TjsP6z7l8P9bV2hgh8jHT5Q+vj7ilP2hJU+1plYEzS4qJjxZmYd4LhRgQ53Fdu85JDvkH97pEL3bYXF//o5m6Oa8N+buyhw0hKH5D0Mza83hUqY10CwiETUEs0HodVXxNJuPpuAYxieu4jvckhZ5fBgN5gg2PhHg4CIV1/bvmIg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350145665210.9968769090102; Tue, 22 Apr 2025 12:29:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIE-0002O5-3M; Tue, 22 Apr 2025 15:28:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIC-0002Mw-8N for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:28 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JI9-00069G-B0 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:27 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-224171d6826so79561335ad.3 for ; Tue, 22 Apr 2025 12:28:24 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350103; x=1745954903; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gWWqDQpkYSHDISmeC6TzU4TbRuBzp7ZNAHRWv+UuIFE=; b=z8T/eSCZgmrsT8KbhAW/fnMfm61gJKjwvJF3aqGYvlwxv7q68061QQWtPEaukv/0EH uHVFg5MN1WPXn86m4rGjyUJ08Sc4aDl62t22HcTKZSxqrqIjeQcTZwh70eLfacpXFnme m5uCRZ5uah6MgTsP9ckgvJm3pKOm409RnNj08WHDhLXUhZozJ5GGTCJ/i8PgWuzC6Qi+ qH2yBFCg/dvZl6xDlA9Qf/jZwP5FhVfdyKYr8Zt/+WqMMGWHwhmfH8ouSWSxO9fVW55Z bgqHb5eIE/kQ49Osqpv7nWiRpxrY+DnWaUEhW7ceQWFDOqoiGqlaDGGzxLrwCivKirw4 xbBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350103; x=1745954903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gWWqDQpkYSHDISmeC6TzU4TbRuBzp7ZNAHRWv+UuIFE=; b=byGrFtSIgRzde2+2Jkk9A4L9wIjI6r3rrHZyZ237C3t/qNfOS6+vEBWQN70+6qyFV4 X7VnzVLpclO7fCVKfq6VW2ImCfN3r4RHSPRDKS6dgel7eFPbBAarHuIcV8+H0J1mCDTg /qCYIOzfzJj3YAHsL+WTUq+dy+o6lmSOzyCyFLMMiwQs6Nmu0GyUD8yM+afB7cx2Dm/2 v+DG1hdcRo9Pgmp0y8gCnb4X39OEU/q3jlWuJefqmkzgZsWWflWDO4V9ihtliEUsZg/S sReDJAXNUF/ZUuf9aCQAgdaqQ49d0REzEcKvFFPBjSIOcdU5ikIpoqRHWsTs4rSCyG/v olLA== X-Gm-Message-State: AOJu0Yysl1p1x+Qg/1UnjU+NA/obQQCWhWg+AuZmE6t2mnjUxjYX75vh tLpL6tiTFuThYXBGS7YTB3VaRdVmo/oKf02jMZfoqikp2mG7yYLO0/Y9S5terDYHg3PYiJcDdQF o X-Gm-Gg: ASbGncuRc8iebt2IMTJxUMArf1kI4tdaQRfJsFyrtPenu9ijxXjf0ETWHbhNRe4dFlB pQBuMjwnSZMeBTD8Mfcu9cd/YkTV2d4eOe8fqWM+RcYrYR7GM5RE4778I5XTswfFN+J5sjJMbAh Zr8utBeYfReZSPYM6OidB2QDRwLyCg5s12XpCcsuRcnSGu0SPaoon1BhHu62Fdnvrv+n4SPhRtZ VhJxRFmITNwwTpP7lM1m++kBZzGx9ILHY5ohZBmbRqp+y4GXzHFanAPARYoqGg2GfcBJaLsbafQ RZ3o2ky9zihn+Q8AvqHVgrMaaPlBUvhCzTegWUt7ZRnJpnmZJ8Zewnw7mM5l1AMw9rG7dI+zA5E = X-Google-Smtp-Source: AGHT+IFjNGOr6kN0kRNsDskBJlp5cVQp9iX41/VjkgvsEaQT7PFUrDMvK1k1783RUU1ewH+aAQmOKA== X-Received: by 2002:a17:90b:3885:b0:2ff:6aa6:47a3 with SMTP id 98e67ed59e1d1-3087bbad709mr24953034a91.25.1745350103306; Tue, 22 Apr 2025 12:28:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 004/147] exec/memory_ldst_phys: extract memory_ldst_phys declarations from cpu-all.h Date: Tue, 22 Apr 2025 12:25:53 -0700 Message-ID: <20250422192819.302784-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350147028019000 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier They are now accessible through exec/memory.h instead, and we make sure all variants are available for common or target dependent code. Move stl_phys_notdirty function as well. Cached endianness agnostic version rely on st/ld*_p, which is available through tswap.h. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-5-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 31 ----------------------------- include/exec/memory.h | 10 ++++++++++ include/exec/memory_ldst_phys.h.inc | 5 +---- 3 files changed, 11 insertions(+), 35 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 7e8d66de31..66a4252269 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -25,37 +25,6 @@ #include "exec/memory.h" #include "exec/tswap.h" #include "hw/core/cpu.h" - -/* MMU memory access macros */ - -#if !defined(CONFIG_USER_ONLY) - -#include "exec/hwaddr.h" - -static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32= _t val) -{ - address_space_stl_notdirty(as, addr, val, - MEMTXATTRS_UNSPECIFIED, NULL); -} - -#define SUFFIX -#define ARG1 as -#define ARG1_DECL AddressSpace *as -#define TARGET_ENDIANNESS -#include "exec/memory_ldst_phys.h.inc" - -/* Inline fast path for direct RAM access. */ -#define ENDIANNESS -#include "exec/memory_ldst_cached.h.inc" - -#define SUFFIX _cached -#define ARG1 cache -#define ARG1_DECL MemoryRegionCache *cache -#define TARGET_ENDIANNESS -#include "exec/memory_ldst_phys.h.inc" -#endif - -/* page related stuff */ #include "exec/cpu-defs.h" #include "exec/target_page.h" =20 diff --git a/include/exec/memory.h b/include/exec/memory.h index e1c196a0c2..cc5915033c 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -21,6 +21,7 @@ #include "exec/memattrs.h" #include "exec/memop.h" #include "exec/ramlist.h" +#include "exec/tswap.h" #include "qemu/bswap.h" #include "qemu/queue.h" #include "qemu/int128.h" @@ -2732,6 +2733,12 @@ MemTxResult address_space_write_rom(AddressSpace *as= , hwaddr addr, #define ARG1_DECL AddressSpace *as #include "exec/memory_ldst.h.inc" =20 +static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32= _t val) +{ + address_space_stl_notdirty(as, addr, val, + MEMTXATTRS_UNSPECIFIED, NULL); +} + #define SUFFIX #define ARG1 as #define ARG1_DECL AddressSpace *as @@ -2798,6 +2805,9 @@ static inline void address_space_stb_cached(MemoryReg= ionCache *cache, } } =20 +#define ENDIANNESS +#include "exec/memory_ldst_cached.h.inc" + #define ENDIANNESS _le #include "exec/memory_ldst_cached.h.inc" =20 diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst= _phys.h.inc index ecd678610d..db67de7525 100644 --- a/include/exec/memory_ldst_phys.h.inc +++ b/include/exec/memory_ldst_phys.h.inc @@ -19,7 +19,6 @@ * License along with this library; if not, see . */ =20 -#ifdef TARGET_ENDIANNESS static inline uint16_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_lduw, SUFFIX)(ARG1, addr, @@ -55,7 +54,7 @@ static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwad= dr addr, uint64_t val) glue(address_space_stq, SUFFIX)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } -#else + static inline uint8_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr) { return glue(address_space_ldub, SUFFIX)(ARG1, addr, @@ -139,9 +138,7 @@ static inline void glue(stq_be_phys, SUFFIX)(ARG1_DECL,= hwaddr addr, uint64_t va glue(address_space_stq_be, SUFFIX)(ARG1, addr, val, MEMTXATTRS_UNSPECIFIED, NULL); } -#endif =20 #undef ARG1_DECL #undef ARG1 #undef SUFFIX -#undef TARGET_ENDIANNESS --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350482; cv=none; d=zohomail.com; s=zohoarc; b=PhvstvIIPXPOBQA/KQ3i0KbnIzf2CSG5p8sT2DgeQGJB24Ldq0OfemN5waenDl62QOFOSFvgPm7lRuv9s76zbtiRYG7zB8cOXW9dhL+vX1ANFLs26h2Tz+IssEpZXUpar4kdNdGrNtKq8OkGCalTnh/6Ll5jEth/ZDau+CYJ35E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350482; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-6-pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/memory.h | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index cc5915033c..577f473446 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -3138,25 +3138,17 @@ address_space_write_cached(MemoryRegionCache *cache= , hwaddr addr, MemTxResult address_space_set(AddressSpace *as, hwaddr addr, uint8_t c, hwaddr len, MemTxAttrs attrs); =20 -#ifdef COMPILING_PER_TARGET /* enum device_endian to MemOp. */ static inline MemOp devend_memop(enum device_endian end) { QEMU_BUILD_BUG_ON(DEVICE_HOST_ENDIAN !=3D DEVICE_LITTLE_ENDIAN && DEVICE_HOST_ENDIAN !=3D DEVICE_BIG_ENDIAN); =20 -#if HOST_BIG_ENDIAN !=3D TARGET_BIG_ENDIAN - /* Swap if non-host endianness or native (target) endianness */ - return (end =3D=3D DEVICE_HOST_ENDIAN) ? 0 : MO_BSWAP; -#else - const int non_host_endianness =3D - DEVICE_LITTLE_ENDIAN ^ DEVICE_BIG_ENDIAN ^ DEVICE_HOST_ENDIAN; - - /* In this case, native (target) endianness needs no swap. */ - return (end =3D=3D non_host_endianness) ? MO_BSWAP : 0; -#endif + bool big_endian =3D (end =3D=3D DEVICE_NATIVE_ENDIAN + ? target_words_bigendian() + : end =3D=3D DEVICE_BIG_ENDIAN); + return big_endian ? MO_BE : MO_LE; } -#endif /* COMPILING_PER_TARGET */ =20 /* * Inhibit technologies that require discarding of pages in RAM blocks, e.= g., --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350576; cv=none; d=zohomail.com; s=zohoarc; b=YTYtmiPGuWoABiLLjqdfs5aXUNGlx42f240deGlpszl/ywJZHfiOFHqQxAAitDf0f6FuwIw317wFZRDu4NPSwIBtxpjixjozIP99a5DHCqVeuN85Kxq/D3a96SHjOWgErjLZxdsk7DYObh0r7nLeHBL8j75GIl2qowRX3OpaBGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350576; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=e1yx9YkYhatf0BqQ0DpUnwACHStmKGMnjqmqyTQwR00=; b=grzsq2ov/Eg4tgZ6bdYmNtHPcdUVm0gMd4hQdCUn5QmovwqwxuJWF4t4megrRVQT1UDUa0vAMEWfatxk+HYv2fClsA3q3o2OiKkbLcLlN7Z0wGhNAqupFWnBLVjxkAIF4ZcL+iZThTWlFDH8bvakT2wLnzYxbgYlh/vIdTnvD00= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350576959585.334812425555; Tue, 22 Apr 2025 12:36:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIH-0002Pe-Lu; Tue, 22 Apr 2025 15:28:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIC-0002ND-M4 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:28 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIA-00069Z-Ei for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:28 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2ff784dc055so5238682a91.1 for ; Tue, 22 Apr 2025 12:28:25 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:28:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 006/147] codebase: prepare to remove cpu.h from exec/exec-all.h Date: Tue, 22 Apr 2025 12:25:55 -0700 Message-ID: <20250422192819.302784-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350579180019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-7-pierrick.bouvier@linaro.org> --- include/tcg/tcg-op.h | 1 + target/ppc/helper_regs.h | 2 ++ hw/ppc/spapr_nested.c | 1 + hw/sh4/sh7750.c | 1 + page-vary-target.c | 2 +- target/ppc/tcg-excp_helper.c | 1 + target/riscv/bitmanip_helper.c | 2 +- 7 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index a02850583b..bc46b5570c 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -9,6 +9,7 @@ #define TCG_TCG_OP_H =20 #include "tcg/tcg-op-common.h" +#include "exec/target_long.h" =20 #ifndef TARGET_LONG_BITS #error must include QEMU headers diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 8196c1346d..b928c2c452 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -20,6 +20,8 @@ #ifndef HELPER_REGS_H #define HELPER_REGS_H =20 +#include "target/ppc/cpu.h" + void hreg_swap_gpr_tgpr(CPUPPCState *env); void hreg_compute_hflags(CPUPPCState *env); void hreg_update_pmu_hflags(CPUPPCState *env); diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 201f629203..a79e398c13 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -2,6 +2,7 @@ #include "qemu/cutils.h" #include "exec/exec-all.h" #include "exec/cputlb.h" +#include "exec/target_long.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" #include "hw/ppc/spapr.h" diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 6faf0e3ca8..41306fb600 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -29,6 +29,7 @@ #include "hw/irq.h" #include "hw/sh4/sh.h" #include "system/system.h" +#include "target/sh4/cpu.h" #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" #include "sh7750_regs.h" diff --git a/page-vary-target.c b/page-vary-target.c index 3f81144cda..84ddeb7c26 100644 --- a/page-vary-target.c +++ b/page-vary-target.c @@ -21,7 +21,7 @@ =20 #include "qemu/osdep.h" #include "exec/page-vary.h" -#include "exec/exec-all.h" +#include "exec/target_page.h" =20 bool set_preferred_target_page_bits(int bits) { diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index 5a189dc3d7..c422648cfd 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "qemu/log.h" +#include "target/ppc/cpu.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c index b99c4a39a1..e9c8d7f778 100644 --- a/target/riscv/bitmanip_helper.c +++ b/target/riscv/bitmanip_helper.c @@ -20,7 +20,7 @@ =20 #include "qemu/osdep.h" #include "qemu/host-utils.h" -#include "exec/exec-all.h" +#include "exec/target_long.h" #include "exec/helper-proto.h" #include "tcg/tcg.h" =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-8-pierrick.bouvier@linaro.org> --- include/exec/exec-all.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index dd5c40f223..19b0eda44a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -20,7 +20,6 @@ #ifndef EXEC_ALL_H #define EXEC_ALL_H =20 -#include "cpu.h" #if defined(CONFIG_USER_ONLY) #include "exec/cpu_ldst.h" #endif --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350145; cv=none; d=zohomail.com; s=zohoarc; b=YGZbqZihG30uZ6Ge0oKguB+RbCOXFAoZ9QJCcT549G/sBDTmv5f74njA5SmMMgg3e80J8mMp5HD8z4XFq6XpIvduERilWuHAciwK4sdwV0o2ir9PYuVljY7fUVfuBWJdz4llU4nWT/tBmyqUwBrcNq/ffKnkqIiHlts6tVeDXaY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350145; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=C24thF1lHDac0cqqp26h4qdOGOfLrlU2eZE0vToxCKw=; b=cYoxk+qvWXMAG9fId627XGhc8J2lvX7AQUVhvjizTRjc/Wceqiz5G9dqLM1R9YbOwOh4gc8Cdz/vRVzbD96Cw+U96OyjeF0R92Q1/5n6d4/Ui/eRdiz0yHLxYYgLqpzaIskipVxwAhfSY7TrjWo7pdmvOrrfKsq6tlSu9fJvI9I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350145790949.1576305925039; Tue, 22 Apr 2025 12:29:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIN-0002Th-En; Tue, 22 Apr 2025 15:28:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JID-0002O4-P1 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:29 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIB-00069s-FL for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:29 -0400 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-309d2e8c20cso1361841a91.0 for ; Tue, 22 Apr 2025 12:28:26 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350106; x=1745954906; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C24thF1lHDac0cqqp26h4qdOGOfLrlU2eZE0vToxCKw=; b=UzJoxDmu/i9sUpB6AG/z20Kp0WSz9x+M29B3ZafSM9AVswbXOKrnwIVWaOt1P2CW1P F+SvjRQQzzvkvk0Of62qZLm4ts5xjDzPmYzvRA4WHn7Be0i5KlQpUI2hpj4JwYq9K6uX JX0bl5u7TJuWMayFMjfBPE2xxtXvFndrW2B/eE2AZh5GPBPsaYEpd/SIe0LbLsEiRZNN XRe3Dkf6ak2FOaIHlrmtWBLsrUrTw83LNEvPrEY/9vX8pD3JCJii/+f/af9WkQgbI2Z2 0kWChvr/8Gu+YDeJPyUagrgg3hPJ+GtuleITv/5GJJH0A8KpyMS8MLgruuxZCoMtcTut uG1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350106; x=1745954906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C24thF1lHDac0cqqp26h4qdOGOfLrlU2eZE0vToxCKw=; b=NZK0SxO7d4SnW0yd+cbSde5lbK7hF64RQbfLYuOkeW7pYGR1UuMutKhZPZeCo87N2U cqo4hzYA4c2uDZXlM1lnucczToVf5StjwPOEwv0/Be9MKmCe9BRvLDI2xd3Da031matm J9KOdxE3Hg+CFcsUsNHh+XJJwmNydCrm9yW67R2zI7CLj5xpwofu6o4MOz11WgD96tLL nXe30f+vsIRJpX7L0DrlYyzQg/aFyH76bmN/3E5rgM5N6xS5AGaYONzlWsH+vLdNVdXz zUAMmHv2pmTKwDjHcT3h7ey89BVYSbO1zaJqLIHLvb0j0Lzl61Cr8R+PCsIJGFbzwdZg SjWg== X-Gm-Message-State: AOJu0YzRVBvUDL2eeJqwg/kIeCdU8G916sz9VIsoOQhOfikuXiVOPRjY Xwfs8w1AJoIZ0O+sA/nCHrCRjdqZjEPiGklOLhOOWvOfMcSYysAO471p1x1i6MjQPCyaeXp4ZgL y X-Gm-Gg: ASbGnctHag7RIF7yPspz3y2T+Sdtl1jtrp5QRGMzrMXLmQ9gNJC2BL4aj8AHrqQXroQ f1vGKph1T5DJ2JUKDb+5jjqTlg+3tHqQQnT+RK+NgAPmoX1xliB3R+giv7KvYEXKhyj8uHcKFNs OstSPW/QXczvGGIovBnSSUNGzawUqLZXuOiZ7et/KkpuesgClGzq/lf49JkK1Y5rBQy7dAoyhb9 DH8naHaJybax+YNjqS77cpv+lURUGgyXrjRpc3Rz6cEVcgjWqa/9YcV1c8jLwXwZhtA2hrblo8T N1Q5/AAqLsqOKZADAkQvIrdnCU3ZH3DGKPZMDmaXD5ou0lw/IUlTey9XJ5/lVokbMvNixdTvTr8 = X-Google-Smtp-Source: AGHT+IEj13CjKIbt2L7GJQmDk0HrsQeSD+dCh0zbHycu7epvjHyOyq1rRDTBdSsfwsm8njCgz8+zgQ== X-Received: by 2002:a17:90b:5444:b0:2fe:b735:87da with SMTP id 98e67ed59e1d1-3087ba5d6f9mr28732542a91.0.1745350105815; Tue, 22 Apr 2025 12:28:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 008/147] exec/memory-internal: remove dependency on cpu.h Date: Tue, 22 Apr 2025 12:25:57 -0700 Message-ID: <20250422192819.302784-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350148479019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Needed so compilation units including it can be common. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-9-pierrick.bouvier@linaro.org> --- include/exec/memory-internal.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h index 100c1237ac..b729f3b25a 100644 --- a/include/exec/memory-internal.h +++ b/include/exec/memory-internal.h @@ -20,8 +20,6 @@ #ifndef MEMORY_INTERNAL_H #define MEMORY_INTERNAL_H =20 -#include "cpu.h" - #ifndef CONFIG_USER_ONLY static inline AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv) { --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350265; cv=none; d=zohomail.com; s=zohoarc; b=KiMaldtJoiydD9xEhu5dO3yaRjzFox6ym2ukNb7O38a8ToosWMN/vRL+i8p8YWlPnSsJgavjhhWw5OkMedrns/V5PGYbYN5oTK+kn37YBzQs+OppQ1zk3/iZAFxfXrzqicvmT24T5I7v/Eyss0Mp3g2FSnLvD/DQniJaok3ZlbY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350265; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1+iLT1/Bfyh6dr5m+/UJ8NdE52qvtvxZT56N4nM2rJs=; b=GiGO69COQXRKfiOvHz/NE8HH2Pjx7F5VZiU4d3fSuR6BlLxctJqOEFf2lZkNy4B8NemayQKD8uj/0VLHrpTL0XQqgkLAG/Hj+rcw9Ad1TOr27xEFEQBdVkVoAcBrZn3fySU8C0zAZetkWYyW0CPI2R5J6dMwkAJuSQLMWTMAKhU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350265789234.35796988288337; Tue, 22 Apr 2025 12:31:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIJ-0002TK-6T; Tue, 22 Apr 2025 15:28:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIH-0002Oq-1Z for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:33 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIB-0006AB-T0 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:30 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-306b6ae4fb3so5444062a91.1 for ; Tue, 22 Apr 2025 12:28:27 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350106; x=1745954906; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1+iLT1/Bfyh6dr5m+/UJ8NdE52qvtvxZT56N4nM2rJs=; b=G7XOLLWqO30WEQZ4xqlZULxayOxwqvuBIWRy+KxSWAmxZZY1gL/tIbLj1dfOG4/GsM AmJvFcrKL5Ra5o+PzuyG+/Ef5f/nTLSdsuJgx/YwHEjfM/xQyIeRQD6f/kyCrpEJn8f3 cTEUzDBjxJEuFatsuaS3G+BuE7cKPGHPn+W6QiW3m9IbtLgo3rFmGyldpcDK+h7LZ79U OKb3rnIgDRjpOpUolOH1+oGopl/3kjmZ/pzmDjHBM/l6kMO3NEJsiVpGH1n87hH2QdAS hp3QoVx/dNlM9ZDPcvqirBnT6rTDw5DSWRDo9ZeR3CCYmfTv5xcsdUHsJ/MdAgH/hoGC GRZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350106; x=1745954906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1+iLT1/Bfyh6dr5m+/UJ8NdE52qvtvxZT56N4nM2rJs=; b=u7twx9sbSOwEkCcHMzH/WMPTovg3Rapz1aXyJpGXYBj1n4Q6jqPsaZu78cY3YYe/co DwOWZKaAn1RR/v6EdPMc/6Mp95ye3Mj2PRQwzjoNkw2PaVxr+le+Lk9WL59Noslru7Bw lSw2mOpZ7blO3kGw/pCKr9yMbQL2snnpu0lTz75scund/+ul0fjYIlDAo6EFaOPZAQcl qIcoGTXE10E5bsgftHo/dL9dF2fC9P8yW5eY7zR0zuRRs5b/XeaoAz89pDSBs6cXSugh g8+y/DpPc3tCGLqQl5uRIMgT9Pi7Z5RZnn5MNbVY4zdit9eHbPP/Y19TwU7TLp7tgb4j xxVw== X-Gm-Message-State: AOJu0YyFs/bh78EpukVuOmvYtFWb0F+nWuu95b1hJzxGeLLAdY+TFapO 5XhXlnR3pSmAV83NqjROmy2uxTVyTezuQzEAFo2aEUG+dUrL+nQ41oj8HF/iUUDc34BycIaWpR2 q X-Gm-Gg: ASbGncvl+t0RunXl/WIfevEJ1WIlKqooOcO/C4XJo/sLqPhc46MUUX3m13+6YNqSQnc ntjD5O4Dkjhh+2+UQbjsKUUnPrW6rJLQfgeoqjBCww1ilpNsw4pdD41iTBgdjl4vzy30Oc1E4rd 8G3+4WhNAtWbbtc6jE5tHdnOUH1U+/uCxiKDPXVbo2MUjw++JaBjTy9QEIjGhLVRk3zzmBB4h6z zgeP03wJ2kvgLeKhaWFvporfdHe3PAIUi+/9YzdAq8yIveZ1vp+CNhK8MFq95PcsjnUHagL1an5 08r7ZBHitGNrpiQaiOh4bZa2/7LUl6NNb/hRGhgIRF913c3VB62HbZcSb8lyorg5ARibeALfsC0 nTJiGgpA9dg== X-Google-Smtp-Source: AGHT+IFolnarNUJnhByCYoB8VbPcwTaRocfidq8IqjyapB5NaeyuXCRyXzdeHwb0B5aRr25ww7Dj1A== X-Received: by 2002:a17:90b:540e:b0:2f8:49ad:4079 with SMTP id 98e67ed59e1d1-3087bb41876mr20463153a91.6.1745350106554; Tue, 22 Apr 2025 12:28:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 009/147] exec/ram_addr: remove dependency on cpu.h Date: Tue, 22 Apr 2025 12:25:58 -0700 Message-ID: <20250422192819.302784-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350267065019000 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Needed so compilation units including it can be common. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-10-pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/ram_addr.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index e4c28fbec9..f5d574261a 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -20,13 +20,14 @@ #define RAM_ADDR_H =20 #ifndef CONFIG_USER_ONLY -#include "cpu.h" #include "system/xen.h" #include "system/tcg.h" #include "exec/cputlb.h" #include "exec/ramlist.h" #include "exec/ramblock.h" #include "exec/exec-all.h" +#include "exec/memory.h" +#include "exec/target_page.h" #include "qemu/rcu.h" =20 #include "exec/hwaddr.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350332; cv=none; d=zohomail.com; s=zohoarc; b=lxumUBwuwzsiQ4RZ10id5z4nGRGwaRm0k3PgszovEpNOOJFXtTJupvDNFeRrKQTAGiSJvbZ4x9UT9QaqZx1ZFaULltQX9v4sMP4/X2YU5f4O1dd22xcnPsZg2HFizAIkX/hj1/51me6m0WKutbzEumbccTdWQO1jvcixXBXgG/s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350332; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lG5GR1LgS5q2ZsGX0HNw3y+WcVPJJCWNVDcD2UvIEdE=; b=F3ajdibs+/cSL2oWVEaGw15l9tA+rR/7v3HCvTSdNuFu9rKXky6TaTI5ockxpXASMppUo78ok6RNPYe14KnxeJajA/J6oVwQMT2G4KAjXWaZv/GBhJk3BSGzGCu8SdiPuqocfQkoAAY9Z+y89L2mEVvUlUpbPB6NneibbHhRuMQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350331945744.6759781081071; Tue, 22 Apr 2025 12:32:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIU-0002Vf-NO; Tue, 22 Apr 2025 15:28:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIH-0002Op-1C for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:33 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIC-0006AQ-R4 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:30 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-b07d607dc83so4278187a12.1 for ; Tue, 22 Apr 2025 12:28:28 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350107; x=1745954907; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lG5GR1LgS5q2ZsGX0HNw3y+WcVPJJCWNVDcD2UvIEdE=; b=aYEoco6e8pLd3bvf0NnqHfzYWOuROZVQVKNV6hQKfMMvt38WcRopUzvE+x0NJSlbaX ciwChYo0BukrKxiE7Lj/dn+KYwptXmeGt3oXkkxLi0xrlUqhvGka+aG8JmWtfDVoKf8G CHngq2ZlXE9vxN4AEQlQksbrTxAYLt+jA+QttZG8ZLkI+XPBVCDa3fPr12pbnaeE9cA/ fTGhOV7rURCj3ca+XEMashcuUep4EcoDA6K02ZD52sOR2U1PKbjbQEmeHiI/PCPz3jdJ HULE+bJSmtRD0xD1TOE2ocy/tApMgOlBsotKElUxTuAmBAmMku0etWQtYUnwlaMInDzn xMVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350107; x=1745954907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lG5GR1LgS5q2ZsGX0HNw3y+WcVPJJCWNVDcD2UvIEdE=; b=OB2n7A+RXllc/Nm6jyw+tYha27ML1Pgjl+S7i5O0CMQD1H0DvQ079H95OqkoVGdpt5 CAg8Gp+N5i8/TPFpzd+hXWqnP8/3KfJowzEl4EPavXAQUhfCiYthwnsM9tetzF51qYAa 9HCHVRb84WMHtWBrtTXuvtooTPOV3n31rPiwUvCvaVBTgbwOMG6TGjU2iGAsou5cQLQS FCAfaob/nBZ2nmDYhDnsr23B1zpA/NbFWrMLg5AiVm5lE4SNfo8WMWh9pCpFAsuMl2ET EEjHMUrsL1thhlSNZReBkEx8N1mGZmlSL8dsQmryubLLJ+w5CPMG2QwyIx3+IVlYUS/w ThIQ== X-Gm-Message-State: AOJu0YzW+oqSxwhzJXEmDmy6os6GS9rSelBw8NsxcRvsTLTBcGQvwBcV 2Mx1o9x/ZkZFw41PsxW1fYmKdzG0NONjDewP2QWmrKaeBnyPUjarjZ/e3A+Wsis0OI53JEz4ZXY L X-Gm-Gg: ASbGncuQLEjFBY1Xsx/pfxEIH3ap0mfn08JMLjjq0yJQcPizWPiVOy5W+zCKA87uDhA DjYo9h+jDNGL5RONoaGeaRUHAFRbcIzDjdLLQgRyZBt5cbww9hb/CvYDZPr4R9S6TeQ4fwdoyfK uL8rtEtGYtH/XsyKIrVv0J2IoTu6hvtiQxYifgTv0ZwF9uPUu5VANCYYmq6REWmBMrwTUX7Gvpt HJrvrufjIPy+AEnkTVJHIjoiXfmgL5LbaA63SeOQdsdJz1CBrmLm5L1C1ReW1U6juWp6MsMkWlC osGq2JPwzTObogpSAQn5hBVvqVrpS0eHk7vgV3KYXzv9GkL2jVsIrcXoppvpF5nL4Jj7AJyovQE = X-Google-Smtp-Source: AGHT+IEUJKbf7X+M9bzS4q1774LQzNqrQVFSwKH5sgQSrhuSuW9S3bffIHTGeyXigdsVZuouEfff0w== X-Received: by 2002:a17:90b:2807:b0:2ee:ee5e:42fb with SMTP id 98e67ed59e1d1-3087bb4d0bbmr26115450a91.13.1745350107271; Tue, 22 Apr 2025 12:28:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 010/147] system/kvm: make kvm_flush_coalesced_mmio_buffer() accessible for common code Date: Tue, 22 Apr 2025 12:25:59 -0700 Message-ID: <20250422192819.302784-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350335006019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier This function is used by system/physmem.c will be turn into common code in next commit. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-11-pierrick.bouvier@linaro.org> --- include/system/kvm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/system/kvm.h b/include/system/kvm.h index ab17c09a55..21da3b8b05 100644 --- a/include/system/kvm.h +++ b/include/system/kvm.h @@ -210,11 +210,11 @@ bool kvm_arm_supports_user_irq(void); int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); int kvm_on_sigbus(int code, void *addr); =20 +void kvm_flush_coalesced_mmio_buffer(void); + #ifdef COMPILING_PER_TARGET #include "cpu.h" =20 -void kvm_flush_coalesced_mmio_buffer(void); - /** * kvm_update_guest_debug(): ensure KVM debug structures updated * @cs: the CPUState for this cpu --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350335; cv=none; d=zohomail.com; s=zohoarc; b=EEwoEcyZFNvAhDPmTfjqEs00wZrQALCjorNM2OBbkf12tkmx6keZJ7EYniQKlvBcIf2rhXc02jS9uOttH8/j6gHwA1Jgt4slognwHgtDz3VsULsd1bQX8+ZfqtJpD2uvlTjjCPJIbd3rCkl8eWf1WDT9NVakmBO/pn9iCwGeDs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350335; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XogLtFAmQTWKnFni/PyMhKIavN2RURu41I1WKUUy13M=; b=J9lqbtiro8hdjxFqpa3iBFXC77eTZPDvRvjwP6XZtgu7BLaSNHIYImycq+1U7427tJRIxru0+lHNUPD2G5JWxwjWisZCx/gdOwBax3V2MKX5vzsvNXyM6yZPfkDPxPEc5cKoSMk1CL/NTXvzpgvi4GCXCw6Ht+Kk3wVEyArDGC4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350335817251.4451042571261; Tue, 22 Apr 2025 12:32:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIU-0002Vi-Nr; Tue, 22 Apr 2025 15:28:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIH-0002Oo-06 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:33 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JID-0006Af-EJ for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:31 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-7fd581c2bf4so4589823a12.3 for ; Tue, 22 Apr 2025 12:28:28 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350109; x=1745954909; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uUDSMb2yaWobcfq2T8zvFcLGEMZI8wXQ4enYzV4I/Bs=; b=euiKftqLZ07t+NtkP7Pdx55QJIBNhO+sEkBy/+23LiidypbkTIkqmAIpDBLyI+5G++ xhCXH1I0GwKqRUKGYpzSFPTtCE82bQIIcR8H+fJnMih19rkn9hmVCjWxSqCZ5z6Tg0qV 9KpQ8rDsCZV/e36uO7m351V/VOM5FCZdW/sx8QIboLdBf2oXP3c2WOp/NjbNvwwE8XW2 B6ABFOn4iFVoayq/06+kQJabXBHS9DmCei+GmMuXzBfNorfG85kBnGeA3xJ5B2dWJD17 Y8C8zXJ5+u/gFG8RpRPTgmdY7vWUS41uyLZbZVhTRFfRNWHtP4wEcexFZ4aVQUqQibd0 BacQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350109; x=1745954909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uUDSMb2yaWobcfq2T8zvFcLGEMZI8wXQ4enYzV4I/Bs=; b=OQgYyfx1ep2EWKF4LwFH83+fvgAltiCERt+9uUOMFyM2QTLgrhBfQ9ZYLxXMrs/9UU t853bUIL/Df05Fnpjouu+1tANGQRArUQ4EZpNaPLVc+lEiaIAM4m/al1lfjQf+1Gstj1 c1sT5rUJj8sA/lhV2bJY1yMSuj74mvg/kQWnODZB8D6jkFgAvkws/ePZ89Xgi0vXmWhU YcyBuSsHoe2PPqI/zakzd5BTSYV9BEYg8Ovyhoz1P87W9CS80HU1vLmnrcCl53dDB15a s/dlCYKVaJALUsNGLq2kyCUMw57nLJVYU7f6zBbimTo8d4lxlwJO/A+zfXN9yCK+f95w FTFw== X-Gm-Message-State: AOJu0Yz86GFfffI3Dr05xQYHTugjmCMAdO4YBleQ3vTtpn1lPQdB3I6I kmGQjx+Sh3mr8uIfv1259EzisQlC/AORuq4mfLcECmoZcut1dkFzmJUkl/GgtP4hTOKA9477ylg 7 X-Gm-Gg: ASbGnctejfkR8m8Xuu46Qpo4JbZq6XGdl0WIEih2q1HNSueId0AgTg4GjeSKn0os0tl +O9PD5umgXJjHpfNRaX9n3gfgHXhk4HAzCtBtGo2IzuddXK8X80SMwEoBVLtLKEJ4rJ832vfJCH mWQIkekA8vJs7MJlzGYkiMJeiNQ125j668IC9OtWg4ZhhcgKKUITr6hzCY4kGQ12JE9DaFgwlzc UNBN2BB6wlrupjIrSYss67wV/3BCnrS6IhZ6HKBuxVWOXGNCM3yb+k8u5yZUM6SkJlrr/L0x0Cj MhBSWu22mc/Nf+HiiAHV9W1Y1Z2uDmfIcptapl4i/XMJ6jrw4DvL0qlEHwJExU0gYmpdGGINJ1P aZ+c4VgXDtQ== X-Google-Smtp-Source: AGHT+IHz/426LNDuiMCmZd7RnzHi3ly1ulePkGLgfWOAzIdRbXwRVIXJLXMQDzMDWRr8OFTFCDCGSA== X-Received: by 2002:a17:90b:58ec:b0:2ee:8e75:4aeb with SMTP id 98e67ed59e1d1-3087bb69d13mr27495369a91.17.1745350108650; Tue, 22 Apr 2025 12:28:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Anthony PERARD Subject: [PATCH 012/147] hw/xen: add stubs for various functions Date: Tue, 22 Apr 2025 12:26:01 -0700 Message-ID: <20250422192819.302784-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351131691019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Those symbols are used by system/physmem.c, and are called only if xen_enabled() (which happens only if CONFIG_XEN is set and xen is available). So we can crash the stubs in case those are called, as they are linked only when CONFIG_XEN is not set. Acked-by: Richard Henderson Reviewed-by: Anthony PERARD Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-13-pierrick.bouvier@linaro.org> --- hw/xen/xen_stubs.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++ hw/xen/meson.build | 3 +++ 2 files changed, 54 insertions(+) create mode 100644 hw/xen/xen_stubs.c diff --git a/hw/xen/xen_stubs.c b/hw/xen/xen_stubs.c new file mode 100644 index 0000000000..5e565df392 --- /dev/null +++ b/hw/xen/xen_stubs.c @@ -0,0 +1,51 @@ +/* + * Various stubs for xen functions + * + * Those functions are used only if xen_enabled(). This file is linked onl= y if + * CONFIG_XEN is not set, so they should never be called. + * + * Copyright (c) 2025 Linaro, Ltd. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "system/xen.h" +#include "system/xen-mapcache.h" + +void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t length) +{ + g_assert_not_reached(); +} + +void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size, + struct MemoryRegion *mr, Error **errp) +{ + g_assert_not_reached(); +} + +bool xen_mr_is_memory(MemoryRegion *mr) +{ + g_assert_not_reached(); +} + +void xen_invalidate_map_cache_entry(uint8_t *buffer) +{ + g_assert_not_reached(); +} + +ram_addr_t xen_ram_addr_from_mapcache(void *ptr) +{ + g_assert_not_reached(); +} + +uint8_t *xen_map_cache(MemoryRegion *mr, + hwaddr phys_addr, + hwaddr size, + ram_addr_t ram_addr_offset, + uint8_t lock, + bool dma, + bool is_write) +{ + g_assert_not_reached(); +} diff --git a/hw/xen/meson.build b/hw/xen/meson.build index 4a486e3673..a1850e7698 100644 --- a/hw/xen/meson.build +++ b/hw/xen/meson.build @@ -9,6 +9,9 @@ system_ss.add(when: ['CONFIG_XEN_BUS'], if_true: files( =20 system_ss.add(when: ['CONFIG_XEN', xen], if_true: files( 'xen-operations.c', +), +if_false: files( + 'xen_stubs.c', )) =20 xen_specific_ss =3D ss.source_set() --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351373; cv=none; d=zohomail.com; s=zohoarc; b=nKcpzBWrlPf5fpCpXR3fLPhBJaR9/FzZnb91Ayew3vZGAj2eYokfr+MMjB07ZTHomIznGxKjIUjLIKB6BbIXeeRYyTZuN5VpXTz2xjOt4EwudpMPkxK/n2kL5QKlJOXGsxGPmY6bqlZbp1lz3Le/Ky8gDO1fN2qYC4Lf//qjR1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351373; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tJ+EfqFiptMAQIqFH9MrlUuf9tOxdmhxubkBN2YjdQI=; b=P4hbOKQhts9D4wDuyCpZagRCSU36ECGj45aCZkz3k2NbwEb/AjjbdVTSLqRf6mo1mKAHSUVnE4blqZVMeLeZRYvXD6PRN+89aqt9b9uXSa7juWjuCPKLEcAotXcBXpLTKnwM0u1vUK+UIHlL5jTfyo2InrLPUuf6sD5SbsopiX0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351373271941.4910326713574; Tue, 22 Apr 2025 12:49:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIW-0002WB-TQ; Tue, 22 Apr 2025 15:28:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIP-0002UP-GZ for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:41 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIG-0006BA-Pw for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:39 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-7370a2d1981so4558193b3a.2 for ; Tue, 22 Apr 2025 12:28:30 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:28:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 013/147] system/xen: remove inline stubs Date: Tue, 22 Apr 2025 12:26:02 -0700 Message-ID: <20250422192819.302784-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351374369019000 From: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-14-pierrick.bouvier@linaro.org> --- include/system/xen-mapcache.h | 41 ----------------------------------- include/system/xen.h | 21 +++--------------- 2 files changed, 3 insertions(+), 59 deletions(-) diff --git a/include/system/xen-mapcache.h b/include/system/xen-mapcache.h index b68f196ddd..bb454a7c96 100644 --- a/include/system/xen-mapcache.h +++ b/include/system/xen-mapcache.h @@ -14,8 +14,6 @@ =20 typedef hwaddr (*phys_offset_to_gaddr_t)(hwaddr phys_offset, ram_addr_t size); -#ifdef CONFIG_XEN_IS_POSSIBLE - void xen_map_cache_init(phys_offset_to_gaddr_t f, void *opaque); uint8_t *xen_map_cache(MemoryRegion *mr, hwaddr phys_addr, hwaddr size, @@ -28,44 +26,5 @@ void xen_invalidate_map_cache(void); uint8_t *xen_replace_cache_entry(hwaddr old_phys_addr, hwaddr new_phys_addr, hwaddr size); -#else - -static inline void xen_map_cache_init(phys_offset_to_gaddr_t f, - void *opaque) -{ -} - -static inline uint8_t *xen_map_cache(MemoryRegion *mr, - hwaddr phys_addr, - hwaddr size, - ram_addr_t ram_addr_offset, - uint8_t lock, - bool dma, - bool is_write) -{ - abort(); -} - -static inline ram_addr_t xen_ram_addr_from_mapcache(void *ptr) -{ - abort(); -} - -static inline void xen_invalidate_map_cache_entry(uint8_t *buffer) -{ -} - -static inline void xen_invalidate_map_cache(void) -{ -} - -static inline uint8_t *xen_replace_cache_entry(hwaddr old_phys_addr, - hwaddr new_phys_addr, - hwaddr size) -{ - abort(); -} - -#endif =20 #endif /* XEN_MAPCACHE_H */ diff --git a/include/system/xen.h b/include/system/xen.h index 990c19a8ef..5f41915732 100644 --- a/include/system/xen.h +++ b/include/system/xen.h @@ -25,30 +25,15 @@ #endif /* COMPILING_PER_TARGET */ =20 #ifdef CONFIG_XEN_IS_POSSIBLE - extern bool xen_allowed; - #define xen_enabled() (xen_allowed) +#else /* !CONFIG_XEN_IS_POSSIBLE */ +#define xen_enabled() 0 +#endif /* CONFIG_XEN_IS_POSSIBLE */ =20 void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t length); void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size, struct MemoryRegion *mr, Error **errp); - -#else /* !CONFIG_XEN_IS_POSSIBLE */ - -#define xen_enabled() 0 -static inline void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t le= ngth) -{ - /* nothing */ -} -static inline void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size, - MemoryRegion *mr, Error **errp) -{ - g_assert_not_reached(); -} - -#endif /* CONFIG_XEN_IS_POSSIBLE */ - bool xen_mr_is_memory(MemoryRegion *mr); bool xen_mr_is_grants(MemoryRegion *mr); #endif --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 22 Apr 2025 12:28:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 014/147] system/physmem: compilation unit is now common to all targets Date: Tue, 22 Apr 2025 12:26:03 -0700 Message-ID: <20250422192819.302784-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351366630019000 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-15-pierrick.bouvier@linaro.org> --- system/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/meson.build b/system/meson.build index eec07a9451..bd82ef132e 100644 --- a/system/meson.build +++ b/system/meson.build @@ -3,7 +3,6 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files( 'ioport.c', 'globals-target.c', 'memory.c', - 'physmem.c', )]) =20 system_ss.add(files( @@ -16,6 +15,7 @@ system_ss.add(files( 'dma-helpers.c', 'globals.c', 'memory_mapping.c', + 'physmem.c', 'qdev-monitor.c', 'qtest.c', 'rtc.c', --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350110; x=1745954910; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8Sl3ykiXNh537Gb60LwyKbiNxYZ045w+WbZ93YXcawE=; b=k6vTI3ZJw2Hw7jiGcjc7LAK24CMyVYBflYr0w0M3ZLIKyKevmn1Nw5Ttk3vDsNcZ2O RKpSt2VZkc+pASgYMhm9ZttUrR3wcBJ3pHtLsm/VgZ612N8hnpuwV4SA0yEhIauKoHjL RvdVGodBaQdTzCNre06T6kPraS8KDQPco9YSW5Zstn8VaW9GUGO6b9t/+OFMO/i/aukJ 1HCTa3x/etv3YTA968h7PNS4CME1lBzfUmH2WPEj8lECBN2XWNdfgkZ7SA3nRd3DWZ2U 3rQyM/CDfRLiJdw0H70Cd+9BqTW9BE1WyXzOJ0u3+gdkopSBpD/3cmKhg/vIMSyN/Pa9 3lcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350110; x=1745954910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8Sl3ykiXNh537Gb60LwyKbiNxYZ045w+WbZ93YXcawE=; b=ptiH4DbmRvsZp2stLSr4Et1gLZ5HiTPAtPc5kGtS9e3lQ7mbV8F0KVaFkr/QqbcSms B0+ytB0ZTVZZkP5QXiv/YpMJ218FK1qLSLpcHJIfEOCdQw0At28I3fEV6nRLVz71himc 02yq2aLTJ3VMx5iYDp7iLSUFc1LeYzC+VJpO+uKDC9HXYOaqjGDyl2ofR2g8aa7SKPoz Cf0nDOp027ZmB2onVUCExguwdv6pEDDMvP+LMXiD1srO7xrokixH/oWJAIRsORK6NjDy Jng/hcpvt4hfTnJbx1/hq6BHwDk5TlD7XWRGA4VvvHzpvMPM6wecLofjrq6PIO/vN1OD MEcw== X-Gm-Message-State: AOJu0Yy7+MNL2dVNZs+RpuBhIOaHR0DhprnnqvtMKGPTE4wsxJ7jRmnX lVwYBsEISCmJXleGUu7DFGZLeiDzY0Qcu2976AEfmVFPpT8eibVsA2lhrNgXlAc/n6hNhXg/4DP K X-Gm-Gg: ASbGnctwO3ANN1SLulNOJrk8wLkyOFet6l0weR6MT09lTKoh3zc6xKQC4sUmcLWsg80 Atsa8YuXDMzWyZDJs6rKcGJbTfz4N5VFEjwVjCOz7Pisn2vKTdCfT/zETaYI7WhOjwICrM01Ciq vFYvNtg47E25ZVuvL0EF0PNNOPNifqyisumi4Lf9Akr8Tf2r9gbkX8BudU+UJtlQLxtIshEsHk3 XJjN97iZ//9gf+brpZDo7CiwNcdXJODhO6Vt9PKcaMOl27yAKCPW6ZtqTjKu5VnQcFxHuWb4Er5 8+ayTC2l1S7quu9EYZAUWT9ANdb33sczfT5KFafNZGCr/8R8nikn4nMQRLRBX82R5cp57T1/uUs = X-Google-Smtp-Source: AGHT+IEZWC+LXbS7xP6d6QIgLZk5oaHQcwTjWYFvqeArb55HkvUGhT4FPUBL2ion4ZIwNmT9L25fFQ== X-Received: by 2002:a17:90b:5404:b0:305:2d68:8d39 with SMTP id 98e67ed59e1d1-3087bb571a2mr29583503a91.12.1745350110457; Tue, 22 Apr 2025 12:28:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 015/147] include/exec/memory: extract devend_big_endian from devend_memop Date: Tue, 22 Apr 2025 12:26:04 -0700 Message-ID: <20250422192819.302784-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351144708019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier we'll use it in system/memory.c. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-16-pierrick.bouvier@linaro.org> --- include/exec/memory.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index 577f473446..fc07f69916 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -3138,16 +3138,22 @@ address_space_write_cached(MemoryRegionCache *cache= , hwaddr addr, MemTxResult address_space_set(AddressSpace *as, hwaddr addr, uint8_t c, hwaddr len, MemTxAttrs attrs); =20 -/* enum device_endian to MemOp. */ -static inline MemOp devend_memop(enum device_endian end) +/* returns true if end is big endian. */ +static inline bool devend_big_endian(enum device_endian end) { QEMU_BUILD_BUG_ON(DEVICE_HOST_ENDIAN !=3D DEVICE_LITTLE_ENDIAN && DEVICE_HOST_ENDIAN !=3D DEVICE_BIG_ENDIAN); =20 - bool big_endian =3D (end =3D=3D DEVICE_NATIVE_ENDIAN - ? target_words_bigendian() - : end =3D=3D DEVICE_BIG_ENDIAN); - return big_endian ? MO_BE : MO_LE; + if (end =3D=3D DEVICE_NATIVE_ENDIAN) { + return target_words_bigendian(); + } + return end =3D=3D DEVICE_BIG_ENDIAN; +} + +/* enum device_endian to MemOp. */ +static inline MemOp devend_memop(enum device_endian end) +{ + return devend_big_endian(end) ? MO_BE : MO_LE; } =20 /* --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350573; cv=none; d=zohomail.com; s=zohoarc; b=Y9rOgnTLAe7kF2HPerMoDZnOInwvr7VpYybkUDjgzK7UgENzfDkn5UsWzjNQGUTEyLwsF6Jnvp2ni7CMQGC6Dl/DKfdrinhiSGbkSIbwfHBDMEdpLIEhb6ODiIFzysSFfR8+XyXvs4nR69+UyQ5PGE77kX93ckM5HKTNHrATGYk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350573; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=I6MDZmD8wHi337leE/VPRqxkP9hRcv8+ycuZ+hH6Uq0=; b=Z+O7yqPv+cYVIPUpKGCvtGiZEyUl83JYdjhcJuzLGkNX0hHBncA1pkEhc2UsphC3N8mmhBAmcfTrgw3ARJ0mCcJmsOffLVhIooGaDiRRgwqpwPVtvG8s+NNhMv7Wuteh+nM2qx9H6aVdvMVwB207jXQowSRqGrZF6loGIbGhC1w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350573020530.0977747093813; Tue, 22 Apr 2025 12:36:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIY-0002XN-Vm; Tue, 22 Apr 2025 15:28:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JII-0002St-QE for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:34 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIG-0006BU-O1 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:34 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-af28bc68846so4772653a12.1 for ; Tue, 22 Apr 2025 12:28:31 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-17-pierrick.bouvier@linaro.org> --- include/exec/memory-internal.h | 19 +++++++++++++++++++ include/exec/memory.h | 18 ------------------ 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h index b729f3b25a..c75178a3d6 100644 --- a/include/exec/memory-internal.h +++ b/include/exec/memory-internal.h @@ -43,5 +43,24 @@ void address_space_dispatch_free(AddressSpaceDispatch *d= ); =20 void mtree_print_dispatch(struct AddressSpaceDispatch *d, MemoryRegion *root); + +/* returns true if end is big endian. */ +static inline bool devend_big_endian(enum device_endian end) +{ + QEMU_BUILD_BUG_ON(DEVICE_HOST_ENDIAN !=3D DEVICE_LITTLE_ENDIAN && + DEVICE_HOST_ENDIAN !=3D DEVICE_BIG_ENDIAN); + + if (end =3D=3D DEVICE_NATIVE_ENDIAN) { + return target_words_bigendian(); + } + return end =3D=3D DEVICE_BIG_ENDIAN; +} + +/* enum device_endian to MemOp. */ +static inline MemOp devend_memop(enum device_endian end) +{ + return devend_big_endian(end) ? MO_BE : MO_LE; +} + #endif #endif diff --git a/include/exec/memory.h b/include/exec/memory.h index fc07f69916..2f84a7cfed 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -3138,24 +3138,6 @@ address_space_write_cached(MemoryRegionCache *cache,= hwaddr addr, MemTxResult address_space_set(AddressSpace *as, hwaddr addr, uint8_t c, hwaddr len, MemTxAttrs attrs); =20 -/* returns true if end is big endian. */ -static inline bool devend_big_endian(enum device_endian end) -{ - QEMU_BUILD_BUG_ON(DEVICE_HOST_ENDIAN !=3D DEVICE_LITTLE_ENDIAN && - DEVICE_HOST_ENDIAN !=3D DEVICE_BIG_ENDIAN); - - if (end =3D=3D DEVICE_NATIVE_ENDIAN) { - return target_words_bigendian(); - } - return end =3D=3D DEVICE_BIG_ENDIAN; -} - -/* enum device_endian to MemOp. */ -static inline MemOp devend_memop(enum device_endian end) -{ - return devend_big_endian(end) ? MO_BE : MO_LE; -} - /* * Inhibit technologies that require discarding of pages in RAM blocks, e.= g., * to manage the actual amount of memory consumed by the VM (then, the mem= ory --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351004; cv=none; d=zohomail.com; s=zohoarc; b=hf9heRE/HhzlqdXZxJcreAe5Eh47Xey9R7FKX1tH/gSRs80xzzbcAS9krmmrw/YtzSzsRMG9GIRd/GH+p78cYtm10g6E1YYvjo338VfwJDpmMMxd8wmfpxxqRPVvR7y+EbTyUgWslSC9IQVu8XCqHAGdBUSxPOsq3vKIN1LTfAA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351004; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CwyTBdqp13kCnM3X/zqfhjWljdjzp0yIZaSQfrCHsoc=; b=RsuEhnoTWn4Z+OB4uIBVCZlAOFgJ8RohMHOTMG/SzCyRuE6DIJR/54+DQxPmgmdMIbkNAfl7yp5usO4rtPxajhe/4Re1HX591mopDCJtRSkJgGUUJY/sWUnqI6ZZXEyu6nFyUAmb80TbMLon6T8NT1nqJy5s5d0qGjWSAkINdPk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351004249373.3507885427739; Tue, 22 Apr 2025 12:43:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIc-0002aG-Fm; Tue, 22 Apr 2025 15:28:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIP-0002UR-IR for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:41 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIH-0006Bg-Go for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:36 -0400 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-3081f72c271so4854831a91.0 for ; Tue, 22 Apr 2025 12:28:32 -0700 (PDT) Received: from stoup.. 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*/ access_size =3D MAX(MIN(size, access_size_max), access_size_min); access_mask =3D MAKE_64BIT_MASK(0, access_size * 8); - if (memory_region_big_endian(mr)) { + if (devend_big_endian(mr->ops->endianness)) { for (i =3D 0; i < size; i +=3D access_size) { r |=3D access_fn(mr, addr + i, value, access_size, (size - access_size - i) * 8, access_mask, attrs); @@ -2584,7 +2575,8 @@ void memory_region_add_eventfd(MemoryRegion *mr, unsigned i; =20 if (size) { - adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE); + MemOp mop =3D (target_words_bigendian() ? MO_BE : MO_LE) | size_me= mop(size); + adjust_endianness(mr, &mrfd.data, mop); } memory_region_transaction_begin(); for (i =3D 0; i < mr->ioeventfd_nb; ++i) { @@ -2619,7 +2611,8 @@ void memory_region_del_eventfd(MemoryRegion *mr, unsigned i; =20 if (size) { - adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE); + MemOp mop =3D (target_words_bigendian() ? MO_BE : MO_LE) | size_me= mop(size); + adjust_endianness(mr, &mrfd.data, mop); } memory_region_transaction_begin(); for (i =3D 0; i < mr->ioeventfd_nb; ++i) { diff --git a/system/meson.build b/system/meson.build index bd82ef132e..4f44b78df3 100644 --- a/system/meson.build +++ b/system/meson.build @@ -2,7 +2,6 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files( 'arch_init.c', 'ioport.c', 'globals-target.c', - 'memory.c', )]) =20 system_ss.add(files( @@ -15,6 +14,7 @@ system_ss.add(files( 'dma-helpers.c', 'globals.c', 'memory_mapping.c', + 'memory.c', 'physmem.c', 'qdev-monitor.c', 'qtest.c', --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350788; cv=none; d=zohomail.com; s=zohoarc; b=PEKUI3BVm5DSzCxVLPsCRQ+eYFNUdyf4DOYRnN5nOav7XK+6fECUUu0WVX+fw9vDDWFAeFuf09y+an9C68lljmscURybSREWnQeaF7EXjm8bIboAFJvCtk+IVrxoADKwN/snC2wEchahygTyqTGeaZb0dkEYqlRMxwOxW9rfCgI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350788; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=C4uV9K+TLMfIMj+MUCSSrjCJ+qc1eJ+tR/bSlvHT0v8=; b=O00klOWfGcs/NdOK202122RoSWkVFxw/bF5nMs0LWPkAOZZH0IkGFw3JeOpVv+xUMessYofIfwXJzOhvIn3gTMhusDl81zEeGA/Sefs9B7NCAApQ4OE91zhim5Z1jZNQM0FLi/+Dnk3UpsCgGznQHSwYtM00TI9lNLsVQB64AGo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350788843862.5907098201837; Tue, 22 Apr 2025 12:39:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIa-0002YE-7U; Tue, 22 Apr 2025 15:28:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIP-0002Ub-K0 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:43 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JII-0006Bm-3T for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:40 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-af9925bbeb7so3663139a12.3 for ; Tue, 22 Apr 2025 12:28:33 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:28:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 018/147] system/ioport: make compilation unit common Date: Tue, 22 Apr 2025 12:26:07 -0700 Message-ID: <20250422192819.302784-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350791232019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250317183417.285700-19-pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- system/ioport.c | 1 - system/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/system/ioport.c b/system/ioport.c index 55c2a75239..89daae9d60 100644 --- a/system/ioport.c +++ b/system/ioport.c @@ -26,7 +26,6 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" #include "exec/ioport.h" #include "exec/memory.h" #include "exec/address-spaces.h" diff --git a/system/meson.build b/system/meson.build index 4f44b78df3..063301c3ad 100644 --- a/system/meson.build +++ b/system/meson.build @@ -1,6 +1,5 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [files( 'arch_init.c', - 'ioport.c', 'globals-target.c', )]) =20 @@ -13,6 +12,7 @@ system_ss.add(files( 'dirtylimit.c', 'dma-helpers.c', 'globals.c', + 'ioport.c', 'memory_mapping.c', 'memory.c', 'physmem.c', --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Therefore it's cleaner to just add to user_ss. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/meson.build | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 38ff227eb0..14bf797fda 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -12,7 +12,6 @@ tcg_specific_ss.add(files( 'translator.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) -tcg_specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec= -stub.c')) if get_option('plugins') tcg_specific_ss.add(files('plugin-gen.c')) endif @@ -22,6 +21,10 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG= '], if_true: files( 'cputlb.c', )) =20 +user_ss.add(when: ['CONFIG_TCG'], if_true: files( + 'user-exec-stub.c', +)) + system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'icount-common.c', 'monitor.c', --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351942; cv=none; d=zohomail.com; s=zohoarc; b=iuKWDre8SqBuRwDEQOKTe7DkQG/CncogGIShY5hMHqDZOIY5fDZF3Bm+qirYPwrH13Z0+hGBoQXnVdWn7f8gRBem7SI33OPZpWdARDKlpqVDCpD7n9dPohDqG+IWqi5oqB2Q4z9Debo+KHkg0DShlkoVBoIkWwcrnFsTPNBYdM0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351942; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jprqwHHwWojdGfQ1QgUvwGwX1dYcnH5RZgYMJfPxUv8=; b=QmTgIdbssIRhIJP2DPKXt2oPIqgCDplD8zjiHLVOK+xlvzUj0zH8XyWy2C9sYIUvx0gVHR3s2PWtao+Al6fOByGqsRrbwooNmrw+/GUp92EtJAN4oRldTFaEK85HyTjcFVpCqmriaEb3xp7guWuNh+646bcDjMUNC3bNfK+/fLo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351942262639.5245025162614; Tue, 22 Apr 2025 12:59:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JId-0002aM-4r; Tue, 22 Apr 2025 15:28:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIP-0002Ue-LG for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:43 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIJ-0006CI-06 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:40 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2ff6e91cff5so5299808a91.2 for ; Tue, 22 Apr 2025 12:28:34 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350113; x=1745954913; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jprqwHHwWojdGfQ1QgUvwGwX1dYcnH5RZgYMJfPxUv8=; b=mQGACf9dhegM/COoRNRFK/Fbn96R+tb8J+wRYPiJgnOd0TFIpMcnu/jELbOTetI+jv PAI5OiGe5YZ8XH1zHaRH80yG74H8bERRcMcXPzhlvK8K7KSyWznb2QgSuRj/P/jHJmIA Q2LIW1VjKYLG5m3yQac5UWJRgR6dfzfp0eCY1J992PQUiINghAoTRDU+XDKe4vUZFr1N Od92hZRJ/p89oRi550dSA/J78h3e4OtA4PmhVhNu+KLyPiZvDAcC7hTbUkhQuBTPXHtF eICE/SuCdbyYVc2sIBoQmg4dvo+krvzQFwbFXsFla70v8nZ2nGSENG5yp0R7hAFsxuiu iEbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350113; x=1745954913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jprqwHHwWojdGfQ1QgUvwGwX1dYcnH5RZgYMJfPxUv8=; b=Z6JamqI17gFCR5Yu4q1LCaWL/NuFTEhRrA5lQu7t0G2U+GtNkVp+HiiHegBmBSyIVf qkE9mmzg7jLxJV6ZAlBeKnFyh5JGcjxmuhCKGdyw0itMNv0+mc5GAIEYTeAohzWGwneT q9U4V9f7woEG41euikHdqOGB60ud/Mnln9cqz+iGznefNbVBJ+3FEFE1xZEKdcPiZsev dVosjXbr2BFLbqz0E8ro18aLyM/UlQ1P/VSoZVJx+kCA7XvvDpNTBLOuNaoTplfr7z6a wtLxjSYzA1qRAiHixpYPfIJtB9nA+wZqrhSEupuHBdFvtvzsvJkus0f7AFr+tqtLs5vN GWsw== X-Gm-Message-State: AOJu0YxnziAGAoyJY7XqG/AiNTZJ0tuUZGHGAHkBPYD/L6577dJoblix 9/vbyVBI+1n0M4Pc7loCwckJTe+yLHT5wq6k6sDzVqATG+mLIRgxBKilmLhceYzkpSSRiTSi0X+ y X-Gm-Gg: ASbGncvUVWWWTVIoQZTkIiOZzSOQp8aCNdtYp4jrukXHdrOGr3SIkHdkFWsbkabcFDe /T/yGXU1B4u1XeQsQXYO32OxlcixLtIxsRnn25kAL3V9Hftfynbw4VOjvWBA48QePO0PXsT0936 07QgE72faIOHRSTuA91qmrWvnzY8/tCUthUvkNeZkDxbdzK63YsKNSn3U+fA/alNvHqQuPF8Lmr 6KzfxCSJiXvN50wzaAuH5CKFGE+fbhmyyHtl0tYoUsBPLZmtOJ3SF8xjoHiOmMKq/NZa8e2gLdP jTtAgpbW4/ZF502KCkkdNZisphZzrbduKyerpisWcgYyj9oqRP8FfVCHtTDqsPxub78MQg8LRiA = X-Google-Smtp-Source: AGHT+IEDIfI3INze8eWIOIADXSblh/NNFwPGO+YNXLb6Fk61tZEsuFBXN3l9b5kekOFsJObT101koQ== X-Received: by 2002:a17:90b:582b:b0:2ee:c04a:4276 with SMTP id 98e67ed59e1d1-3087bb36bd4mr24228876a91.5.1745350113569; Tue, 22 Apr 2025 12:28:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier Subject: [PATCH 020/147] accel/tcg: Build plugin-gen.c once Date: Tue, 22 Apr 2025 12:26:09 -0700 Message-ID: <20250422192819.302784-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351942537019000 We assert that env immediately follows CPUState in cpu-all.h. Change the offsetof expressions to be based on CPUState instead of ArchCPU. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 13 +++++-------- accel/tcg/meson.build | 7 ++++--- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 7e5f040bf7..c1da753894 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -22,13 +22,12 @@ #include "qemu/osdep.h" #include "qemu/plugin.h" #include "qemu/log.h" -#include "cpu.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" -#include "exec/exec-all.h" +#include "tcg/tcg-op-common.h" #include "exec/plugin-gen.h" #include "exec/translator.h" +#include "exec/translation-block.h" =20 enum plugin_gen_from { PLUGIN_GEN_FROM_TB, @@ -89,15 +88,13 @@ static void gen_enable_mem_helper(struct qemu_plugin_tb= *ptb, qemu_plugin_add_dyn_cb_arr(arr); =20 tcg_gen_st_ptr(tcg_constant_ptr((intptr_t)arr), tcg_env, - offsetof(CPUState, neg.plugin_mem_cbs) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.plugin_mem_cbs) - sizeof(CPUStat= e)); } =20 static void gen_disable_mem_helper(void) { tcg_gen_st_ptr(tcg_constant_ptr(0), tcg_env, - offsetof(CPUState, neg.plugin_mem_cbs) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.plugin_mem_cbs) - sizeof(CPUStat= e)); } =20 static TCGv_i32 gen_cpu_index(void) @@ -113,7 +110,7 @@ static TCGv_i32 gen_cpu_index(void) } TCGv_i32 cpu_index =3D tcg_temp_ebb_new_i32(); tcg_gen_ld_i32(cpu_index, tcg_env, - -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); + offsetof(CPUState, cpu_index) - sizeof(CPUState)); return cpu_index; } =20 diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 14bf797fda..185830d0f5 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -3,6 +3,10 @@ common_ss.add(when: 'CONFIG_TCG', if_true: files( 'tcg-runtime.c', 'tcg-runtime-gvec.c', )) +if get_option('plugins') + common_ss.add(when: 'CONFIG_TCG', if_true: files('plugin-gen.c')) +endif + tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', @@ -12,9 +16,6 @@ tcg_specific_ss.add(files( 'translator.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) -if get_option('plugins') - tcg_specific_ss.add(files('plugin-gen.c')) -endif specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) =20 specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351093; cv=none; d=zohomail.com; s=zohoarc; b=ftXP62mrxysKVA467XWcRef77MBfObmsqlNQOlBQCNSom55K6oM7DqO8fXSPD79bUqUobwv5BrvQBSLzXONL1AN/+QsyQUatGpIPWfvC/ac/l1p7Qt1bI+qV5FArcHmP05vCwK1KmEINy3w2E7ASMfG0IZ/K9z8ZVdM8bhT6EQk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351093; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lVaQ8uivr0ZSIFp6lnsLbuP1aUnA44gVuobbLqVlt/s=; b=FlszFg+FjToGJZNGLTG81QDlcHG4SZKtrRZycCb4CspERLZKd1nPbNTcZA8OOtkNVAqMyvejfDuhFqolMqM0uvi3z8+jmAZSJRwo5qxtyOuY1dTjMhiTw7vtGGr+lnS+7TcEy7bUHxf4rtCrz7/sDECH8XNNxwJgcL9VC+nNlcA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351093451404.41231827060983; Tue, 22 Apr 2025 12:44:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIe-0002aw-PU; Tue, 22 Apr 2025 15:28:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIT-0002Vg-6n for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:45 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIP-0006Cd-5D for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:44 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-308702998fbso5010904a91.1 for ; Tue, 22 Apr 2025 12:28:35 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350114; x=1745954914; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lVaQ8uivr0ZSIFp6lnsLbuP1aUnA44gVuobbLqVlt/s=; b=SPZlSHPiFamSHNBsL2ksaFIsvWyj1SnRypY2hG02lpArYy0VfGwOXV8MmAPxyMky40 naol++jgbj7wJAfADNC53vfywseLURvnG5KMXxilb8QJm9EOHiiLzBRI2NMsA35MsP1Y hTLDukRajS4jMXgsCycOmrothu5C0vWXNdBYIzTnL6SJlNpRrrD8oIS4nknGCTfi8CDI dJVpZezCzNjZw6HTnbsz8Spf/YY5Q4FpGlhqlTrKvdVukSHoCsQYGYRZquvc7XdUSeHm uBM+aF+rf/1H76TAq/vj+kLvU7/BM7915/ZQ70lNjt8M/cAvDBACHECiCLDY9WRqDNOB mJwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350114; x=1745954914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lVaQ8uivr0ZSIFp6lnsLbuP1aUnA44gVuobbLqVlt/s=; b=jMNS6gwfflGUf60Vlzr1VG8tAxF4yPj4CZl0LvJ+7YvbuXis8LSBheXPKJeLKhzCv5 kvI6tw1ASlc2R+Zto6Y5ebREAgowL4fKBht6gEwkfWtithnv2IbIiBzTsu95ARY6lWHO 8GQgoyfnxmcE5uMiTQDCL7f2TBr7cDPRJ/JpNblnBCT1yjNQ9COMOaBgSiI064OYopw3 xFjCaM/RtgGPxQO3sysmCiBWOPLH/2gjc8GAK7lVBWFKBdhX5nY3uPtwfLYSt61P2R88 lAHrpJKsAszp8eipFrVBEwGxdGdgnOQ0itVP7N7aSMEPI5LhyNduweEYSTnoj2hzuxM1 ZZJQ== X-Gm-Message-State: AOJu0YxiSIL6LFvoMSrvqD34gGuTMPw6MkWuH+GFqt4viktir7j273YA bOcahr9D6NZiPzLuCFYRRsAjT7MCwNt6WQ/1zmThfjEsapM2LhwG1w6YlqCSrUS3eE/ahkwNjna U X-Gm-Gg: ASbGnctfG70GsM4hkrNEzgRlhrpcr0RrFANyOx1NI1atL/SRc1SpK4qmO9HS8mh7MBA /TTUP+EjjxlS0gkSHySg/DwOlJxIfGzRhs/oYYdHrHWK+CowB25Yag2kN3K+Qu3H8fKYRTYbkYS eFmQ2zgxtkrhsOVZuqIVTJ739wcaoOqTR/WKPUN7drVMDXk4p9hE0hVIxR+IKFy2rDqLGNEn6cR SuSTU6GwhZvPRzU2Chc50hVNX3Nmqs+ZwJJ5oNjWwc/E6rkTFTSRqt5rf/8obkWy1TfMQdmascr c1GssL2FQCEtypX9DjOHqGJKyTS10l0N+JPjy/THIvbt8pwwlveAGaRQYYYQVf9Ul/WB6VaAvps = X-Google-Smtp-Source: AGHT+IHeIN9/7OF7X0azbbbfAD73V7MTV5FfetqOkT+DBbiHv1+pdnmDjoQtREkvSnfDTwUmkUGGZA== X-Received: by 2002:a17:90b:4ecf:b0:2ee:693e:ed7a with SMTP id 98e67ed59e1d1-3087bccc3a5mr23409251a91.35.1745350114420; Tue, 22 Apr 2025 12:28:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 021/147] accel/tcg: Fix cpu_ld*_code_mmu for user mode Date: Tue, 22 Apr 2025 12:26:10 -0700 Message-ID: <20250422192819.302784-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351095306019000 Content-Type: text/plain; charset="utf-8" These routines are buggy in multiple ways: - Use of target-endian loads, then a bswap that depends on the host endiannness. - A non-unwinding code load must set_helper_retaddr 1, which is magic within adjust_signal_pc. - cpu_ldq_code_mmu used MMU_DATA_LOAD The bugs are hidden because all current uses of cpu_ld*_code_mmu are from system mode. Fixes: 2899062614a ("accel/tcg: Add cpu_ld*_code_mmu") Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 41 ++++------------------------------------- 1 file changed, 4 insertions(+), 37 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 2322181b15..629a1c9ce6 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1257,58 +1257,25 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr pt= r) uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - void *haddr; - uint8_t ret; - - haddr =3D cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_INST_FETCH); - ret =3D ldub_p(haddr); - clear_helper_retaddr(); - return ret; + return do_ld1_mmu(env_cpu(env), addr, oi, ra ? ra : 1, MMU_INST_FETCH); } =20 uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - void *haddr; - uint16_t ret; - - haddr =3D cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_INST_FETCH); - ret =3D lduw_p(haddr); - clear_helper_retaddr(); - if (get_memop(oi) & MO_BSWAP) { - ret =3D bswap16(ret); - } - return ret; + return do_ld2_mmu(env_cpu(env), addr, oi, ra ? ra : 1, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - void *haddr; - uint32_t ret; - - haddr =3D cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_INST_FETCH); - ret =3D ldl_p(haddr); - clear_helper_retaddr(); - if (get_memop(oi) & MO_BSWAP) { - ret =3D bswap32(ret); - } - return ret; + return do_ld4_mmu(env_cpu(env), addr, oi, ra ? ra : 1, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - void *haddr; - uint64_t ret; - - haddr =3D cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); - ret =3D ldq_p(haddr); - clear_helper_retaddr(); - if (get_memop(oi) & MO_BSWAP) { - ret =3D bswap64(ret); - } - return ret; + return do_ld8_mmu(env_cpu(env), addr, oi, ra ? ra : 1, MMU_INST_FETCH); } =20 #include "ldst_common.c.inc" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350535; cv=none; d=zohomail.com; s=zohoarc; b=OA8wIkp1E2pruywQCjv2s9P+giD+gyTITA2IF9XN7ZSKI401rZQ4z+GG6yN3T7fiQa+AorHPeS3dbGMKI2K2Ro/86AWSG+Eb66pvYq3QeOznhXeOO3V5YMCI9IK/8ZfSEC8gXEpD4AY5Qw6RPpMjJ8NEEUr0il03nsPPHQHbkjM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350535; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2/SnGbiJXxdcdsQzFocCM8W+C/HoHgmlhXBwGvsNJIU=; b=gABcqBFTOzq+JXLYET2Vg/ha4xHL7VjH9KMYoz3mSEZMnSCx+B4NJKxWeY4SSEMPRqlIRiPAJc2rNBqOB/49Ybi7FbTsYDMmZyF30xlh7kZLJ1Lez+vI7wgqXvdcKl9VzvgRx9ie0rnAhZFIuCX7wqOhuGPiQJjugpsh6rcfkBA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350535374934.7312729838444; Tue, 22 Apr 2025 12:35:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JJY-0003L3-9A; Tue, 22 Apr 2025 15:29:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIU-0002Vj-74 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:46 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIP-0006Ci-5T for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:45 -0400 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-301cda78d48so5304746a91.0 for ; Tue, 22 Apr 2025 12:28:36 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350115; x=1745954915; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2/SnGbiJXxdcdsQzFocCM8W+C/HoHgmlhXBwGvsNJIU=; b=kVL/CRyHL72Ri5L0mTd4NDta4GmABgFC9C6bDV0Xv2pSVZCASz9KI9EhAJkHPcF+hI Qny6EBqcjlBhsVNv33tdBCSYjvdZ9317Ra+/Wxn1IpwCk0GjrtC4JS2DVd6tfE2+vzlS 3T6SaYv9Z44w0kI+C2yqvq3AGVJhKVbrU0ExLuzTdAPO5nae4sfVDTBpCsSD/ETaNrpR 9N50SOcw/4czSeC/5J9tGxh1ZmKMnxAZQD/x8hTyePQ8LwxZTqS/dYwwbPUFrpxr6za/ VlKAVSs5/K4z9h4OOWg869V1LVS6BljSuP/1czmbe9FLpzHzzbAt2tO9PrWNx3YGl6MO /zZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350115; x=1745954915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2/SnGbiJXxdcdsQzFocCM8W+C/HoHgmlhXBwGvsNJIU=; b=qfMRcgujzbuJm/DqgzB84/Xb50TA3RWkJ3Nw439uQ5lUgK7bnoF/mI7rOcJp0g7cd5 LF1lCUdUz0yX61wbr2v05equYt5vXbCdA+qC4MQ2NUd0P1sg+xSxe5TvnlzbtXZFLToQ LQ0Y9SEH6ZpVR90JnxjbqxpoXcB5bWYl8XgWkrzo3Ppo84q4T7nV5X7xYwD04R2kkqkq jH7xPhY021AynVDA+F3dstfoB6H6g6M9WIYhhfY2lMVfFybiAXu9x9CSu/ug4jFRmIM2 mHgqiS+70FSF98hao3652svKZhutaf0G+0nh5PV1/JCSoMEjsbydSwCMOFRAivmwfrNu x4QA== X-Gm-Message-State: AOJu0Yz6j+CzWTT4QzlSjDR15AF5HuWONKX5VgjEPYtHRRinNwWzZiNK ZZXkNMeT66x5bNU1dK9NLqP/jV2mdEUrnMkvveKn3SV6G8TVoGkqunY5SPw478I9LB92UTF7NQW c X-Gm-Gg: ASbGncvOMU4LAoQYfLUxMviS6/5uK6lwWARR3vZvDIh5PE/g52SdDLuJe4a/EVnOLSU WHe2o9qvAslHqAt16dZjXOHlLywiEPJCSWFpMIp3+2ZiPDAoics+kZivuoMXllC2ZH4IOhkOvrC kAoNQCIA05mmxIjbqSoMLKNhKQ0bjxlpVOuT2JGZUthDQvGpb8fqVRgIr1415ol7DfMZhBKYQ9w OGi8yAlIkDHqEHCi739yv17UTDTnkcQ4a5TwFbINiV3+xtHB7fuetfMPf3dG6YIblaklDT1OSMN atpRDbzIC9cfyfxOMZ7bH83hmOfDm0Et+6tyGpUy5BirGAodrL5Mo0fk2JI2CSoGV/dW8KotXdE = X-Google-Smtp-Source: AGHT+IGoiCUJBGpDDMy5GQqRe5+Q6ztLiyrkan2iMbDabDTQpnJGriceD1LwlLhLoQjoElBNUGmD5g== X-Received: by 2002:a17:90b:2d0d:b0:2ee:8427:4b02 with SMTP id 98e67ed59e1d1-3087bbbddc7mr23917817a91.28.1745350115115; Tue, 22 Apr 2025 12:28:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 022/147] include/exec: Use vaddr for *_mmu guest memory access routines Date: Tue, 22 Apr 2025 12:26:11 -0700 Message-ID: <20250422192819.302784-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350537062019100 Content-Type: text/plain; charset="utf-8" Use vaddr only for the newest api, because it has the least number of uses and therefore is the easiest to audit. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 16 ++++++------- include/exec/cpu_ldst.h | 48 ++++++++++++++++++------------------- accel/tcg/cputlb.c | 8 +++---- accel/tcg/user-exec.c | 8 +++---- accel/tcg/ldst_common.c.inc | 20 ++++++++-------- 5 files changed, 50 insertions(+), 50 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 89593b2502..08a475c10c 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -77,7 +77,7 @@ # define END _le #endif =20 -ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_ptr addr, +ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, vaddr addr, ABI_TYPE cmpv, ABI_TYPE newv, MemOpIdx oi, uintptr_t retaddr) { @@ -101,7 +101,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_pt= r addr, } =20 #if DATA_SIZE < 16 -ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, abi_ptr addr, ABI_TYPE val, +ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, vaddr addr, ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, @@ -120,7 +120,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, abi_ptr a= ddr, ABI_TYPE val, } =20 #define GEN_ATOMIC_HELPER(X) \ -ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr, \ +ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, vaddr addr, \ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ { \ DATA_TYPE *haddr, ret; \ @@ -156,7 +156,7 @@ GEN_ATOMIC_HELPER(xor_fetch) * of CF_PARALLEL's value, we'll trace just a read and a write. */ #define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \ -ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr, \ +ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, vaddr addr, \ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ { \ XDATA_TYPE *haddr, cmp, old, new, val =3D xval; \ @@ -202,7 +202,7 @@ GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new) # define END _be #endif =20 -ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_ptr addr, +ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, vaddr addr, ABI_TYPE cmpv, ABI_TYPE newv, MemOpIdx oi, uintptr_t retaddr) { @@ -226,7 +226,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_pt= r addr, } =20 #if DATA_SIZE < 16 -ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, abi_ptr addr, ABI_TYPE val, +ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, vaddr addr, ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) { DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, @@ -245,7 +245,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, abi_ptr a= ddr, ABI_TYPE val, } =20 #define GEN_ATOMIC_HELPER(X) \ -ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr, \ +ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, vaddr addr, \ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ { \ DATA_TYPE *haddr, ret; \ @@ -278,7 +278,7 @@ GEN_ATOMIC_HELPER(xor_fetch) * of CF_PARALLEL's value, we'll trace just a read and a write. */ #define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \ -ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr, \ +ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, vaddr addr, \ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ { \ XDATA_TYPE *haddr, ldo, ldn, old, new, val =3D xval; \ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 769e9fc440..ddd8e0cf48 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -157,48 +157,48 @@ void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr = ptr, uint32_t val, void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, int mmu_idx, uintptr_t ra); =20 -uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t= ra); -uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_= t ra); -uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_= t ra); -uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_= t ra); -Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_= t ra); +uint8_t cpu_ldb_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t r= a); +uint16_t cpu_ldw_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t = ra); +uint32_t cpu_ldl_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t = ra); +uint64_t cpu_ldq_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t = ra); +Int128 cpu_ld16_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t = ra); =20 -void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val, +void cpu_stb_mmu(CPUArchState *env, vaddr ptr, uint8_t val, MemOpIdx oi, uintptr_t ra); -void cpu_stw_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, +void cpu_stw_mmu(CPUArchState *env, vaddr ptr, uint16_t val, MemOpIdx oi, uintptr_t ra); -void cpu_stl_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, +void cpu_stl_mmu(CPUArchState *env, vaddr ptr, uint32_t val, MemOpIdx oi, uintptr_t ra); -void cpu_stq_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, +void cpu_stq_mmu(CPUArchState *env, vaddr ptr, uint64_t val, MemOpIdx oi, uintptr_t ra); -void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val, +void cpu_st16_mmu(CPUArchState *env, vaddr addr, Int128 val, MemOpIdx oi, uintptr_t ra); =20 -uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, abi_ptr addr, +uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, vaddr addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, abi_ptr addr, +uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, vaddr addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, abi_ptr addr, +uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, vaddr addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, abi_ptr addr, +uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, vaddr addr, uint64_t cmpv, uint64_t newv, MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, abi_ptr addr, +uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, vaddr addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, abi_ptr addr, +uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, vaddr addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, abi_ptr addr, +uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, vaddr addr, uint64_t cmpv, uint64_t newv, MemOpIdx oi, uintptr_t retaddr); =20 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ - (CPUArchState *env, abi_ptr addr, TYPE val, \ + (CPUArchState *env, vaddr addr, TYPE val, \ MemOpIdx oi, uintptr_t retaddr); =20 #ifdef CONFIG_ATOMIC64 @@ -244,10 +244,10 @@ GEN_ATOMIC_HELPER_ALL(xchg) #undef GEN_ATOMIC_HELPER_ALL #undef GEN_ATOMIC_HELPER =20 -Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, abi_ptr addr, +Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, vaddr addr, Int128 cmpv, Int128 newv, MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, abi_ptr addr, +Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, vaddr addr, Int128 cmpv, Int128 newv, MemOpIdx oi, uintptr_t retaddr); =20 @@ -297,13 +297,13 @@ Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, = abi_ptr addr, # define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra #endif =20 -uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, +uint8_t cpu_ldb_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra); -uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, +uint16_t cpu_ldw_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra); -uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, +uint32_t cpu_ldl_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra); -uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, +uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra); =20 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index fb22048876..b03998f926 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2925,25 +2925,25 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ad= dr) return do_ld8_mmu(cs, addr, oi, 0, MMU_INST_FETCH); } =20 -uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, +uint8_t cpu_ldb_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t retaddr) { return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } =20 -uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, +uint16_t cpu_ldw_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t retaddr) { return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } =20 -uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, +uint32_t cpu_ldl_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t retaddr) { return do_ld4_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } =20 -uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, +uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t retaddr) { return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 629a1c9ce6..dec17435c5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1254,25 +1254,25 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr pt= r) return ret; } =20 -uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, +uint8_t cpu_ldb_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { return do_ld1_mmu(env_cpu(env), addr, oi, ra ? ra : 1, MMU_INST_FETCH); } =20 -uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, +uint16_t cpu_ldw_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { return do_ld2_mmu(env_cpu(env), addr, oi, ra ? ra : 1, MMU_INST_FETCH); } =20 -uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, +uint32_t cpu_ldl_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { return do_ld4_mmu(env_cpu(env), addr, oi, ra ? ra : 1, MMU_INST_FETCH); } =20 -uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, +uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { return do_ld8_mmu(env_cpu(env), addr, oi, ra ? ra : 1, MMU_INST_FETCH); diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index ebbf380d76..0447c0bb92 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -135,7 +135,7 @@ static void plugin_load_cb(CPUArchState *env, abi_ptr a= ddr, } } =20 -uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_= t ra) +uint8_t cpu_ldb_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t = ra) { uint8_t ret; =20 @@ -145,7 +145,7 @@ uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, Me= mOpIdx oi, uintptr_t ra) return ret; } =20 -uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, +uint16_t cpu_ldw_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { uint16_t ret; @@ -156,7 +156,7 @@ uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, return ret; } =20 -uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, +uint32_t cpu_ldl_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { uint32_t ret; @@ -167,7 +167,7 @@ uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, return ret; } =20 -uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, +uint64_t cpu_ldq_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { uint64_t ret; @@ -178,7 +178,7 @@ uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, return ret; } =20 -Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, +Int128 cpu_ld16_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { Int128 ret; @@ -205,14 +205,14 @@ static void plugin_store_cb(CPUArchState *env, abi_pt= r addr, } } =20 -void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, +void cpu_stb_mmu(CPUArchState *env, vaddr addr, uint8_t val, MemOpIdx oi, uintptr_t retaddr) { helper_stb_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, val, 0, oi); } =20 -void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, +void cpu_stw_mmu(CPUArchState *env, vaddr addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); @@ -220,7 +220,7 @@ void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uint1= 6_t val, plugin_store_cb(env, addr, val, 0, oi); } =20 -void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, +void cpu_stl_mmu(CPUArchState *env, vaddr addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); @@ -228,7 +228,7 @@ void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uint3= 2_t val, plugin_store_cb(env, addr, val, 0, oi); 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350116; x=1745954916; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Eyx3jHfuOzS1kFXjXoFUhMf/lfjFavDcf4Lxs2+4npE=; b=byD2SDUgLR54PHfXv5rq3LUirY0FVaKs6UJmCDd2cJKs3pntShKCswUXBINbRzsvxU 9fRC67KkKfYSh9AaeO9WYwUS4tI9v+MigDu3v7J2CjDakwOlBvQKYoGUghjQIyaYgkIj ajfGOlGWTNvg+MneMbBP/2D9FewFxXByjbrztKMHyqNcovRPT5hLMFQKpWuMl38YwQOA ev62cU/HBbPNsTpHzCr8LB98SASMq+LY7sdvmjkZlo05242SkE88YD0XtErj+iRuWegj VieRbw3R+wcY4exQWF6TixBC8R5+QEj7XPOjrz1yneBvVsKwiYG/uslKUUgiO/4vbfIU 6Rrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350116; x=1745954916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Eyx3jHfuOzS1kFXjXoFUhMf/lfjFavDcf4Lxs2+4npE=; b=vpnIrzft3Ohu3Y+EoqoB7N6D34Q1rfg3BC4rG6B9LOMhZMZik7/TRjdxsGxPiHlZN1 DWcnUqqVArcvLV6NOYd3NWrFaEVFoRwdhiv5yMP1TezIdjmLk4YNPOQw3CqBZxuJicrZ X5jpZdswCqZBUIxPtEEuqt3rQA6Nf1PC7dAsBqGtWmfOvIS/SYZ3Z0X4GqZFwa3TBxsp g/FnuBqkGFYJ9F72+tHV0ynEyv2xdKGEIJjLG92ilrcNLkj2+B+KPz5ighFrceEQO51a a3BwPV7G7pgz8+TbPN/sKNw49q32K8fKPi7MJpc8BJzuF6U8Z7jrCCi7gn7QIRaWXANK 5OOw== X-Gm-Message-State: AOJu0Ywoj4OCr0YzuFKKGIsBwf43AcyaTPylLRmlL1S2TUDBpt06D23r QF0yFZ7MlRPYa3Y0+nML7fDwz+11Q14umrBfo7mCRGxlsxyFU8Pas7pGGRJsHWeDUCUB+Qxyn0j k X-Gm-Gg: ASbGnctOOkKvdb3UAjoRZW2DuN9Qjxj7/5cp+hSa+RIdtb4CoZ8lTSXmlVenw+RsRxK d4nMA06ziMHXZALWAn2ZvswZvJsUc5aAH4YUrPgQLbo9WM3T8MD96pOI4/tW8Uoa9KVg5Zf0pnG w8awr5AxLcb+5mA7Wa9AlbX+RwddoiF1PHE8BXXafUuI4mpIbMScMFj0KaAI1V+duB2MDU1iqOc pAvwfqeycxTO//rbBnReft0zo7cEciIAv2K63BphmokyCb6vnQlONLqGwMs0jcAGnaqdNCBeSSC IW93l6BoS1O4bNlaxt0Oh9lpnzxGbaBxduZ05mXUB0KurcmE6SPApbeFm8X7IN8vIY99UeknIrc = X-Google-Smtp-Source: AGHT+IFdeApbYfgJ9rE+Q4uLUmOMTM0MnRVeGHgCg1MtEEiazxmFUOJnAqYAnAOCXNI9TaZZiQHSqw== X-Received: by 2002:a17:90b:274a:b0:2ee:b875:6d30 with SMTP id 98e67ed59e1d1-3087bb525cemr25959745a91.9.1745350115816; Tue, 22 Apr 2025 12:28:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 023/147] include/exec: Split out cpu-ldst-common.h Date: Tue, 22 Apr 2025 12:26:12 -0700 Message-ID: <20250422192819.302784-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350505228019100 Content-Type: text/plain; charset="utf-8" Split out the *_mmu api, which no longer uses target specific argument types. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu-ldst-common.h | 122 +++++++++++++++++++++++++++++++++ include/exec/cpu_ldst.h | 108 +---------------------------- 2 files changed, 123 insertions(+), 107 deletions(-) create mode 100644 include/exec/cpu-ldst-common.h diff --git a/include/exec/cpu-ldst-common.h b/include/exec/cpu-ldst-common.h new file mode 100644 index 0000000000..c46a6ade5d --- /dev/null +++ b/include/exec/cpu-ldst-common.h @@ -0,0 +1,122 @@ +/* + * Software MMU support + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef CPU_LDST_COMMON_H +#define CPU_LDST_COMMON_H + +#ifndef CONFIG_TCG +#error Can only include this header with TCG +#endif + +#include "exec/memopidx.h" +#include "exec/vaddr.h" +#include "exec/mmu-access-type.h" +#include "qemu/int128.h" + +uint8_t cpu_ldb_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t r= a); +uint16_t cpu_ldw_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t = ra); +uint32_t cpu_ldl_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t = ra); +uint64_t cpu_ldq_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t = ra); +Int128 cpu_ld16_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t = ra); + +void cpu_stb_mmu(CPUArchState *env, vaddr ptr, uint8_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stw_mmu(CPUArchState *env, vaddr ptr, uint16_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stl_mmu(CPUArchState *env, vaddr ptr, uint32_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stq_mmu(CPUArchState *env, vaddr ptr, uint64_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_st16_mmu(CPUArchState *env, vaddr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); + +uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, vaddr addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, vaddr addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, vaddr addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, vaddr addr, + uint64_t cmpv, uint64_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, vaddr addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, vaddr addr, + uint32_t cmpv, uint32_t newv, + MemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, vaddr addr, + uint64_t cmpv, uint64_t newv, + MemOpIdx oi, uintptr_t retaddr); + +#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ +TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ + (CPUArchState *env, vaddr addr, TYPE val, \ + MemOpIdx oi, uintptr_t retaddr); + +#ifdef CONFIG_ATOMIC64 +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) +#else +#define GEN_ATOMIC_HELPER_ALL(NAME) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) +#endif + +GEN_ATOMIC_HELPER_ALL(fetch_add) +GEN_ATOMIC_HELPER_ALL(fetch_sub) +GEN_ATOMIC_HELPER_ALL(fetch_and) +GEN_ATOMIC_HELPER_ALL(fetch_or) +GEN_ATOMIC_HELPER_ALL(fetch_xor) +GEN_ATOMIC_HELPER_ALL(fetch_smin) +GEN_ATOMIC_HELPER_ALL(fetch_umin) +GEN_ATOMIC_HELPER_ALL(fetch_smax) +GEN_ATOMIC_HELPER_ALL(fetch_umax) + +GEN_ATOMIC_HELPER_ALL(add_fetch) +GEN_ATOMIC_HELPER_ALL(sub_fetch) +GEN_ATOMIC_HELPER_ALL(and_fetch) +GEN_ATOMIC_HELPER_ALL(or_fetch) +GEN_ATOMIC_HELPER_ALL(xor_fetch) +GEN_ATOMIC_HELPER_ALL(smin_fetch) +GEN_ATOMIC_HELPER_ALL(umin_fetch) +GEN_ATOMIC_HELPER_ALL(smax_fetch) +GEN_ATOMIC_HELPER_ALL(umax_fetch) + +GEN_ATOMIC_HELPER_ALL(xchg) + +#undef GEN_ATOMIC_HELPER_ALL +#undef GEN_ATOMIC_HELPER + +Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, vaddr addr, + Int128 cmpv, Int128 newv, + MemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, vaddr addr, + Int128 cmpv, Int128 newv, + MemOpIdx oi, uintptr_t retaddr); + +uint8_t cpu_ldb_code_mmu(CPUArchState *env, vaddr addr, + MemOpIdx oi, uintptr_t ra); +uint16_t cpu_ldw_code_mmu(CPUArchState *env, vaddr addr, + MemOpIdx oi, uintptr_t ra); +uint32_t cpu_ldl_code_mmu(CPUArchState *env, vaddr addr, + MemOpIdx oi, uintptr_t ra); +uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr addr, + MemOpIdx oi, uintptr_t ra); + +#endif /* CPU_LDST_COMMON_H */ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index ddd8e0cf48..1fbdbe59ae 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -66,11 +66,8 @@ #error Can only include this header with TCG #endif =20 -#include "exec/memopidx.h" -#include "exec/vaddr.h" +#include "exec/cpu-ldst-common.h" #include "exec/abi_ptr.h" -#include "exec/mmu-access-type.h" -#include "qemu/int128.h" =20 #if defined(CONFIG_USER_ONLY) #include "user/guest-host.h" @@ -157,100 +154,6 @@ void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr = ptr, uint32_t val, void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, int mmu_idx, uintptr_t ra); =20 -uint8_t cpu_ldb_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t r= a); -uint16_t cpu_ldw_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t = ra); -uint32_t cpu_ldl_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t = ra); -uint64_t cpu_ldq_mmu(CPUArchState *env, vaddr ptr, MemOpIdx oi, uintptr_t = ra); -Int128 cpu_ld16_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t = ra); - -void cpu_stb_mmu(CPUArchState *env, vaddr ptr, uint8_t val, - MemOpIdx oi, uintptr_t ra); -void cpu_stw_mmu(CPUArchState *env, vaddr ptr, uint16_t val, - MemOpIdx oi, uintptr_t ra); -void cpu_stl_mmu(CPUArchState *env, vaddr ptr, uint32_t val, - MemOpIdx oi, uintptr_t ra); -void cpu_stq_mmu(CPUArchState *env, vaddr ptr, uint64_t val, - MemOpIdx oi, uintptr_t ra); -void cpu_st16_mmu(CPUArchState *env, vaddr addr, Int128 val, - MemOpIdx oi, uintptr_t ra); - -uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, vaddr addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, vaddr addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, vaddr addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, vaddr addr, - uint64_t cmpv, uint64_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, vaddr addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, vaddr addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, vaddr addr, - uint64_t cmpv, uint64_t newv, - MemOpIdx oi, uintptr_t retaddr); - -#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ -TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ - (CPUArchState *env, vaddr addr, TYPE val, \ - MemOpIdx oi, uintptr_t retaddr); - -#ifdef CONFIG_ATOMIC64 -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) -#else -#define GEN_ATOMIC_HELPER_ALL(NAME) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) -#endif - -GEN_ATOMIC_HELPER_ALL(fetch_add) -GEN_ATOMIC_HELPER_ALL(fetch_sub) -GEN_ATOMIC_HELPER_ALL(fetch_and) -GEN_ATOMIC_HELPER_ALL(fetch_or) -GEN_ATOMIC_HELPER_ALL(fetch_xor) -GEN_ATOMIC_HELPER_ALL(fetch_smin) -GEN_ATOMIC_HELPER_ALL(fetch_umin) -GEN_ATOMIC_HELPER_ALL(fetch_smax) -GEN_ATOMIC_HELPER_ALL(fetch_umax) - -GEN_ATOMIC_HELPER_ALL(add_fetch) -GEN_ATOMIC_HELPER_ALL(sub_fetch) -GEN_ATOMIC_HELPER_ALL(and_fetch) -GEN_ATOMIC_HELPER_ALL(or_fetch) -GEN_ATOMIC_HELPER_ALL(xor_fetch) -GEN_ATOMIC_HELPER_ALL(smin_fetch) -GEN_ATOMIC_HELPER_ALL(umin_fetch) -GEN_ATOMIC_HELPER_ALL(smax_fetch) -GEN_ATOMIC_HELPER_ALL(umax_fetch) - -GEN_ATOMIC_HELPER_ALL(xchg) - -#undef GEN_ATOMIC_HELPER_ALL -#undef GEN_ATOMIC_HELPER - -Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, vaddr addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, vaddr addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); - #if TARGET_BIG_ENDIAN # define cpu_lduw_data cpu_lduw_be_data # define cpu_ldsw_data cpu_ldsw_be_data @@ -297,15 +200,6 @@ Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, v= addr addr, # define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra #endif =20 -uint8_t cpu_ldb_code_mmu(CPUArchState *env, vaddr addr, - MemOpIdx oi, uintptr_t ra); -uint16_t cpu_ldw_code_mmu(CPUArchState *env, vaddr addr, - MemOpIdx oi, uintptr_t ra); -uint32_t cpu_ldl_code_mmu(CPUArchState *env, vaddr addr, - MemOpIdx oi, uintptr_t ra); -uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr addr, - MemOpIdx oi, uintptr_t ra); - uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr); uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr); uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350116; x=1745954916; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mAgu0wIwkbdnUvyofBHak8JNLbydpwL/6z5/1xS+61g=; b=jTuQQuv3z4AcWL4jcpdg7oowKWzPmrrR8g0ymjCD8J4X/7y63vgb/Um+wLVpITRRAr 9YT1YeoZJV0TINhOvfkq5CVECfzbRCTTDwaAMLdvu8iGhmYRTwX0HvNESTFJYOGGyHKd PffV7iDF3kwPoA7fqx3WztCuI4F5UoQLmZieFW06RZwcrCZZWcb2dwOcNLZqjWrJTDiM QqQNSF5VhSuWJMUdChIT0uYpIe2qMIHU5BWe8D9QLZGd0LP4k45lHAla+BmwIeGh9f+t QmbVFUrKxBYfTK6pGdMjDO1Eq6h6BcbCy+QE3hMPrOTYjtgAAizb+GH9VZabsL7YL0yF /qoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350116; x=1745954916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mAgu0wIwkbdnUvyofBHak8JNLbydpwL/6z5/1xS+61g=; b=CkURc1tJKEAX5ctFOXl+jGU61RHoY525WUCDtZ4r3mBew60+NGGm8lB9W44OXW5R3I ZMaOt7PMQ6cm1rcC/Dwjh/qJ1YSOv09BwOrsYn/EO/fTsNvVBAn5uYyeyZzlZs3dISHN Mi3Q19/NougpHiFEj0npnGumDHO4Zxme1DKdLmJUYC5TjkKEuH8aZGHp+08ByCDD+xKz BlvxbwvIytJVNns79gvSTlVeULkF8YFkzcCK8+RuYZvSGg5W3ww7aP2gEIVM5ooHitw/ lBMQbjJy1w9cGA5DInOtXyDqhJ1cqjK2Ave/rGN+t+UDudvMecpvEm4C31dQ1kRHKrz2 CyJA== X-Gm-Message-State: AOJu0YyQnOrFqugiZqJGYId77lXSC7NSuEDQ+3GjzA2ChXbvJbqk+Zub vgcWAGBpFznEUScp3IfVHdTpi5l69gfsalHfQfrsNJTdTZKcdGXV9yPi23QA5WfkcWCRTtj4g48 W X-Gm-Gg: ASbGncs3TwiPqwAD2oqCoqNv6Jx8wSGAvwTDEHnupXWZXltGPHm+GvTAaw1U976vvQX gMuwdt1y1GamDVKslY2Jz4M71lMkaQ4bvLF1K/nS8HQM2np5+guMO+7ZRiBR0cTyLR06MPAZXo1 CfThVEUzm/YEJ98qYvi0sZBxL9Td6bjQpnKoBK997dxFzvE6pa5seFKqzKaTObL1JGqHa1fDbAq hWVGu3ANfHg/8hPIPtSxgkmWFcx+uFuyufRnNZPc8MpqstHXIG6A8ujItgvckFAaNRDO/Qo+odV Fn7MjR4rj4EKpeSpEjrpuLXlz3w9Qdxsx/z3rBnhUQSzPqz/4Bxv1Tzpc2YIl0/hDaQm3HtZw6Y = X-Google-Smtp-Source: AGHT+IFJ4sOl2GVCntaoUxKdjC9tBhmTh4jkbaqVIPt01ChPkHewKi0sptNA6mo7pLaWZAV3Z4dWOA== X-Received: by 2002:a17:90a:e190:b0:2ee:c30f:33c9 with SMTP id 98e67ed59e1d1-309df13d219mr309195a91.14.1745350116429; Tue, 22 Apr 2025 12:28:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 024/147] include/exec: Split out accel/tcg/cpu-mmu-index.h Date: Tue, 22 Apr 2025 12:26:13 -0700 Message-ID: <20250422192819.302784-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350210697019000 Content-Type: text/plain; charset="utf-8" The implementation of cpu_mmu_index was split between cpu-common.h and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the plumbing common to user and system mode. Using MMU_USER_IDX requires the cpu.h for a specific target, and so is restricted to when we're compiling per-target. Include the new header only where needed. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-mmu-index.h | 41 +++++++++++++++++++++++++++++++ include/exec/cpu-all.h | 6 ----- include/exec/cpu-common.h | 20 --------------- include/exec/cpu_ldst.h | 1 + semihosting/uaccess.c | 1 + target/arm/gdbstub64.c | 3 +++ target/hppa/mem_helper.c | 1 + target/i386/tcg/translate.c | 1 + target/loongarch/cpu_helper.c | 1 + target/microblaze/helper.c | 1 + target/microblaze/mmu.c | 1 + target/openrisc/translate.c | 1 + target/sparc/cpu.c | 1 + target/sparc/mmu_helper.c | 1 + target/tricore/helper.c | 1 + target/xtensa/mmu_helper.c | 1 + 16 files changed, 56 insertions(+), 26 deletions(-) create mode 100644 include/accel/tcg/cpu-mmu-index.h diff --git a/include/accel/tcg/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-= index.h new file mode 100644 index 0000000000..8d1cb53bfa --- /dev/null +++ b/include/accel/tcg/cpu-mmu-index.h @@ -0,0 +1,41 @@ +/* + * cpu_mmu_index() + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_CPU_MMU_INDEX_H +#define ACCEL_TCG_CPU_MMU_INDEX_H + +#include "hw/core/cpu.h" +#include "tcg/debug-assert.h" +#ifdef COMPILING_PER_TARGET +# ifdef CONFIG_USER_ONLY +# include "cpu.h" +# endif +#endif + +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ +static inline int cpu_mmu_index(CPUState *cs, bool ifetch) +{ +#ifdef COMPILING_PER_TARGET +# ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +# endif +#endif + + int ret =3D cs->cc->mmu_index(cs, ifetch); + tcg_debug_assert(ret >=3D 0 && ret < NB_MMU_MODES); + return ret; +} + +#endif /* ACCEL_TCG_CPU_MMU_INDEX_H */ diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 66a4252269..33b9dc81eb 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -34,8 +34,6 @@ CPUArchState *cpu_copy(CPUArchState *env); =20 #ifdef CONFIG_USER_ONLY =20 -static inline int cpu_mmu_index(CPUState *cs, bool ifetch); - /* * Allow some level of source compatibility with softmmu. We do not * support any of the more exotic features, so only invalid pages may @@ -45,10 +43,6 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetc= h); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) #define TLB_WATCHPOINT 0 =20 -static inline int cpu_mmu_index(CPUState *cs, bool ifetch) -{ - return MMU_USER_IDX; -} #else =20 /* diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 3771b2130c..be032e1a49 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -272,24 +272,4 @@ static inline CPUState *env_cpu(CPUArchState *env) return (CPUState *)env_cpu_const(env); } =20 -#ifndef CONFIG_USER_ONLY -/** - * cpu_mmu_index: - * @env: The cpu environment - * @ifetch: True for code access, false for data access. - * - * Return the core mmu index for the current translation regime. - * This function is used by generic TCG code paths. - * - * The user-only version of this function is inline in cpu-all.h, - * where it always returns MMU_USER_IDX. - */ -static inline int cpu_mmu_index(CPUState *cs, bool ifetch) -{ - int ret =3D cs->cc->mmu_index(cs, ifetch); - tcg_debug_assert(ret >=3D 0 && ret < NB_MMU_MODES); - return ret; -} -#endif /* !CONFIG_USER_ONLY */ - #endif /* CPU_COMMON_H */ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 1fbdbe59ae..740f5d937f 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -67,6 +67,7 @@ #endif =20 #include "exec/cpu-ldst-common.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/abi_ptr.h" =20 #if defined(CONFIG_USER_ONLY) diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index 382a366ce3..2e33596428 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -9,6 +9,7 @@ =20 #include "qemu/osdep.h" #include "exec/cpu-all.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "semihosting/uaccess.h" =20 diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 1a4dbec567..be38016fc7 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -27,6 +27,9 @@ #include #include "mte_user_helper.h" #endif +#ifdef CONFIG_TCG +#include "accel/tcg/cpu-mmu-index.h" +#endif =20 int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index fb1d93ef1f..a1ade9079e 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a8935f487a..e000073459 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -20,6 +20,7 @@ =20 #include "qemu/host-utils.h" #include "cpu.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/translation-block.h" #include "tcg/tcg-op.h" diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 930466ca48..f8965cd155 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "accel/tcg/cpu-mmu-index.h" #include "internals.h" #include "cpu-csr.h" =20 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 27fc929bee..022c98f0c3 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "qemu/host-utils.h" #include "exec/log.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index f8587d5ac4..2d18659b99 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" =20 static unsigned int tlb_decode_size(unsigned int f) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7a6af183ae..da033bffff 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "qemu/log.h" diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 5716120117..57fbf16ad2 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "qemu/module.h" #include "qemu/qemu-print.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/translation-block.h" #include "hw/qdev-properties.h" diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 3821cd91ec..78cb24a8e2 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "qemu/qemu-print.h" #include "trace.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index a64412e6bd..b1ee126112 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -20,6 +20,7 @@ #include "hw/registerfields.h" #include "cpu.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 63be741a42..40b02f0a2c 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -33,6 +33,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/cputlb.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/page-protection.h" =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350117; x=1745954917; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I5ZBESgZTecJR5yHsh6hj9Vd3EM7w2X/AFWoGjqfiC8=; b=GRjQRfEqCbAP2K3U3YuuaCbaNxiSwqOfnfByNGKgJBYR7XeF5I+dyfpcjQKo0pgA8Q eEiRxZuc6Y7SjNBhHyTA7GBEVLUiIIhAE780bQ6zIOoIXW2J8L8TzpHPV7mCE/TWS+wN sWH4/25B472ySBkNoVg9mQ2vvkEu7BPxL+G7QZ7Ig38zjkuGjvoNuS1yZOEucrvDbMPn pZQOmsVpwuH7CR4CmLH3N6rAprVTfx/MhR1R05hEfIP7pfWehN3SXlQW2kc6Duh5AZ/y wGQ+RQ33teBaYYYJN5sHlL+/jT1W9ttniqDPXHg7Z+dKY87br0cRE6GZg6iMktaXPtwv rcbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350117; x=1745954917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I5ZBESgZTecJR5yHsh6hj9Vd3EM7w2X/AFWoGjqfiC8=; b=Ao3hGvtf4VXCuSOpjiyqO4CaBaozp10oKU9/LvEg6VDABdoIz1w+1OH4eblwFYpp2g 133BdPVqEAohvlfBGTl1ttG+ZRbKnZ7HvDZzG1Exd21/OnYOGLjwBA5Wc+DQUOasUhWz 8RLG0rOW9A3/xbrbYpoOTF4pH8GzFo9Hf8kITRZsy40P3ROrM+85+LtfQrhFajCHc5wq aEJDBoUc1PfSQ7hVW6O/1tQR0/6Dt0VZuDY+PWlrz9guL9RqZypyM92NKyiOgl7/7QcM tzPGf/DgZydYG1Nbedv1y9w+bpK6fXwPTtXiCxXl7XCBrmuKG08HCQjxpw2uqFVuNxjO Xq/w== X-Gm-Message-State: AOJu0YwFdmXFRDd2A3nF9E0c6m92cMOdYYUV0yL5dF+UtMdCB/3iVwfX nfY4ql0tanyuTYIvQb0OMkZXfEFH9JUY+eYK61Pr/B0yj66tmAEEUNQCGA7XKvxP4Eb/ZwWtvlV 2 X-Gm-Gg: ASbGncv2FMRCL7lL2XJ+LhxgySoUi4G04Pu6SEvIMQjGJ1AwNeyE8XH2eKUV4YtVTqX dOXdeZkIK60IjhLh6y7/VDlVmCAOpOtAzY5arbltqTPyissvF7EWv3c4smitHkb7io3OGmKBytg Jb3l8LKJbxM2OQhsMXQqwfGaBC+IKmHEhApAbL+u4+RRpydSayig38qZ6YoV8VxJ6kNsfzWQeiX kQvDi97SGMHOh1RRLY6wzmvW4qdi1DlMF34VUW1Hfcw7h5FiXOBjbpVLBAyfIbiWKBxeXgR6ura 3mPB0gtlHaf8ABazNTPSEWhr3eS7Z1Vrfs8411Vb5z5HSks4E7G+53EZIITcOll53twC9Le8fFw = X-Google-Smtp-Source: AGHT+IFhx60RJClnYMoHo7fsEk/PcivatXI3xAKYMUaVgo5Opr19xujRozgLxpX+zSr9MvDdGxcjEQ== X-Received: by 2002:a17:90b:3d50:b0:2f5:747:cbd with SMTP id 98e67ed59e1d1-3087bb69fa6mr27181478a91.18.1745350117041; Tue, 22 Apr 2025 12:28:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 025/147] include/exec: Inline *_mmuidx_ra memory operations Date: Tue, 22 Apr 2025 12:26:14 -0700 Message-ID: <20250422192819.302784-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350198445019100 Content-Type: text/plain; charset="utf-8" These need to be per-target for 'abi_ptr'. Expand inline to the *_mmu api with trivial massaging of the arguments. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 163 ++++++++++++++++++++++++++++-------- accel/tcg/ldst_common.c.inc | 118 -------------------------- 2 files changed, 129 insertions(+), 152 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 740f5d937f..8e8b9b53f7 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -119,41 +119,136 @@ void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr p= tr, void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, uintptr_t ra); =20 -uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); -int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); -int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); -uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); -int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); -uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); -uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, - int mmu_idx, uintptr_t ra); +static inline uint32_t +cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t= ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + return cpu_ldb_mmu(env, addr, oi, ra); +} =20 -void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, - int mmu_idx, uintptr_t ra); -void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, - int mmu_idx, uintptr_t ra); -void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, - int mmu_idx, uintptr_t ra); -void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, - int mmu_idx, uintptr_t ra); -void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, - int mmu_idx, uintptr_t ra); -void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val, - int mmu_idx, uintptr_t ra); -void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val, - int mmu_idx, uintptr_t ra); +static inline int +cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t= ra) +{ + return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra); +} + +static inline uint32_t +cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); + return cpu_ldw_mmu(env, addr, oi, ra); +} + +static inline int +cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra); +} + +static inline uint32_t +cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); + return cpu_ldl_mmu(env, addr, oi, ra); +} + +static inline uint64_t +cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx); + return cpu_ldq_mmu(env, addr, oi, ra); +} + +static inline uint32_t +cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); + return cpu_ldw_mmu(env, addr, oi, ra); +} + +static inline int +cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra); +} + +static inline uint32_t +cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); + return cpu_ldl_mmu(env, addr, oi, ra); +} + +static inline uint64_t +cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx); + return cpu_ldq_mmu(env, addr, oi, ra); +} + +static inline void +cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + cpu_stb_mmu(env, addr, val, oi, ra); +} + +static inline void +cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); + cpu_stw_mmu(env, addr, val, oi, ra); +} + +static inline void +cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); + cpu_stl_mmu(env, addr, val, oi, ra); +} + +static inline void +cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx); + cpu_stq_mmu(env, addr, val, oi, ra); +} + +static inline void +cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); + cpu_stw_mmu(env, addr, val, oi, ra); +} + +static inline void +cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); + cpu_stl_mmu(env, addr, val, oi, ra); +} + +static inline void +cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, + int mmu_idx, uintptr_t ra) +{ + MemOpIdx oi =3D make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx); + cpu_stq_mmu(env, addr, val, oi, ra); +} =20 #if TARGET_BIG_ENDIAN # define cpu_lduw_data cpu_lduw_be_data diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index 0447c0bb92..99a56df3fb 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -248,124 +248,6 @@ void cpu_st16_mmu(CPUArchState *env, vaddr addr, Int1= 28 val, * Wrappers of the above */ =20 -uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); - return cpu_ldb_mmu(env, addr, oi, ra); -} - -int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra); -} - -uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); - return cpu_ldw_mmu(env, addr, oi, ra); -} - -int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra); -} - -uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); - return cpu_ldl_mmu(env, addr, oi, ra); -} - -uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx); - return cpu_ldq_mmu(env, addr, oi, ra); -} - -uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); - return cpu_ldw_mmu(env, addr, oi, ra); -} - -int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra); -} - -uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); - return cpu_ldl_mmu(env, addr, oi, ra); -} - -uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx); - return cpu_ldq_mmu(env, addr, oi, ra); -} - -void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); - cpu_stb_mmu(env, addr, val, oi, ra); -} - -void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); - cpu_stw_mmu(env, addr, val, oi, ra); -} - -void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); - cpu_stl_mmu(env, addr, val, oi, ra); -} - -void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx); - cpu_stq_mmu(env, addr, val, oi, ra); -} - -void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); - cpu_stw_mmu(env, addr, val, oi, ra); -} - -void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); - cpu_stl_mmu(env, addr, val, oi, ra); -} - -void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, - int mmu_idx, uintptr_t ra) -{ - MemOpIdx oi =3D make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx); - cpu_stq_mmu(env, addr, val, oi, ra); -} - -/*--------------------------*/ - uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) { int mmu_index =3D cpu_mmu_index(env_cpu(env), false); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351859; cv=none; d=zohomail.com; s=zohoarc; b=oGg0IxB2d0XVXaV/GhhkrpwFQKk3wzFhL1BGtzGKjZcGCJQYXow5eAhnYlgznEeBvxuzpAnJg1v4LpElrmnTgdZSb87p3ULGJoEp6IMMC53v+Ii4SMlxtsMPeCVv5/3+Pv8tQrDYuHZAtziTjg5vTeQT17xb6DP2qysrGPGMwMM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351859; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350117; x=1745954917; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mBJ25CW2meY1UvcVJM9MvkFiNWSNHNlPBGliBqgnkKg=; b=xDiylsLDoFy/WzdeIg+MQ3iGS4Pntlu37xf2/u4AaoAuRHf3RzqpNU4Zaslvijht40 VUwejp6FXUR99HPmxv8+XCtXYnQ1lyTiqrYcEQftKcc9TQPUwq4ETKaIzNc6fMzezJLx nUScedAGYTutNati7zpS3efwGdT2wz3mRktAMaTcLyExzNZhHjY5x9f+8UYHyHDAUDB/ 9sKLSH2kXo8Ae+tXWRhDglV/GHc6B+AOkEZThdn1moWXFy6i6oYhnaRixwnBRh0+2CQk r0U8FLqI2U5oJXs4MzC7ngtKe4l2QcR8yOorjxbNuT5k2XTrL+APjlgWrs36jfwqKsMM agUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350117; x=1745954917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mBJ25CW2meY1UvcVJM9MvkFiNWSNHNlPBGliBqgnkKg=; b=GLoqKGMY6PBgrfmt1WNw+PECtBI4phUU3919FwzexbHFyXCRf5mp3h2QtLRIrJxcqX +jrh7UDXDGuAr8IKLcqzphSyln+0Mwe9PShx2LOmgXVGgx5JIq48Fuh31R3DBTB2IkU4 6n+XbIh0i84s4RWnoRhLl8T0929L20mZzxGy4x95fkowV6J2CXnyS09VCnlTZw8xO+EJ t3mO2bl/aTSKuayWhiH2hU56GRr/jtzbHnJx8Jzi/v2qrw9G2tuU4ZYArTTdBD+xIrTg HlqOB0DZnJkjKRoJlt3aLQRx9wrtc+cGuuN4nL6CWNBAmQpJoWBVZAQxQ4eLb9czCUST 8Xuw== X-Gm-Message-State: AOJu0Yxom99EW+Y/HnJM7u4wxslvTT6KJbNFRvzUjxGb1kEWM81tiIwY ulvmbap9hQa5A8qAWpNYJcEdfFmdxGguzffcHtVN0cBJWHi21zZ8qsPZ58wDzwRuoOtGiVf2ho6 2 X-Gm-Gg: ASbGncuTdCaDXVRbBRcREdmjm/XfcKABGxQ57SZtct/QK2m998iY+q+QTlsgQlmHIgx isTF6D5/yv82podcEno0RmVjDExq+AriOBxoCe+x2o26wLF9VHVEU1WDxugUhVZXVBpFMff3+7D tPbCSjZo9eI+UdH03BgjPKgJ2TXKIKeMWzsptlB76nWQGb5Yf58NVpg2WHKPu6v737LtHLMnobm pnAWGaH8lNQnI2FAqDRojx4rNesj4sYJ2RjYMoz1+QbD4Mmd8AFrp/xjHJOCq0Cz9ya0fyB48WE o7Sm8+sAmQ277HxzWoxZ8cULRJ/iRpJYLkUXvR+oRXI+15lGVcGse0oKWD5GZXya1V716Rsex6c = X-Google-Smtp-Source: AGHT+IFPvflrERpoZTsZ6yKf1gL79NXvd9JiSz1/poZgBkuyUCcMJedy7A3LCLtC6hMlgD01YVk/5Q== X-Received: by 2002:a17:90b:5646:b0:2f2:ab09:c256 with SMTP id 98e67ed59e1d1-3087bcc3a23mr27201413a91.33.1745350117636; Tue, 22 Apr 2025 12:28:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 026/147] include/exec: Inline *_data_ra memory operations Date: Tue, 22 Apr 2025 12:26:15 -0700 Message-ID: <20250422192819.302784-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351860282019100 Content-Type: text/plain; charset="utf-8" These need to be per-target for 'abi_ptr'. Expand inline to the *_mmuidx_ra api with a lookup of the target's cpu_mmu_index(). Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 144 +++++++++++++++++++++++++++++------- accel/tcg/ldst_common.c.inc | 108 --------------------------- 2 files changed, 118 insertions(+), 134 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 8e8b9b53f7..2eda652a38 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -85,17 +85,6 @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr); uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr); uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr); =20 -uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); -int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); -uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); -int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); -uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); -uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); -uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); -int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); -uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); -uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra); - void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); @@ -104,21 +93,6 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, ui= nt32_t val); void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val); void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val); =20 -void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t ra); -void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t ra); -void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t ra); -void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr, - uint64_t val, uintptr_t ra); -void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t ra); -void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint32_t val, uintptr_t ra); -void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr, - uint64_t val, uintptr_t ra); - static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t= ra) { @@ -250,6 +224,124 @@ cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,= uint64_t val, cpu_stq_mmu(env, addr, val, oi, ra); } =20 +/*--------------------------*/ + +static inline uint32_t +cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldub_mmuidx_ra(env, addr, mmu_index, ra); +} + +static inline int +cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int8_t)cpu_ldub_data_ra(env, addr, ra); +} + +static inline uint32_t +cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_lduw_be_mmuidx_ra(env, addr, mmu_index, ra); +} + +static inline int +cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int16_t)cpu_lduw_be_data_ra(env, addr, ra); +} + +static inline uint32_t +cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldl_be_mmuidx_ra(env, addr, mmu_index, ra); +} + +static inline uint64_t +cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldq_be_mmuidx_ra(env, addr, mmu_index, ra); +} + +static inline uint32_t +cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_lduw_le_mmuidx_ra(env, addr, mmu_index, ra); +} + +static inline int +cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + return (int16_t)cpu_lduw_le_data_ra(env, addr, ra); +} + +static inline uint32_t +cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldl_le_mmuidx_ra(env, addr, mmu_index, ra); +} + +static inline uint64_t +cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + return cpu_ldq_le_mmuidx_ra(env, addr, mmu_index, ra); +} + +static inline void +cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t r= a) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stb_mmuidx_ra(env, addr, val, mmu_index, ra); +} + +static inline void +cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_= t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stw_be_mmuidx_ra(env, addr, val, mmu_index, ra); +} + +static inline void +cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_= t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stl_be_mmuidx_ra(env, addr, val, mmu_index, ra); +} + +static inline void +cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_= t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stq_be_mmuidx_ra(env, addr, val, mmu_index, ra); +} + +static inline void +cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_= t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stw_le_mmuidx_ra(env, addr, val, mmu_index, ra); +} + +static inline void +cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_= t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stl_le_mmuidx_ra(env, addr, val, mmu_index, ra); +} + +static inline void +cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_= t ra) +{ + int mmu_index =3D cpu_mmu_index(env_cpu(env), false); + cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra); +} + #if TARGET_BIG_ENDIAN # define cpu_lduw_data cpu_lduw_be_data # define cpu_ldsw_data cpu_ldsw_be_data diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index 99a56df3fb..2f203290db 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -248,114 +248,6 @@ void cpu_st16_mmu(CPUArchState *env, vaddr addr, Int1= 28 val, * Wrappers of the above */ =20 -uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - return cpu_ldub_mmuidx_ra(env, addr, mmu_index, ra); -} - -int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - return (int8_t)cpu_ldub_data_ra(env, addr, ra); -} - -uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - return cpu_lduw_be_mmuidx_ra(env, addr, mmu_index, ra); -} - -int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - return (int16_t)cpu_lduw_be_data_ra(env, addr, ra); -} - -uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - return cpu_ldl_be_mmuidx_ra(env, addr, mmu_index, ra); -} - -uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - return cpu_ldq_be_mmuidx_ra(env, addr, mmu_index, ra); -} - -uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - return cpu_lduw_le_mmuidx_ra(env, addr, mmu_index, ra); -} - -int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - return (int16_t)cpu_lduw_le_data_ra(env, addr, ra); -} - -uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - return cpu_ldl_le_mmuidx_ra(env, addr, mmu_index, ra); -} - -uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - return cpu_ldq_le_mmuidx_ra(env, addr, mmu_index, ra); -} - -void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - cpu_stb_mmuidx_ra(env, addr, val, mmu_index, ra); -} - -void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - cpu_stw_be_mmuidx_ra(env, addr, val, mmu_index, ra); -} - -void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - cpu_stl_be_mmuidx_ra(env, addr, val, mmu_index, ra); -} - -void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, - uint64_t val, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - cpu_stq_be_mmuidx_ra(env, addr, val, mmu_index, ra); -} - -void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - cpu_stw_le_mmuidx_ra(env, addr, val, mmu_index, ra); -} - -void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, - uint32_t val, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - cpu_stl_le_mmuidx_ra(env, addr, val, mmu_index, ra); -} - -void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, - uint64_t val, uintptr_t ra) -{ - int mmu_index =3D cpu_mmu_index(env_cpu(env), false); - cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra); -} - -/*--------------------------*/ - uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr addr) { return cpu_ldub_data_ra(env, addr, 0); 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350118; x=1745954918; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kj/uYgShChkHdccTvFGCpCr1FhgqEsUyeN3aymTPxRo=; b=al0lt5ofSHZwHp9fNK7ZoOIwK5I2eDFcGYEW//WNb+1BVW5NeJ9/lqXyjlMpQCJHQC CxGzxEENfUgcAgyxoWe+Rcro8R3ycC4vCiVXm5IN9mYBNPjvaAaNXWVGDXGYDToko14z PHC+kc36NIbL/5JF4CcFQjwAdQanYre5Atz4pkFINLkQbIDVdJSo93JQwcoeVaHJs9DO VSwzrtG2ZH0frUCqcZL6WLSfMmfaVBiAzm37ZaHG7QizR1yuE5VjkiqC3c3FXIDsiVdu rngIE9tpNypwlkTdPvWVJQMBic0YZmu6Eu/X8PO22o4CiNEWvwzABKlSlIQThZfrwv44 ATWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350118; x=1745954918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kj/uYgShChkHdccTvFGCpCr1FhgqEsUyeN3aymTPxRo=; b=t9iBj0XjC/6M9ldos+VYIVkZ992IOyu/hwH1UN4kpHp9SSk7Cb976PV2aTb6I8d5Co gNuYVX6xWe4zn+KsYcM9OnNHuHM37HMA6us5HtfwUJLjYpYXdpn899Rvu9/OwVfryZef SBACT7UsGQ3vCbAX75O20mikFhVBWMeLG2p+32eJNQ0aVC/2gYxkh/6U7wdoo0xEQXYh Dyf+iCEirzFQJLkmCPL6OyxTg/EocPVRhin9i/Hnt9sKpBZAvQC83waQMu7WCFwDfCXm le5yXJt6OQWHH8qUIsBZUnlh0gBD6dAaf89OvuqUkXbAtH83FOyDsGn15tPmz56sX94X N3sA== X-Gm-Message-State: AOJu0YwCoapuZ4MmrB/L429zwehKS4X9e7H8PippIC48l9GvXM4m3k3c RDqsTEAJhFLWttWXOucIpR62x3n7/Bz0jJgBBcdQUy2PnIySgHGzUxRSVMsAeRfevyDxquJ75HU q X-Gm-Gg: ASbGnctERG0RcdsIpbXO4RnfH0v8+J0SwVU7niL14G51XmgAQyVDIY71Kml1mjmuHKi wtEGOoeu6oC6fDlsAsMvg9iEoqqyLpXqsYV6t8Or1qdr+FRqQyUs03HNXGnmlZU2uiwNUwHVmhk 4JeCo9jULJptxi4cluqllo5AYJhYLrpvcggF8Qk3QRXq96OlKg5NMCzUneRJ1slO6VU8T3pNGVu 55aWB9aZ09sL28ggDr0ak9KEB4N39QqNy9K9dRfLtPfqe4sMDoEchaLrKkm+xOpIabOKge7nwFF JRGLG7r0BhgfLcB2jEL7lSen8PsWLtT8bLvwfLNM9us9wqtO1uSqBAwgtX5WjuD5M33OY3OgUSs = X-Google-Smtp-Source: AGHT+IHe+ugXSFANmzKiX4YCJRbzr3VWWVjxda0zigfHlLWfgob/U4m6gLw3H7x+cYNKmAzBoSwgjA== X-Received: by 2002:a17:90b:51c2:b0:2ee:edae:75e with SMTP id 98e67ed59e1d1-3087bb53218mr25611166a91.13.1745350118256; Tue, 22 Apr 2025 12:28:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 027/147] include/exec: Inline *_data memory operations Date: Tue, 22 Apr 2025 12:26:16 -0700 Message-ID: <20250422192819.302784-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350465058019100 Content-Type: text/plain; charset="utf-8" These need to be per-target for 'abi_ptr'. Expand inline to the *_data_ra api with ra =3D=3D 0. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 123 ++++++++++++++++++++++++++++++------ accel/tcg/ldst_common.c.inc | 89 -------------------------- 2 files changed, 104 insertions(+), 108 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 2eda652a38..0054508eda 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -74,25 +74,6 @@ #include "user/guest-host.h" #endif /* CONFIG_USER_ONLY */ =20 -uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); -int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr); -uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr); -int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr); -uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr); -uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr); -uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr); -int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr); -uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr); -uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr); - -void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val); -void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); -void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val); -void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val); -void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val); -void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val); -void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val); - static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t= ra) { @@ -342,6 +323,110 @@ cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, u= int64_t val, uintptr_t ra) cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra); } =20 +/*--------------------------*/ + +static inline uint32_t +cpu_ldub_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldub_data_ra(env, addr, 0); +} + +static inline int +cpu_ldsb_data(CPUArchState *env, abi_ptr addr) +{ + return (int8_t)cpu_ldub_data(env, addr); +} + +static inline uint32_t +cpu_lduw_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_lduw_be_data_ra(env, addr, 0); +} + +static inline int +cpu_ldsw_be_data(CPUArchState *env, abi_ptr addr) +{ + return (int16_t)cpu_lduw_be_data(env, addr); +} + +static inline uint32_t +cpu_ldl_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldl_be_data_ra(env, addr, 0); +} + +static inline uint64_t +cpu_ldq_be_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldq_be_data_ra(env, addr, 0); +} + +static inline uint32_t +cpu_lduw_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_lduw_le_data_ra(env, addr, 0); +} + +static inline int +cpu_ldsw_le_data(CPUArchState *env, abi_ptr addr) +{ + return (int16_t)cpu_lduw_le_data(env, addr); +} + +static inline uint32_t +cpu_ldl_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldl_le_data_ra(env, addr, 0); +} + +static inline uint64_t +cpu_ldq_le_data(CPUArchState *env, abi_ptr addr) +{ + return cpu_ldq_le_data_ra(env, addr, 0); +} + +static inline void +cpu_stb_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stb_data_ra(env, addr, val, 0); +} + +static inline void +cpu_stw_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stw_be_data_ra(env, addr, val, 0); +} + +static inline void +cpu_stl_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stl_be_data_ra(env, addr, val, 0); +} + +static inline void +cpu_stq_be_data(CPUArchState *env, abi_ptr addr, uint64_t val) +{ + cpu_stq_be_data_ra(env, addr, val, 0); +} + +static inline void +cpu_stw_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stw_le_data_ra(env, addr, val, 0); +} + +static inline void +cpu_stl_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) +{ + cpu_stl_le_data_ra(env, addr, val, 0); +} + +static inline void +cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val) +{ + cpu_stq_le_data_ra(env, addr, val, 0); +} + #if TARGET_BIG_ENDIAN # define cpu_lduw_data cpu_lduw_be_data # define cpu_ldsw_data cpu_ldsw_be_data diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index 2f203290db..9791a4e9ef 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -243,92 +243,3 @@ void cpu_st16_mmu(CPUArchState *env, vaddr addr, Int12= 8 val, do_st16_mmu(env_cpu(env), addr, val, oi, retaddr); plugin_store_cb(env, addr, int128_getlo(val), int128_gethi(val), oi); } - -/* - * Wrappers of the above - */ - -uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr addr) -{ - return cpu_ldub_data_ra(env, addr, 0); -} - -int cpu_ldsb_data(CPUArchState *env, abi_ptr addr) -{ - return (int8_t)cpu_ldub_data(env, addr); -} - -uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr addr) -{ - return cpu_lduw_be_data_ra(env, addr, 0); -} - -int cpu_ldsw_be_data(CPUArchState *env, abi_ptr addr) -{ - return (int16_t)cpu_lduw_be_data(env, addr); -} - -uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr addr) -{ - return cpu_ldl_be_data_ra(env, addr, 0); -} - -uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr addr) -{ - return cpu_ldq_be_data_ra(env, addr, 0); -} - -uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr addr) -{ - return cpu_lduw_le_data_ra(env, addr, 0); -} - -int cpu_ldsw_le_data(CPUArchState *env, abi_ptr addr) -{ - return (int16_t)cpu_lduw_le_data(env, addr); -} - -uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr addr) -{ - return cpu_ldl_le_data_ra(env, addr, 0); -} - -uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr addr) -{ - return cpu_ldq_le_data_ra(env, addr, 0); -} - -void cpu_stb_data(CPUArchState *env, abi_ptr addr, uint32_t val) -{ - cpu_stb_data_ra(env, addr, val, 0); -} - -void cpu_stw_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) -{ - cpu_stw_be_data_ra(env, addr, val, 0); -} - -void cpu_stl_be_data(CPUArchState *env, abi_ptr addr, uint32_t val) -{ - cpu_stl_be_data_ra(env, addr, val, 0); -} - -void cpu_stq_be_data(CPUArchState *env, abi_ptr addr, uint64_t val) -{ - cpu_stq_be_data_ra(env, addr, val, 0); -} - -void cpu_stw_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) -{ - cpu_stw_le_data_ra(env, addr, val, 0); -} - -void cpu_stl_le_data(CPUArchState *env, abi_ptr addr, uint32_t val) -{ - cpu_stl_le_data_ra(env, addr, val, 0); -} - -void cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val) -{ - cpu_stq_le_data_ra(env, addr, val, 0); -} --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350119; x=1745954919; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+VfuDyBOkc/7EHQm2vvPTUefKvEeqjpVe/tI2ANIcRc=; b=F39T21ZBjwq3sLIacHgZBQlA0Bap6WYoKwIHGv2BcHhgcDi3tyh9n3GKsBToCYBPr0 zehhf86jeW4I2DVRUR4WonB8WZfVsZUXqt6vH7iNevVAoCyWsDxMdSDinrwLLZlLC596 dcxjRGwee6AmCiqmpqLHSi8kZaYwiR96+RTbo/KuL3sPaTNZTD1OBEnS5N78h8GRMaxV wJO64ICkaCmMnhC5Z96UQJR/TN0NqhByMibWugcxbRJZvj9DXzmGqN3LlobyzpntVmRZ HH4Q66HXxyWyCljr5X/4cpE8NcghsDZP0GO/OO4fkWutbbxgGNbM/9jjxphrH1x+Fbim /9XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350119; x=1745954919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+VfuDyBOkc/7EHQm2vvPTUefKvEeqjpVe/tI2ANIcRc=; b=GsBr74SR0ti0vFXBpuELYRuTziuvyL95gOE5nJRiiuFsIUtdA1beFn5GtzdJNHIfn0 6pXu20r+z/4+C+hRkRburszft0TBftdzrUrzBsRdptAb2OSrgF9wOxQJL0338j2WvjDg +T9FYYRhT0i6BET1wp4hpegvquysvT0bwlUtgjAULitE8ipQjxPi6am+jnHMIvV+AmNE qS1vGaB33vXKNP4mP9hp8Di4mw1FyKK4xsx98lqpyCXzhx2ABg8yTcQrjVUSNuc6rqGp pUY6btGigsb0XMxURDzdvAGqBVU3i4nx//Onn4PpSAvRj2zgoaSIlK+Gx9qtoZlni8fB BWmg== X-Gm-Message-State: AOJu0YxV8Z06nLWBH06Z3Wvee53ITaKwh6iDmaRVvf4SK/BMdFi6ncyD qz+kUWtMPznzxiMwk5llGhhQMxbMn6qhSSuQxafFzBUz869ssgLJPOtN9o7XY+RwOc7tjSJ6jLG C X-Gm-Gg: ASbGncvgOYzoXYz6xOo+pveQGZ/xu1McR2JkvKe66875BhlvAQlYchcDdbNKqpmupBD SU83DYOQHzu3dAaomDnHGxRfUN4HxOdxd+pDQvDv07W/wJ8trEZCFeSsfpHfvgzO/5BKS+iHUJh nP1+hHeIOWP0nIxa/vof039JIs6As6gW1D67ZTB/Ck6K/xTitgT0iy2AEqYOqedLOHEobLRXMKY P1mowzRXTHORNM2HwEPCLsmlsMFEpLSlt0Wf7pBRivyvFYnZhlK2RetXom/5XVhSz2U6sId+Ft9 3O7GZLEvjTONj1zzCtnHg394RFWfLfk2dG8MzT0+q3tui3PXV10Bm0VHTm0m9koSnb0iZR57iMf vFTEtp6J4KA== X-Google-Smtp-Source: AGHT+IGyF414h3eDTtB1RQqm5DXsEGEL56AEmDbopIY/qfgbn4zYr1TuBD6N0qtphY47j9qabsndgg== X-Received: by 2002:a17:902:db0f:b0:215:7421:262 with SMTP id d9443c01a7336-22c5357f020mr267068115ad.12.1745350118868; Tue, 22 Apr 2025 12:28:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 028/147] include/exec: Inline *_code memory operations Date: Tue, 22 Apr 2025 12:26:17 -0700 Message-ID: <20250422192819.302784-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350214572019100 Content-Type: text/plain; charset="utf-8" These need to be per-target for 'abi_ptr' and endianness. These expand inline to the *_mmu api with a lookup of the target's cpu_mmu_index() and ra =3D=3D 0. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 31 +++++++++++++++++++++++++++---- accel/tcg/cputlb.c | 28 ---------------------------- accel/tcg/user-exec.c | 40 ---------------------------------------- 3 files changed, 27 insertions(+), 72 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 0054508eda..77dc5ac61c 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -473,10 +473,33 @@ cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint= 64_t val) # define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra #endif =20 -uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr); -uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr); -uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr); -uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr); +static inline uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) +{ + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(cs, true)); + return cpu_ldb_code_mmu(env, addr, oi, 0); +} + +static inline uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) +{ + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(cs, true)); + return cpu_ldw_code_mmu(env, addr, oi, 0); +} + +static inline uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) +{ + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(cs, true)); + return cpu_ldl_code_mmu(env, addr, oi, 0); +} + +static inline uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) +{ + CPUState *cs =3D env_cpu(env); + MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true)); + return cpu_ldq_code_mmu(env, addr, oi, 0); +} =20 /** * tlb_vaddr_to_host: diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b03998f926..2817c9dbdd 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2897,34 +2897,6 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, I= nt128 val, =20 /* Code access functions. */ =20 -uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) -{ - CPUState *cs =3D env_cpu(env); - MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(cs, true)); - return do_ld1_mmu(cs, addr, oi, 0, MMU_INST_FETCH); -} - -uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) -{ - CPUState *cs =3D env_cpu(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(cs, true)); - return do_ld2_mmu(cs, addr, oi, 0, MMU_INST_FETCH); -} - -uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) -{ - CPUState *cs =3D env_cpu(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(cs, true)); - return do_ld4_mmu(cs, addr, oi, 0, MMU_INST_FETCH); -} - -uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) -{ - CPUState *cs =3D env_cpu(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true)); - return do_ld8_mmu(cs, addr, oi, 0, MMU_INST_FETCH); -} - uint8_t cpu_ldb_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t retaddr) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index dec17435c5..ebc7c3ecf5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1214,46 +1214,6 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, I= nt128 val, clear_helper_retaddr(); } =20 -uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) -{ - uint32_t ret; - - set_helper_retaddr(1); - ret =3D ldub_p(g2h_untagged(ptr)); - clear_helper_retaddr(); - return ret; -} - -uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr) -{ - uint32_t ret; - - set_helper_retaddr(1); - ret =3D lduw_p(g2h_untagged(ptr)); - clear_helper_retaddr(); - return ret; -} - -uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr) -{ - uint32_t ret; - - set_helper_retaddr(1); - ret =3D ldl_p(g2h_untagged(ptr)); - clear_helper_retaddr(); - return ret; -} - -uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) -{ - uint64_t ret; - - set_helper_retaddr(1); - ret =3D ldq_p(g2h_untagged(ptr)); - clear_helper_retaddr(); - return ret; -} - uint8_t cpu_ldb_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350120; x=1745954920; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oR/Buc0tAK+dwpT4/jUuGVtANFEG+DcYq0rCH3hrxCg=; b=rc1yAO/FT/sL39Ru2U3JutPt3ep7xC3LeJZRwW/p+FsdigYfLsw+RMH4jQnctPuxTv IZiGIYe2yt1MtoAIoFWUIyAzZEmA+ItwwxaTiletgoCq2WeojkWTvxaRzvXCTlUqM64B beS/FEaclyuZeFGqlMcMBomNWd7HrJBP7NUylYe/7GJ/yL1cHCoonnvPs41c0y8RXQoj 8dfPDHf6diue0HA1hXE4xLGmWcCYj/HFqgAtfhXE1fPDYOq5QWY5WwouLYIEb12O0B1J uPv6hiu6B4LXWVR1m8Oi4IeffmbLuHkzVjir9mu4in5cXcrTJkrR9ruh4kyxpk1sfAX6 BwNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350120; x=1745954920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oR/Buc0tAK+dwpT4/jUuGVtANFEG+DcYq0rCH3hrxCg=; b=W8IY3uLOlafhi1fWssu0Ln/u5H2j1jouh4txPyhjOQQp4Bh7Rkkwjgz5if65KVtilM kT0bT7RRrVpQXwQIhX1jx6HH9M3jmkDndQNIuv6Qi0TH0TwO5pjoI2XhMS3Q3pkmP8ZL liWeDJQUbUQ9qR5kD6mP6uMCyT+T0OJl9IokRd4Pds7mMmhjuU02KAqQWJPw8rW5dDeo oXxjj9nP8W1v49I24sTXfrUK+HvkYJf1mwT7UBxAHTpGhOspq9+adHRLPDhU4cPpAexH IIVY1lc2lSzlpg2zQ43F08bnqOdFqBORV1HoIcCOTQx/VnlVKovOcyG56aDHdkJ7wwcz VVGw== X-Gm-Message-State: AOJu0YwK7z01iUXXxGPkn1L1Jrix8EbnFCwmLM02esr9scNyVru49wX1 hkD4SGuu7nOTWh+6Mn0nIlhrsTOEkJV1JrH2KF3ujYY2npwKoynzNlHjweVQ/y9g0P1opMYUiUO g X-Gm-Gg: ASbGncu3nm/YOU4PeUHFbySXTgHYoeNNIKFJg7NDowAid8UWMmrlQhWi3WHazAFLUFx jYjjdd2/KViwjDIwe0L0h1pTwH5cJeRgPHuwOBLP/UOoRiKM18JZdAatreJ1dnnXj6GvLpdRXLh ara8Y5z4gnk6heBZNNV+TAsPRp0/UHB/DPBcDvL5ckstxh/drJhP6MBC65+J3Y1LlUCFe88l9qz VR4cnb8OCgZp/EJygM+xNiUIdtiuuhwY17Sv9nzM3G4zMuzRyH3Svq1Rkr1xfkHfBSutnpIeNX/ 6p4dYy619HfGmqqeaV4b3hv5sUk2zAkjWuukJk49iELUApXdMOBamjivOGbzTfanYgx1oMh2U9E = X-Google-Smtp-Source: AGHT+IEZrCzU6UJBCk/bM/WFbETYZWgd52yv1ydrjphKnTWBTQVI0h8AUgZx3MkJElGl87elnOB+4w== X-Received: by 2002:a17:90b:1f90:b0:2fe:b937:2a51 with SMTP id 98e67ed59e1d1-3087bccb23fmr25611431a91.33.1745350119559; Tue, 22 Apr 2025 12:28:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Alistair Francis , Pierrick Bouvier Subject: [PATCH 029/147] accel/tcg: Perform aligned atomic reads in translator_ld Date: Tue, 22 Apr 2025 12:26:18 -0700 Message-ID: <20250422192819.302784-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351297078019100 Content-Type: text/plain; charset="utf-8" Perform aligned atomic reads in translator_ld, if possible. According to https://lore.kernel.org/qemu-devel/20240607101403.1109-1-jim.shu@sifive.com/ this is required for RISC-V Ziccif. Reviewed-by: Alistair Francis Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/translator.c | 42 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index ef1538b4fc..157be33bf6 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -265,12 +265,14 @@ static bool translator_ld(CPUArchState *env, DisasCon= textBase *db, =20 if (likely(((base ^ last) & TARGET_PAGE_MASK) =3D=3D 0)) { /* Entire read is from the first page. */ - memcpy(dest, host + (pc - base), len); - return true; + goto do_read; } =20 if (unlikely(((base ^ pc) & TARGET_PAGE_MASK) =3D=3D 0)) { - /* Read begins on the first page and extends to the second. */ + /* + * Read begins on the first page and extends to the second. + * The unaligned read is never atomic. + */ size_t len0 =3D -(pc | TARGET_PAGE_MASK); memcpy(dest, host + (pc - base), len0); pc +=3D len0; @@ -329,7 +331,39 @@ static bool translator_ld(CPUArchState *env, DisasCont= extBase *db, host =3D db->host_addr[1]; } =20 - memcpy(dest, host + (pc - base), len); + do_read: + /* + * Assume aligned reads should be atomic, if possible. + * We're not in a position to jump out with EXCP_ATOMIC. + */ + host +=3D pc - base; + switch (len) { + case 2: + if (QEMU_IS_ALIGNED(pc, 2)) { + uint16_t t =3D qatomic_read((uint16_t *)host); + stw_he_p(dest, t); + return true; + } + break; + case 4: + if (QEMU_IS_ALIGNED(pc, 4)) { + uint32_t t =3D qatomic_read((uint32_t *)host); + stl_he_p(dest, t); + return true; + } + break; +#ifdef CONFIG_ATOMIC64 + case 8: + if (QEMU_IS_ALIGNED(pc, 8)) { + uint64_t t =3D qatomic_read__nocheck((uint64_t *)host); + stq_he_p(dest, t); + return true; + } + break; +#endif + } + /* Unaligned or partial read from the second page is not atomic. */ + memcpy(dest, host, len); return true; } =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350510; cv=none; d=zohomail.com; s=zohoarc; b=Y9XcUnGknLZouQByTMb49ObiSt4zwTihAlnp0rSPn7HnN9+ZKLD2snVXBphg+LsmJOrwYuw+swI5xmpzG9cYg46onum1KyLSZRrX527L2ff7csXjypcR3UgIk+E6ZSF8gHL9z5GjniyS+4upHw+Zve7ZeKb2p7Wsxm6/8TYFJ1Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350510; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=T2VFGDCYeUXugtnoDK4L20D4ZqSx0NDgVw90btmYdaY=; b=HV+rBJDd8qSMIT54WvHNGcfFTdNmo2EN5A0AvP3tszApOcGqGfTEo3/fiN6Ak84iZWO59bOj+ZUjS8Rw4gYhMAWHNich2nFoetXNqUAfSIuUXS7GnKzLbOLyP7uwOuDokCJqiHZ7UoNbOW6kR/YSTSMR+qp6pYHtTYR/aQCL6U0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350510462946.5236653765418; Tue, 22 Apr 2025 12:35:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIl-0002ej-Qe; Tue, 22 Apr 2025 15:29:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIW-0002WF-Ft for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:48 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIR-0006DN-7Z for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:48 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-301918a4e3bso6027180a91.3 for ; Tue, 22 Apr 2025 12:28:41 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350120; x=1745954920; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=T2VFGDCYeUXugtnoDK4L20D4ZqSx0NDgVw90btmYdaY=; b=pby+hWVGwqgGvYhgcSJTfj0nM9rubtdYkQaVbqSzbDksXBilVbkhMMbYZ/896IyXNU hekn9cMbnG/DV3oGOmcdJkfrgogSITy123hkeGTIY/6sSoQ0dxj4YI0+YC6QKDB77LFR +3ZjORhLsgfjG+uewyrmvCXRZdV1UnQ4JXuulzP2KN1sUTJvHvHxuX4394F8J81V5X6q w074VuOQoAgmzXtNTUWPCGmDewMbGz87xdBJja6gRfVfq/S5HoF/OZUyonixzKUVeiO7 n47tFWcQ1vYXfkQvR928m37iIYOxwZQ4cW4CT22mmsDTuoRhx8g402/ZF1akgFV5H2QG xHXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350120; x=1745954920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T2VFGDCYeUXugtnoDK4L20D4ZqSx0NDgVw90btmYdaY=; b=I+1U3omkg0R+lR5dmayp3xvHw3mWQnYTSWqKLdMzUFvNikwC0Id3/F4fE/9QnOkDdi HA/CDOdjBuOz5Ccg031VCjRr1SQFhxq4Cho8xHrKyEjYgGdqLDhQ/rdVa0ATxxLC0y9P yrlsjJkExnYGQ3pn1ovDJOLbBmUgyH3Z3nORyCK6blaHr5SC9B4n/UozVMOBqTSbpkBx ENS/T6FWi59PD4izUu+SZgZMI2WidAnJ18kq2TWkYJtA+BfrsxgqIa6d/A7YQADJ87TX bM6dd9qHOIgGYCN5dZVWQfKiFOEdoc0yB6iXxZij9Tdp1aCMgUK/Me7DEzh1QlFIYg2+ S94w== X-Gm-Message-State: AOJu0YwcZcZIj1P94HoT+wyxke6B8ve8dg82Dr+DZXg5xI0F5xP17Xio dM/ScYF7mUpstRBA3m3UVAeUn9Pxyob8fvPSSoA9rhCI1l4dogR1/769gfTvC8hh2Yu58TX903Y m X-Gm-Gg: ASbGncvzGII6eI+/FEvK1Ly/hIG1irFgaI8ksF6JoYSiXuXw9hiOQR3ju6PB1N+njxt eDj0Y+szmi5k88W6OF/JOlQR7NhpiYS02UUs4xeD1k+RQajwuMHlWk4NQq76MbB/2xLr0F7zAj2 i9QEbbWWMyUUJ8eb9a1HEafpl43e4wUH9RUUfsfmQ1Xtm74qHgnz2jkoHJsx4PpY2v4yVkP35MQ rLr4lBNe3ozse8c44i8xLqIZtjOCMkAEJnMmBN16HxaX99q0y90ucKbc0T5Q30Af7FzFgMvJB8i RkKEiqNNqhXkm+8OKBE2S3gwksGELnEqJwd6uaH4OyttmuEWqcdzgMLZL1SfkiKSf3FMsJ1gFFo = X-Google-Smtp-Source: AGHT+IEoSN06BiUWaHKCFynQCceObz/Qa/lu/l+wrQyDuVxw6u9nHyH5eMU/ZRjVeF2ODOwMhaesFw== X-Received: by 2002:a17:90a:d888:b0:2fa:137f:5c61 with SMTP id 98e67ed59e1d1-3087bb53ee8mr28737474a91.12.1745350120323; Tue, 22 Apr 2025 12:28:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 030/147] accel/tcg: Use cpu_ld*_code_mmu in translator.c Date: Tue, 22 Apr 2025 12:26:19 -0700 Message-ID: <20250422192819.302784-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350512158019000 Content-Type: text/plain; charset="utf-8" Cache the mmu index in DisasContextBase. Perform the read on host endianness, which lets us share code with the translator_ld fast path. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/exec/translator.h | 1 + accel/tcg/translator.c | 58 ++++++++++++++++++--------------------- 2 files changed, 28 insertions(+), 31 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index d70942a10f..205dd85bba 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -73,6 +73,7 @@ struct DisasContextBase { int max_insns; bool plugin_enabled; bool fake_insn; + uint8_t code_mmuidx; struct TCGOp *insn_start; void *host_addr[2]; =20 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 157be33bf6..4c320ab9c3 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -11,10 +11,10 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "exec/exec-all.h" +#include "exec/cpu-ldst-common.h" +#include "accel/tcg/cpu-mmu-index.h" #include "exec/translator.h" -#include "exec/cpu_ldst.h" #include "exec/plugin-gen.h" -#include "exec/cpu_ldst.h" #include "exec/tswap.h" #include "tcg/tcg-op-common.h" #include "internal-target.h" @@ -142,6 +142,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, db->host_addr[1] =3D NULL; db->record_start =3D 0; db->record_len =3D 0; + db->code_mmuidx =3D cpu_mmu_index(cpu, true); =20 ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ @@ -457,55 +458,50 @@ bool translator_st(const DisasContextBase *db, void *= dest, =20 uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, vaddr pc) { - uint8_t raw; + uint8_t val; =20 - if (!translator_ld(env, db, &raw, pc, sizeof(raw))) { - raw =3D cpu_ldub_code(env, pc); - record_save(db, pc, &raw, sizeof(raw)); + if (!translator_ld(env, db, &val, pc, sizeof(val))) { + MemOpIdx oi =3D make_memop_idx(MO_UB, db->code_mmuidx); + val =3D cpu_ldb_code_mmu(env, pc, oi, 0); + record_save(db, pc, &val, sizeof(val)); } - return raw; + return val; } =20 uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc) { - uint16_t raw, tgt; + uint16_t val; =20 - if (translator_ld(env, db, &raw, pc, sizeof(raw))) { - tgt =3D tswap16(raw); - } else { - tgt =3D cpu_lduw_code(env, pc); - raw =3D tswap16(tgt); - record_save(db, pc, &raw, sizeof(raw)); + if (!translator_ld(env, db, &val, pc, sizeof(val))) { + MemOpIdx oi =3D make_memop_idx(MO_UW, db->code_mmuidx); + val =3D cpu_ldw_code_mmu(env, pc, oi, 0); + record_save(db, pc, &val, sizeof(val)); } - return tgt; + return tswap16(val); } =20 uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc) { - uint32_t raw, tgt; + uint32_t val; =20 - if (translator_ld(env, db, &raw, pc, sizeof(raw))) { - tgt =3D tswap32(raw); - } else { - tgt =3D cpu_ldl_code(env, pc); - raw =3D tswap32(tgt); - record_save(db, pc, &raw, sizeof(raw)); + if (!translator_ld(env, db, &val, pc, sizeof(val))) { + MemOpIdx oi =3D make_memop_idx(MO_UL, db->code_mmuidx); + val =3D cpu_ldl_code_mmu(env, pc, oi, 0); + record_save(db, pc, &val, sizeof(val)); } - return tgt; + return tswap32(val); } =20 uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc) { - uint64_t raw, tgt; + uint64_t val; =20 - if (translator_ld(env, db, &raw, pc, sizeof(raw))) { - tgt =3D tswap64(raw); - } else { - tgt =3D cpu_ldq_code(env, pc); - raw =3D tswap64(tgt); - record_save(db, pc, &raw, sizeof(raw)); + if (!translator_ld(env, db, &val, pc, sizeof(val))) { + MemOpIdx oi =3D make_memop_idx(MO_UQ, db->code_mmuidx); + val =3D cpu_ldq_code_mmu(env, pc, oi, 0); + record_save(db, pc, &val, sizeof(val)); } - return tgt; + return tswap64(val); } =20 void translator_fake_ld(DisasContextBase *db, const void *data, size_t len) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350316; cv=none; d=zohomail.com; s=zohoarc; b=d2s21qJwO6+tCLHZA3ix88Wd/5XMzznua+7S2V4BCtMVkIlRDj1dT6CmHBPe4HmsvvFqcU4aglOH6ZwVLYKui+1Ur8R6X4xGWiHpGuE8fnpmDsxcfyH6cWj3WHAhkijqIxzdApRg1UIrB0FNbNUSWcDQYIGSOzP9LECDE+NZT1k= ARC-Message-Signature: i=1; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350121; x=1745954921; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6RZv4stV/SvG8IKjkEcJ2d9gwvNpfIIefKf42fhrHvc=; b=FpeiSF9Ij8bCgDyiHyQNeUdRY2pEORXgaEc+rNLNnkrxv7ZJqQgrrn5cr+JKjAtYsP 4MevcwMoPhvNVMiSeaH46w+XxwoOvQCMUbEUneh3AxG2qUYwZBjF8XKCibN4viqi10zH 24npOtMT1voxpngwaHadyKvFZ1lxI31p3f61XH0XzGTi5/Lahwp2YFtWBZVz9f9PEvRt 7JNM/m0nHiKMkelV/7V+CnWCUlg9v7CXLm2tGz1C0jzQ7kDi05EzUPHMU5ZKagMfJtQv Z34gVxRCmONmZ3e8fVKBnQKreIwfuxMB8/afYFUQbpIO32V3uXpivG8PHsMnTBXr6gj5 suoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350121; x=1745954921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6RZv4stV/SvG8IKjkEcJ2d9gwvNpfIIefKf42fhrHvc=; b=D0lU1x6nxosrWdbHbBn+ZujurTNIoqBqZfUbEcyp+nat2tNFEwEGXXGG0lVihbEIci LTPFavxz0neLIy8cdVz8J/uo1W/jcCRAW2Ippzmz9+7bz039XL2IaJurU+tpI0BxzE+v tNLl5T5ZuKSQZb+mznfIGqSnj/4oKHBXA0BA7iUj9D+awn+pTqQTIWmnD5bj9YMmGGJ/ dENJDko6IbA4WaBy4cZiiMYG3YB0PR2AbpdwP3NVPoi38mYEEp6Yyy+1RhL10UGKnUcZ umCV7Bj5bXPkm/u7yYHWFM65hKYZLV65xJgJUyOsGZGPSdC/pOHJYiQKDjdqbOGdNK3U dfIg== X-Gm-Message-State: AOJu0YyJjYBA+bVaABPAuz30mE/VA2N+baG41VWzDjf2dtWSSBHU+vGz GBCX1bJ2NYlYlWW/pV6kAhzC6Fw9Y0az5k5lGUl8gLk5udo2dqaM0/BUlYE6PvSLyanEcAzvHjG 6 X-Gm-Gg: ASbGnctNx+Ti/dgwARmluGdY60GZw8btbHuI3g0NtdVDEMGTqmc7s7Z4JKQOTBnAA7I oJ3EhYs02F5tGYV/8yfBYzAHQwiUktK/OGTZJl+fLhiRn2sVOyHqcLyifLAP45bkPAtH6MsCBRF Lts81hH/WD4K1rztnukOtlHHHTyCweuniSFG/XnDIIj+U/HjCfbPuSMSvXpsPAFX/uz2o0wITz7 AqVn7a2vHPMCVsDR6qNr458AVD2xOI8POYoHmhadXr5iAzGPjXPNbD5J4lMjn31pzazL3fFnt1+ J4uUakLYqXTUOtHVCof/36ZqThByV02QT2DzKeqQcLnweorKmvXldwssZPzlqnYA/miM45bl/D8 = X-Google-Smtp-Source: AGHT+IEWk7L3ccoCC5sgJ9kxTNjMsWtg9MSvxa0w0caogTbuZI4rSRxifq2fifQPHEma9CNg3xbweg== X-Received: by 2002:a17:90b:37c3:b0:305:5f33:980f with SMTP id 98e67ed59e1d1-3087bcc3a75mr22991045a91.27.1745350120963; Tue, 22 Apr 2025 12:28:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 031/147] accel/tcg: Implement translator_ld*_end Date: Tue, 22 Apr 2025 12:26:20 -0700 Message-ID: <20250422192819.302784-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350317204019000 Content-Type: text/plain; charset="utf-8" Add a new family of translator load functions which take an absolute endianness value in the form of MO_BE/MO_LE. Expand the other translator_ld* functions on top of this. Remove exec/tswap.h from translator.c. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/translator.h | 49 ++++++++++++++++++++++++--------------- accel/tcg/translator.c | 26 +++++++++++++++------ 2 files changed, 49 insertions(+), 26 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 205dd85bba..3c32655569 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -18,7 +18,7 @@ * member in your target-specific DisasContext. */ =20 -#include "qemu/bswap.h" +#include "exec/memop.h" #include "exec/vaddr.h" =20 /** @@ -181,42 +181,53 @@ bool translator_io_start(DisasContextBase *db); */ =20 uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, vaddr pc); -uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc= ); -uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc); -uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc); +uint16_t translator_lduw_end(CPUArchState *env, DisasContextBase *db, + vaddr pc, MemOp endian); +uint32_t translator_ldl_end(CPUArchState *env, DisasContextBase *db, + vaddr pc, MemOp endian); +uint64_t translator_ldq_end(CPUArchState *env, DisasContextBase *db, + vaddr pc, MemOp endian); + +#ifdef COMPILING_PER_TARGET +static inline uint16_t +translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc) +{ + return translator_lduw_end(env, db, pc, MO_TE); +} + +static inline uint32_t +translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc) +{ + return translator_ldl_end(env, db, pc, MO_TE); +} + +static inline uint64_t +translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc) +{ + return translator_ldq_end(env, db, pc, MO_TE); +} =20 static inline uint16_t translator_lduw_swap(CPUArchState *env, DisasContextBase *db, vaddr pc, bool do_swap) { - uint16_t ret =3D translator_lduw(env, db, pc); - if (do_swap) { - ret =3D bswap16(ret); - } - return ret; + return translator_lduw_end(env, db, pc, MO_TE ^ (do_swap * MO_BSWAP)); } =20 static inline uint32_t translator_ldl_swap(CPUArchState *env, DisasContextBase *db, vaddr pc, bool do_swap) { - uint32_t ret =3D translator_ldl(env, db, pc); - if (do_swap) { - ret =3D bswap32(ret); - } - return ret; + return translator_ldl_end(env, db, pc, MO_TE ^ (do_swap * MO_BSWAP)); } =20 static inline uint64_t translator_ldq_swap(CPUArchState *env, DisasContextBase *db, vaddr pc, bool do_swap) { - uint64_t ret =3D translator_ldq(env, db, pc); - if (do_swap) { - ret =3D bswap64(ret); - } - return ret; + return translator_ldq_end(env, db, pc, MO_TE ^ (do_swap * MO_BSWAP)); } +#endif /* COMPILING_PER_TARGET */ =20 /** * translator_fake_ld - fake instruction load diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 4c320ab9c3..2ab081b95f 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -8,6 +8,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/bswap.h" #include "qemu/log.h" #include "qemu/error-report.h" #include "exec/exec-all.h" @@ -15,7 +16,6 @@ #include "accel/tcg/cpu-mmu-index.h" #include "exec/translator.h" #include "exec/plugin-gen.h" -#include "exec/tswap.h" #include "tcg/tcg-op-common.h" #include "internal-target.h" #include "disas/disas.h" @@ -468,7 +468,8 @@ uint8_t translator_ldub(CPUArchState *env, DisasContext= Base *db, vaddr pc) return val; } =20 -uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc) +uint16_t translator_lduw_end(CPUArchState *env, DisasContextBase *db, + vaddr pc, MemOp endian) { uint16_t val; =20 @@ -477,10 +478,14 @@ uint16_t translator_lduw(CPUArchState *env, DisasCont= extBase *db, vaddr pc) val =3D cpu_ldw_code_mmu(env, pc, oi, 0); record_save(db, pc, &val, sizeof(val)); } - return tswap16(val); + if (endian & MO_BSWAP) { + val =3D bswap16(val); + } + return val; } =20 -uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc) +uint32_t translator_ldl_end(CPUArchState *env, DisasContextBase *db, + vaddr pc, MemOp endian) { uint32_t val; =20 @@ -489,10 +494,14 @@ uint32_t translator_ldl(CPUArchState *env, DisasConte= xtBase *db, vaddr pc) val =3D cpu_ldl_code_mmu(env, pc, oi, 0); record_save(db, pc, &val, sizeof(val)); } - return tswap32(val); + if (endian & MO_BSWAP) { + val =3D bswap32(val); + } + return val; } =20 -uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc) +uint64_t translator_ldq_end(CPUArchState *env, DisasContextBase *db, + vaddr pc, MemOp endian) { uint64_t val; =20 @@ -501,7 +510,10 @@ uint64_t translator_ldq(CPUArchState *env, DisasContex= tBase *db, vaddr pc) val =3D cpu_ldq_code_mmu(env, pc, oi, 0); record_save(db, pc, &val, sizeof(val)); } - return tswap64(val); + if (endian & MO_BSWAP) { + val =3D bswap64(val); + } + return val; } =20 void translator_fake_ld(DisasContextBase *db, const void *data, size_t len) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350199; cv=none; d=zohomail.com; s=zohoarc; b=h/DMW3j+6jdXISoIALpzaj6PEdGiQSFH+gpOt5ka1kVDgY+ek9flzIwsTCsor/isgNSDxmAFJ33IuBNQ2zGARf4ivVrOf983DiALUcii6Naz2ABCS0EXe5vwpvoi5xfYFDRV4uUqwSJduRqjF9vXejKfj3D/cKTImn5/QcxVGRc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350121; x=1745954921; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EXxySmM5H2uZxfcMpHXVVabc3DpRRBx3hmcc7DOhhC4=; b=IYM484aP3CZY4OOhegmYBKTLIPdHTw3PNnhBnGg0k7NrdYaWuxP677JOCJ0PFdr6ZI c1WBWFZZoX27TwXyCV50+26fIWUu6kRPIkeMYybYqhs7lIlSzeA+i+XjETLmi9b3APno 0ZHJmSiokYUhNA2ls5sh/YCyCwlCUHW7HGlMVZKJDGeLCo4OIbApaHmwKxyHQXSTQySX Y6kK01q1ZLloGZ0k/RKrMI6i3urJqrjcVTayog2fSWDUs2hs/7GDEOdrex0EnPHtF/j3 xg9/tpSr6LycPSANtC+MJuKTha4AOb7uWraxYfjpFxNI5DHGRYJhF89KADMxP5jOXXIJ Ec/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350121; x=1745954921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EXxySmM5H2uZxfcMpHXVVabc3DpRRBx3hmcc7DOhhC4=; b=PMZQXDTd9Yl8ZvmAHvdiZuvt3yokYeMu9RQw6JKAvSrOYGtinw1o2xcocR+KqSo9dn nS87GbySA6w7GRN+aaQ6vRUU0GFWH5rehIxqkNeuuc85iK+AzxJm8F/u1xsxJttANQQc xkBzNfSpcev94TcwmHbq49TcBmWqtdbYsbnfuM5TT/4J9FVoSNq//5NPdfckCskMRaOX I4qpB4J5q/sFFcDGSVyS+0hJ7xNqyrmD54L1M886kI2Qd3abQPUYFNTD+t3HNCjy/Y12 MlC5L9uPcKTi1gfGvAduKcqfoVgdDESb1zDSUay4ZWV7BElqumkSyqteJrkHHkuKIQj9 8mDg== X-Gm-Message-State: AOJu0YwSJJhsYz/cs8Cb2NMqB9jNSjaWDYXcO8g7w0nzvajKmJ+oOXZF fw/n7s6MKGy1uiURG8G/D+HzOtBzo1DtpXS3jUFd1PEEVQ8Z4ab0LrzwaV3WQNRnNI6IjliBove N X-Gm-Gg: ASbGncvNnRoGuFeoerElxh/fQSh7CJUMa6IW5XVLAQTEuxNoraWB8j+x8JzD1YNx+fF gJglwy8c53JFlnF15tr2uYf6IcWKTQwS3lSiEGQW3bKZQlGXySNNq5KvvUla4MB0Vx/k3wSduph 5KW5fh5/qaJZflkwJ9xeTn4+urL0vjaUCRsgQgYI0kxdBEZ/hHSyj2BfpiDOLQ+bv1J20TpUHr2 G71Va/hK49UlBdZADJULp9Y4eXXAQNDaP8k1+DqHnMKC31cnY8NzqAM8eWDuEwKZPu5AzsIaXGF 7iHLSXlCfkzLxma/CchSXhvjhxmYS9jnVrIQWeGgfpA2K2AmB0aHFEyENA1oLVbPv0l/YtJhdlt KD2uHpygy7A== X-Google-Smtp-Source: AGHT+IFYJTdTUxGCbycuUuE2IW9ONJSEuAHMG7ztwLNGsjBWkU3mdiQUOMIEIqu/Tirzak6pW1CUJA== X-Received: by 2002:a17:90b:2d0d:b0:2ee:8427:4b02 with SMTP id 98e67ed59e1d1-3087bbbddc7mr23918181a91.28.1745350121583; Tue, 22 Apr 2025 12:28:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 032/147] accel/tcg: Remove mmap_lock/unlock from watchpoint.c Date: Tue, 22 Apr 2025 12:26:21 -0700 Message-ID: <20250422192819.302784-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350200518019100 The mmap_lock is user-only, whereas watchpoint.c is only compiled for system mode. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/watchpoint.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c index 65b21884ce..cfb37a49e7 100644 --- a/accel/tcg/watchpoint.c +++ b/accel/tcg/watchpoint.c @@ -124,17 +124,14 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, = vaddr len, } cpu->watchpoint_hit =3D wp; =20 - mmap_lock(); /* This call also restores vCPU state */ tb_check_watchpoint(cpu, ra); if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index =3D EXCP_DEBUG; - mmap_unlock(); cpu_loop_exit(cpu); } else { /* Force execution of one insn next time. */ cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(cpu); - mmap_unlock(); cpu_loop_exit_noexc(cpu); } } else { --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350463; cv=none; d=zohomail.com; s=zohoarc; b=nBN5InWNNnqzrorDI3GgvV46qbiLk2dPexAgcKR/M+ELW9/ZVOv/GedLxTEvIDOTFk/QLxZs+Ogeo5bbLN6UH1bSmFGWCYUxe6g6Uk3bomZJCLrETgvoO9orODNDg9S6gUUJRNX1pEXg25LVx/E2qMd/1Ox1Mz6oKoaAzSr/S04= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350463; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+Ub0hq5/yq5YmhOhnwj/NcA4w3lCN1y7A820aqoMspw=; b=cOKvceGJ0Id2jXYYo8G7C56h7U6IVZUR+xFAmbkPf7yJbLSNlsHj3NbUHJIQwrYIVQ0ZogBN0lHmOApuJ6Vsyymt6Z3YH9k/T5z2o1kMJsLIk3R6/xcTFN6j2mZqeulRMFztxRBhLLrQEkY7QftpLBDqjJ32rF1OY5rQ42XqnWw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350463257139.67658357372716; Tue, 22 Apr 2025 12:34:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JIg-0002cW-JG; Tue, 22 Apr 2025 15:28:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JIY-0002X7-8d for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:50 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JIR-0006EB-Px for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:28:49 -0400 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-3015001f862so4330994a91.3 for ; Tue, 22 Apr 2025 12:28:43 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350122; x=1745954922; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+Ub0hq5/yq5YmhOhnwj/NcA4w3lCN1y7A820aqoMspw=; b=F0/ejIix+gqutI+p1ecvyvFsxxMJoqpVAr5rVHV+ee8Dmu3mIczYksFMRnbnU8pLLl D0R+25HbQIjJ564wmqQj4L0Yti2PJ8sBF+JTNw7tUl7u7kdXx1bQFyui48dG/GjcRKk3 imrjdaqCIOZpyLJlcpi+RqHwJrByQgTkad/viYBfxT4FDvMB8IiwsaVUslZeXU/Rsm9u X1bXXimptWJ6muTUOOxcRftk6+68aFimwA4jQVBavH+N3khxmGC5MltswbBaF3rSJe2n bNPQhl912PordvHJQlkJnum80i5DzExNywaZ7mxOyBxo+cszArX34e9FPYyfnCSdJLxV 46FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350122; x=1745954922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+Ub0hq5/yq5YmhOhnwj/NcA4w3lCN1y7A820aqoMspw=; b=UjJ4nKFoAGIuxNHipe7CKhUDgQO61F43A5p7XEOk4T6Z0J1H2DTxwIQDiO1XEtrpC6 Qc6M30K7+XqjRX4jj1z7P8ujI8EAJYHXe54C0j8p9KjjiRT6aVnhte1bUD/5WGZuVXoe wQtbwVSn0sgveHKp0NCrKfeeuVpK/5MONbCXGWr42RH/xOTv3y072jYyDDaUkFR3AM83 kneKEYs+w/Rbqt/GPQlVx1AtLb/MJ1ZvSB2Eb/8ffDnhWDhh0LJXxxRRg5HPxzDAE3Hm 5yPqDgJbdEZplMAk9M8IPR6KoJJUA/Qtn8mRWQdUl5n92rspe2mdGAqRMWUDPsMGITma grvA== X-Gm-Message-State: AOJu0Yz5tsKS99FX8W098WxfTU2CwsQbulW83cCNKlA3Xec3TSAjV/QV 7y/C/eOQukXqE+NOgNC4K5rUS3zmCu6+DR1q37iA+POha+tAEl6gvks8P1UyoCxAk6b5l1ukvTy T X-Gm-Gg: ASbGncvuhfY+2vm5NoHvvZwcYa6iT9gM63emyUNeJcOajShyPWqijSeHRGo9UnVIgXl x1xt62fuv0swoklf/iCkFvkcH35Mf7XAJ3euxb2b21UuLS6gFYsZNGsVyZUBgQ59/Gl4PHsYDYF I8zdqwhfEnZkwT602A/mKO/nUqTSK22Kbe8GAQ9K5j0bXm/TN6nLuscI2gXm/m/xn/AObLt1TNF 6xs20V0tBOXgl3pxGIa/sFUteka0jieO1HSA3r3ts6BE4sYCQo7+9pTMnIzHAuHYTP+T86eXx2o vZcGJj9WWTVFddjtuccTvGtG3l2gjI9pppHdtpyZxLIZg/Q+EKiXkLhSipE28hXXL1hXmNoMihY = X-Google-Smtp-Source: AGHT+IFdl/0oxu06pG5VTBQfbSzz9TdtIe/00/xqLp0bUXlx9XI7fNHIPfzTK5t45Z+wDY9TNfF//Q== X-Received: by 2002:a17:90b:5410:b0:2fc:a3b7:108e with SMTP id 98e67ed59e1d1-3087bb3e865mr25026117a91.4.1745350122263; Tue, 22 Apr 2025 12:28:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 033/147] include/exec: Split out mmap-lock.h Date: Tue, 22 Apr 2025 12:26:22 -0700 Message-ID: <20250422192819.302784-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350465225019100 Content-Type: text/plain; charset="utf-8" Split out mmap_lock, et al from page-protection.h to a new header. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/internal-target.h | 1 + bsd-user/bsd-mem.h | 1 + include/exec/mmap-lock.h | 33 +++++++++++++++++++++++++++++++++ include/exec/page-protection.h | 22 ---------------------- accel/tcg/cpu-exec.c | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/translate-all.c | 1 + bsd-user/mmap.c | 1 + linux-user/arm/cpu_loop.c | 1 + linux-user/elfload.c | 1 + linux-user/flatload.c | 1 + linux-user/mmap.c | 1 + linux-user/syscall.c | 1 + target/arm/helper.c | 1 + 14 files changed, 45 insertions(+), 22 deletions(-) create mode 100644 include/exec/mmap-lock.h diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 2cdf11c905..c88f007ffb 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -13,6 +13,7 @@ #include "exec/translation-block.h" #include "tb-internal.h" #include "tcg-target-mo.h" +#include "exec/mmap-lock.h" =20 /* * Access to the various translations structures need to be serialised diff --git a/bsd-user/bsd-mem.h b/bsd-user/bsd-mem.h index 90ca0e3377..1be906c591 100644 --- a/bsd-user/bsd-mem.h +++ b/bsd-user/bsd-mem.h @@ -56,6 +56,7 @@ #include =20 #include "qemu-bsd.h" +#include "exec/mmap-lock.h" #include "exec/page-protection.h" #include "user/page-protection.h" =20 diff --git a/include/exec/mmap-lock.h b/include/exec/mmap-lock.h new file mode 100644 index 0000000000..50ffdab9c5 --- /dev/null +++ b/include/exec/mmap-lock.h @@ -0,0 +1,33 @@ +/* + * QEMU user-only mmap lock, with stubs for system mode + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef EXEC_MMAP_LOCK_H +#define EXEC_MMAP_LOCK_H + +#ifdef CONFIG_USER_ONLY + +void TSA_NO_TSA mmap_lock(void); +void TSA_NO_TSA mmap_unlock(void); +bool have_mmap_lock(void); + +static inline void mmap_unlock_guard(void *unused) +{ + mmap_unlock(); +} + +#define WITH_MMAP_LOCK_GUARD() \ + for (int _mmap_lock_iter __attribute__((cleanup(mmap_unlock_guard))) \ + =3D (mmap_lock(), 0); _mmap_lock_iter =3D=3D 0; _mmap_lock_iter = =3D 1) + +#else + +static inline void mmap_lock(void) {} +static inline void mmap_unlock(void) {} +#define WITH_MMAP_LOCK_GUARD() + +#endif /* CONFIG_USER_ONLY */ +#endif /* EXEC_MMAP_LOCK_H */ diff --git a/include/exec/page-protection.h b/include/exec/page-protection.h index 3e0a8a0333..c43231af8b 100644 --- a/include/exec/page-protection.h +++ b/include/exec/page-protection.h @@ -38,26 +38,4 @@ */ #define PAGE_PASSTHROUGH 0x0800 =20 -#ifdef CONFIG_USER_ONLY - -void TSA_NO_TSA mmap_lock(void); -void TSA_NO_TSA mmap_unlock(void); -bool have_mmap_lock(void); - -static inline void mmap_unlock_guard(void *unused) -{ - mmap_unlock(); -} - -#define WITH_MMAP_LOCK_GUARD() \ - for (int _mmap_lock_iter __attribute__((cleanup(mmap_unlock_guard))) \ - =3D (mmap_lock(), 0); _mmap_lock_iter =3D=3D 0; _mmap_lock_iter = =3D 1) -#else - -static inline void mmap_lock(void) {} -static inline void mmap_unlock(void) {} -#define WITH_MMAP_LOCK_GUARD() - -#endif /* !CONFIG_USER_ONLY */ - #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ef3d967e3a..372b876604 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -27,6 +27,7 @@ #include "disas/disas.h" #include "exec/cpu-common.h" #include "exec/page-protection.h" +#include "exec/mmap-lock.h" #include "exec/translation-block.h" #include "tcg/tcg.h" #include "qemu/atomic.h" diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 3f1bebf6ab..d5899ad047 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -24,6 +24,7 @@ #include "exec/log.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/mmap-lock.h" #include "exec/tb-flush.h" #include "tb-internal.h" #include "system/tcg.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 82bc16bd53..16e5043597 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -45,6 +45,7 @@ =20 #include "exec/cputlb.h" #include "exec/page-protection.h" +#include "exec/mmap-lock.h" #include "tb-internal.h" #include "exec/translator.h" #include "exec/tb-flush.h" diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c index 3f0df79c37..47e317517c 100644 --- a/bsd-user/mmap.c +++ b/bsd-user/mmap.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ #include "qemu/osdep.h" +#include "exec/mmap-lock.h" #include "exec/page-protection.h" #include "user/page-protection.h" =20 diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 7416e3216e..e8417d0406 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -25,6 +25,7 @@ #include "signal-common.h" #include "semihosting/common-semi.h" #include "exec/page-protection.h" +#include "exec/mmap-lock.h" #include "user/page-protection.h" #include "target/arm/syndrome.h" =20 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index fa83d78667..99811af5e7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -10,6 +10,7 @@ #include "user/tswap-target.h" #include "user/page-protection.h" #include "exec/page-protection.h" +#include "exec/mmap-lock.h" #include "exec/translation-block.h" #include "user/guest-base.h" #include "user-internals.h" diff --git a/linux-user/flatload.c b/linux-user/flatload.c index d5cb1830dd..4beb3ed1b9 100644 --- a/linux-user/flatload.c +++ b/linux-user/flatload.c @@ -35,6 +35,7 @@ =20 #include "qemu.h" #include "exec/page-protection.h" +#include "exec/mmap-lock.h" #include "user-internals.h" #include "loader.h" #include "user-mmap.h" diff --git a/linux-user/mmap.c b/linux-user/mmap.c index d1f36e6f16..f88a80c31e 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -21,6 +21,7 @@ #include "trace.h" #include "exec/log.h" #include "exec/page-protection.h" +#include "exec/mmap-lock.h" #include "exec/tb-flush.h" #include "exec/translation-block.h" #include "qemu.h" diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 8bfe4912e1..5826ac3adb 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -26,6 +26,7 @@ #include "tcg/startup.h" #include "target_mman.h" #include "exec/page-protection.h" +#include "exec/mmap-lock.h" #include "exec/tb-flush.h" #include "exec/translation-block.h" #include diff --git a/target/arm/helper.c b/target/arm/helper.c index bb445e30cd..0454b06a6c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -14,6 +14,7 @@ #include "cpu-features.h" #include "exec/helper-proto.h" #include "exec/page-protection.h" +#include "exec/mmap-lock.h" #include "qemu/main-loop.h" #include "qemu/timer.h" #include "qemu/bitops.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- hw/arm/strongarm.h | 2 +- hw/display/apple-gfx.h | 2 +- hw/display/framebuffer.h | 2 +- hw/display/vga_int.h | 2 +- hw/hyperv/hv-balloon-our_range_memslots.h | 2 +- hw/intc/ioapic_internal.h | 2 +- hw/net/i82596.h | 2 +- hw/net/pcnet.h | 2 +- hw/tpm/tpm_ppi.h | 2 +- hw/usb/hcd-uhci.h | 2 +- hw/vfio/pci.h | 2 +- hw/virtio/vhost-iova-tree.h | 2 +- include/exec/cpu-all.h | 5 ++++- include/exec/ioport.h | 2 +- include/exec/ram_addr.h | 2 +- include/hw/acpi/acpi.h | 2 +- include/hw/acpi/ich9_tco.h | 2 +- include/hw/arm/fsl-imx25.h | 2 +- include/hw/arm/fsl-imx31.h | 2 +- include/hw/arm/fsl-imx6.h | 2 +- include/hw/arm/fsl-imx6ul.h | 2 +- include/hw/arm/omap.h | 2 +- include/hw/arm/stm32l4x5_soc.h | 2 +- include/hw/boards.h | 2 +- include/hw/char/parallel.h | 2 +- include/hw/char/riscv_htif.h | 2 +- include/hw/char/serial-mm.h | 2 +- include/hw/char/serial.h | 2 +- include/hw/display/macfb.h | 2 +- include/hw/fsi/aspeed_apb2opb.h | 2 +- include/hw/fsi/cfam.h | 2 +- include/hw/fsi/fsi-master.h | 2 +- include/hw/fsi/fsi.h | 2 +- include/hw/fsi/lbus.h | 2 +- include/hw/gpio/npcm7xx_gpio.h | 2 +- include/hw/i2c/npcm7xx_smbus.h | 2 +- include/hw/i2c/pm_smbus.h | 2 +- include/hw/i386/apic_internal.h | 2 +- include/hw/i386/x86.h | 2 +- include/hw/ide/ahci.h | 2 +- include/hw/ipmi/ipmi.h | 2 +- include/hw/isa/apm.h | 2 +- include/hw/isa/isa.h | 2 +- include/hw/m68k/q800.h | 2 +- include/hw/mem/npcm7xx_mc.h | 2 +- include/hw/mem/pc-dimm.h | 2 +- include/hw/mips/mips.h | 2 +- include/hw/misc/auxbus.h | 2 +- include/hw/misc/ivshmem-flat.h | 2 +- include/hw/misc/mac_via.h | 2 +- include/hw/misc/npcm7xx_mft.h | 2 +- include/hw/misc/npcm_clk.h | 2 +- include/hw/misc/npcm_gcr.h | 2 +- include/hw/misc/pvpanic.h | 2 +- include/hw/net/dp8393x.h | 2 +- include/hw/net/msf2-emac.h | 2 +- include/hw/nvram/mac_nvram.h | 2 +- include/hw/nvram/npcm7xx_otp.h | 2 +- include/hw/pci-host/fsl_imx8m_phy.h | 2 +- include/hw/pci-host/pam.h | 2 +- include/hw/pci-host/remote.h | 2 +- include/hw/pci/pci.h | 2 +- include/hw/pci/pcie_host.h | 2 +- include/hw/pci/shpc.h | 2 +- include/hw/ppc/mac_dbdma.h | 2 +- include/hw/ppc/pnv_lpc.h | 2 +- include/hw/ppc/pnv_occ.h | 2 +- include/hw/ppc/pnv_sbe.h | 2 +- include/hw/ppc/pnv_xscom.h | 2 +- include/hw/ppc/ppc4xx.h | 2 +- include/hw/ppc/vof.h | 2 +- include/hw/ppc/xics.h | 2 +- include/hw/register.h | 2 +- include/hw/remote/proxy-memory-listener.h | 2 +- include/hw/sh4/sh_intc.h | 2 +- include/hw/southbridge/ich9.h | 2 +- include/hw/sysbus.h | 2 +- include/hw/timer/npcm7xx_timer.h | 2 +- include/hw/tricore/tricore.h | 2 +- include/hw/usb.h | 2 +- include/hw/vfio/vfio-common.h | 2 +- include/hw/vfio/vfio-container-base.h | 2 +- include/hw/virtio/vhost-backend.h | 2 +- include/hw/virtio/vhost.h | 2 +- include/hw/virtio/virtio.h | 2 +- include/hw/xen/xen-pvh-common.h | 2 +- include/hw/xtensa/mx_pic.h | 2 +- include/qemu/iova-tree.h | 2 +- include/qemu/reserved-region.h | 2 +- include/system/dma.h | 2 +- include/system/hostmem.h | 2 +- include/system/kvm_int.h | 2 +- include/{exec =3D> system}/memory.h | 8 ++------ include/system/vhost-user-backend.h | 2 +- migration/rdma.h | 2 +- rust/wrapper.h | 2 +- target/avr/cpu.h | 2 +- target/loongarch/cpu.h | 2 +- target/mips/cpu.h | 2 +- accel/kvm/kvm-all.c | 2 +- accel/tcg/cputlb.c | 2 +- backends/tpm/tpm_util.c | 2 +- block/blkio.c | 4 ++-- disas/disas-mon.c | 2 +- hw/acpi/erst.c | 2 +- hw/avr/atmega.c | 2 +- hw/block/fdc-sysbus.c | 2 +- hw/core/cpu-system.c | 2 +- hw/core/loader-fit.c | 2 +- hw/core/loader.c | 2 +- hw/display/edid-region.c | 2 +- hw/hyperv/hyperv.c | 2 +- hw/i386/acpi-common.c | 2 +- hw/i386/acpi-microvm.c | 2 +- hw/i386/pc_piix.c | 2 +- hw/intc/mips_gic.c | 2 +- hw/intc/ompic.c | 2 +- hw/net/ne2000.c | 2 +- hw/pci-bridge/pci_bridge_dev.c | 2 +- hw/pci-host/remote.c | 2 +- hw/ppc/pnv_homer.c | 2 +- hw/ppc/sam460ex.c | 2 +- hw/remote/iommu.c | 2 +- hw/remote/machine.c | 2 +- hw/remote/proxy-memory-listener.c | 2 +- hw/remote/vfio-user-obj.c | 2 +- hw/s390x/s390-pci-inst.c | 2 +- hw/timer/sh_timer.c | 2 +- hw/vfio/common.c | 2 +- hw/vfio/container.c | 2 +- hw/vfio/platform.c | 2 +- hw/xtensa/sim.c | 2 +- hw/xtensa/virt.c | 2 +- hw/xtensa/xtensa_memory.c | 2 +- hw/xtensa/xtfpga.c | 2 +- migration/dirtyrate.c | 2 +- migration/rdma.c | 2 +- migration/savevm.c | 2 +- monitor/hmp-cmds-target.c | 2 +- stubs/ram-block.c | 2 +- system/dirtylimit.c | 2 +- system/ioport.c | 2 +- system/memory.c | 2 +- system/memory_mapping.c | 2 +- system/physmem.c | 2 +- system/qtest.c | 2 +- target/xtensa/cpu.c | 2 +- tests/qtest/fuzz/generic_fuzz.c | 2 +- tests/qtest/fuzz/qos_fuzz.c | 2 +- tests/unit/test-resv-mem.c | 2 +- ui/console.c | 2 +- util/vfio-helpers.c | 2 +- MAINTAINERS | 2 +- docs/devel/memory.rst | 2 +- scripts/analyze-inclusions | 2 +- 155 files changed, 160 insertions(+), 161 deletions(-) rename include/{exec =3D> system}/memory.h (99%) diff --git a/hw/arm/strongarm.h b/hw/arm/strongarm.h index 192821f6aa..b11b3a3379 100644 --- a/hw/arm/strongarm.h +++ b/hw/arm/strongarm.h @@ -1,7 +1,7 @@ #ifndef STRONGARM_H #define STRONGARM_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "target/arm/cpu-qom.h" =20 #define SA_CS0 0x00000000 diff --git a/hw/display/apple-gfx.h b/hw/display/apple-gfx.h index 3900cdbabb..a8b1d1efc0 100644 --- a/hw/display/apple-gfx.h +++ b/hw/display/apple-gfx.h @@ -9,7 +9,7 @@ #define QEMU_APPLE_GFX_H =20 #include "qemu/queue.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-properties.h" #include "ui/surface.h" =20 diff --git a/hw/display/framebuffer.h b/hw/display/framebuffer.h index 38fa0dcec6..29a828ce7a 100644 --- a/hw/display/framebuffer.h +++ b/hw/display/framebuffer.h @@ -1,7 +1,7 @@ #ifndef QEMU_FRAMEBUFFER_H #define QEMU_FRAMEBUFFER_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 /* Framebuffer device helper routines. */ =20 diff --git a/hw/display/vga_int.h b/hw/display/vga_int.h index f77c1c1145..60ad26e03e 100644 --- a/hw/display/vga_int.h +++ b/hw/display/vga_int.h @@ -27,7 +27,7 @@ =20 #include "ui/console.h" #include "exec/ioport.h" -#include "exec/memory.h" +#include "system/memory.h" =20 #include "hw/display/bochs-vbe.h" #include "hw/acpi/acpi_aml_interface.h" diff --git a/hw/hyperv/hv-balloon-our_range_memslots.h b/hw/hyperv/hv-ballo= on-our_range_memslots.h index df3b686bc7..b1f19d77da 100644 --- a/hw/hyperv/hv-balloon-our_range_memslots.h +++ b/hw/hyperv/hv-balloon-our_range_memslots.h @@ -11,7 +11,7 @@ #define HW_HYPERV_HV_BALLOON_OUR_RANGE_MEMSLOTS_H =20 =20 -#include "exec/memory.h" +#include "system/memory.h" #include "qom/object.h" #include "hv-balloon-page_range_tree.h" =20 diff --git a/hw/intc/ioapic_internal.h b/hw/intc/ioapic_internal.h index 37b8565539..51205767f4 100644 --- a/hw/intc/ioapic_internal.h +++ b/hw/intc/ioapic_internal.h @@ -22,7 +22,7 @@ #ifndef HW_INTC_IOAPIC_INTERNAL_H #define HW_INTC_IOAPIC_INTERNAL_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/intc/ioapic.h" #include "hw/sysbus.h" #include "qemu/notify.h" diff --git a/hw/net/i82596.h b/hw/net/i82596.h index f0bbe810eb..4bdfcaf856 100644 --- a/hw/net/i82596.h +++ b/hw/net/i82596.h @@ -3,7 +3,7 @@ =20 #define I82596_IOPORT_SIZE 0x20 =20 -#include "exec/memory.h" +#include "system/memory.h" #include "exec/address-spaces.h" =20 #define PORT_RESET 0x00 /* reset 82596 */ diff --git a/hw/net/pcnet.h b/hw/net/pcnet.h index eb7f46aab3..a94356ec30 100644 --- a/hw/net/pcnet.h +++ b/hw/net/pcnet.h @@ -7,7 +7,7 @@ #define PCNET_LOOPTEST_CRC 1 #define PCNET_LOOPTEST_NOCRC 2 =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/irq.h" =20 /* BUS CONFIGURATION REGISTERS */ diff --git a/hw/tpm/tpm_ppi.h b/hw/tpm/tpm_ppi.h index bf5d4a300f..88f316ee95 100644 --- a/hw/tpm/tpm_ppi.h +++ b/hw/tpm/tpm_ppi.h @@ -12,7 +12,7 @@ #ifndef TPM_TPM_PPI_H #define TPM_TPM_PPI_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 typedef struct TPMPPI { MemoryRegion ram; diff --git a/hw/usb/hcd-uhci.h b/hw/usb/hcd-uhci.h index 6d26b94e92..d4664297cf 100644 --- a/hw/usb/hcd-uhci.h +++ b/hw/usb/hcd-uhci.h @@ -28,7 +28,7 @@ #ifndef HW_USB_HCD_UHCI_H #define HW_USB_HCD_UHCI_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/timer.h" #include "hw/pci/pci_device.h" #include "hw/usb.h" diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index d94ecaba68..6c59300248 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -12,7 +12,7 @@ #ifndef HW_VFIO_VFIO_PCI_H #define HW_VFIO_VFIO_PCI_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/pci/pci_device.h" #include "hw/vfio/vfio-common.h" #include "qemu/event_notifier.h" diff --git a/hw/virtio/vhost-iova-tree.h b/hw/virtio/vhost-iova-tree.h index 0c4ba5abd5..08f63b61cd 100644 --- a/hw/virtio/vhost-iova-tree.h +++ b/hw/virtio/vhost-iova-tree.h @@ -11,7 +11,7 @@ #define HW_VIRTIO_VHOST_IOVA_TREE_H =20 #include "qemu/iova-tree.h" -#include "exec/memory.h" +#include "system/memory.h" =20 typedef struct VhostIOVATree VhostIOVATree; =20 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 33b9dc81eb..4395fd08af 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -22,11 +22,14 @@ #include "exec/page-protection.h" #include "exec/cpu-common.h" #include "exec/cpu-interrupt.h" -#include "exec/memory.h" #include "exec/tswap.h" #include "hw/core/cpu.h" #include "exec/cpu-defs.h" #include "exec/target_page.h" +#ifndef CONFIG_USER_ONLY +#include "system/memory.h" +#endif + =20 CPUArchState *cpu_copy(CPUArchState *env); =20 diff --git a/include/exec/ioport.h b/include/exec/ioport.h index 4397f12f93..ecea3575bc 100644 --- a/include/exec/ioport.h +++ b/include/exec/ioport.h @@ -24,7 +24,7 @@ #ifndef IOPORT_H #define IOPORT_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 #define MAX_IOPORTS (64 * 1024) #define IOPORTS_MASK (MAX_IOPORTS - 1) diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 92e8708af7..8677761af5 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -26,7 +26,7 @@ #include "exec/ramlist.h" #include "exec/ramblock.h" #include "exec/exec-all.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/target_page.h" #include "qemu/rcu.h" =20 diff --git a/include/hw/acpi/acpi.h b/include/hw/acpi/acpi.h index d1a4fa2af8..4b8ee094c4 100644 --- a/include/hw/acpi/acpi.h +++ b/include/hw/acpi/acpi.h @@ -21,7 +21,7 @@ */ =20 #include "qemu/notify.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/acpi/acpi_dev_interface.h" =20 /* diff --git a/include/hw/acpi/ich9_tco.h b/include/hw/acpi/ich9_tco.h index 2562a7cf39..b3c3f69451 100644 --- a/include/hw/acpi/ich9_tco.h +++ b/include/hw/acpi/ich9_tco.h @@ -10,7 +10,7 @@ #ifndef HW_ACPI_TCO_H #define HW_ACPI_TCO_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "migration/vmstate.h" =20 /* As per ICH9 spec, the internal timer has an error of ~0.6s on every tic= k */ diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index df2f83980f..b68d4334a0 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -29,7 +29,7 @@ #include "hw/sd/sdhci.h" #include "hw/usb/chipidea.h" #include "hw/watchdog/wdt_imx2.h" -#include "exec/memory.h" +#include "system/memory.h" #include "target/arm/cpu.h" #include "qom/object.h" =20 diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h index 40c593a5cf..41232a2237 100644 --- a/include/hw/arm/fsl-imx31.h +++ b/include/hw/arm/fsl-imx31.h @@ -25,7 +25,7 @@ #include "hw/i2c/imx_i2c.h" #include "hw/gpio/imx_gpio.h" #include "hw/watchdog/wdt_imx2.h" -#include "exec/memory.h" +#include "system/memory.h" #include "target/arm/cpu.h" #include "qom/object.h" =20 diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 9da32fc189..124bbd478f 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -34,7 +34,7 @@ #include "hw/usb/imx-usb-phy.h" #include "hw/pci-host/designware.h" #include "hw/or-irq.h" -#include "exec/memory.h" +#include "system/memory.h" #include "cpu.h" #include "qom/object.h" =20 diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 8277b0e8b2..4e3209b25b 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -33,7 +33,7 @@ #include "hw/net/imx_fec.h" #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" -#include "exec/memory.h" +#include "system/memory.h" #include "cpu.h" #include "qom/object.h" #include "qemu/units.h" diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 7cb87ea89c..6185507373 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -20,7 +20,7 @@ #ifndef HW_ARM_OMAP_H #define HW_ARM_OMAP_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "target/arm/cpu-qom.h" #include "qemu/log.h" #include "qom/object.h" diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h index c243fb0e7f..c2fae6e23f 100644 --- a/include/hw/arm/stm32l4x5_soc.h +++ b/include/hw/arm/stm32l4x5_soc.h @@ -24,7 +24,7 @@ #ifndef HW_ARM_STM32L4x5_SOC_H #define HW_ARM_STM32L4x5_SOC_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/arm/armv7m.h" #include "hw/or-irq.h" #include "hw/misc/stm32l4x5_syscfg.h" diff --git a/include/hw/boards.h b/include/hw/boards.h index f22b2e7fc7..02f43ac5d4 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -3,7 +3,7 @@ #ifndef HW_BOARDS_H #define HW_BOARDS_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "system/hostmem.h" #include "system/blockdev.h" #include "qapi/qapi-types-machine.h" diff --git a/include/hw/char/parallel.h b/include/hw/char/parallel.h index cfb97cc7cc..7b04478226 100644 --- a/include/hw/char/parallel.h +++ b/include/hw/char/parallel.h @@ -1,7 +1,7 @@ #ifndef HW_PARALLEL_H #define HW_PARALLEL_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/isa/isa.h" #include "hw/irq.h" #include "chardev/char-fe.h" diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h index df493fdf6b..ee0ca29902 100644 --- a/include/hw/char/riscv_htif.h +++ b/include/hw/char/riscv_htif.h @@ -22,7 +22,7 @@ =20 #include "chardev/char.h" #include "chardev/char-fe.h" -#include "exec/memory.h" +#include "system/memory.h" =20 #define TYPE_HTIF_UART "riscv.htif.uart" =20 diff --git a/include/hw/char/serial-mm.h b/include/hw/char/serial-mm.h index 62a8489d69..77abd098e0 100644 --- a/include/hw/char/serial-mm.h +++ b/include/hw/char/serial-mm.h @@ -27,7 +27,7 @@ #define HW_SERIAL_MM_H =20 #include "hw/char/serial.h" -#include "exec/memory.h" +#include "system/memory.h" #include "chardev/char.h" #include "hw/sysbus.h" #include "qom/object.h" diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h index 942b372df6..4bf90a46f3 100644 --- a/include/hw/char/serial.h +++ b/include/hw/char/serial.h @@ -27,7 +27,7 @@ #define HW_SERIAL_H =20 #include "chardev/char-fe.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/fifo8.h" #include "qom/object.h" =20 diff --git a/include/hw/display/macfb.h b/include/hw/display/macfb.h index 27cebefc9e..0fae1f33a6 100644 --- a/include/hw/display/macfb.h +++ b/include/hw/display/macfb.h @@ -13,7 +13,7 @@ #ifndef MACFB_H #define MACFB_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/irq.h" #include "hw/nubus/nubus.h" #include "hw/sysbus.h" diff --git a/include/hw/fsi/aspeed_apb2opb.h b/include/hw/fsi/aspeed_apb2op= b.h index f6a2387abf..878619eafa 100644 --- a/include/hw/fsi/aspeed_apb2opb.h +++ b/include/hw/fsi/aspeed_apb2opb.h @@ -8,7 +8,7 @@ #ifndef FSI_ASPEED_APB2OPB_H #define FSI_ASPEED_APB2OPB_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/fsi/fsi-master.h" #include "hw/sysbus.h" =20 diff --git a/include/hw/fsi/cfam.h b/include/hw/fsi/cfam.h index 7abc3b287b..cceb4bd6f1 100644 --- a/include/hw/fsi/cfam.h +++ b/include/hw/fsi/cfam.h @@ -7,7 +7,7 @@ #ifndef FSI_CFAM_H #define FSI_CFAM_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 #include "hw/fsi/fsi.h" #include "hw/fsi/lbus.h" diff --git a/include/hw/fsi/fsi-master.h b/include/hw/fsi/fsi-master.h index 68e5f56db2..b634ecd393 100644 --- a/include/hw/fsi/fsi-master.h +++ b/include/hw/fsi/fsi-master.h @@ -7,7 +7,7 @@ #ifndef FSI_FSI_MASTER_H #define FSI_FSI_MASTER_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" #include "hw/fsi/fsi.h" #include "hw/fsi/cfam.h" diff --git a/include/hw/fsi/fsi.h b/include/hw/fsi/fsi.h index e00f6ef078..f34765ed80 100644 --- a/include/hw/fsi/fsi.h +++ b/include/hw/fsi/fsi.h @@ -7,7 +7,7 @@ #ifndef FSI_FSI_H #define FSI_FSI_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" #include "hw/fsi/lbus.h" #include "qemu/bitops.h" diff --git a/include/hw/fsi/lbus.h b/include/hw/fsi/lbus.h index 558268c013..12519073cd 100644 --- a/include/hw/fsi/lbus.h +++ b/include/hw/fsi/lbus.h @@ -9,7 +9,7 @@ =20 #include "hw/qdev-core.h" #include "qemu/units.h" -#include "exec/memory.h" +#include "system/memory.h" =20 #define TYPE_FSI_LBUS_DEVICE "fsi.lbus.device" OBJECT_DECLARE_SIMPLE_TYPE(FSILBusDevice, FSI_LBUS_DEVICE) diff --git a/include/hw/gpio/npcm7xx_gpio.h b/include/hw/gpio/npcm7xx_gpio.h index b1d771bd77..7c0bf61a96 100644 --- a/include/hw/gpio/npcm7xx_gpio.h +++ b/include/hw/gpio/npcm7xx_gpio.h @@ -15,7 +15,7 @@ #ifndef NPCM7XX_GPIO_H #define NPCM7XX_GPIO_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/sysbus.h" =20 /* Number of pins managed by each controller. */ diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h index dc45963c0e..9c544c561b 100644 --- a/include/hw/i2c/npcm7xx_smbus.h +++ b/include/hw/i2c/npcm7xx_smbus.h @@ -16,7 +16,7 @@ #ifndef NPCM7XX_SMBUS_H #define NPCM7XX_SMBUS_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/i2c/i2c.h" #include "hw/irq.h" #include "hw/sysbus.h" diff --git a/include/hw/i2c/pm_smbus.h b/include/hw/i2c/pm_smbus.h index 0d74207efb..dafe0df4f6 100644 --- a/include/hw/i2c/pm_smbus.h +++ b/include/hw/i2c/pm_smbus.h @@ -1,7 +1,7 @@ #ifndef PM_SMBUS_H #define PM_SMBUS_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/i2c/smbus_master.h" =20 #define PM_SMBUS_MAX_MSG_SIZE 32 diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_interna= l.h index d6e85833da..429278da61 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -22,7 +22,7 @@ #define QEMU_APIC_INTERNAL_H =20 #include "cpu.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/timer.h" #include "target/i386/cpu-qom.h" #include "qom/object.h" diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index d43cb3908e..258b1343a1 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -18,7 +18,7 @@ #define HW_I386_X86_H =20 #include "exec/hwaddr.h" -#include "exec/memory.h" +#include "system/memory.h" =20 #include "hw/boards.h" #include "hw/i386/topology.h" diff --git a/include/hw/ide/ahci.h b/include/hw/ide/ahci.h index ac0292c634..cd07b87811 100644 --- a/include/hw/ide/ahci.h +++ b/include/hw/ide/ahci.h @@ -24,7 +24,7 @@ #ifndef HW_IDE_AHCI_H #define HW_IDE_AHCI_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 typedef struct AHCIDevice AHCIDevice; =20 diff --git a/include/hw/ipmi/ipmi.h b/include/hw/ipmi/ipmi.h index 77a7213ed9..2882eb7f3d 100644 --- a/include/hw/ipmi/ipmi.h +++ b/include/hw/ipmi/ipmi.h @@ -25,7 +25,7 @@ #ifndef HW_IPMI_H #define HW_IPMI_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" #include "qom/object.h" =20 diff --git a/include/hw/isa/apm.h b/include/hw/isa/apm.h index b6e070c00e..0834539045 100644 --- a/include/hw/isa/apm.h +++ b/include/hw/isa/apm.h @@ -1,7 +1,7 @@ #ifndef APM_H #define APM_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 #define APM_CNT_IOPORT 0xb2 #define ACPI_PORT_SMI_CMD APM_CNT_IOPORT diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h index 40d6224a4e..1d852011b3 100644 --- a/include/hw/isa/isa.h +++ b/include/hw/isa/isa.h @@ -3,7 +3,7 @@ =20 /* ISA bus */ =20 -#include "exec/memory.h" +#include "system/memory.h" #include "exec/ioport.h" #include "hw/qdev-core.h" #include "qom/object.h" diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index 34365c9860..9caaed9692 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -26,7 +26,7 @@ #include "hw/boards.h" #include "qom/object.h" #include "target/m68k/cpu-qom.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/m68k/q800-glue.h" #include "hw/misc/mac_via.h" #include "hw/net/dp8393x.h" diff --git a/include/hw/mem/npcm7xx_mc.h b/include/hw/mem/npcm7xx_mc.h index 7ed38be243..568cc35fdd 100644 --- a/include/hw/mem/npcm7xx_mc.h +++ b/include/hw/mem/npcm7xx_mc.h @@ -16,7 +16,7 @@ #ifndef NPCM7XX_MC_H #define NPCM7XX_MC_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/sysbus.h" =20 /** diff --git a/include/hw/mem/pc-dimm.h b/include/hw/mem/pc-dimm.h index fe0f3ea963..e0dbdd43dc 100644 --- a/include/hw/mem/pc-dimm.h +++ b/include/hw/mem/pc-dimm.h @@ -16,7 +16,7 @@ #ifndef QEMU_PC_DIMM_H #define QEMU_PC_DIMM_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" #include "qom/object.h" =20 diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h index 101799f7d3..1f3672ba5f 100644 --- a/include/hw/mips/mips.h +++ b/include/hw/mips/mips.h @@ -7,7 +7,7 @@ /* Kernels can be configured with 64KB pages */ #define INITRD_PAGE_SIZE (64 * KiB) =20 -#include "exec/memory.h" +#include "system/memory.h" =20 /* bonito.c */ PCIBus *bonito_init(qemu_irq *pic); diff --git a/include/hw/misc/auxbus.h b/include/hw/misc/auxbus.h index 03cacdee42..ccd18ce209 100644 --- a/include/hw/misc/auxbus.h +++ b/include/hw/misc/auxbus.h @@ -25,7 +25,7 @@ #ifndef HW_MISC_AUXBUS_H #define HW_MISC_AUXBUS_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" #include "qom/object.h" =20 diff --git a/include/hw/misc/ivshmem-flat.h b/include/hw/misc/ivshmem-flat.h index 0c2b015781..09bc3abcad 100644 --- a/include/hw/misc/ivshmem-flat.h +++ b/include/hw/misc/ivshmem-flat.h @@ -14,7 +14,7 @@ #include "qemu/queue.h" #include "qemu/event_notifier.h" #include "chardev/char-fe.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qom/object.h" #include "hw/sysbus.h" =20 diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h index 63cdcf7c69..6a15228150 100644 --- a/include/hw/misc/mac_via.h +++ b/include/hw/misc/mac_via.h @@ -9,7 +9,7 @@ #ifndef HW_MISC_MAC_VIA_H #define HW_MISC_MAC_VIA_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/sysbus.h" #include "hw/misc/mos6522.h" #include "hw/input/adb.h" diff --git a/include/hw/misc/npcm7xx_mft.h b/include/hw/misc/npcm7xx_mft.h index d6384382ce..e4b997a6ad 100644 --- a/include/hw/misc/npcm7xx_mft.h +++ b/include/hw/misc/npcm7xx_mft.h @@ -16,7 +16,7 @@ #ifndef NPCM7XX_MFT_H #define NPCM7XX_MFT_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/clock.h" #include "hw/irq.h" #include "hw/sysbus.h" diff --git a/include/hw/misc/npcm_clk.h b/include/hw/misc/npcm_clk.h index 8fa1e14bdd..52e972f460 100644 --- a/include/hw/misc/npcm_clk.h +++ b/include/hw/misc/npcm_clk.h @@ -16,7 +16,7 @@ #ifndef NPCM_CLK_H #define NPCM_CLK_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/clock.h" #include "hw/sysbus.h" =20 diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h index d81bb9afb2..702e7fddb1 100644 --- a/include/hw/misc/npcm_gcr.h +++ b/include/hw/misc/npcm_gcr.h @@ -16,7 +16,7 @@ #ifndef NPCM_GCR_H #define NPCM_GCR_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/sysbus.h" #include "qom/object.h" =20 diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h index 049a94c112..5098693437 100644 --- a/include/hw/misc/pvpanic.h +++ b/include/hw/misc/pvpanic.h @@ -15,7 +15,7 @@ #ifndef HW_MISC_PVPANIC_H #define HW_MISC_PVPANIC_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "qom/object.h" =20 #include "standard-headers/misc/pvpanic.h" diff --git a/include/hw/net/dp8393x.h b/include/hw/net/dp8393x.h index 4a3f7478be..24273dc1f4 100644 --- a/include/hw/net/dp8393x.h +++ b/include/hw/net/dp8393x.h @@ -22,7 +22,7 @@ =20 #include "hw/sysbus.h" #include "net/net.h" -#include "exec/memory.h" +#include "system/memory.h" =20 #define SONIC_REG_COUNT 0x40 =20 diff --git a/include/hw/net/msf2-emac.h b/include/hw/net/msf2-emac.h index 846ba6e6dc..b5d9127e46 100644 --- a/include/hw/net/msf2-emac.h +++ b/include/hw/net/msf2-emac.h @@ -23,7 +23,7 @@ */ =20 #include "hw/sysbus.h" -#include "exec/memory.h" +#include "system/memory.h" #include "net/net.h" #include "net/eth.h" #include "qom/object.h" diff --git a/include/hw/nvram/mac_nvram.h b/include/hw/nvram/mac_nvram.h index 0c4dfaeff6..e9d8398f84 100644 --- a/include/hw/nvram/mac_nvram.h +++ b/include/hw/nvram/mac_nvram.h @@ -26,7 +26,7 @@ #ifndef MAC_NVRAM_H #define MAC_NVRAM_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/sysbus.h" =20 #define MACIO_NVRAM_SIZE 0x2000 diff --git a/include/hw/nvram/npcm7xx_otp.h b/include/hw/nvram/npcm7xx_otp.h index ea4b5d0731..77b05f8b82 100644 --- a/include/hw/nvram/npcm7xx_otp.h +++ b/include/hw/nvram/npcm7xx_otp.h @@ -16,7 +16,7 @@ #ifndef NPCM7XX_OTP_H #define NPCM7XX_OTP_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/sysbus.h" =20 /* Each OTP module holds 8192 bits of one-time programmable storage */ diff --git a/include/hw/pci-host/fsl_imx8m_phy.h b/include/hw/pci-host/fsl_= imx8m_phy.h index 4f4875b37d..5f1b212fd9 100644 --- a/include/hw/pci-host/fsl_imx8m_phy.h +++ b/include/hw/pci-host/fsl_imx8m_phy.h @@ -11,7 +11,7 @@ =20 #include "hw/sysbus.h" #include "qom/object.h" -#include "exec/memory.h" +#include "system/memory.h" =20 #define TYPE_FSL_IMX8M_PCIE_PHY "fsl-imx8m-pcie-phy" OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mPciePhyState, FSL_IMX8M_PCIE_PHY) diff --git a/include/hw/pci-host/pam.h b/include/hw/pci-host/pam.h index 005916f826..44f3908160 100644 --- a/include/hw/pci-host/pam.h +++ b/include/hw/pci-host/pam.h @@ -50,7 +50,7 @@ * 0xf0000 - 0xfffff System BIOS Area Memory Segments */ =20 -#include "exec/memory.h" +#include "system/memory.h" =20 #define SMRAM_C_BASE 0xa0000 #define SMRAM_C_END 0xc0000 diff --git a/include/hw/pci-host/remote.h b/include/hw/pci-host/remote.h index 690a01f0fe..5264c35936 100644 --- a/include/hw/pci-host/remote.h +++ b/include/hw/pci-host/remote.h @@ -11,7 +11,7 @@ #ifndef PCI_HOST_REMOTE_H #define PCI_HOST_REMOTE_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/pci/pcie_host.h" =20 #define TYPE_REMOTE_PCIHOST "remote-pcihost" diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 822fbacdf0..c2fe6caa2c 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -1,7 +1,7 @@ #ifndef QEMU_PCI_H #define QEMU_PCI_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "system/dma.h" #include "system/host_iommu_device.h" =20 diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h index 82d92177da..f09de76bfe 100644 --- a/include/hw/pci/pcie_host.h +++ b/include/hw/pci/pcie_host.h @@ -22,7 +22,7 @@ #define PCIE_HOST_H =20 #include "hw/pci/pci_host.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qom/object.h" =20 #define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge" diff --git a/include/hw/pci/shpc.h b/include/hw/pci/shpc.h index a0789df153..ad1089567a 100644 --- a/include/hw/pci/shpc.h +++ b/include/hw/pci/shpc.h @@ -1,7 +1,7 @@ #ifndef SHPC_H #define SHPC_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/hotplug.h" #include "hw/pci/pci_device.h" #include "migration/vmstate.h" diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h index 672c2be471..896ee4a2b1 100644 --- a/include/hw/ppc/mac_dbdma.h +++ b/include/hw/ppc/mac_dbdma.h @@ -23,7 +23,7 @@ #ifndef HW_MAC_DBDMA_H #define HW_MAC_DBDMA_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/iov.h" #include "system/dma.h" #include "hw/sysbus.h" diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 174add4c53..266d56214f 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -20,7 +20,7 @@ #ifndef PPC_PNV_LPC_H #define PPC_PNV_LPC_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/ppc/pnv.h" #include "hw/qdev-core.h" #include "hw/isa/isa.h" /* For ISA_NUM_IRQS */ diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h index 3ec42de0ff..013ea2e53e 100644 --- a/include/hw/ppc/pnv_occ.h +++ b/include/hw/ppc/pnv_occ.h @@ -20,7 +20,7 @@ #ifndef PPC_PNV_OCC_H #define PPC_PNV_OCC_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" =20 #define TYPE_PNV_OCC "pnv-occ" diff --git a/include/hw/ppc/pnv_sbe.h b/include/hw/ppc/pnv_sbe.h index b6b378ad14..48a8b86a80 100644 --- a/include/hw/ppc/pnv_sbe.h +++ b/include/hw/ppc/pnv_sbe.h @@ -20,7 +20,7 @@ #ifndef PPC_PNV_SBE_H #define PPC_PNV_SBE_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" =20 #define TYPE_PNV_SBE "pnv-sbe" diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index a927aea1c0..b14549db70 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -20,7 +20,7 @@ #ifndef PPC_PNV_XSCOM_H #define PPC_PNV_XSCOM_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 typedef struct PnvXScomInterface PnvXScomInterface; typedef struct PnvChip PnvChip; diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 1bd9b8821b..2e94b00673 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -26,7 +26,7 @@ #define PPC4XX_H =20 #include "hw/ppc/ppc.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/sysbus.h" =20 /* diff --git a/include/hw/ppc/vof.h b/include/hw/ppc/vof.h index d3f293da8b..2918aaab12 100644 --- a/include/hw/ppc/vof.h +++ b/include/hw/ppc/vof.h @@ -8,7 +8,7 @@ =20 #include "qom/object.h" #include "exec/address-spaces.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/cpu-defs.h" =20 typedef struct Vof { diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index e94d53405f..097fcdf00f 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -28,7 +28,7 @@ #ifndef XICS_H #define XICS_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" #include "qom/object.h" =20 diff --git a/include/hw/register.h b/include/hw/register.h index 6a076cfcdf..a913c52aee 100644 --- a/include/hw/register.h +++ b/include/hw/register.h @@ -12,7 +12,7 @@ #define REGISTER_H =20 #include "hw/qdev-core.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/registerfields.h" #include "qom/object.h" =20 diff --git a/include/hw/remote/proxy-memory-listener.h b/include/hw/remote/= proxy-memory-listener.h index c4f3efb928..ec516d8267 100644 --- a/include/hw/remote/proxy-memory-listener.h +++ b/include/hw/remote/proxy-memory-listener.h @@ -9,7 +9,7 @@ #ifndef PROXY_MEMORY_LISTENER_H #define PROXY_MEMORY_LISTENER_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "io/channel.h" =20 typedef struct ProxyMemoryListener { diff --git a/include/hw/sh4/sh_intc.h b/include/hw/sh4/sh_intc.h index f62d5c5e13..94f183121e 100644 --- a/include/hw/sh4/sh_intc.h +++ b/include/hw/sh4/sh_intc.h @@ -1,7 +1,7 @@ #ifndef SH_INTC_H #define SH_INTC_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 typedef unsigned char intc_enum; =20 diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h index 6c60017024..1e231e89c9 100644 --- a/include/hw/southbridge/ich9.h +++ b/include/hw/southbridge/ich9.h @@ -7,7 +7,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_device.h" #include "hw/rtc/mc146818rtc.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/notify.h" #include "qom/object.h" =20 diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h index 81bbda10d3..7dc88aaa27 100644 --- a/include/hw/sysbus.h +++ b/include/hw/sysbus.h @@ -4,7 +4,7 @@ /* Devices attached directly to the main system bus. */ =20 #include "hw/qdev-core.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qom/object.h" =20 #define QDEV_MAX_MMIO 32 diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_ti= mer.h index d45c051b56..e287375dce 100644 --- a/include/hw/timer/npcm7xx_timer.h +++ b/include/hw/timer/npcm7xx_timer.h @@ -16,7 +16,7 @@ #ifndef NPCM7XX_TIMER_H #define NPCM7XX_TIMER_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/sysbus.h" #include "qemu/timer.h" =20 diff --git a/include/hw/tricore/tricore.h b/include/hw/tricore/tricore.h index c19ed3f013..4ffc0fe1d6 100644 --- a/include/hw/tricore/tricore.h +++ b/include/hw/tricore/tricore.h @@ -1,7 +1,7 @@ #ifndef HW_TRICORE_H #define HW_TRICORE_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 struct tricore_boot_info { uint64_t ram_size; diff --git a/include/hw/usb.h b/include/hw/usb.h index e410693d0c..26a9f3ecde 100644 --- a/include/hw/usb.h +++ b/include/hw/usb.h @@ -25,7 +25,7 @@ * THE SOFTWARE. */ =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" #include "qemu/iov.h" #include "qemu/queue.h" diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h index 04b123a6c9..f5b3f45a43 100644 --- a/include/hw/vfio/vfio-common.h +++ b/include/hw/vfio/vfio-common.h @@ -21,7 +21,7 @@ #ifndef HW_VFIO_VFIO_COMMON_H #define HW_VFIO_VFIO_COMMON_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/queue.h" #include "qemu/notify.h" #include "ui/console.h" diff --git a/include/hw/vfio/vfio-container-base.h b/include/hw/vfio/vfio-c= ontainer-base.h index 4cff9943ab..6aca02fb3d 100644 --- a/include/hw/vfio/vfio-container-base.h +++ b/include/hw/vfio/vfio-container-base.h @@ -13,7 +13,7 @@ #ifndef HW_VFIO_VFIO_CONTAINER_BASE_H #define HW_VFIO_VFIO_CONTAINER_BASE_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 typedef struct VFIODevice VFIODevice; typedef struct VFIOIOMMUClass VFIOIOMMUClass; diff --git a/include/hw/virtio/vhost-backend.h b/include/hw/virtio/vhost-ba= ckend.h index 70c2e8ffee..d6df209a2f 100644 --- a/include/hw/virtio/vhost-backend.h +++ b/include/hw/virtio/vhost-backend.h @@ -11,7 +11,7 @@ #ifndef VHOST_BACKEND_H #define VHOST_BACKEND_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 typedef enum VhostBackendType { VHOST_BACKEND_TYPE_NONE =3D 0, diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h index a9469d50bc..bb4b58e115 100644 --- a/include/hw/virtio/vhost.h +++ b/include/hw/virtio/vhost.h @@ -3,7 +3,7 @@ =20 #include "hw/virtio/vhost-backend.h" #include "hw/virtio/virtio.h" -#include "exec/memory.h" +#include "system/memory.h" =20 #define VHOST_F_DEVICE_IOTLB 63 #define VHOST_USER_F_PROTOCOL_FEATURES 30 diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h index 6386910280..7e0c471ea4 100644 --- a/include/hw/virtio/virtio.h +++ b/include/hw/virtio/virtio.h @@ -14,7 +14,7 @@ #ifndef QEMU_VIRTIO_H #define QEMU_VIRTIO_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-core.h" #include "net/net.h" #include "migration/vmstate.h" diff --git a/include/hw/xen/xen-pvh-common.h b/include/hw/xen/xen-pvh-commo= n.h index 17c5a58a5a..5db83d88ec 100644 --- a/include/hw/xen/xen-pvh-common.h +++ b/include/hw/xen/xen-pvh-common.h @@ -9,7 +9,7 @@ #ifndef XEN_PVH_COMMON_H__ #define XEN_PVH_COMMON_H__ =20 -#include "exec/memory.h" +#include "system/memory.h" #include "qom/object.h" #include "hw/boards.h" #include "hw/pci-host/gpex.h" diff --git a/include/hw/xtensa/mx_pic.h b/include/hw/xtensa/mx_pic.h index 500424c8d3..cd316d86eb 100644 --- a/include/hw/xtensa/mx_pic.h +++ b/include/hw/xtensa/mx_pic.h @@ -28,7 +28,7 @@ #ifndef XTENSA_MX_PIC_H #define XTENSA_MX_PIC_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 struct XtensaMxPic; typedef struct XtensaMxPic XtensaMxPic; diff --git a/include/qemu/iova-tree.h b/include/qemu/iova-tree.h index 16d354a814..14e82a22d5 100644 --- a/include/qemu/iova-tree.h +++ b/include/qemu/iova-tree.h @@ -23,7 +23,7 @@ * for the thread safety issue. */ =20 -#include "exec/memory.h" +#include "system/memory.h" #include "exec/hwaddr.h" =20 #define IOVA_OK (0) diff --git a/include/qemu/reserved-region.h b/include/qemu/reserved-region.h index 8e6f0a97e2..9026cf08fd 100644 --- a/include/qemu/reserved-region.h +++ b/include/qemu/reserved-region.h @@ -20,7 +20,7 @@ #ifndef QEMU_RESERVED_REGION_H #define QEMU_RESERVED_REGION_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 /* * Insert a new region into a sorted list of reserved regions. In case diff --git a/include/system/dma.h b/include/system/dma.h index e142f7efa6..aaa03b9711 100644 --- a/include/system/dma.h +++ b/include/system/dma.h @@ -10,7 +10,7 @@ #ifndef DMA_H #define DMA_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "exec/address-spaces.h" #include "block/block.h" #include "block/accounting.h" diff --git a/include/system/hostmem.h b/include/system/hostmem.h index 62642e602c..88fa791ac7 100644 --- a/include/system/hostmem.h +++ b/include/system/hostmem.h @@ -16,7 +16,7 @@ #include "system/numa.h" #include "qapi/qapi-types-machine.h" #include "qom/object.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/bitmap.h" #include "qemu/thread-context.h" =20 diff --git a/include/system/kvm_int.h b/include/system/kvm_int.h index 4de6106869..756a3c0a25 100644 --- a/include/system/kvm_int.h +++ b/include/system/kvm_int.h @@ -9,7 +9,7 @@ #ifndef QEMU_KVM_INT_H #define QEMU_KVM_INT_H =20 -#include "exec/memory.h" +#include "system/memory.h" #include "qapi/qapi-types-common.h" #include "qemu/accel.h" #include "qemu/queue.h" diff --git a/include/exec/memory.h b/include/system/memory.h similarity index 99% rename from include/exec/memory.h rename to include/system/memory.h index 2f84a7cfed..fbbf4cf911 100644 --- a/include/exec/memory.h +++ b/include/system/memory.h @@ -11,10 +11,8 @@ * */ =20 -#ifndef MEMORY_H -#define MEMORY_H - -#ifndef CONFIG_USER_ONLY +#ifndef SYSTEM_MEMORY_H +#define SYSTEM_MEMORY_H =20 #include "exec/cpu-common.h" #include "exec/hwaddr.h" @@ -3197,5 +3195,3 @@ void ram_block_add_cpr_blocker(RAMBlock *rb, Error **= errp); void ram_block_del_cpr_blocker(RAMBlock *rb); =20 #endif - -#endif diff --git a/include/system/vhost-user-backend.h b/include/system/vhost-use= r-backend.h index 327b0b84f1..5ed953cd53 100644 --- a/include/system/vhost-user-backend.h +++ b/include/system/vhost-user-backend.h @@ -13,7 +13,7 @@ #define QEMU_VHOST_USER_BACKEND_H =20 #include "qom/object.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/option.h" #include "qemu/bitmap.h" #include "hw/virtio/vhost.h" diff --git a/migration/rdma.h b/migration/rdma.h index f55f28bbed..4d3386b84a 100644 --- a/migration/rdma.h +++ b/migration/rdma.h @@ -19,7 +19,7 @@ #ifndef QEMU_MIGRATION_RDMA_H #define QEMU_MIGRATION_RDMA_H =20 -#include "exec/memory.h" +#include "system/memory.h" =20 void rdma_start_outgoing_migration(void *opaque, InetSocketAddress *host_p= ort, Error **errp); diff --git a/rust/wrapper.h b/rust/wrapper.h index d4fec54657..94866b7e32 100644 --- a/rust/wrapper.h +++ b/rust/wrapper.h @@ -52,7 +52,7 @@ typedef enum memory_order { #include "qemu-io.h" #include "system/system.h" #include "hw/sysbus.h" -#include "exec/memory.h" +#include "system/memory.h" #include "chardev/char-fe.h" #include "hw/clock.h" #include "hw/qdev-clock.h" diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 9862705c6a..b0518a1f60 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,7 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" -#include "exec/memory.h" +#include "system/memory.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 254e4fbdcd..02ef6ddecb 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -14,7 +14,7 @@ #include "hw/registerfields.h" #include "qemu/timer.h" #ifndef CONFIG_USER_ONLY -#include "exec/memory.h" +#include "system/memory.h" #endif #include "cpu-csr.h" #include "cpu-qom.h" diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f6877ece8b..9ef72a95d7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -4,7 +4,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #ifndef CONFIG_USER_ONLY -#include "exec/memory.h" +#include "system/memory.h" #endif #include "fpu/softfloat-types.h" #include "hw/clock.h" diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index f89568bfa3..0d47bb0d9b 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -33,7 +33,7 @@ #include "system/cpus.h" #include "system/accel-blocker.h" #include "qemu/bswap.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/ram_addr.h" #include "qemu/event_notifier.h" #include "qemu/main-loop.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2817c9dbdd..6f0ea9067b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -22,7 +22,7 @@ #include "accel/tcg/cpu-ops.h" #include "exec/exec-all.h" #include "exec/page-protection.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/cpu_ldst.h" #include "exec/cputlb.h" #include "exec/tb-flush.h" diff --git a/backends/tpm/tpm_util.c b/backends/tpm/tpm_util.c index f07a2656ce..f2d1739e33 100644 --- a/backends/tpm/tpm_util.c +++ b/backends/tpm/tpm_util.c @@ -25,7 +25,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "tpm_int.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/qdev-properties.h" #include "system/tpm_backend.h" #include "system/tpm_util.h" diff --git a/block/blkio.c b/block/blkio.c index 5f4fce2b1b..4142673984 100644 --- a/block/blkio.c +++ b/block/blkio.c @@ -11,7 +11,7 @@ #include "qemu/osdep.h" #include #include "block/block_int.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/cpu-common.h" /* for qemu_ram_get_fd() */ #include "qemu/defer-call.h" #include "qapi/error.h" @@ -19,7 +19,7 @@ #include "qobject/qdict.h" #include "qemu/module.h" #include "system/block-backend.h" -#include "exec/memory.h" /* for ram_block_discard_disable() */ +#include "system/memory.h" /* for ram_block_discard_disable() */ =20 #include "block/block-io.h" =20 diff --git a/disas/disas-mon.c b/disas/disas-mon.c index 37bf16ac79..9c693618c2 100644 --- a/disas/disas-mon.c +++ b/disas/disas-mon.c @@ -7,7 +7,7 @@ #include "qemu/osdep.h" #include "disas-internal.h" #include "disas/disas.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/core/cpu.h" #include "monitor/monitor.h" =20 diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c index ec64f92893..5c4c1dc638 100644 --- a/hw/acpi/erst.c +++ b/hw/acpi/erst.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/qdev-core.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qom/object.h" #include "hw/pci/pci_device.h" #include "qom/object_interfaces.h" diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 11fab184de..cb721c96b7 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -12,7 +12,7 @@ #include "qemu/module.h" #include "qemu/units.h" #include "qapi/error.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/address-spaces.h" #include "system/system.h" #include "hw/qdev-properties.h" diff --git a/hw/block/fdc-sysbus.c b/hw/block/fdc-sysbus.c index 381b492aec..4955e478cd 100644 --- a/hw/block/fdc-sysbus.c +++ b/hw/block/fdc-sysbus.c @@ -26,7 +26,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qom/object.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/sysbus.h" #include "hw/block/fdc.h" #include "migration/vmstate.h" diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index aed5076ec7..5ef8c24b5b 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -22,7 +22,7 @@ #include "qapi/error.h" #include "exec/address-spaces.h" #include "exec/cputlb.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/tb-flush.h" #include "exec/tswap.h" #include "hw/qdev-core.h" diff --git a/hw/core/loader-fit.c b/hw/core/loader-fit.c index 6eb66406b0..2dea485ae0 100644 --- a/hw/core/loader-fit.c +++ b/hw/core/loader-fit.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/units.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/loader.h" #include "hw/loader-fit.h" #include "qemu/cutils.h" diff --git a/hw/core/loader.c b/hw/core/loader.c index 2e35f0aa90..a3aa62d132 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -59,7 +59,7 @@ #include "uboot_image.h" #include "hw/loader.h" #include "hw/nvram/fw_cfg.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/boards.h" #include "qemu/cutils.h" #include "system/runstate.h" diff --git a/hw/display/edid-region.c b/hw/display/edid-region.c index 675429dc18..f1596fba9a 100644 --- a/hw/display/edid-region.c +++ b/hw/display/edid-region.c @@ -1,5 +1,5 @@ #include "qemu/osdep.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/display/edid.h" =20 static uint64_t edid_region_read(void *ptr, hwaddr addr, unsigned size) diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c index 831e04f214..382c62d668 100644 --- a/hw/hyperv/hyperv.c +++ b/hw/hyperv/hyperv.c @@ -12,7 +12,7 @@ #include "qemu/module.h" #include "qapi/error.h" #include "exec/address-spaces.h" -#include "exec/memory.h" +#include "system/memory.h" #include "system/kvm.h" #include "qemu/bitops.h" #include "qemu/error-report.h" diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c index 0cc2919bb8..7bd08067a7 100644 --- a/hw/i386/acpi-common.c +++ b/hw/i386/acpi-common.c @@ -23,7 +23,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/aml-build.h" #include "hw/acpi/utils.h" diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c index 279da6b4aa..bc6571778c 100644 --- a/hw/i386/acpi-microvm.c +++ b/hw/i386/acpi-microvm.c @@ -24,7 +24,7 @@ #include "qemu/cutils.h" #include "qapi/error.h" =20 -#include "exec/memory.h" +#include "system/memory.h" #include "hw/acpi/acpi.h" #include "hw/acpi/acpi_aml_interface.h" #include "hw/acpi/aml-build.h" diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6c91e2d292..e9dbbe086a 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -47,7 +47,7 @@ #include "hw/i386/kvm/clock.h" #include "hw/sysbus.h" #include "hw/i2c/smbus_eeprom.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/acpi/acpi.h" #include "qapi/error.h" #include "qemu/error-report.h" diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 5e3cbeabec..12d3908938 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -14,7 +14,7 @@ #include "qemu/module.h" #include "qapi/error.h" #include "hw/sysbus.h" -#include "exec/memory.h" +#include "system/memory.h" #include "system/kvm.h" #include "system/reset.h" #include "kvm_mips.h" diff --git a/hw/intc/ompic.c b/hw/intc/ompic.c index 42af4567c6..169baf2ded 100644 --- a/hw/intc/ompic.c +++ b/hw/intc/ompic.c @@ -13,7 +13,7 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qom/object.h" =20 #define TYPE_OR1K_OMPIC "or1k-ompic" diff --git a/hw/net/ne2000.c b/hw/net/ne2000.c index b482c5f3af..b1923c8c3e 100644 --- a/hw/net/ne2000.c +++ b/hw/net/ne2000.c @@ -25,7 +25,7 @@ #include "qemu/osdep.h" #include "net/eth.h" #include "qemu/module.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/irq.h" #include "migration/vmstate.h" #include "ne2000.h" diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 0a91a8ae6c..4931ea24f6 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -28,7 +28,7 @@ #include "hw/pci/shpc.h" #include "hw/pci/slotid_cap.h" #include "hw/qdev-properties.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/pci/pci_bus.h" #include "hw/hotplug.h" #include "qom/object.h" diff --git a/hw/pci-host/remote.c b/hw/pci-host/remote.c index bfb25ef6af..be077d075e 100644 --- a/hw/pci-host/remote.c +++ b/hw/pci-host/remote.c @@ -28,7 +28,7 @@ #include "hw/pci/pcie_host.h" #include "hw/qdev-properties.h" #include "hw/pci-host/remote.h" -#include "exec/memory.h" +#include "system/memory.h" =20 static const char *remote_pcihost_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus) diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index 18a53a80c1..0521f9a428 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -20,7 +20,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "exec/hwaddr.h" -#include "exec/memory.h" +#include "system/memory.h" #include "system/cpus.h" #include "hw/qdev-core.h" #include "hw/qdev-properties.h" diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 7dc3b309c8..a070de23cf 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -24,7 +24,7 @@ #include "exec/page-protection.h" #include "hw/loader.h" #include "elf.h" -#include "exec/memory.h" +#include "system/memory.h" #include "ppc440.h" #include "hw/pci-host/ppc4xx.h" #include "hw/block/flash.h" diff --git a/hw/remote/iommu.c b/hw/remote/iommu.c index 7c56aad0fc..ec845d1f58 100644 --- a/hw/remote/iommu.c +++ b/hw/remote/iommu.c @@ -13,7 +13,7 @@ #include "hw/remote/iommu.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/address-spaces.h" #include "trace.h" =20 diff --git a/hw/remote/machine.c b/hw/remote/machine.c index fdc6c441bb..d4616025e8 100644 --- a/hw/remote/machine.c +++ b/hw/remote/machine.c @@ -16,7 +16,7 @@ #include "qemu/osdep.h" =20 #include "hw/remote/machine.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qapi/error.h" #include "hw/pci/pci_host.h" #include "hw/remote/iohub.h" diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-lis= tener.c index a926f61ebe..ce7f5b9bfb 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -10,7 +10,7 @@ =20 #include "qemu/int128.h" #include "qemu/range.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/cpu-common.h" #include "exec/ram_addr.h" #include "qapi/error.h" diff --git a/hw/remote/vfio-user-obj.c b/hw/remote/vfio-user-obj.c index 6e51a92856..9bdd0a465b 100644 --- a/hw/remote/vfio-user-obj.c +++ b/hw/remote/vfio-user-obj.c @@ -57,7 +57,7 @@ #include "hw/qdev-core.h" #include "hw/pci/pci.h" #include "qemu/timer.h" -#include "exec/memory.h" +#include "system/memory.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/remote/vfio-user-obj.h" diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 8cdeb6cb7f..b4e003c19c 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -13,7 +13,7 @@ =20 #include "qemu/osdep.h" #include "exec/memop.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/error-report.h" #include "system/hw_accel.h" #include "hw/boards.h" diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 7788939766..d4fa32c9d6 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -9,7 +9,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/log.h" #include "hw/irq.h" #include "hw/sh4/sh.h" diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 1a0d9290f8..989c6ee83d 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -28,7 +28,7 @@ #include "hw/vfio/vfio-common.h" #include "hw/vfio/pci.h" #include "exec/address-spaces.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/ram_addr.h" #include "exec/target_page.h" #include "hw/hw.h" diff --git a/hw/vfio/container.c b/hw/vfio/container.c index 7c57bdd27b..1d1c5f9a77 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -24,7 +24,7 @@ =20 #include "hw/vfio/vfio-common.h" #include "exec/address-spaces.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/ram_addr.h" #include "qemu/error-report.h" #include "qemu/range.h" diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c index 67bc57409c..96c6bf5654 100644 --- a/hw/vfio/platform.c +++ b/hw/vfio/platform.c @@ -28,7 +28,7 @@ #include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/range.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/address-spaces.h" #include "qemu/queue.h" #include "hw/sysbus.h" diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index 1cea29c66d..49d17e7bb2 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -32,7 +32,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/error-report.h" #include "xtensa_memory.h" #include "xtensa_sim.h" diff --git a/hw/xtensa/virt.c b/hw/xtensa/virt.c index b08404fc17..b10866ccd8 100644 --- a/hw/xtensa/virt.c +++ b/hw/xtensa/virt.c @@ -33,7 +33,7 @@ #include "hw/pci-host/gpex.h" #include "net/net.h" #include "elf.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/error-report.h" #include "xtensa_memory.h" #include "xtensa_sim.h" diff --git a/hw/xtensa/xtensa_memory.c b/hw/xtensa/xtensa_memory.c index 2c1095f017..13a6077d86 100644 --- a/hw/xtensa/xtensa_memory.c +++ b/hw/xtensa/xtensa_memory.c @@ -27,7 +27,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/error-report.h" #include "xtensa_memory.h" =20 diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 3f3677f1c9..3bd0ef8268 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -34,7 +34,7 @@ #include "hw/loader.h" #include "hw/qdev-properties.h" #include "elf.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/tswap.h" #include "hw/char/serial-mm.h" #include "net/net.h" diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c index 4cd14779d6..09caf92f87 100644 --- a/migration/dirtyrate.c +++ b/migration/dirtyrate.c @@ -27,7 +27,7 @@ #include "qobject/qdict.h" #include "system/kvm.h" #include "system/runstate.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/xxhash.h" #include "migration.h" =20 diff --git a/migration/rdma.c b/migration/rdma.c index 76fb034923..d9603ab603 100644 --- a/migration/rdma.c +++ b/migration/rdma.c @@ -30,7 +30,7 @@ #include "qemu/sockets.h" #include "qemu/bitmap.h" #include "qemu/coroutine.h" -#include "exec/memory.h" +#include "system/memory.h" #include #include #include diff --git a/migration/savevm.c b/migration/savevm.c index ce158c3512..c33200a33f 100644 --- a/migration/savevm.c +++ b/migration/savevm.c @@ -48,7 +48,7 @@ #include "qapi/qapi-builtin-visit.h" #include "qemu/error-report.h" #include "system/cpus.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/target_page.h" #include "trace.h" #include "qemu/iov.h" diff --git a/monitor/hmp-cmds-target.c b/monitor/hmp-cmds-target.c index 239c2a61a4..6654d31406 100644 --- a/monitor/hmp-cmds-target.c +++ b/monitor/hmp-cmds-target.c @@ -25,7 +25,7 @@ #include "qemu/osdep.h" #include "disas/disas.h" #include "exec/address-spaces.h" -#include "exec/memory.h" +#include "system/memory.h" #include "monitor/hmp-target.h" #include "monitor/monitor-internal.h" #include "qapi/error.h" diff --git a/stubs/ram-block.c b/stubs/ram-block.c index 108197683b..e88fab31a5 100644 --- a/stubs/ram-block.c +++ b/stubs/ram-block.c @@ -1,7 +1,7 @@ #include "qemu/osdep.h" #include "exec/ramlist.h" #include "exec/cpu-common.h" -#include "exec/memory.h" +#include "system/memory.h" =20 void *qemu_ram_get_host_addr(RAMBlock *rb) { diff --git a/system/dirtylimit.c b/system/dirtylimit.c index 7dedef8dd4..30cd09f3d1 100644 --- a/system/dirtylimit.c +++ b/system/dirtylimit.c @@ -19,7 +19,7 @@ #include "system/dirtylimit.h" #include "monitor/hmp.h" #include "monitor/monitor.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/target_page.h" #include "hw/boards.h" #include "system/kvm.h" diff --git a/system/ioport.c b/system/ioport.c index 89daae9d60..2291739039 100644 --- a/system/ioport.c +++ b/system/ioport.c @@ -27,7 +27,7 @@ =20 #include "qemu/osdep.h" #include "exec/ioport.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/address-spaces.h" #include "trace.h" =20 diff --git a/system/memory.c b/system/memory.c index eddd21a6cd..2865d0deb1 100644 --- a/system/memory.c +++ b/system/memory.c @@ -16,7 +16,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qapi/error.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qapi/visitor.h" #include "qemu/bitops.h" #include "qemu/error-report.h" diff --git a/system/memory_mapping.c b/system/memory_mapping.c index 37d3325f77..8538a8241e 100644 --- a/system/memory_mapping.c +++ b/system/memory_mapping.c @@ -16,7 +16,7 @@ #include "qapi/error.h" =20 #include "system/memory_mapping.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/address-spaces.h" #include "hw/core/cpu.h" =20 diff --git a/system/physmem.c b/system/physmem.c index 333a5eb94d..e61fea41b5 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -50,7 +50,7 @@ #include "qemu/log.h" #include "qemu/memalign.h" #include "qemu/memfd.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/ioport.h" #include "system/dma.h" #include "system/hostmem.h" diff --git a/system/qtest.c b/system/qtest.c index 12152efbcd..5407289154 100644 --- a/system/qtest.c +++ b/system/qtest.c @@ -17,7 +17,7 @@ #include "system/runstate.h" #include "chardev/char-fe.h" #include "exec/ioport.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/tswap.h" #include "hw/qdev-core.h" #include "hw/irq.h" diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 7663b62d01..ec6a0a8b66 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -36,7 +36,7 @@ #include "migration/vmstate.h" #include "hw/qdev-clock.h" #ifndef CONFIG_USER_ONLY -#include "exec/memory.h" +#include "system/memory.h" #endif =20 =20 diff --git a/tests/qtest/fuzz/generic_fuzz.c b/tests/qtest/fuzz/generic_fuz= z.c index d107a496da..239be9372d 100644 --- a/tests/qtest/fuzz/generic_fuzz.c +++ b/tests/qtest/fuzz/generic_fuzz.c @@ -20,7 +20,7 @@ #include "tests/qtest/libqos/pci-pc.h" #include "fuzz.h" #include "string.h" -#include "exec/memory.h" +#include "system/memory.h" #include "exec/ramblock.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" diff --git a/tests/qtest/fuzz/qos_fuzz.c b/tests/qtest/fuzz/qos_fuzz.c index d3839bf999..9afe8bf6d8 100644 --- a/tests/qtest/fuzz/qos_fuzz.c +++ b/tests/qtest/fuzz/qos_fuzz.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/main-loop.h" =20 #include "tests/qtest/libqtest.h" diff --git a/tests/unit/test-resv-mem.c b/tests/unit/test-resv-mem.c index cd8f7318cc..4de2d042d1 100644 --- a/tests/unit/test-resv-mem.c +++ b/tests/unit/test-resv-mem.c @@ -10,7 +10,7 @@ =20 #include "qemu/osdep.h" #include "qemu/range.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qemu/reserved-region.h" =20 #define DEBUG 0 diff --git a/ui/console.c b/ui/console.c index 6456e8dd90..6cd122cf40 100644 --- a/ui/console.c +++ b/ui/console.c @@ -35,7 +35,7 @@ #include "qemu/option.h" #include "chardev/char.h" #include "trace.h" -#include "exec/memory.h" +#include "system/memory.h" #include "qom/object.h" #include "qemu/memfd.h" =20 diff --git a/util/vfio-helpers.c b/util/vfio-helpers.c index f8bab46c68..fdff042ab4 100644 --- a/util/vfio-helpers.c +++ b/util/vfio-helpers.c @@ -16,7 +16,7 @@ #include "qapi/error.h" #include "exec/ramlist.h" #include "exec/cpu-common.h" -#include "exec/memory.h" +#include "system/memory.h" #include "trace.h" #include "qemu/error-report.h" #include "standard-headers/linux/pci_regs.h" diff --git a/MAINTAINERS b/MAINTAINERS index d54b5578f8..163814b4c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3107,7 +3107,7 @@ R: Philippe Mathieu-Daud=C3=A9 S: Supported F: include/exec/ioport.h F: include/exec/memop.h -F: include/exec/memory.h +F: include/system/memory.h F: include/exec/ram_addr.h F: include/exec/ramblock.h F: include/system/memory_mapping.h diff --git a/docs/devel/memory.rst b/docs/devel/memory.rst index 69c5e3f914..57fb2aec76 100644 --- a/docs/devel/memory.rst +++ b/docs/devel/memory.rst @@ -369,4 +369,4 @@ callbacks are called: API Reference ------------- =20 -.. kernel-doc:: include/exec/memory.h +.. kernel-doc:: include/system/memory.h diff --git a/scripts/analyze-inclusions b/scripts/analyze-inclusions index b6280f25c8..d2c566667d 100644 --- a/scripts/analyze-inclusions +++ b/scripts/analyze-inclusions @@ -53,7 +53,7 @@ echo $(grep_include -F 'trace/generated-tracers.h') files= include generated-trac echo $(grep_include -F 'qapi/error.h') files include qapi/error.h echo $(grep_include -F 'qom/object.h') files include qom/object.h echo $(grep_include -F 'block/aio.h') files include block/aio.h -echo $(grep_include -F 'exec/memory.h') files include exec/memory.h +echo $(grep_include -F 'system/memory.h') files include system/memory.h echo $(grep_include -F 'fpu/softfloat.h') files include fpu/softfloat.h echo $(grep_include -F 'qemu/bswap.h') files include qemu/bswap.h echo --=20 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- hw/net/i82596.h | 2 +- hw/s390x/ipl.h | 2 +- include/hw/misc/lasi.h | 2 +- include/hw/nubus/nubus.h | 2 +- include/hw/ppc/vof.h | 2 +- include/hw/tricore/triboard.h | 2 +- include/{exec =3D> system}/address-spaces.h | 8 ++------ include/system/dma.h | 2 +- rust/wrapper.h | 2 +- target/i386/hvf/vmx.h | 2 +- accel/hvf/hvf-accel-ops.c | 2 +- hw/acpi/erst.c | 2 +- hw/arm/aspeed_ast10x0.c | 2 +- hw/arm/bananapi_m2u.c | 2 +- hw/arm/collie.c | 2 +- hw/arm/exynos4_boards.c | 2 +- hw/arm/fsl-imx31.c | 2 +- hw/arm/fsl-imx8mp.c | 2 +- hw/arm/imx8mp-evk.c | 2 +- hw/arm/integratorcp.c | 2 +- hw/arm/kzm.c | 2 +- hw/arm/microbit.c | 2 +- hw/arm/mps2-tz.c | 2 +- hw/arm/mps2.c | 2 +- hw/arm/mps3r.c | 2 +- hw/arm/msf2-soc.c | 2 +- hw/arm/msf2-som.c | 2 +- hw/arm/musca.c | 2 +- hw/arm/omap1.c | 2 +- hw/arm/omap_sx1.c | 2 +- hw/arm/orangepi.c | 2 +- hw/arm/stellaris.c | 2 +- hw/arm/stm32f100_soc.c | 2 +- hw/arm/stm32f205_soc.c | 2 +- hw/arm/stm32f405_soc.c | 2 +- hw/arm/stm32l4x5_soc.c | 2 +- hw/avr/atmega.c | 2 +- hw/char/goldfish_tty.c | 2 +- hw/char/omap_uart.c | 2 +- hw/char/riscv_htif.c | 2 +- hw/core/cpu-system.c | 2 +- hw/core/null-machine.c | 2 +- hw/core/sysbus.c | 2 +- hw/dma/rc4030.c | 2 +- hw/hyperv/hv-balloon.c | 2 +- hw/hyperv/hyperv.c | 2 +- hw/i386/kvm/xen_evtchn.c | 2 +- hw/i386/kvm/xen_gnttab.c | 2 +- hw/i386/kvm/xen_overlay.c | 2 +- hw/i386/sgx-epc.c | 2 +- hw/i386/sgx.c | 2 +- hw/i386/vapic.c | 2 +- hw/ide/ahci-sysbus.c | 2 +- hw/input/lasips2.c | 2 +- hw/intc/loongarch_extioi.c | 2 +- hw/intc/riscv_aplic.c | 2 +- hw/intc/riscv_imsic.c | 2 +- hw/loongarch/virt.c | 2 +- hw/mem/memory-device.c | 2 +- hw/microblaze/petalogix_ml605_mmu.c | 2 +- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +- hw/microblaze/xlnx-zynqmp-pmu.c | 2 +- hw/mips/mipssim.c | 2 +- hw/misc/allwinner-h3-dramc.c | 2 +- hw/misc/allwinner-r40-dramc.c | 2 +- hw/misc/ivshmem-flat.c | 2 +- hw/misc/mac_via.c | 2 +- hw/net/i82596.c | 2 +- hw/nvram/fw_cfg.c | 2 +- hw/openrisc/openrisc_sim.c | 2 +- hw/openrisc/virt.c | 2 +- hw/pci-host/mv64361.c | 2 +- hw/ppc/pegasos2.c | 2 +- hw/ppc/pnv_psi.c | 2 +- hw/ppc/ppc4xx_sdram.c | 2 +- hw/ppc/prep_systemio.c | 2 +- hw/ppc/rs6000_mc.c | 2 +- hw/ppc/spapr_ovec.c | 2 +- hw/ppc/vof.c | 2 +- hw/remote/iommu.c | 2 +- hw/riscv/microblaze-v-generic.c | 2 +- hw/riscv/opentitan.c | 2 +- hw/riscv/shakti_c.c | 2 +- hw/s390x/css.c | 2 +- hw/s390x/s390-skeys.c | 2 +- hw/s390x/virtio-ccw.c | 2 +- hw/sparc/sun4m_iommu.c | 2 +- hw/sparc64/sun4u_iommu.c | 2 +- hw/timer/hpet.c | 2 +- hw/tpm/tpm_crb.c | 2 +- hw/vfio/ap.c | 2 +- hw/vfio/ccw.c | 2 +- hw/vfio/common.c | 2 +- hw/vfio/container.c | 2 +- hw/vfio/platform.c | 2 +- hw/vfio/spapr.c | 2 +- hw/virtio/vhost-vdpa.c | 2 +- hw/virtio/virtio-balloon.c | 2 +- hw/virtio/virtio-bus.c | 2 +- monitor/hmp-cmds-target.c | 2 +- monitor/hmp-cmds.c | 2 +- system/ioport.c | 2 +- system/memory.c | 2 +- system/memory_mapping.c | 2 +- target/arm/hvf/hvf.c | 2 +- target/arm/kvm.c | 2 +- target/avr/cpu.c | 2 +- target/i386/cpu-apic.c | 2 +- target/i386/cpu.c | 2 +- target/i386/kvm/xen-emu.c | 2 +- target/i386/nvmm/nvmm-all.c | 2 +- target/i386/sev.c | 2 +- target/i386/tcg/system/misc_helper.c | 2 +- target/i386/tcg/system/tcg-cpu.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- target/loongarch/kvm/kvm.c | 2 +- target/riscv/kvm/kvm-cpu.c | 2 +- target/s390x/mmu_helper.c | 2 +- target/s390x/sigp.c | 2 +- target/s390x/tcg/excp_helper.c | 2 +- target/xtensa/dbg_helper.c | 2 +- hw/display/apple-gfx.m | 2 +- 122 files changed, 123 insertions(+), 127 deletions(-) rename include/{exec =3D> system}/address-spaces.h (89%) diff --git a/hw/net/i82596.h b/hw/net/i82596.h index 4bdfcaf856..dc1fa1a1dc 100644 --- a/hw/net/i82596.h +++ b/hw/net/i82596.h @@ -4,7 +4,7 @@ #define I82596_IOPORT_SIZE 0x20 =20 #include "system/memory.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 #define PORT_RESET 0x00 /* reset 82596 */ #define PORT_SELFTEST 0x01 /* selftest */ diff --git a/hw/s390x/ipl.h b/hw/s390x/ipl.h index 8e3882d506..c6ecb3433c 100644 --- a/hw/s390x/ipl.h +++ b/hw/s390x/ipl.h @@ -14,7 +14,7 @@ #define HW_S390_IPL_H =20 #include "cpu.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/qdev-core.h" #include "hw/s390x/ipl/qipl.h" #include "qom/object.h" diff --git a/include/hw/misc/lasi.h b/include/hw/misc/lasi.h index f01c0f680a..0bdfb11b50 100644 --- a/include/hw/misc/lasi.h +++ b/include/hw/misc/lasi.h @@ -12,7 +12,7 @@ #ifndef LASI_H #define LASI_H =20 -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/pci/pci_host.h" #include "hw/boards.h" =20 diff --git a/include/hw/nubus/nubus.h b/include/hw/nubus/nubus.h index fee79b71d1..7825840dca 100644 --- a/include/hw/nubus/nubus.h +++ b/include/hw/nubus/nubus.h @@ -11,7 +11,7 @@ =20 #include "hw/qdev-properties.h" #include "hw/sysbus.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qom/object.h" #include "qemu/units.h" =20 diff --git a/include/hw/ppc/vof.h b/include/hw/ppc/vof.h index 2918aaab12..3a0fbffe54 100644 --- a/include/hw/ppc/vof.h +++ b/include/hw/ppc/vof.h @@ -7,7 +7,7 @@ #define HW_VOF_H =20 #include "qom/object.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/memory.h" #include "exec/cpu-defs.h" =20 diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h index 8250470643..ca49a0c752 100644 --- a/include/hw/tricore/triboard.h +++ b/include/hw/tricore/triboard.h @@ -21,7 +21,7 @@ #include "qapi/error.h" #include "hw/boards.h" #include "system/system.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qom/object.h" =20 #include "hw/tricore/tc27x_soc.h" diff --git a/include/exec/address-spaces.h b/include/system/address-spaces.h similarity index 89% rename from include/exec/address-spaces.h rename to include/system/address-spaces.h index 0d0aa61d68..72d17afb0f 100644 --- a/include/exec/address-spaces.h +++ b/include/system/address-spaces.h @@ -11,16 +11,14 @@ * */ =20 -#ifndef EXEC_ADDRESS_SPACES_H -#define EXEC_ADDRESS_SPACES_H +#ifndef SYSTEM_ADDRESS_SPACES_H +#define SYSTEM_ADDRESS_SPACES_H =20 /* * Internal interfaces between memory.c/exec.c/vl.c. Do not #include unle= ss * you're one of them. */ =20 -#ifndef CONFIG_USER_ONLY - /* Get the root memory region. This interface should only be used tempora= rily * until a proper bus interface is available. */ @@ -35,5 +33,3 @@ extern AddressSpace address_space_memory; extern AddressSpace address_space_io; =20 #endif - -#endif diff --git a/include/system/dma.h b/include/system/dma.h index aaa03b9711..82e7ad5437 100644 --- a/include/system/dma.h +++ b/include/system/dma.h @@ -11,7 +11,7 @@ #define DMA_H =20 #include "system/memory.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "block/block.h" #include "block/accounting.h" =20 diff --git a/rust/wrapper.h b/rust/wrapper.h index 94866b7e32..beddd9aab2 100644 --- a/rust/wrapper.h +++ b/rust/wrapper.h @@ -64,5 +64,5 @@ typedef enum memory_order { #include "chardev/char-serial.h" #include "exec/memattrs.h" #include "qemu/timer.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/char/pl011.h" diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 80ce26279b..87a478f7fd 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -33,7 +33,7 @@ #include "system/hvf.h" #include "system/hvf_int.h" =20 -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 static inline uint64_t rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg) { diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 12fc30c276..601c3bc0ac 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -50,7 +50,7 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "exec/exec-all.h" #include "gdbstub/enums.h" #include "hw/boards.h" diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c index 5c4c1dc638..2e49b551f2 100644 --- a/hw/acpi/erst.c +++ b/hw/acpi/erst.c @@ -23,7 +23,7 @@ #include "hw/acpi/acpi-defs.h" #include "hw/acpi/aml-build.h" #include "hw/acpi/bios-linker-loader.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/hostmem.h" #include "hw/acpi/erst.h" #include "trace.h" diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index ec329f4991..21ffab10f3 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -11,7 +11,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/system.h" #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index 4d84d10d24..b750a575f7 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/boards.h" diff --git a/hw/arm/collie.c b/hw/arm/collie.c index eaa5c52d45..e83aee58c6 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -16,7 +16,7 @@ #include "strongarm.h" #include "hw/arm/boot.h" #include "hw/block/flash.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qom/object.h" #include "qemu/error-report.h" =20 diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 43dc89d902..2d8f2d7326 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -28,7 +28,7 @@ #include "hw/sysbus.h" #include "net/net.h" #include "hw/arm/boot.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/arm/exynos4210.h" #include "hw/net/lan9118.h" #include "hw/qdev-properties.h" diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 9de0f2148f..2a8ffb15f7 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -23,7 +23,7 @@ #include "qapi/error.h" #include "hw/arm/fsl-imx31.h" #include "system/system.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/qdev-properties.h" #include "chardev/char.h" #include "target/arm/cpu-qom.h" diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 82edf61082..af7a7e6745 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -9,7 +9,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/arm/bsa.h" #include "hw/arm/fsl-imx8mp.h" #include "hw/intc/arm_gicv3.h" diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c index b5aec06ec5..b3082fa60d 100644 --- a/hw/arm/imx8mp-evk.c +++ b/hw/arm/imx8mp-evk.c @@ -7,7 +7,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/arm/boot.h" #include "hw/arm/fsl-imx8mp.h" #include "hw/boards.h" diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 8aa2e6e98e..ac0c6c6096 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -16,7 +16,7 @@ #include "hw/misc/arm_integrator_debug.h" #include "hw/net/smc91c111.h" #include "net/net.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/runstate.h" #include "system/system.h" #include "qemu/log.h" diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index 08d2b3025c..362c145409 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -19,7 +19,7 @@ #include "hw/arm/boot.h" #include "hw/boards.h" #include "qemu/error-report.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "net/net.h" #include "hw/net/lan9118.h" #include "hw/char/serial-mm.h" diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 3f56fb45ce..ade363daaa 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -13,7 +13,7 @@ #include "hw/boards.h" #include "hw/arm/boot.h" #include "system/system.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 #include "hw/arm/nrf51_soc.h" #include "hw/i2c/microbit_i2c.h" diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 13ed868b6b..b0633a5a69 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -54,7 +54,7 @@ #include "hw/arm/armv7m.h" #include "hw/or-irq.h" #include "hw/boards.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/system.h" #include "system/reset.h" #include "hw/misc/unimp.h" diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 3f8db0cab6..6958485a66 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -33,7 +33,7 @@ #include "hw/arm/armv7m.h" #include "hw/or-irq.h" #include "hw/boards.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/system.h" #include "hw/qdev-properties.h" #include "hw/misc/unimp.h" diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c index 1bddb5e822..4dd1e8a718 100644 --- a/hw/arm/mps3r.c +++ b/hw/arm/mps3r.c @@ -28,7 +28,7 @@ #include "qemu/units.h" #include "qapi/error.h" #include "qobject/qlist.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "cpu.h" #include "system/system.h" #include "hw/boards.h" diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index e8a5b231ba..bc9b419e37 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -25,7 +25,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/char/serial-mm.h" #include "hw/arm/msf2-soc.h" #include "hw/misc/unimp.h" diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 9b20f1e2c9..29c76c6860 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -33,7 +33,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/boot.h" #include "hw/qdev-clock.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/arm/msf2-soc.h" =20 #define DDR_BASE_ADDRESS 0xA0000000 diff --git a/hw/arm/musca.c b/hw/arm/musca.c index e9c092abc3..a4f43f1992 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -22,7 +22,7 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/system.h" #include "hw/arm/boot.h" #include "hw/arm/armsse.h" diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 3ee10b4777..91d7e3f04b 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -23,7 +23,7 @@ #include "qemu/main-loop.h" #include "qapi/error.h" #include "cpu.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 24b4043183..aa1e96b3ad 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -34,7 +34,7 @@ #include "hw/arm/boot.h" #include "hw/block/flash.h" #include "system/qtest.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qemu/cutils.h" #include "qemu/error-report.h" =20 diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 634af9b0a1..e0956880d1 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/boards.h" diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 3361111360..cbe914c93e 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -20,7 +20,7 @@ #include "net/net.h" #include "hw/boards.h" #include "qemu/log.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/system.h" #include "hw/arm/armv7m.h" #include "hw/char/pl011.h" diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c index 53b5636452..0eabaf8d9b 100644 --- a/hw/arm/stm32f100_soc.c +++ b/hw/arm/stm32f100_soc.c @@ -27,7 +27,7 @@ #include "qapi/error.h" #include "qemu/module.h" #include "hw/arm/boot.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/arm/stm32f100_soc.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 47a54e592b..32e96912f0 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -26,7 +26,7 @@ #include "qapi/error.h" #include "qemu/module.h" #include "hw/arm/boot.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/arm/stm32f205_soc.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index 18d8824f29..bba9060daf 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -24,7 +24,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/system.h" #include "hw/arm/stm32f405_soc.h" #include "hw/qdev-clock.h" diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index dbf75329f7..6278d354c8 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -24,7 +24,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/system.h" #include "hw/or-irq.h" #include "hw/arm/stm32l4x5_soc.h" diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index cb721c96b7..2e8b8e8c67 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -13,7 +13,7 @@ #include "qemu/units.h" #include "qapi/error.h" #include "system/memory.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/system.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" diff --git a/hw/char/goldfish_tty.c b/hw/char/goldfish_tty.c index 7374561141..f0891ffa4d 100644 --- a/hw/char/goldfish_tty.c +++ b/hw/char/goldfish_tty.c @@ -15,7 +15,7 @@ #include "chardev/char-fe.h" #include "qemu/log.h" #include "trace.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/dma.h" #include "hw/char/goldfish_tty.h" =20 diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c index 07fb868965..8cbf6ce803 100644 --- a/hw/char/omap_uart.c +++ b/hw/char/omap_uart.c @@ -21,7 +21,7 @@ #include "chardev/char.h" #include "hw/arm/omap.h" #include "hw/char/serial-mm.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 /* UARTs */ struct omap_uart_s { diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index ec5db5a597..c884be5d75 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -28,7 +28,7 @@ #include "chardev/char-fe.h" #include "qemu/timer.h" #include "qemu/error-report.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "exec/tswap.h" #include "system/dma.h" #include "system/runstate.h" diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 5ef8c24b5b..82b68b8927 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -20,7 +20,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "exec/cputlb.h" #include "system/memory.h" #include "exec/tb-flush.h" diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 7f1fb562be..a6e477a2d8 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -14,7 +14,7 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "hw/boards.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/core/cpu.h" =20 static void machine_none_init(MachineState *mch) diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index 98819d5dc6..6eb4c0f15a 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -21,7 +21,7 @@ #include "qapi/error.h" #include "hw/sysbus.h" #include "monitor/monitor.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent); static char *sysbus_get_fw_dev_path(DeviceState *dev); diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c index 5bf54347ed..6842e7d491 100644 --- a/hw/dma/rc4030.c +++ b/hw/dma/rc4030.c @@ -32,7 +32,7 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "qemu/module.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "trace.h" #include "qom/object.h" =20 diff --git a/hw/hyperv/hv-balloon.c b/hw/hyperv/hv-balloon.c index 6f33c3e741..0b1da723c8 100644 --- a/hw/hyperv/hv-balloon.c +++ b/hw/hyperv/hv-balloon.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "hv-balloon-internal.h" =20 -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "exec/cpu-common.h" #include "exec/ramblock.h" #include "hw/boards.h" diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c index 382c62d668..d21e428eae 100644 --- a/hw/hyperv/hyperv.c +++ b/hw/hyperv/hyperv.c @@ -11,7 +11,7 @@ #include "qemu/main-loop.h" #include "qemu/module.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/memory.h" #include "system/kvm.h" #include "qemu/bitops.h" diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c index 9b8b092bc2..f9223ef1a1 100644 --- a/hw/i386/kvm/xen_evtchn.c +++ b/hw/i386/kvm/xen_evtchn.c @@ -23,7 +23,7 @@ #include "qobject/qdict.h" #include "qom/object.h" #include "exec/target_page.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "migration/vmstate.h" #include "trace.h" =20 diff --git a/hw/i386/kvm/xen_gnttab.c b/hw/i386/kvm/xen_gnttab.c index 7b843a72b1..430ba62896 100644 --- a/hw/i386/kvm/xen_gnttab.c +++ b/hw/i386/kvm/xen_gnttab.c @@ -17,7 +17,7 @@ #include "qapi/error.h" #include "qom/object.h" #include "exec/target_page.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "migration/vmstate.h" =20 #include "hw/sysbus.h" diff --git a/hw/i386/kvm/xen_overlay.c b/hw/i386/kvm/xen_overlay.c index db9aa7942d..a2b26e9906 100644 --- a/hw/i386/kvm/xen_overlay.c +++ b/hw/i386/kvm/xen_overlay.c @@ -16,7 +16,7 @@ #include "qapi/error.h" #include "qom/object.h" #include "exec/target_page.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "migration/vmstate.h" =20 #include "hw/sysbus.h" diff --git a/hw/i386/sgx-epc.c b/hw/i386/sgx-epc.c index 875e1c5c33..00b220d4d6 100644 --- a/hw/i386/sgx-epc.c +++ b/hw/i386/sgx-epc.c @@ -17,7 +17,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "target/i386/cpu.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 static const Property sgx_epc_properties[] =3D { DEFINE_PROP_UINT64(SGX_EPC_ADDR_PROP, SGXEPCDevice, addr, 0), diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index e665e2111c..5685c4fb80 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -20,7 +20,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qapi/qapi-commands-misc-target.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/hw_accel.h" #include "system/reset.h" #include diff --git a/hw/i386/vapic.c b/hw/i386/vapic.c index 14de9b7a82..26aae64e5d 100644 --- a/hw/i386/vapic.c +++ b/hw/i386/vapic.c @@ -16,7 +16,7 @@ #include "system/hw_accel.h" #include "system/kvm.h" #include "system/runstate.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/i386/apic_internal.h" #include "hw/sysbus.h" #include "hw/boards.h" diff --git a/hw/ide/ahci-sysbus.c b/hw/ide/ahci-sysbus.c index 03a5bd42d0..3c1935d81c 100644 --- a/hw/ide/ahci-sysbus.c +++ b/hw/ide/ahci-sysbus.c @@ -22,7 +22,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" =20 diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c index d9f8c36778..987034efd3 100644 --- a/hw/input/lasips2.c +++ b/hw/input/lasips2.c @@ -29,7 +29,7 @@ #include "hw/input/lasips2.h" #include "exec/hwaddr.h" #include "trace.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "migration/vmstate.h" #include "hw/irq.h" #include "qapi/error.h" diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index a51a215e6e..a558c50185 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -11,7 +11,7 @@ #include "qapi/error.h" #include "hw/irq.h" #include "hw/loongarch/virt.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/intc/loongarch_extioi.h" #include "trace.h" =20 diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 5964cde7e0..789c4a4d6e 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -22,7 +22,7 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "qemu/bswap.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/sysbus.h" #include "hw/pci/msi.h" #include "hw/boards.h" diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 241b12fef0..852f413e5a 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -22,7 +22,7 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "qemu/bswap.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/sysbus.h" #include "hw/pci/msi.h" #include "hw/boards.h" diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 65c9027feb..f1eb42c2c1 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -18,7 +18,7 @@ #include "system/reset.h" #include "system/rtc.h" #include "hw/loongarch/virt.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/irq.h" #include "net/net.h" #include "hw/loader.h" diff --git a/hw/mem/memory-device.c b/hw/mem/memory-device.c index 1de8dfec7d..1a432e9bd2 100644 --- a/hw/mem/memory-device.c +++ b/hw/mem/memory-device.c @@ -17,7 +17,7 @@ #include "qemu/range.h" #include "hw/virtio/vhost.h" #include "system/kvm.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "trace.h" =20 static bool memory_device_is_empty(const MemoryDeviceState *md) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_= ml605_mmu.c index 21ad215e44..c887c7a99e 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -36,7 +36,7 @@ #include "hw/boards.h" #include "hw/char/serial-mm.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/ssi/ssi.h" =20 #include "boot.h" diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petal= ogix_s3adsp1800_mmu.c index bdba2006b7..f976c90bd2 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -33,7 +33,7 @@ #include "system/system.h" #include "hw/boards.h" #include "hw/misc/unimp.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/char/xilinx_uartlite.h" =20 #include "boot.h" diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pm= u.c index bdbf7328bf..0922c65295 100644 --- a/hw/microblaze/xlnx-zynqmp-pmu.c +++ b/hw/microblaze/xlnx-zynqmp-pmu.c @@ -17,7 +17,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/boards.h" #include "cpu.h" #include "boot.h" diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index c530688e76..b6dabf2893 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -28,7 +28,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/datadir.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/clock.h" #include "hw/mips/mips.h" #include "hw/char/serial-mm.h" diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c index c4f3eb9274..74ff71b753 100644 --- a/hw/misc/allwinner-h3-dramc.c +++ b/hw/misc/allwinner-h3-dramc.c @@ -24,7 +24,7 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "hw/misc/allwinner-h3-dramc.h" diff --git a/hw/misc/allwinner-r40-dramc.c b/hw/misc/allwinner-r40-dramc.c index 96e1848c21..5908a059e8 100644 --- a/hw/misc/allwinner-r40-dramc.c +++ b/hw/misc/allwinner-r40-dramc.c @@ -24,7 +24,7 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/bitops.h" diff --git a/hw/misc/ivshmem-flat.c b/hw/misc/ivshmem-flat.c index 40309a8ff3..076c4b42de 100644 --- a/hw/misc/ivshmem-flat.c +++ b/hw/misc/ivshmem-flat.c @@ -17,7 +17,7 @@ #include "hw/qdev-properties-system.h" #include "hw/sysbus.h" #include "chardev/char-fe.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "trace.h" =20 #include "hw/misc/ivshmem-flat.h" diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 03b1feda50..3c0819c58a 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -16,7 +16,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "migration/vmstate.h" #include "hw/sysbus.h" #include "hw/irq.h" diff --git a/hw/net/i82596.c b/hw/net/i82596.c index ee919dab3c..64ed3c8390 100644 --- a/hw/net/i82596.c +++ b/hw/net/i82596.c @@ -15,7 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qemu/module.h" #include "trace.h" #include "i82596.h" diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index a757939cfb..cbfb2b5303 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -27,7 +27,7 @@ #include "system/system.h" #include "system/dma.h" #include "system/reset.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/boards.h" #include "hw/nvram/fw_cfg.h" #include "hw/qdev-properties.h" diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 83d7c2a8af..c2284a7d41 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -28,7 +28,7 @@ #include "net/net.h" #include "hw/openrisc/boot.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/device_tree.h" #include "system/system.h" #include "hw/sysbus.h" diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c index 3055306783..0d1c1f103c 100644 --- a/hw/openrisc/virt.c +++ b/hw/openrisc/virt.c @@ -11,7 +11,7 @@ #include "qemu/guest-random.h" #include "qapi/error.h" #include "cpu.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/irq.h" #include "hw/boards.h" #include "hw/char/serial-mm.h" diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c index 9c41c155fb..a297318c6e 100644 --- a/hw/pci-host/mv64361.c +++ b/hw/pci-host/mv64361.c @@ -17,7 +17,7 @@ #include "hw/irq.h" #include "hw/intc/i8259.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qemu/log.h" #include "qemu/error-report.h" #include "trace.h" diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 246d6d633b..7b2dc6985c 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -31,7 +31,7 @@ #include "qemu/error-report.h" #include "system/kvm.h" #include "kvm_ppc.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qom/qom-qobject.h" #include "qobject/qdict.h" #include "trace.h" diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 1fe11dde50..f832ee61e8 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -18,7 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/irq.h" #include "target/ppc/cpu.h" #include "qemu/log.h" diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index 562bff8d53..bf0faad9e7 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -34,7 +34,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/error-report.h" -#include "exec/address-spaces.h" /* get_system_memory() */ +#include "system/address-spaces.h" /* get_system_memory() */ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/ppc/ppc4xx.h" diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c index b1f2e130f0..08f29e72e4 100644 --- a/hw/ppc/prep_systemio.c +++ b/hw/ppc/prep_systemio.c @@ -28,7 +28,7 @@ #include "hw/isa/isa.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qom/object.h" #include "qemu/error-report.h" /* for error_report() */ #include "qemu/module.h" diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c index 0e5d53b8b6..27f1c90f06 100644 --- a/hw/ppc/rs6000_mc.c +++ b/hw/ppc/rs6000_mc.c @@ -24,7 +24,7 @@ #include "hw/isa/isa.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qapi/error.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_ovec.c index 88e29536aa..6d6eaf67cb 100644 --- a/hw/ppc/spapr_ovec.c +++ b/hw/ppc/spapr_ovec.c @@ -15,7 +15,7 @@ #include "hw/ppc/spapr_ovec.h" #include "migration/vmstate.h" #include "qemu/bitmap.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qemu/error-report.h" #include "trace.h" #include diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c index 09cb77de93..f14efa3a7c 100644 --- a/hw/ppc/vof.c +++ b/hw/ppc/vof.c @@ -15,7 +15,7 @@ #include "qemu/units.h" #include "qemu/log.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/ppc/vof.h" #include "hw/ppc/fdt.h" #include "system/runstate.h" diff --git a/hw/remote/iommu.c b/hw/remote/iommu.c index ec845d1f58..3e0758a21e 100644 --- a/hw/remote/iommu.c +++ b/hw/remote/iommu.c @@ -14,7 +14,7 @@ #include "hw/pci/pci_bus.h" #include "hw/pci/pci.h" #include "system/memory.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "trace.h" =20 /** diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index d8e67906d2..e863c50cbc 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -22,7 +22,7 @@ #include "net/net.h" #include "hw/boards.h" #include "hw/char/serial-mm.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/char/xilinx_uartlite.h" #include "hw/misc/unimp.h" =20 diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 98a67fe52a..019d6b3986 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -28,7 +28,7 @@ #include "hw/riscv/boot.h" #include "qemu/units.h" #include "system/system.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 /* * This version of the OpenTitan machine currently supports diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index e2242b97d0..17c5c72102 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -25,7 +25,7 @@ #include "hw/intc/riscv_aclint.h" #include "system/system.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/riscv/boot.h" =20 static const struct MemmapEntry { diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 738800c98d..2059c5dd0b 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -14,7 +14,7 @@ #include "qapi/visitor.h" #include "qemu/bitops.h" #include "qemu/error-report.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/s390x/ioinst.h" #include "hw/qdev-properties.h" #include "hw/s390x/css.h" diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c index 811d892122..425e3e4a87 100644 --- a/hw/s390x/s390-skeys.c +++ b/hw/s390x/s390-skeys.c @@ -19,7 +19,7 @@ #include "qobject/qdict.h" #include "qemu/error-report.h" #include "system/memory_mapping.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/kvm.h" #include "migration/qemu-file-types.h" #include "migration/register.h" diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 43f3b162c8..e8ecb90826 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -12,7 +12,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/kvm.h" #include "net/net.h" #include "hw/virtio/virtio.h" diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index 5a4c1f5e3b..4a542b18d2 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -29,7 +29,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/module.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "trace.h" =20 /* diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index eba811af0c..533fcae1fb 100644 --- a/hw/sparc64/sun4u_iommu.c +++ b/hw/sparc64/sun4u_iommu.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/sparc/sun4u_iommu.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qemu/log.h" #include "qemu/module.h" #include "trace.h" diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index ccb97b6806..ea82472105 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -36,7 +36,7 @@ #include "hw/rtc/mc146818rtc_regs.h" #include "migration/vmstate.h" #include "hw/timer/i8254.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qom/object.h" #include "trace.h" =20 diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index 6cdeb72df0..b668aee97a 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -18,7 +18,7 @@ =20 #include "qemu/module.h" #include "qapi/error.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/qdev-properties.h" #include "hw/pci/pci_ids.h" #include "hw/acpi/tpm.h" diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c index c7ab4ff57a..d6575d7c44 100644 --- a/hw/vfio/ap.c +++ b/hw/vfio/ap.c @@ -28,7 +28,7 @@ #include "migration/vmstate.h" #include "hw/qdev-properties.h" #include "hw/s390x/ap-bridge.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qom/object.h" =20 #define TYPE_VFIO_AP_DEVICE "vfio-ap" diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c index e5e0d9e3e7..29e804e122 100644 --- a/hw/vfio/ccw.c +++ b/hw/vfio/ccw.c @@ -27,7 +27,7 @@ #include "hw/s390x/vfio-ccw.h" #include "hw/qdev-properties.h" #include "hw/s390x/ccw-device.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/module.h" diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 989c6ee83d..98832af88d 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -27,7 +27,7 @@ =20 #include "hw/vfio/vfio-common.h" #include "hw/vfio/pci.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/memory.h" #include "exec/ram_addr.h" #include "exec/target_page.h" diff --git a/hw/vfio/container.c b/hw/vfio/container.c index 1d1c5f9a77..2e993c7e73 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -23,7 +23,7 @@ #include =20 #include "hw/vfio/vfio-common.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/memory.h" #include "exec/ram_addr.h" #include "qemu/error-report.h" diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c index 96c6bf5654..c6edbdd4ae 100644 --- a/hw/vfio/platform.c +++ b/hw/vfio/platform.c @@ -29,7 +29,7 @@ #include "qemu/module.h" #include "qemu/range.h" #include "system/memory.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qemu/queue.h" #include "hw/sysbus.h" #include "trace.h" diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c index 1a5d1611f2..c9a7dd8d68 100644 --- a/hw/vfio/spapr.c +++ b/hw/vfio/spapr.c @@ -13,7 +13,7 @@ #include #include "system/kvm.h" #include "system/hostmem.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 #include "hw/vfio/vfio-common.h" #include "hw/hw.h" diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c index 7efbde3d4c..1e0336df1d 100644 --- a/hw/virtio/vhost-vdpa.c +++ b/hw/virtio/vhost-vdpa.c @@ -20,7 +20,7 @@ #include "hw/virtio/virtio-net.h" #include "hw/virtio/vhost-shadow-virtqueue.h" #include "hw/virtio/vhost-vdpa.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "migration/blocker.h" #include "qemu/cutils.h" #include "qemu/main-loop.h" diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c index 2eb5a14fa2..0d0603c674 100644 --- a/hw/virtio/virtio-balloon.c +++ b/hw/virtio/virtio-balloon.c @@ -24,7 +24,7 @@ #include "hw/boards.h" #include "system/balloon.h" #include "hw/virtio/virtio-balloon.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qapi/error.h" #include "qapi/qapi-events-machine.h" #include "qapi/visitor.h" diff --git a/hw/virtio/virtio-bus.c b/hw/virtio/virtio-bus.c index 896feb37a1..d1c79c567b 100644 --- a/hw/virtio/virtio-bus.c +++ b/hw/virtio/virtio-bus.c @@ -28,7 +28,7 @@ #include "qapi/error.h" #include "hw/virtio/virtio-bus.h" #include "hw/virtio/virtio.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 /* #define DEBUG_VIRTIO_BUS */ =20 diff --git a/monitor/hmp-cmds-target.c b/monitor/hmp-cmds-target.c index 6654d31406..011a367357 100644 --- a/monitor/hmp-cmds-target.c +++ b/monitor/hmp-cmds-target.c @@ -24,7 +24,7 @@ =20 #include "qemu/osdep.h" #include "disas/disas.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/memory.h" #include "monitor/hmp-target.h" #include "monitor/monitor-internal.h" diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c index 7ded3378cf..8ddcdd76c1 100644 --- a/monitor/hmp-cmds.c +++ b/monitor/hmp-cmds.c @@ -14,7 +14,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "exec/ioport.h" #include "exec/gdbstub.h" #include "gdbstub/enums.h" diff --git a/system/ioport.c b/system/ioport.c index 2291739039..5300716464 100644 --- a/system/ioport.c +++ b/system/ioport.c @@ -28,7 +28,7 @@ #include "qemu/osdep.h" #include "exec/ioport.h" #include "system/memory.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "trace.h" =20 struct MemoryRegionPortioList { diff --git a/system/memory.c b/system/memory.c index 2865d0deb1..a4185ea353 100644 --- a/system/memory.c +++ b/system/memory.c @@ -33,7 +33,7 @@ #include "qemu/accel.h" #include "hw/boards.h" #include "migration/vmstate.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 //#define DEBUG_UNASSIGNED =20 diff --git a/system/memory_mapping.c b/system/memory_mapping.c index 8538a8241e..da708a08ab 100644 --- a/system/memory_mapping.c +++ b/system/memory_mapping.c @@ -17,7 +17,7 @@ =20 #include "system/memory_mapping.h" #include "system/memory.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/core/cpu.h" =20 //#define DEBUG_GUEST_PHYS_REGION_ADD diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 2439af63a0..93a3f9b53d 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -22,7 +22,7 @@ =20 #include =20 -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/boards.h" #include "hw/irq.h" #include "qemu/main-loop.h" diff --git a/target/arm/kvm.c b/target/arm/kvm.c index da30bdbb23..97de8c7e93 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -30,7 +30,7 @@ #include "internals.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "gdbstub/enums.h" #include "hw/boards.h" #include "hw/irq.h" diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0b14b36c17..1121822470 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,7 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/exec-all.h" #include "exec/translation-block.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c index c1708b04bb..242a05fdbe 100644 --- a/target/i386/cpu-apic.c +++ b/target/i386/cpu-apic.c @@ -14,7 +14,7 @@ #include "system/hw_accel.h" #include "system/kvm.h" #include "system/xen.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/qdev-properties.h" #include "hw/i386/apic_internal.h" #include "cpu-internal.h" diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1b64ceaaba..dba1b3ffef 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -38,7 +38,7 @@ #ifndef CONFIG_USER_ONLY #include "system/reset.h" #include "qapi/qapi-commands-machine-target.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c index e81a245881..b23010374f 100644 --- a/target/i386/kvm/xen-emu.c +++ b/target/i386/kvm/xen-emu.c @@ -17,7 +17,7 @@ #include "system/kvm_int.h" #include "system/kvm_xen.h" #include "kvm/kvm_i386.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "xen-emu.h" #include "trace.h" #include "system/runstate.h" diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 04e5f7e637..91f0e32366 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -9,7 +9,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "exec/ioport.h" #include "qemu/accel.h" #include "system/nvmm.h" diff --git a/target/i386/sev.c b/target/i386/sev.c index 0e1dbb6959..ba88976e9f 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -39,7 +39,7 @@ #include "qapi/qapi-commands-misc-target.h" #include "confidential-guest.h" #include "hw/i386/pc.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "qemu/queue.h" =20 OBJECT_DECLARE_TYPE(SevCommonState, SevCommonStateClass, SEV_COMMON) diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/= misc_helper.c index ce18c75b9f..0555cf2604 100644 --- a/target/i386/tcg/system/misc_helper.c +++ b/target/i386/tcg/system/misc_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "exec/cputlb.h" #include "tcg/helper-tcg.h" #include "hw/i386/apic.h" diff --git a/target/i386/tcg/system/tcg-cpu.c b/target/i386/tcg/system/tcg-= cpu.c index 13a3507863..ab1f3c7c59 100644 --- a/target/i386/tcg/system/tcg-cpu.c +++ b/target/i386/tcg/system/tcg-cpu.c @@ -23,7 +23,7 @@ =20 #include "system/system.h" #include "qemu/units.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 #include "tcg/tcg-cpu.h" =20 diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 41fb8c5a4e..d58cb11cee 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -10,7 +10,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "exec/ioport.h" #include "gdbstub/helpers.h" #include "qemu/accel.h" diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index f0e3cfef03..1bda570482 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -18,7 +18,7 @@ #include "system/kvm_int.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/boards.h" #include "hw/irq.h" #include "hw/loongarch/virt.h" diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 0f4997a918..5315134e08 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -35,7 +35,7 @@ #include "accel/accel-cpu-target.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/boards.h" #include "hw/irq.h" #include "hw/intc/riscv_imsic.h" diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index d8f483898d..b079d120db 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -17,7 +17,7 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "cpu.h" #include "s390x-internal.h" #include "kvm/kvm_s390x.h" diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index 6a4d9c5081..a3347f1236 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -14,7 +14,7 @@ #include "hw/boards.h" #include "system/hw_accel.h" #include "system/runstate.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "exec/cputlb.h" #include "exec/exec-all.h" #include "system/tcg.h" diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index f969850f87..ac733f407f 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -28,7 +28,7 @@ #include "tcg_s390x.h" #ifndef CONFIG_USER_ONLY #include "qemu/timer.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "hw/s390x/ioinst.h" #include "hw/s390x/s390_flic.h" #include "hw/boards.h" diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 5546c82ecd..163a1ffc7b 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -31,7 +31,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" =20 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) { diff --git a/hw/display/apple-gfx.m b/hw/display/apple-gfx.m index c4323574e1..2ff1c90df7 100644 --- a/hw/display/apple-gfx.m +++ b/hw/display/apple-gfx.m @@ -18,7 +18,7 @@ #include "qapi/visitor.h" #include "qapi/error.h" #include "block/aio-wait.h" -#include "exec/address-spaces.h" +#include "system/address-spaces.h" #include "system/dma.h" #include "migration/blocker.h" #include "ui/console.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350268; cv=none; d=zohomail.com; s=zohoarc; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/display/vga_int.h | 2 +- include/hw/char/parallel-isa.h | 2 +- include/hw/dma/i8257.h | 2 +- include/hw/ide/ide-bus.h | 2 +- include/hw/isa/isa.h | 2 +- include/{exec =3D> system}/ioport.h | 6 ++---- hw/block/fdc-isa.c | 2 +- monitor/hmp-cmds.c | 2 +- system/ioport.c | 2 +- system/physmem.c | 2 +- system/qtest.c | 2 +- target/i386/nvmm/nvmm-all.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- tests/qtest/fuzz/qtest_wrappers.c | 2 +- MAINTAINERS | 2 +- 15 files changed, 16 insertions(+), 18 deletions(-) rename include/{exec =3D> system}/ioport.h (97%) diff --git a/hw/display/vga_int.h b/hw/display/vga_int.h index 60ad26e03e..747b5cc6cf 100644 --- a/hw/display/vga_int.h +++ b/hw/display/vga_int.h @@ -26,7 +26,7 @@ #define HW_VGA_INT_H =20 #include "ui/console.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "system/memory.h" =20 #include "hw/display/bochs-vbe.h" diff --git a/include/hw/char/parallel-isa.h b/include/hw/char/parallel-isa.h index 5284b2ffec..3edaf9dbe4 100644 --- a/include/hw/char/parallel-isa.h +++ b/include/hw/char/parallel-isa.h @@ -12,7 +12,7 @@ =20 #include "parallel.h" =20 -#include "exec/ioport.h" +#include "system/ioport.h" #include "hw/isa/isa.h" #include "qom/object.h" =20 diff --git a/include/hw/dma/i8257.h b/include/hw/dma/i8257.h index 4342e4a91e..33b6286d5a 100644 --- a/include/hw/dma/i8257.h +++ b/include/hw/dma/i8257.h @@ -2,7 +2,7 @@ #define HW_I8257_H =20 #include "hw/isa/isa.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "qom/object.h" =20 #define TYPE_I8257 "i8257" diff --git a/include/hw/ide/ide-bus.h b/include/hw/ide/ide-bus.h index 4841a7dcd6..121b455fcd 100644 --- a/include/hw/ide/ide-bus.h +++ b/include/hw/ide/ide-bus.h @@ -1,7 +1,7 @@ #ifndef HW_IDE_BUS_H #define HW_IDE_BUS_H =20 -#include "exec/ioport.h" +#include "system/ioport.h" #include "hw/ide/ide-dev.h" #include "hw/ide/ide-dma.h" =20 diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h index 1d852011b3..a82c5f1004 100644 --- a/include/hw/isa/isa.h +++ b/include/hw/isa/isa.h @@ -4,7 +4,7 @@ /* ISA bus */ =20 #include "system/memory.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "hw/qdev-core.h" #include "qom/object.h" =20 diff --git a/include/exec/ioport.h b/include/system/ioport.h similarity index 97% rename from include/exec/ioport.h rename to include/system/ioport.h index ecea3575bc..780ea5a676 100644 --- a/include/exec/ioport.h +++ b/include/system/ioport.h @@ -21,8 +21,8 @@ * IO ports API */ =20 -#ifndef IOPORT_H -#define IOPORT_H +#ifndef SYSTEM_IOPORT_H +#define SYSTEM_IOPORT_H =20 #include "system/memory.h" =20 @@ -39,9 +39,7 @@ typedef struct MemoryRegionPortio { =20 #define PORTIO_END_OF_LIST() { } =20 -#ifndef CONFIG_USER_ONLY extern const MemoryRegionOps unassigned_io_ops; -#endif =20 void cpu_outb(uint32_t addr, uint8_t val); void cpu_outw(uint32_t addr, uint16_t val); diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c index a10c24aab1..561cfa47c1 100644 --- a/hw/block/fdc-isa.c +++ b/hw/block/fdc-isa.c @@ -42,7 +42,7 @@ #include "system/block-backend.h" #include "system/blockdev.h" #include "system/system.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "qemu/log.h" #include "qemu/main-loop.h" #include "qemu/module.h" diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c index 8ddcdd76c1..74a0f56566 100644 --- a/monitor/hmp-cmds.c +++ b/monitor/hmp-cmds.c @@ -15,7 +15,7 @@ =20 #include "qemu/osdep.h" #include "system/address-spaces.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "exec/gdbstub.h" #include "gdbstub/enums.h" #include "monitor/hmp.h" diff --git a/system/ioport.c b/system/ioport.c index 5300716464..4f96e9119f 100644 --- a/system/ioport.c +++ b/system/ioport.c @@ -26,7 +26,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "system/memory.h" #include "system/address-spaces.h" #include "trace.h" diff --git a/system/physmem.c b/system/physmem.c index e61fea41b5..234e489199 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -51,7 +51,7 @@ #include "qemu/memalign.h" #include "qemu/memfd.h" #include "system/memory.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "system/dma.h" #include "system/hostmem.h" #include "system/hw_accel.h" diff --git a/system/qtest.c b/system/qtest.c index 5407289154..523a047995 100644 --- a/system/qtest.c +++ b/system/qtest.c @@ -16,7 +16,7 @@ #include "system/qtest.h" #include "system/runstate.h" #include "chardev/char-fe.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "system/memory.h" #include "exec/tswap.h" #include "hw/qdev-core.h" diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 91f0e32366..17394d073d 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -10,7 +10,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "system/address-spaces.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "qemu/accel.h" #include "system/nvmm.h" #include "system/cpus.h" diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index d58cb11cee..b64852e13e 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -11,7 +11,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "system/address-spaces.h" -#include "exec/ioport.h" +#include "system/ioport.h" #include "gdbstub/helpers.h" #include "qemu/accel.h" #include "system/whpx.h" diff --git a/tests/qtest/fuzz/qtest_wrappers.c b/tests/qtest/fuzz/qtest_wra= ppers.c index 0580f8df86..d7adcbe3fd 100644 --- a/tests/qtest/fuzz/qtest_wrappers.c +++ b/tests/qtest/fuzz/qtest_wrappers.c @@ -13,7 +13,7 @@ =20 #include "qemu/osdep.h" #include "hw/core/cpu.h" -#include "exec/ioport.h" +#include "system/ioport.h" =20 #include "fuzz.h" =20 diff --git a/MAINTAINERS b/MAINTAINERS index 163814b4c6..fa4bbc2b7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3105,7 +3105,7 @@ M: Peter Xu M: David Hildenbrand R: Philippe Mathieu-Daud=C3=A9 S: Supported -F: include/exec/ioport.h +F: include/system/ioport.h F: include/exec/memop.h F: include/system/memory.h F: include/exec/ram_addr.h --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/{exec =3D> system}/ram_addr.h | 7 +++---- accel/kvm/kvm-all.c | 2 +- accel/tcg/cputlb.c | 2 +- accel/tcg/translate-all.c | 2 +- hw/ppc/spapr.c | 2 +- hw/ppc/spapr_caps.c | 2 +- hw/ppc/spapr_pci.c | 2 +- hw/remote/memory.c | 2 +- hw/remote/proxy-memory-listener.c | 2 +- hw/s390x/s390-stattrib-kvm.c | 2 +- hw/s390x/s390-stattrib.c | 2 +- hw/s390x/s390-virtio-ccw.c | 2 +- hw/vfio/common.c | 3 +-- hw/vfio/container.c | 2 +- hw/vfio/spapr.c | 2 +- hw/virtio/virtio-mem.c | 2 +- migration/ram.c | 2 +- system/memory.c | 2 +- system/physmem.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/ppc/kvm.c | 2 +- target/s390x/kvm/kvm.c | 2 +- MAINTAINERS | 2 +- 23 files changed, 25 insertions(+), 27 deletions(-) rename include/{exec =3D> system}/ram_addr.h (99%) diff --git a/include/exec/ram_addr.h b/include/system/ram_addr.h similarity index 99% rename from include/exec/ram_addr.h rename to include/system/ram_addr.h index 8677761af5..3b81c3091f 100644 --- a/include/exec/ram_addr.h +++ b/include/system/ram_addr.h @@ -16,10 +16,9 @@ * The functions declared here will be removed soon. */ =20 -#ifndef RAM_ADDR_H -#define RAM_ADDR_H +#ifndef SYSTEM_RAM_ADDR_H +#define SYSTEM_RAM_ADDR_H =20 -#ifndef CONFIG_USER_ONLY #include "system/xen.h" #include "system/tcg.h" #include "exec/cputlb.h" @@ -559,5 +558,5 @@ uint64_t cpu_physical_memory_sync_dirty_bitmap(RAMBlock= *rb, =20 return num_dirty; } -#endif + #endif diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 0d47bb0d9b..0723a3933b 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -34,7 +34,7 @@ #include "system/accel-blocker.h" #include "qemu/bswap.h" #include "system/memory.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "qemu/event_notifier.h" #include "qemu/main-loop.h" #include "trace.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6f0ea9067b..134e523cab 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -27,7 +27,7 @@ #include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/memory-internal.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "exec/mmu-access-type.h" #include "exec/tlb-common.h" #include "exec/vaddr.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 16e5043597..167535bcb1 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -40,7 +40,7 @@ #endif #endif #else -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #endif =20 #include "exec/cputlb.h" diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b0a0f8c689..e0e7509c59 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -77,7 +77,7 @@ #include "hw/virtio/virtio-scsi.h" #include "hw/virtio/vhost-scsi-common.h" =20 -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "system/confidential-guest-support.h" #include "hw/usb.h" #include "qemu/config-file.h" diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 815c94ed2f..f2f5722d8a 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -27,7 +27,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "system/hw_accel.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "target/ppc/cpu.h" #include "target/ppc/mmu-hash64.h" #include "cpu-models.h" diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index e0a9d50edc..384269b831 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -34,7 +34,7 @@ #include "hw/pci/pci_host.h" #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include #include "trace.h" #include "qemu/error-report.h" diff --git a/hw/remote/memory.c b/hw/remote/memory.c index 6d60da91e0..00193a552f 100644 --- a/hw/remote/memory.c +++ b/hw/remote/memory.c @@ -11,7 +11,7 @@ #include "qemu/osdep.h" =20 #include "hw/remote/memory.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "qapi/error.h" =20 static void remote_sysmem_reset(void) diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-lis= tener.c index ce7f5b9bfb..30ac74961d 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -12,7 +12,7 @@ #include "qemu/range.h" #include "system/memory.h" #include "exec/cpu-common.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/remote/mpqemu-link.h" diff --git a/hw/s390x/s390-stattrib-kvm.c b/hw/s390x/s390-stattrib-kvm.c index 2a8e31718b..f5695b0e53 100644 --- a/hw/s390x/s390-stattrib-kvm.c +++ b/hw/s390x/s390-stattrib-kvm.c @@ -16,7 +16,7 @@ #include "qemu/error-report.h" #include "system/kvm.h" #include "system/memory_mapping.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "kvm/kvm_s390x.h" #include "qapi/error.h" =20 diff --git a/hw/s390x/s390-stattrib.c b/hw/s390x/s390-stattrib.c index be07c28c6e..d95b58a8a8 100644 --- a/hw/s390x/s390-stattrib.c +++ b/hw/s390x/s390-stattrib.c @@ -16,7 +16,7 @@ #include "hw/qdev-properties.h" #include "hw/s390x/storage-attributes.h" #include "qemu/error-report.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "qapi/error.h" #include "qobject/qdict.h" #include "cpu.h" diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 75b32182eb..81e570905e 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -13,7 +13,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "system/confidential-guest-support.h" #include "hw/boards.h" #include "hw/s390x/sclp.h" diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 98832af88d..bae0633c3d 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -29,8 +29,7 @@ #include "hw/vfio/pci.h" #include "system/address-spaces.h" #include "system/memory.h" -#include "exec/ram_addr.h" -#include "exec/target_page.h" +#include "system/ram_addr.h" #include "hw/hw.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/hw/vfio/container.c b/hw/vfio/container.c index 2e993c7e73..812d5edbcf 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -25,7 +25,7 @@ #include "hw/vfio/vfio-common.h" #include "system/address-spaces.h" #include "system/memory.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "qemu/error-report.h" #include "qemu/range.h" #include "system/reset.h" diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c index c9a7dd8d68..66a2d2bb0d 100644 --- a/hw/vfio/spapr.c +++ b/hw/vfio/spapr.c @@ -17,7 +17,7 @@ =20 #include "hw/vfio/vfio-common.h" #include "hw/hw.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "trace.h" diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index 5f57eccbb6..c7968ee0c6 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -24,7 +24,7 @@ #include "hw/virtio/virtio-mem.h" #include "qapi/error.h" #include "qapi/visitor.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "migration/misc.h" #include "hw/boards.h" #include "hw/qdev-properties.h" diff --git a/migration/ram.c b/migration/ram.c index 424df6d9f1..6295f675df 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -48,7 +48,7 @@ #include "qapi/qapi-commands-migration.h" #include "qapi/qmp/qerror.h" #include "trace.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "exec/target_page.h" #include "qemu/rcu_queue.h" #include "migration/colo.h" diff --git a/system/memory.c b/system/memory.c index a4185ea353..6a5d853071 100644 --- a/system/memory.c +++ b/system/memory.c @@ -26,7 +26,7 @@ #include "trace.h" =20 #include "exec/memory-internal.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "system/kvm.h" #include "system/runstate.h" #include "system/tcg.h" diff --git a/system/physmem.c b/system/physmem.c index 234e489199..307d0764b6 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -67,7 +67,7 @@ #include "system/replay.h" =20 #include "exec/memory-internal.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" =20 #include "qemu/pmem.h" =20 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 5d6d8a17ae..80164a8050 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -27,7 +27,7 @@ #include "user/cpu_loop.h" #include "user/page-protection.h" #else -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #endif #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 992356cb75..8b12b8e7d2 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -41,7 +41,7 @@ #include "trace.h" #include "gdbstub/enums.h" #include "exec/memattrs.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "system/hostmem.h" #include "qemu/cutils.h" #include "qemu/main-loop.h" diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 4d56e653dd..b9f1422197 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -41,7 +41,7 @@ #include "system/runstate.h" #include "system/device_tree.h" #include "gdbstub/enums.h" -#include "exec/ram_addr.h" +#include "system/ram_addr.h" #include "trace.h" #include "hw/s390x/s390-pci-inst.h" #include "hw/s390x/s390-pci-bus.h" diff --git a/MAINTAINERS b/MAINTAINERS index fa4bbc2b7c..afacc10ac2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3108,7 +3108,7 @@ S: Supported F: include/system/ioport.h F: include/exec/memop.h F: include/system/memory.h -F: include/exec/ram_addr.h +F: include/system/ram_addr.h F: include/exec/ramblock.h F: include/system/memory_mapping.h F: system/dma-helpers.c --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/system/ram_addr.h | 2 +- include/{exec =3D> system}/ramblock.h | 9 ++++----- hw/display/virtio-gpu-udmabuf.c | 2 +- hw/hyperv/hv-balloon.c | 2 +- hw/virtio/vhost-user.c | 2 +- migration/dirtyrate.c | 2 +- migration/file.c | 2 +- migration/multifd-nocomp.c | 2 +- migration/multifd-qatzip.c | 2 +- migration/multifd-qpl.c | 2 +- migration/multifd-uadk.c | 2 +- migration/multifd-zero-page.c | 2 +- migration/multifd-zlib.c | 2 +- migration/multifd-zstd.c | 2 +- migration/multifd.c | 2 +- migration/postcopy-ram.c | 2 +- tests/qtest/fuzz/generic_fuzz.c | 2 +- MAINTAINERS | 2 +- 18 files changed, 21 insertions(+), 22 deletions(-) rename include/{exec =3D> system}/ramblock.h (96%) diff --git a/include/system/ram_addr.h b/include/system/ram_addr.h index 3b81c3091f..b4e4425acb 100644 --- a/include/system/ram_addr.h +++ b/include/system/ram_addr.h @@ -23,7 +23,7 @@ #include "system/tcg.h" #include "exec/cputlb.h" #include "exec/ramlist.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "exec/exec-all.h" #include "system/memory.h" #include "exec/target_page.h" diff --git a/include/exec/ramblock.h b/include/system/ramblock.h similarity index 96% rename from include/exec/ramblock.h rename to include/system/ramblock.h index 64484cd821..d8a116ba99 100644 --- a/include/exec/ramblock.h +++ b/include/system/ramblock.h @@ -16,11 +16,10 @@ * The functions declared here will be removed soon. */ =20 -#ifndef QEMU_EXEC_RAMBLOCK_H -#define QEMU_EXEC_RAMBLOCK_H +#ifndef SYSTEM_RAMBLOCK_H +#define SYSTEM_RAMBLOCK_H =20 -#ifndef CONFIG_USER_ONLY -#include "cpu-common.h" +#include "exec/cpu-common.h" #include "qemu/rcu.h" #include "exec/ramlist.h" =20 @@ -91,5 +90,5 @@ struct RAMBlock { */ ram_addr_t postcopy_length; }; -#endif + #endif diff --git a/hw/display/virtio-gpu-udmabuf.c b/hw/display/virtio-gpu-udmabu= f.c index 85ca23cb32..0510577475 100644 --- a/hw/display/virtio-gpu-udmabuf.c +++ b/hw/display/virtio-gpu-udmabuf.c @@ -19,7 +19,7 @@ #include "hw/virtio/virtio-gpu.h" #include "hw/virtio/virtio-gpu-pixman.h" #include "trace.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "system/hostmem.h" #include #include diff --git a/hw/hyperv/hv-balloon.c b/hw/hyperv/hv-balloon.c index 0b1da723c8..acabff2c4a 100644 --- a/hw/hyperv/hv-balloon.c +++ b/hw/hyperv/hv-balloon.c @@ -12,7 +12,7 @@ =20 #include "system/address-spaces.h" #include "exec/cpu-common.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "hw/boards.h" #include "hw/hyperv/dynmem-proto.h" #include "hw/hyperv/hv-balloon.h" diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c index 267b612587..48561d3c74 100644 --- a/hw/virtio/vhost-user.c +++ b/hw/virtio/vhost-user.c @@ -28,7 +28,7 @@ #include "system/cryptodev.h" #include "migration/postcopy-ram.h" #include "trace.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" =20 #include #include diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c index 09caf92f87..986624c79a 100644 --- a/migration/dirtyrate.c +++ b/migration/dirtyrate.c @@ -14,7 +14,7 @@ #include "qemu/error-report.h" #include "hw/core/cpu.h" #include "qapi/error.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "exec/target_page.h" #include "qemu/rcu_queue.h" #include "qemu/main-loop.h" diff --git a/migration/file.c b/migration/file.c index 7f11e26f5c..bb8031e3c7 100644 --- a/migration/file.c +++ b/migration/file.c @@ -6,7 +6,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "qemu/cutils.h" #include "qemu/error-report.h" #include "qapi/error.h" diff --git a/migration/multifd-nocomp.c b/migration/multifd-nocomp.c index ffe75256c9..94f248e8a2 100644 --- a/migration/multifd-nocomp.c +++ b/migration/multifd-nocomp.c @@ -11,7 +11,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "exec/target_page.h" #include "file.h" #include "migration-stats.h" diff --git a/migration/multifd-qatzip.c b/migration/multifd-qatzip.c index 6a0e989fae..7419e5dc0d 100644 --- a/migration/multifd-qatzip.c +++ b/migration/multifd-qatzip.c @@ -13,7 +13,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qapi/qapi-types-migration.h" diff --git a/migration/multifd-qpl.c b/migration/multifd-qpl.c index 88e2344af2..52902eb00c 100644 --- a/migration/multifd-qpl.c +++ b/migration/multifd-qpl.c @@ -14,7 +14,7 @@ #include "qemu/module.h" #include "qapi/error.h" #include "qapi/qapi-types-migration.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "multifd.h" #include "qpl/qpl.h" =20 diff --git a/migration/multifd-uadk.c b/migration/multifd-uadk.c index 6895c1f65a..fd7cd9b5e8 100644 --- a/migration/multifd-uadk.c +++ b/migration/multifd-uadk.c @@ -13,7 +13,7 @@ #include "qemu/osdep.h" #include "qemu/module.h" #include "qapi/error.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "migration.h" #include "multifd.h" #include "options.h" diff --git a/migration/multifd-zero-page.c b/migration/multifd-zero-page.c index f1e988a959..dbc1184921 100644 --- a/migration/multifd-zero-page.c +++ b/migration/multifd-zero-page.c @@ -12,7 +12,7 @@ =20 #include "qemu/osdep.h" #include "qemu/cutils.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "migration.h" #include "migration-stats.h" #include "multifd.h" diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index 8cf8a26bb4..8820b2a787 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -13,7 +13,7 @@ #include "qemu/osdep.h" #include #include "qemu/rcu.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "exec/target_page.h" #include "qapi/error.h" #include "migration.h" diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c index abed140855..3c2dcf76b0 100644 --- a/migration/multifd-zstd.c +++ b/migration/multifd-zstd.c @@ -13,7 +13,7 @@ #include "qemu/osdep.h" #include #include "qemu/rcu.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "exec/target_page.h" #include "qapi/error.h" #include "migration.h" diff --git a/migration/multifd.c b/migration/multifd.c index dfb5189f0e..86c83e43c0 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -16,7 +16,7 @@ #include "qemu/rcu.h" #include "exec/target_page.h" #include "system/system.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "file.h" diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c index 5d3edfcfec..995614b38c 100644 --- a/migration/postcopy-ram.c +++ b/migration/postcopy-ram.c @@ -31,7 +31,7 @@ #include "qemu/error-report.h" #include "trace.h" #include "hw/boards.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "socket.h" #include "yank_functions.h" #include "tls.h" diff --git a/tests/qtest/fuzz/generic_fuzz.c b/tests/qtest/fuzz/generic_fuz= z.c index 239be9372d..507de74806 100644 --- a/tests/qtest/fuzz/generic_fuzz.c +++ b/tests/qtest/fuzz/generic_fuzz.c @@ -21,7 +21,7 @@ #include "fuzz.h" #include "string.h" #include "system/memory.h" -#include "exec/ramblock.h" +#include "system/ramblock.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" #include "hw/pci/pci_device.h" diff --git a/MAINTAINERS b/MAINTAINERS index afacc10ac2..e0dc64aa3e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3109,7 +3109,7 @@ F: include/system/ioport.h F: include/exec/memop.h F: include/system/memory.h F: include/system/ram_addr.h -F: include/exec/ramblock.h +F: include/system/ramblock.h F: include/system/memory_mapping.h F: system/dma-helpers.c F: system/ioport.c --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087df21278sm9146865a91.29.2025.04.22.12.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350126; x=1745954926; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hSTxcdVupVH5RULwmr3LUReRVWUe6351QoWFFPPNbok=; b=ldLjh9a++GRUYT+CAJFW0bOPn6rIKB+56VjD8k4+1lrwcZwGjTJlD37FeOyyY+2U1P 3zaL+z2H2CtiZVJWUWPYrHErt7avHJozAgcf+pzd17kfChLCU+AgG0MsX419Gk2SC1w2 tbd1BQA0a8y/7wfby2Djz0QRfoF4Ey7OrOZ/HG4P7XKX1GB917geMahsXwBaxd+QRlpZ MG7hVzNHPIhedbh20dnV0fb7a522BCo8a/5rr+fAWK75RTG2yVJXSiN2HnTz+HlSJxG3 yhhYE21QOdCmyA1b+cRX5QQ4ncvE+PCD1VZ55tL3hfh5n05TiAM+vXAFF8Ai/hRphj8K 7H5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350126; x=1745954926; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hSTxcdVupVH5RULwmr3LUReRVWUe6351QoWFFPPNbok=; b=okZjv0ZkNGL8uDMOePUHTtySmDZRe9nEBjA3cCc05axQDndt5YbVw+BV5ZT5iSbPOv /4cjaEXO/jI0YSa5mvQxkBquiyHxdObweP0pVXfE1+4SDZ8uHQ+Yx+5Gi2jXyeAPJBNc m06aEv2An5RZU7m7ubIPR8RJbdQHPtbeDxJ6/RsJQLdjeMcXXma7HHagR6vK+rvXyFkU fw6plp3glro26OYrEh3xmpQRqg8yhE8Xn7Wn3b2k6xYySg+C5Xldy+0anvWrTCCioyfq icH7ojNBO4778uvX3sAm9mi/3RFoZ6W3KrSg71gId1/F2aiGKxFWzWKjSLXOTUgs5saY 08/g== X-Gm-Message-State: AOJu0Yzm5s+QGOLavKRcD5xZxZaY5ihUXcFk7TbfrN706J2RmEpChD2V 1a05KCCS2rjeCdEet1++PeUzFVFTrh0FJvl+MjzKdFzLWcaJX04YTZscJh1DWnqQ0FyMwtVrydF 1 X-Gm-Gg: ASbGncsI3CZcBHl/+fQyNAgNNbRORFHQVB2rC4zsaYvIL3HaAML8PG6v54s2ZzJOVct cRwZ94TaYD2JYjhSFpNcAfwKwSuzvhzGSs3phlAUZExVdid6XmCBIAzgcV8D8H5zP2Mrr0tHcuE 8k/TGk2m0nFfgNifEQp9rBoIwj1LcVTEBKgsTQ635bgJw0pwLzAPtD1P2AitRZzIbNJ0zEHVXAq PRXFQHTZr/CS+BM6JVbZbVv/xIdNOPTDdiPJtFezNhcPcYnZ7v4H4hRI3bVJk427OzJ9ilNpGyD rG5JLPg4zp1yKKO6/DzI5GtG9HOzyFnUe712rnI06qdzXeQPdO9juzqNaXysQ7+MAfb2AOhkRMc BlKa6a+VA1Q== X-Google-Smtp-Source: AGHT+IE2L8jQekGi3bZ+iuQu940NpUCQSoIQIyIOzEkCM6Yd/Q43rZqH+3oiZEc0tRg2lyWSQMhQIQ== X-Received: by 2002:a17:90b:2752:b0:301:a0e9:66f with SMTP id 98e67ed59e1d1-3087bb579cdmr25356534a91.14.1745350126491; Tue, 22 Apr 2025 12:28:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , David Hildenbrand Subject: [PATCH 039/147] accel/tcg: Remove unnecesary inclusion of memory-internal.h in cputlb.c Date: Tue, 22 Apr 2025 12:26:28 -0700 Message-ID: <20250422192819.302784-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350260631019100 From: Philippe Mathieu-Daud=C3=A9 At some point cputlb.c stopped depending on the "exec/memory-internal.h" header. Clean that now. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson Message-ID: <20250317161329.40300-2-philmd@linaro.org> --- accel/tcg/cputlb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 134e523cab..613f919fff 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -26,7 +26,6 @@ #include "exec/cpu_ldst.h" #include "exec/cputlb.h" #include "exec/tb-flush.h" -#include "exec/memory-internal.h" #include "system/ram_addr.h" #include "exec/mmu-access-type.h" #include "exec/tlb-common.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350558; cv=none; d=zohomail.com; s=zohoarc; b=cUutfper+Y1xyUAhNVRcPVAhsQUSsQE8x5GA10XU7LG98GxPeIddSYl1l8L9vJtLHLJ7SRW/Gl553w8K/KOo0BUL7J7IWTtKC4bEE5lICJKQTmxOICNwXwm054sWFk3osWzdI4tbxkcHzQfwF8E446TzPfWpawhl9+MKdFJHcUs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350558; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D18VcATJhF8EFEqTXXDGcua3PJA4kTwRczbppkM1bEY=; b=aaEKxL5VOZxDkRcpa/1dFVjTpDzT+Wji2XqBfazQe+OcU0egtaDr4uwwltt4Jfvf49QtyE1KroLtCIKHBQpj23AxKdf2ZH6ZMW7nEmxEQdXjpqnQWNivKg/zovHVJz+5imW1CEnjHGjPdPDOtogdF9ZjuXbGmVANB+/GkkRlAak= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350558682215.7694196839517; Tue, 22 Apr 2025 12:35:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JLo-0000pq-8d; Tue, 22 Apr 2025 15:32:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLU-0008RK-7l for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:52 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLR-0006aX-As for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:51 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-22438c356c8so59088945ad.1 for ; Tue, 22 Apr 2025 12:31:48 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350307; x=1745955107; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D18VcATJhF8EFEqTXXDGcua3PJA4kTwRczbppkM1bEY=; b=PNMp0MPNJsnzvWgo21PNpCubqA6bxV4oTfzHnlnuSEwetVgDKIaaBCbrXPCdoAJKxT KS+MnKKj2Cy43XbR49KOvY1nStkV8y+0jYJkCSFgPfbw1Tf9Kf1qnHAeXhalLCQlaxnV D3eJxuiSr66NjKAy6DkcV/8l4Frl1zQFRYu0h2ekQRWDUeLDWrU9m1hlsYqQocLl4UGB avtqbceLScQPy0j6BFVfopeZgYavaN/ZYUKx64eLD0verB6pc+FFRmwsXWecXtYbKEXA tYBJT0gl6S7a9EO8ZtTOIzy3fXCV6sG/sh7ofyBfIs8ZzVOCREwb76KZ532HpeoFt1Cl fuIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350307; x=1745955107; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D18VcATJhF8EFEqTXXDGcua3PJA4kTwRczbppkM1bEY=; b=cTtLCCOPYMsWk6Tt/pdWubuTnxNsPQdGyq9sDM6kzdC54g7deznjAMz12PXaryQWfw ZKVFIk04wgIRKYLmntXaz4V+vufRx0Kd02JbGkzOlP/lmFRzmEc8MNERcTFS8ilFC8Gd wloR4R5l96ujGanx351VTc/nE2HlPG/owmV+mujhJqBP3nHN/z/SZzA3KZ2uoXC1TfYZ u2mej97qJ/rWQfZWrj08dZCcgyK0K73C8RlhZuNTlY5ctYo4lY6E8wSloDR7ntBt3WOk 2UYRtkU1WHJaJbRvrFwfgsjX0JX5ku575UmqJN9pIHi9jjTbF8VonSMFZDu6HCGL9kP7 vYFg== X-Gm-Message-State: AOJu0YwdzDiLTV4ugAgNOtbzI3T5mx7XQ/2PlwNS1W60R3IQshsufWmq 6Dg9CKq5N14xISewo6Iz6eD8ABpJprgfEYkzQVCfIQ0tZ5NwIDmq5p9HQbFN2UMlA4JXsy7uP+T Y X-Gm-Gg: ASbGncuXmNiogWjqBJo+RjRsqQHExBVEHtwgKHgfsEcG7kBZqOAGps+jAgKFS/hkrae 6h5utzWWgiAw6i7bqpc2l2a6ziAwaqAg8N7s0ZoAYKolUpfmsAuvUu7uGqu2tigRKr95oHr5lMD KWFNUzdKIajzkQf97fdF61VYwnTSQHKwQglx8IOmMATpIc766gSJD/tkDGMnk56ZRmBXAvQ6+db GDqoC3MkHYUVljxRaAflFh6dCcU6nt58d5alpnRAFL+NVr8fAV+aCZ6xK9H3xliPRsZe2Y+lZiE D09V9ntG0CJakH9mRFjlrlgiBaTQKBA+lGxl+jYJGZvCzIX2gh2zqt0zxhmNfnzhfo+ZMUinlX8 = X-Google-Smtp-Source: AGHT+IFi2gOqrZWXIZ2s3xc4AD/2pNQDdy4Sfmt/zXrxwzlOuT5NRtXB9ivtXdWU20g5oHSjoZhPFw== X-Received: by 2002:a17:903:11c6:b0:215:b75f:a1cb with SMTP id d9443c01a7336-22c53573db0mr239222625ad.9.1745350307616; Tue, 22 Apr 2025 12:31:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand Subject: [PATCH 040/147] exec: Restrict memory-internal.h to system/ Date: Tue, 22 Apr 2025 12:26:29 -0700 Message-ID: <20250422192819.302784-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350560216019000 From: Philippe Mathieu-Daud=C3=A9 Only file units within the system/ directory need access to "memory-internal.h". Restrict its scope by moving it there. The comment from commit 9d70618c684 ("memory-internal.h: Remove obsolete claim that header is obsolete") is now obsolete, remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson Message-ID: <20250317161329.40300-3-philmd@linaro.org> --- {include/exec =3D> system}/memory-internal.h | 6 ------ system/memory.c | 4 ++-- system/physmem.c | 3 ++- MAINTAINERS | 2 +- 4 files changed, 5 insertions(+), 10 deletions(-) rename {include/exec =3D> system}/memory-internal.h (88%) diff --git a/include/exec/memory-internal.h b/system/memory-internal.h similarity index 88% rename from include/exec/memory-internal.h rename to system/memory-internal.h index c75178a3d6..085e81a9fe 100644 --- a/include/exec/memory-internal.h +++ b/system/memory-internal.h @@ -11,12 +11,6 @@ * */ =20 -/* - * This header is for use by exec.c, memory.c and accel/tcg/cputlb.c ONLY, - * for declarations which are shared between the memory subsystem's - * internals and the TCG TLB code. Do not include it from elsewhere. - */ - #ifndef MEMORY_INTERNAL_H #define MEMORY_INTERNAL_H =20 diff --git a/system/memory.c b/system/memory.c index 6a5d853071..7e2f16f4e9 100644 --- a/system/memory.c +++ b/system/memory.c @@ -24,8 +24,6 @@ #include "qemu/qemu-print.h" #include "qom/object.h" #include "trace.h" - -#include "exec/memory-internal.h" #include "system/ram_addr.h" #include "system/kvm.h" #include "system/runstate.h" @@ -35,6 +33,8 @@ #include "migration/vmstate.h" #include "system/address-spaces.h" =20 +#include "memory-internal.h" + //#define DEBUG_UNASSIGNED =20 static unsigned memory_region_transaction_depth; diff --git a/system/physmem.c b/system/physmem.c index 307d0764b6..16cf557d1a 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -66,7 +66,6 @@ #include "qemu/main-loop.h" #include "system/replay.h" =20 -#include "exec/memory-internal.h" #include "system/ram_addr.h" =20 #include "qemu/pmem.h" @@ -88,6 +87,8 @@ #include #endif =20 +#include "memory-internal.h" + //#define DEBUG_SUBPAGE =20 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes diff --git a/MAINTAINERS b/MAINTAINERS index e0dc64aa3e..c7083ab1d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3116,7 +3116,7 @@ F: system/ioport.c F: system/memory.c F: system/memory_mapping.c F: system/physmem.c -F: include/exec/memory-internal.h +F: system/memory-internal.h F: scripts/coccinelle/memory-region-housekeeping.cocci =20 Memory devices --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351881; cv=none; d=zohomail.com; s=zohoarc; b=aIl0TcCN03DgC+pY6rNV6ke+Aasx+PfzXxNA9/2jNw6N49iL/hkM51ZauYSQIeclGaP6G8zAbCrbukB0upfird1+kGH2C5ggBMNgKeknYGjcs2z9IWKLhbk5OIlLpL+nQNpvQbnCYlABYUsgfVKvEb2KGOXNWHTEDoD5Tc7BZUw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351881; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RK0p9wQfVgEVzHTMYQneP9tRo6BI56q+RabGlzQyjiM=; b=HZK9XOXtXj2C9f21XIinKhD6QcuaTVBxJOuzVkati2PKsxKGeiz4cYpjiCX4qAz8z692YBbBvMTy7Oob7sFXCefOMBFs7B//WOt7d4C7CE2FmREgDO9FqFL+dOa3/qoQSSszswQ/uNWWDeLlW2gZ8p5qD+yA3nbUd8g034drmKI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351881167234.92501915137973; Tue, 22 Apr 2025 12:58:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JLa-0000Hj-I8; Tue, 22 Apr 2025 15:31:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLU-0008QE-3W for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:52 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLS-0006aZ-0G for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:51 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-22401f4d35aso62147115ad.2 for ; Tue, 22 Apr 2025 12:31:49 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350308; x=1745955108; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RK0p9wQfVgEVzHTMYQneP9tRo6BI56q+RabGlzQyjiM=; b=NjUhODq0wFg0Brnr5ilmupwcCAzGvoO5A5a2jmJbo84VxA777dRT+WWxTjujnQ9m6H yPG9cPSJmfISvG4rzUnaZz5OBBA5IAjWroWy+PSsjCTvs9oRTeMVuZduB/tSkiq+zfbo p+5HTrcy3Xgr3EOstxDJRaECPEU8CV5jYSpvPqXTDoplzE6Z5BRkz3wobMrB/pENDHME eE7qmtyqlFZaJOcYRDnHh6sc3+qk3oaY7fG8+1YZLB+SDUAizsdoC9anPdE+2XO7vA45 fJmpBvPibc5DRJofn3V3kFiJp24i9IIFh3bkOGKdQLl3MszpNhJCLqsW1bdvbw9DcVgV pI8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350308; x=1745955108; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RK0p9wQfVgEVzHTMYQneP9tRo6BI56q+RabGlzQyjiM=; b=GrIfiECI5OFggbjNa5SxP/mM4eGUfZgingkWD/DB7DgGnSUGagaGyLVFwSUR1W0HhX tBCXXn6CKsMRHgKskOq3scfZMiFxt0z1sGZ7BTOM8bgGcSFHGwVqKuhm02Ayq49ByjhG XtQm+gYXDHtmxDpnBJyzAhseITl0Tap+RXCZwtySgm7+2qc7MiH5FxeahfGGjnBmedFR N9PUEDgAfjQVh4fOeo+KFMi/+JmJNzKcw/ScTwaC/wVvXWaUW15UrvLNJsb8GE5lB3m1 2alayH6fqER9TtrhoRZ6g6aQjTDCyoZWqe6DEN2snDkrIyULIyQdTfoGbGuCI9cwDbS+ jFBA== X-Gm-Message-State: AOJu0YzwIzE+nnQH6FLxAU4NpySj3tnIT3j8LBPgYnXLfhKHg7Ealput PJKiBUAyZ2EWQ6hirQb7ejBf3rLxtwg9NbmHBCq6P6z9vSfYS1prxqUzEWLUbvJo4qzRqA6IVEz d X-Gm-Gg: ASbGnctjGkH8f3v3IpwFnp19gTH+xK65xeMmLCClWVr3qmvxgrAKyzyKi3maxcKUzmi ksoBCFHSGBBes3wMHQqF+gdkeslYsqxRO3B9o1hl879Df0CxWtAK85pjIe7eggbPreZ5xlGKU01 ps0f9zKFzV1TulWOL9hZMxDEk/LCakPzyVN7LUobSACt3BBBOqrfooe11PoOJe5EL9+rG2PZbw8 0nrHjRl7mrwff1JRFhOUpNEkyyp5zvHjnN76lsPdhswb6SuTBr/UPFszwhtZIdnvyvL0ZiTPEe7 s7KRpdN++G1g0Idqlt3LSIbbV/vU8FFy3fIJbsx1mq/Bv0OQrNV2beFgaGxeTOA0aU0jSgE/uzc = X-Google-Smtp-Source: AGHT+IGexOeAtuv+pWgvR5o9iU8zWslkGHMpbsYRBy3/u1CVMsZb/6FctPrNlkJhYDWZN4iTvniG0g== X-Received: by 2002:a17:903:250:b0:224:1ec0:8a0c with SMTP id d9443c01a7336-22c535acd5cmr253967455ad.29.1745350308249; Tue, 22 Apr 2025 12:31:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 041/147] meson: Introduce top-level libuser_ss and libsystem_ss Date: Tue, 22 Apr 2025 12:26:30 -0700 Message-ID: <20250422192819.302784-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351882427019100 Content-Type: text/plain; charset="utf-8" We already have two subdirectories for which we need to build files twice, for user vs system modes. Move this handling to the top level. This cannot be combined with user_ss or system_ss, because the formulation has not been extended to support configuration symbols. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- gdbstub/meson.build | 32 ++++++++------------------------ meson.build | 22 ++++++++++++++++++++++ tcg/meson.build | 23 ++--------------------- 3 files changed, 32 insertions(+), 45 deletions(-) diff --git a/gdbstub/meson.build b/gdbstub/meson.build index dff741ddd4..0e8099ae9c 100644 --- a/gdbstub/meson.build +++ b/gdbstub/meson.build @@ -4,32 +4,16 @@ # types such as hwaddr. # =20 -# We need to build the core gdb code via a library to be able to tweak -# cflags so: - -gdb_user_ss =3D ss.source_set() -gdb_system_ss =3D ss.source_set() - # We build two versions of gdbstub, one for each mode -gdb_user_ss.add(files('gdbstub.c', 'user.c')) -gdb_system_ss.add(files('gdbstub.c', 'system.c')) +libuser_ss.add(files( + 'gdbstub.c', + 'user.c' +)) =20 -gdb_user_ss =3D gdb_user_ss.apply({}) -gdb_system_ss =3D gdb_system_ss.apply({}) - -libgdb_user =3D static_library('gdb_user', - gdb_user_ss.sources() + genh, - c_args: '-DCONFIG_USER_ONLY', - build_by_default: false) - -libgdb_system =3D static_library('gdb_system', - gdb_system_ss.sources() + genh, - build_by_default: false) - -gdb_user =3D declare_dependency(objects: libgdb_user.extract_all_objects(r= ecursive: false)) -user_ss.add(gdb_user) -gdb_system =3D declare_dependency(objects: libgdb_system.extract_all_objec= ts(recursive: false)) -system_ss.add(gdb_system) +libsystem_ss.add(files( + 'gdbstub.c', + 'system.c' +)) =20 common_ss.add(files('syscalls.c')) =20 diff --git a/meson.build b/meson.build index 41f68d3806..7e22afe135 100644 --- a/meson.build +++ b/meson.build @@ -3662,12 +3662,14 @@ io_ss =3D ss.source_set() qmp_ss =3D ss.source_set() qom_ss =3D ss.source_set() system_ss =3D ss.source_set() +libsystem_ss =3D ss.source_set() specific_fuzz_ss =3D ss.source_set() specific_ss =3D ss.source_set() rust_devices_ss =3D ss.source_set() stub_ss =3D ss.source_set() trace_ss =3D ss.source_set() user_ss =3D ss.source_set() +libuser_ss =3D ss.source_set() util_ss =3D ss.source_set() =20 # accel modules @@ -4045,6 +4047,26 @@ common_ss.add(qom, qemuutil) common_ss.add_all(when: 'CONFIG_SYSTEM_ONLY', if_true: [system_ss]) common_ss.add_all(when: 'CONFIG_USER_ONLY', if_true: user_ss) =20 +libuser_ss =3D libuser_ss.apply({}) +libuser =3D static_library('user', + libuser_ss.sources() + genh, + c_args: '-DCONFIG_USER_ONLY', + dependencies: libuser_ss.dependencies(), + build_by_default: false) +libuser =3D declare_dependency(objects: libuser.extract_all_objects(recurs= ive: false), + dependencies: libuser_ss.dependencies()) +common_ss.add(when: 'CONFIG_USER_ONLY', if_true: libuser) + +libsystem_ss =3D libsystem_ss.apply({}) +libsystem =3D static_library('system', + libsystem_ss.sources() + genh, + c_args: '-DCONFIG_SOFTMMU', + dependencies: libsystem_ss.dependencies(), + build_by_default: false) +libsystem =3D declare_dependency(objects: libsystem.extract_all_objects(re= cursive: false), + dependencies: libsystem_ss.dependencies()) +common_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: libsystem) + # Note that this library is never used directly (only through extract_obje= cts) # and is not built by default; therefore, source files not used by the bui= ld # configuration will be in build.ninja, but are never built by default. diff --git a/tcg/meson.build b/tcg/meson.build index 69ebb4908a..7df378d773 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -27,24 +27,5 @@ if host_os =3D=3D 'linux' tcg_ss.add(files('perf.c')) endif =20 -tcg_ss =3D tcg_ss.apply({}) - -libtcg_user =3D static_library('tcg_user', - tcg_ss.sources() + genh, - dependencies: tcg_ss.dependencies(), - c_args: '-DCONFIG_USER_ONLY', - build_by_default: false) - -tcg_user =3D declare_dependency(objects: libtcg_user.extract_all_objects(r= ecursive: false), - dependencies: tcg_ss.dependencies()) -user_ss.add(tcg_user) - -libtcg_system =3D static_library('tcg_system', - tcg_ss.sources() + genh, - dependencies: tcg_ss.dependencies(), - c_args: '-DCONFIG_SOFTMMU', - build_by_default: false) - -tcg_system =3D declare_dependency(objects: libtcg_system.extract_all_objec= ts(recursive: false), - dependencies: tcg_ss.dependencies()) -system_ss.add(tcg_system) +libuser_ss.add_all(tcg_ss) +libsystem_ss.add_all(tcg_ss) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350309; x=1745955109; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ijlmz6/bRJsdkPdqsV+cz0ErI9CNddyOzeS8owSZGCU=; b=EB5sp5P5qPneKKX6qYyw27kSmlHIWZBm3fJLxvihJ0DOzTzY1Uix5ESv1pu4y+UCrY AiPw4yApGUrohp14eKrGsDqlGWUA/1B4wEe6PTM7PW5O7o5xb3zKVH6XVGxEZ0sdepkm Qrg2qOsXlJuQU9W+qc4KwLKb8OG4IzyRl1xjCWdVQNEdYyINlp286b770PqCGOUtrj3q P/V1uLO8oPohxuSQ4k0u38MpzncTvxH13IdT9dArU3FFtErzn97N+LpxjrRbUf4uG+Pp v8IP3yzrTfukkfeDG9vY2jOMFFF+ghtp4GQWxV0Olv0jBuKr1YoWu8Bm8vZPLAhS+Cx9 ZtKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350309; x=1745955109; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ijlmz6/bRJsdkPdqsV+cz0ErI9CNddyOzeS8owSZGCU=; b=ZGap/OfvCu7mCobFBe0ljJplZhHyCGxc0bp5N2XzC94Eyu/1rSvnMDM9lxJjLfVO0m IGU0jsDzJxLxtDV3qz/9q1h7EqU1Yvr6rrlIR0NLYgtza/jfxOvGxCiaC4MoMC2gF3ob 8qFjtrA87UNrqGmKEPhRNzFZui4hGmrBdCMb1BUbxl+qitu602UpQhup1aqX4EnhA72n /pUq54W4oftlqPcyJ0cXspQy8MsJ+qe7OJyY5P6o1uMMUFJbydALEUoXi+BNlGrWHNe0 ue5UkJiHKN3Ln9EcLfNrGKbhTyVIcLDU6M7Pj67QFki+ly8NLmEmulCz3vAD5iEd6TbY zjjg== X-Gm-Message-State: AOJu0YxAtYxppkR4y4QvaOgyB1Z8NpJxj/01aIYOYKa3bYwxh2oAAjiq UbqMs77Ox5feDl9Rr4mC/RqkSKLJcOU/n61/ouG+jsLUiAwmFgtKqiIbt6xs4hM8npAxLFvCEoV h X-Gm-Gg: ASbGncsAYinsHHC0MN+Hhg3OZgxMJH0mHlwK1ePRKl3zw5r2UD1ojPtqfENPuYA0p7r BUKNUJYyoKQFasuO0y/e0olDs/KXftRZNfEedcGrZWXWExm+wDEmkyyaSJwtN6IBVDHosd5jzvt QrI0HlVnWUgCGf2Jp04CDHitUo7JJMtKJ0+BYof/bLnVy6GOmFeHxnp7F7oEwP+Wdtw4pj+fSRz RutmY4wS1q4mQT3TCM2uMqGbc4wgR/q6uygLMUCEEgOE42FPZvPtpvzJDJDXwhsektnkVG7AFtV 0tFwHoqAmJb7Ja2XgGEndDXGbIFuVJUWWgdViQB7lHi1T+YHaXCYc41JZqE3zkR1vWLgBZRLkOU = X-Google-Smtp-Source: AGHT+IHa+NTrT5AfGZC611pCgFCnqEOJc9c4lmIXbxY3ARZxxjLpeG47s+B2chQcu/p8b0yRffp2qQ== X-Received: by 2002:a17:902:d488:b0:223:fbc7:25f4 with SMTP id d9443c01a7336-22c53596a3cmr231304775ad.14.1745350308924; Tue, 22 Apr 2025 12:31:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 042/147] gdbstub: Move syscalls.c out of common_ss Date: Tue, 22 Apr 2025 12:26:31 -0700 Message-ID: <20250422192819.302784-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352456962019000 Content-Type: text/plain; charset="utf-8" Copy to libuser_ss and libsystem_ss. This file uses semihosting/semihost.h, which has separate implementations with and without CONFIG_USER_ONLY. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- gdbstub/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdbstub/meson.build b/gdbstub/meson.build index 0e8099ae9c..b25db86767 100644 --- a/gdbstub/meson.build +++ b/gdbstub/meson.build @@ -7,15 +7,15 @@ # We build two versions of gdbstub, one for each mode libuser_ss.add(files( 'gdbstub.c', + 'syscalls.c', 'user.c' )) =20 libsystem_ss.add(files( 'gdbstub.c', + 'syscalls.c', 'system.c' )) =20 -common_ss.add(files('syscalls.c')) - # The user-target is specialised by the guest specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-target.c')) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351103; cv=none; d=zohomail.com; s=zohoarc; b=UZGDGiPx3URuvVhBpXfsdFda7uC6yp2C0QqnBwp9ntRH22A+cchY7LbI1mexBx5iZpmJWNGs+I80CyXrwwETTyyA7Bt4GQxBJ8DzGOPBB19sGfU35/FuUAjLE8Dl1rfx3PEmz4/tBaXMbLs/lNEugIWGuhdcsoZJFLa0QMqhtuE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351103; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5QmVx49VUNvE0VebpWYF9vpR8W6QUfLccSgTbYDwMAs=; b=R+ki7tgeF9NtJESDYsTdMJ3XDFBhhTxVQbN+84EOQql3WUrD8i7QhLN7Bg95OEuMWPhChzajRohRYlcGip1tBJs0PZP6BZMLsEuBl7wU/Iw1yQI+K76l02gPYPBQOamH29XC3W2Bc10G00J/H6UWprCLNtQsMhZ1Z3hJ6lv4cm4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351103462830.7348547864004; Tue, 22 Apr 2025 12:45:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JMG-0001b1-EU; Tue, 22 Apr 2025 15:32:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLV-000072-SH for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:54 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLT-0006aj-39 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:53 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-2264aefc45dso90085445ad.0 for ; Tue, 22 Apr 2025 12:31:50 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350309; x=1745955109; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5QmVx49VUNvE0VebpWYF9vpR8W6QUfLccSgTbYDwMAs=; b=XTjFjOYrF0TTEUtMXqSPdyV5MatrWTtbyNyrm0zpaqKzFNJ5Hw7DRRKZUCSUrDhW9t gEjuCDh7C5CAKSs4sA1Txlq9Oyib8bjBJnrB8h4/5Zsm9LE9byF1Ng0jb/mJdEwgE3rn c/TYF3sQ+TxGMNzVBgSw3lpqWyuQBBCcZdEKQCqjWA7+EXAJSBvBLjBT4TlUN/t/Noit /8skuSX+AEaptKnDFkQOWRBYrOt6cQobIzeZqvlhGKBKh/XwKCkYMdBVPaP840CnA30a IeJn9zkKe9vb/QXpXc168lwgPM2bWt/zJbn/VF5h5WLtlW5MB9Wo4f5g235it6ugkkcT mCSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350309; x=1745955109; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5QmVx49VUNvE0VebpWYF9vpR8W6QUfLccSgTbYDwMAs=; b=ntBMrXzo5xB3bBfBgEp3uaQ0wL2j1avi7HD99S+Ibk+ZpYUox8TFURQJ8sIuLuquvR s+4SUsDMezJ7f0pevEnzeue+W54nhljT0m9olB6xhvEEpm02YZMZcZeKC/Uqc37zWfqM xjZgQZ+CsWZW6w8lP2Oz2XF78PT04cUl+nzggJCkJOyzMpiHiaXsHbY8JU3RK3tHpXhP WTl+bfj5q2LR5kyM6HlUzJ7e/zSXb1gIW0t0H68oXyN1aTQFxHWqCKcAdBov6YuTyzNF NeDQW2DX8zR1MLaS9BwJ1ucKdPacPRnEGSNMmbbR5Bt2ZygWice2DSUtJyMWOX7IkO6M UAgw== X-Gm-Message-State: AOJu0YzpVmRZrysMZVhjlO/18bG3GE+F3FS9TtYRJ+SSdM0iPPLQfwcU rOBocPRf+5sfujGv7zp5j2rKgJyZQuYATay4/9ZPf+Pkg0WC199i7tHeL9Ekz7faaVViJwf8o0p 4 X-Gm-Gg: ASbGncuL54vU02xTGtL7bOQuy2K4JTflCNlyRp4doIF9bdLtp0sBT21sITdIMz+3xuk 1qWrpNk+rt0W65xVZ07csW6Ggxw6fkixmG5doe5rkobtImze2cUF7Fm6Wrju4Mc0QNRGgLr++pJ Lqs4aX8wAEIKGUrepHC243td6qBrCjrELycLwgRscc0UHbexIuPjk58XqHyQEdMCGNUYpefglRx HgPrEIH1z6uC7vWkzLnxj4++8FeH5TKKqH7FZwqQ3EktlGLUkcBSbZuzVHue60teykr5kmuBu4b NH6Bp5dk/3Lxs6p4zwAPG6euf65fkh/KpENC8GZmuEts95lea05KteXmWHNbUtd6HVA+aRS6Vl9 9PX+oARKbMQ== X-Google-Smtp-Source: AGHT+IHgIlU2jOE1JIp3ZgCabMdGT83i/Iv7dsXOgmBGXqZTvuAYzSjmy6AMP6gg5Z7iatqQjzV3jw== X-Received: by 2002:a17:903:40cc:b0:223:5c33:56b4 with SMTP id d9443c01a7336-22c53583807mr215595545ad.20.1745350309537; Tue, 22 Apr 2025 12:31:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 043/147] accel/tcg: Use libuser_ss and libsystem_ss Date: Tue, 22 Apr 2025 12:26:32 -0700 Message-ID: <20250422192819.302784-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351105323019000 Content-Type: text/plain; charset="utf-8" While some of these files are built exactly once, due to being in only libuser_ss or libsystem_ss, some of the includes that they depend on require CONFIG_USER_ONLY. So make use of the common infrastructure to allow that. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/meson.build | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 185830d0f5..72d4acfe5e 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,12 +1,21 @@ -common_ss.add(when: 'CONFIG_TCG', if_true: files( +if not get_option('tcg').allowed() + subdir_done() +endif + +tcg_ss =3D ss.source_set() + +tcg_ss.add(files( 'cpu-exec-common.c', 'tcg-runtime.c', 'tcg-runtime-gvec.c', )) if get_option('plugins') - common_ss.add(when: 'CONFIG_TCG', if_true: files('plugin-gen.c')) + tcg_ss.add(files('plugin-gen.c')) endif =20 +libuser_ss.add_all(tcg_ss) +libsystem_ss.add_all(tcg_ss) + tcg_specific_ss =3D ss.source_set() tcg_specific_ss.add(files( 'tcg-all.c', @@ -22,11 +31,11 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TC= G'], if_true: files( 'cputlb.c', )) =20 -user_ss.add(when: ['CONFIG_TCG'], if_true: files( +libuser_ss.add(files( 'user-exec-stub.c', )) =20 -system_ss.add(when: ['CONFIG_TCG'], if_true: files( +libsystem_ss.add(files( 'icount-common.c', 'monitor.c', 'tcg-accel-ops.c', --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351892; cv=none; d=zohomail.com; s=zohoarc; b=VCFGhFg5lzbEFk3qEdlZtiNLNADkdGg5YY91l753sf9EtMMS27IUX7FQ6XcBTYMvJ1YDdZhYmQjfnQCYI1K53Gf6eq2UjUnHdrt6T/GQtucetdcVcOAMgQwDmGrMTxC57cs2KemBdLpCvwoojiL398QNDmVwxRUauCBT/GmaMxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351892; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=F3Y4je3GBLzid5tCgPTNk7pnHDm4dJMb3td8c19mugU=; b=e/rnIzCW2+lcmDAOIK0CR+i0k9gVL7NZ3gsGuv8FoGB7jzbrfRWWl090eCMQ+waqf5tNu92ZcZ/2PIYbiEjmPnCVvbfNTuqNoOEGDMPRwUDndiEs8fm+SVHnYGoTXKsW9MhuYptCYgmfphqr3YOVsmqcDt2RKfFMb3861fQGO5I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351892469371.6599338740066; Tue, 22 Apr 2025 12:58:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPl-0007g0-LK; Tue, 22 Apr 2025 15:36:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLV-000073-SU for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:54 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLT-0006ao-O9 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:53 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-22c3407a87aso84187925ad.3 for ; Tue, 22 Apr 2025 12:31:51 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350310; x=1745955110; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F3Y4je3GBLzid5tCgPTNk7pnHDm4dJMb3td8c19mugU=; b=ke/jja8jHIo8FHbDZPWrEQVapMgnLX+1vx1rgMplbkkc9oPWll+6aCbBp1tLf3QFXB rA7/rz92AL87L2Hvos9sDeej9HAthFyxFqJf2XezvuMcAcpzNk+V0RD2DXPeHjsqDjM+ X2gOa6OktQ7wWPiFCazrMLMT2nSrlN4JInoMtiztRSe7NiHmJh62dfpAWw0A+WPiYhk2 8Fc4MMaIzWfTJZLXl2YJcsPwi+mPG7zlxXnZ65eV9/mWR+icmyByKV+usZr7uC9bnBQT 2XdW6kFk0Nm1PQ+tqPTaH1FiC7ekCMTXAd8kbCd13rpXOYAwtjaY5c+/ETJDakdsbU5R +Odw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350310; x=1745955110; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F3Y4je3GBLzid5tCgPTNk7pnHDm4dJMb3td8c19mugU=; b=eaMbReJAXLxz3oCWlmQt4ddZ5LO4bO98MZalmdCPVulTMDRfUW8QBW37GhVAxCtODh 0EtzmKMdIEL87CVjWop/ECItVBBCg5rwQS8TxpTO/YVngopR/j50qEhz7ZDeb4ISP3LA DvHgSe6jn/McqhaVvtgnhxVvExxtPkgzMlKi5I0itJTbk5ReKQxB770Ve+EzarkTgHTd cRr/zAF5Ivgb3AMbN1M0X6lzMDPEciTvP0WGWX9rZFcQdkAXIkIPyYTzCFq5b78EiF01 lrYjYWyRGQsUNJTAks1Z3NXJNfxnCVq/1Xtjppz0U8u4/iHiRjQnWaDlrG3wQY4UC4Sd Y8YA== X-Gm-Message-State: AOJu0YxscZLscrlIqxqiQyi8UFVkrs1XdNQ3hQ617MZX3nOuliLHTnYB msBLBbrJGS3DufJIOIjxXANv6wJl5bwTJYjCY4SC9YPQIUHPXbaFkOTiTAb6o3RVe6sduFWh8ui 1 X-Gm-Gg: ASbGnctrDbNMredoJabufpCSfIyoDKtYCWoTl5iNlG4i+yBhIpWVOfEoXJZg7omxMdS rI7UF/4V4CBxgZgJXomiafUdkjZ3nC3yaFbk6iGjZoRvT8h9T1Ofy/5hlqf03L9EqMAIgmQYpcf V97USO4lJpu3XJ6yNytNzOXQg6sjwE/ZMfYgCCkP//biDRXWGQBs/2lTm1uulgBoax7shGyG/Mn YkrsKkjCUYz3Zh/Z9JBw4QMM6r7QrSYM7OupOfdYAc+8csChE9nAXi6POJxRq9sNi10mF48yWRs IrwH5URELKt/GHsOJTQwhTQxzf9xfOUFZFQd1mSeqP3DM4ZP1EgUwhTCJOsA6e9ZUqeuZhH4lNt O32uXOy+SeA== X-Google-Smtp-Source: AGHT+IE2ZhyzW8qkwsu70tTBrm7W2PTSbYkzFoWSaTSZlq5CkakDJvkT/VI3w6BbMqjfHg5+H+FIpw== X-Received: by 2002:a17:903:2349:b0:21f:6bda:e492 with SMTP id d9443c01a7336-22c53607715mr256580485ad.35.1745350310078; Tue, 22 Apr 2025 12:31:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 044/147] target/mips: Restrict semihosting tests to system mode Date: Tue, 22 Apr 2025 12:26:33 -0700 Message-ID: <20250422192819.302784-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351894361019100 Content-Type: text/plain; charset="utf-8" We do not set CONFIG_SEMIHOSTING in configs/targets/mips*-linux-user.mak. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index b207106dd7..47df563e12 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -32,8 +32,10 @@ #include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" -#include "semihosting/semihost.h" #include "fpu_helper.h" +#ifndef CONFIG_USER_ONLY +#include "semihosting/semihost.h" +#endif =20 const char regnames[32][3] =3D { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", @@ -415,12 +417,11 @@ static void mips_cpu_reset_hold(Object *obj, ResetTyp= e type) restore_pamask(env); cs->exception_index =3D EXCP_NONE; =20 +#ifndef CONFIG_USER_ONLY if (semihosting_get_argc()) { /* UHI interface can be used to obtain argc and argv */ env->active_tc.gpr[4] =3D -1; } - -#ifndef CONFIG_USER_ONLY if (kvm_enabled()) { kvm_mips_reset_vcpu(cpu); } --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352796; cv=none; d=zohomail.com; s=zohoarc; b=F+l85+37ByKvmJ9TnqoygJBC+1AZmEtk3Ux2sgSzlRLnD7FsvNmPQm2c0fzJVrRyYWOT/dZHtZQqkp707FTZNBxNQDn5uExfEBmZmdQEsqUBOI+JJyHzyXdjyXJ0f+XRWYjDdUg4IzZ/y4rDwoLdS8eZFBnTyU5ZI22oYqYNmV4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352796; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qcw0j/NlWHHUFrSWrBThXyu3TLmFkd4CNoNN4KpSa40=; b=k0MrsxnsJfbdmVFhaMqME2tPcYz7PCZkeAjQBF0WFlW38xCa7s6jVMxUH4Q0/huT1J668iTknlvO8MEUIR2niQpznJfe2M57Ye1d42GYABxLdXVcL+1bUrXPTrpltZtRxqq9ebfGai9ItPBDdpoDHFjoUnXtgb8qF4vNxUyPHlA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352795994788.391661814588; Tue, 22 Apr 2025 13:13:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JQx-00013B-Kc; Tue, 22 Apr 2025 15:37:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLW-0000BL-K0 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:55 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLU-0006as-At for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:54 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-22c3407a87aso84188125ad.3 for ; Tue, 22 Apr 2025 12:31:51 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350310; x=1745955110; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qcw0j/NlWHHUFrSWrBThXyu3TLmFkd4CNoNN4KpSa40=; b=tRvwom6xp9qKY4ahcO1/L3Ry2UUWyv+xm8rP9Y/RXbp8yy+69llJ2ICrcRbQwa5SSQ TBSIU4hDHUEGWcJMan/hBPHXxCmi7P1ruuy/sGhjoFcSr5sJWm7K5MJFMCUcicPpKxkD ZkY/TWWqRV/+zSRm2u3nPSDiVkBXAN5gR4bCNB9r3H4/z238O1KhWqClKkt1hqlp91Lt e9Tv8qQNb1rGx+ePIIa5ZrPmoSy3hOECcsad89vQuZy8xqF/EtaQ2jt/WmzHMAIbvOKL SKrRh2+5YUK1rhOGNNOI/t+xGA1c+MuoM3DdMxKvlvSjN2LxJiA5XGERMuvjal9SSc73 5lPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350310; x=1745955110; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qcw0j/NlWHHUFrSWrBThXyu3TLmFkd4CNoNN4KpSa40=; b=ApqHQsrmC358OhdcS+D+FW09vCfexfK7V2eK/9QC5VUS6IRcMEbjmZ2LWZg/LghlFV 7z4lr/bJoshLIRDVNb6txxvVeIKMKt1S5pT0tc9iUyvKSHOmYhaxei59X+QrDIbPWpO3 mBT4aEUuhpc4O6hLRpa2JsvVTLiqytKuz1hbE4GxdTCZgB++NwtjQLVqgVh3Xi755rMH L9tKx7+W4VK2RP7HiDMCI/AyGha0KSfrotwlQzBWBQoCtW0xw8vnOX2ckhWiYXgUHYiI wJ1OLYwky10LmYWaxd2hk9vGTRHk1Dxw5WnA0ngXOeUyux1DnXTLVwu9w3jiLQ5R0W19 IpYA== X-Gm-Message-State: AOJu0Yy8TNLtj6Gi6p7EX/M/Dv/V0n4ZX3FA1AltFemja1wCWi8Xwj0f 26zEqmzH9RDOZfD8GaiMSkE72X2zCPI8faFilKsxjPCY0Cq/nikPbJL7DDL09UJ2uDS1hX0ZZj5 d X-Gm-Gg: ASbGnctIaJ7jNR/8VCY6BFpU5LILc5uK8D4QfU6D+stdz/EZouOUgGCU5xlniCPKU8e ZavN+/hY/RVvJVqA/SzKgOGmygRA1LpVnb4z5mc2yFRxYZ54RQyYwH9WuS1wi2qRWnRRmOb5tVK SjpshKF21MD+EZYDt3zy0Iu8WK7Z4xCCkQFlfDi95RyMl9gJrtmgPRf/YqUkaQw6H/51qP6VrE3 8u/Y+uriCnpkYB45VOIpnBYFsGZD+3bzwURug4e+vD0hsAOGxY6eGIqnMpKwb/XOWuj1am/ysxY 6fHtktVswzxv0DWrReunFGB8saWbG/70A9AktldI12QZxTJ+Smc7Ti9DYKAbF/w3YSF0RNI1ch8 = X-Google-Smtp-Source: AGHT+IHDSorXWqj3xQPieB+lzrq2kREsklsVBoJeuSkit6cCLpo7Q6OgYjJh7bvT9yTYsCKaRwPl1Q== X-Received: by 2002:a17:903:3bad:b0:220:f59b:6e6 with SMTP id d9443c01a7336-22c5356798amr208685535ad.8.1745350310640; Tue, 22 Apr 2025 12:31:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 045/147] target/xtensa: Restrict semihosting tests to system mode Date: Tue, 22 Apr 2025 12:26:34 -0700 Message-ID: <20250422192819.302784-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352797980019000 Content-Type: text/plain; charset="utf-8" We do not set CONFIG_SEMIHOSTING in configs/targets/xtensa*-linux-user.mak. Do not raise SIGILL for user-only unconditionally. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 4f02cefde3..cb817b3119 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -35,14 +35,14 @@ #include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/qemu-print.h" -#include "semihosting/semihost.h" #include "exec/translator.h" #include "exec/translation-block.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - #include "exec/log.h" +#ifndef CONFIG_USER_ONLY +#include "semihosting/semihost.h" +#endif =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" @@ -2241,17 +2241,15 @@ static uint32_t test_exceptions_simcall(DisasContex= t *dc, const OpcodeArg arg[], const uint32_t par[]) { - bool is_semi =3D semihosting_enabled(dc->cring !=3D 0); -#ifdef CONFIG_USER_ONLY - bool ill =3D true; -#else - /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware.= */ - bool ill =3D dc->config->hw_version <=3D 250002 && !is_semi; -#endif - if (ill || !is_semi) { - qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disable= d\n"); +#ifndef CONFIG_USER_ONLY + if (semihosting_enabled(dc->cring !=3D 0)) { + return 0; } - return ill ? XTENSA_OP_ILL : 0; +#endif + qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"= ); + + /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware.= */ + return dc->config->hw_version <=3D 250002 ? XTENSA_OP_ILL : 0; } =20 static void translate_simcall(DisasContext *dc, const OpcodeArg arg[], --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351101; cv=none; d=zohomail.com; s=zohoarc; b=PjQwBUJhWYv2ZJBj/GiVpFm7hpDzKCJbuK9FCYMLGExr62Gtpze05M+gokFEAFhK3ia6+101Y90B4QsNSN8RcUwpiZssWg6qzvN9gNr4bSJrvmJgi0jxLPGaPm8NqGpoUnjkyo3a4SZP5Nr8qjunox/StAB4xyyBT32ywQhQCRg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351101; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qwbKvRdGoMiUrRuxJx+msL79vGWbZKojWAn1/Wo2xRE=; b=gGECO0wXVo70bknqjaWz0elocLQJJaRMuXj+l6ZmMbMFtx05pOTqbeGDVQm8ZLVOqPZOCzBOaXHFtUVpb85Wsqe4EzxaosoMkBxT9RFInFwEqHkmPO9CVHDoXLEn540YDUpxJGK8R7DDDogaEvl+Ap3s2v4VtYUMK27JfExZT6A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351101395213.24368407142185; Tue, 22 Apr 2025 12:45:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JOc-0004HZ-Uc; Tue, 22 Apr 2025 15:35:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLX-0000Gi-Rr for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:57 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLU-0006b0-Ps for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:55 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2255003f4c6so63552385ad.0 for ; Tue, 22 Apr 2025 12:31:52 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350311; x=1745955111; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qwbKvRdGoMiUrRuxJx+msL79vGWbZKojWAn1/Wo2xRE=; b=KSz90U91TxbwPs/YPi+i/N99eEfoa84OjYJKvwWnTzG7HxRdjUxNagdz/x75zBUQF4 kWcACnWEhzdtbcMrIqTZRLvS4dHYCkG5941TnnB66JhVaQmY0qvpGVDnCHTgVpNASY2+ bSmBHcci1KAt40/1pSXi99wkKTG/UFaZYYMUoSnbDSNEdFgNhh40KZqGzrIisyhLCInZ HWhfblGA0M1EdItAgbiCkyTL7qHv5YmB6k9WLSIMdavg6pQ8zRE5Vg4QA1uKB3Yr4CIh ZtAQSy03F5+BsXZqkHvaLjizLW4Vlo64C+ypu8GDQd6tuBIdVqBnNXtGBwbm0qhO+Evu 9Z6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350311; x=1745955111; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qwbKvRdGoMiUrRuxJx+msL79vGWbZKojWAn1/Wo2xRE=; b=usylenuvNFbs5qBglX3FSCvyy0FTmBphUqZw9AEk/SEWlWAJKbVpUZs1xOno5hJWcJ E7ShoUMam3HhsU1ywwOOkNx01FAb6zalOPVyQg4SD5/ajc/8X2LDE83esngvakia9MRv nJb8RQ0beg4HVhOPPdosS1zuB6wa6KsdpjIxXy4H2+ieKgNXA5U2Of/rsdqXLa1CawnD dwIOtoZEcVZQKYD+27GXbudrZ7hLSO2beOe4PCoH+Ygj/3I5uCHqOH9ehicadd73ab/o zA+P1nQqp1HuGACQq2xKCmcWwusu1Kdwt5fOcM/cN0PA9xBGY8cC2EY6NnM541iG7MQZ qnAg== X-Gm-Message-State: AOJu0YxvVT2Z3tVVsc/Gw6Dg43mg+B2wpz9+/33QCHcyGfEza0xJ30Z1 BRG1988uu3i+wulSv4tGomIFX9RW7h/MGpXtxBVv2UOm2MdGXBqc50waLGsZCL3KlhJynh0yIFH n X-Gm-Gg: ASbGnctY6NM36t7ou63m+gyzlCKZnmyIG7u0ZVUu6+HZtEtQy2i0I2FeaxEKIy2J3DB myo9p+mzLWVatUR7TIqqMLBIk6kXB/4pNqPhxqJI6YLqazZ28PLSPex3DsU3jY9qt/syLVJCzIq SRawr4Hen0PvYOq55j2bPctk8epsvMKqJde/W5drXGx9u4474oSzqf/DPBPnh2uh5L/cfIgK7Mx yaMFjVUS8aE2S2m70rzQfmUt3AnKGeXZiQmNRQ65GPEUPxLIiuIDAJMk7LIZo2DEPTh6sbYPtNf NYINqA9DOuRKxo47ixrzF/7Au0oGkhFtvmzYC5RZYULO3G6o8B0/VztI0DLjk8Cf+zH+Apfq5Rc = X-Google-Smtp-Source: AGHT+IFmNxNoVahXz9LwSUsDMR5zF1z1flQ3FMOvTfGLGyrmwVIUO1rT4eb7MxAPLwTGwZinlK5otQ== X-Received: by 2002:a17:903:228f:b0:223:653e:eb09 with SMTP id d9443c01a7336-22c5356e485mr203047305ad.7.1745350311285; Tue, 22 Apr 2025 12:31:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 046/147] semihosting: Move user-only implementation out-of-line Date: Tue, 22 Apr 2025 12:26:35 -0700 Message-ID: <20250422192819.302784-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DIET_1=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351102821019100 Avoid testing CONFIG_USER_ONLY in semihost.h. The only function that's required is semihosting_enabled. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/semihosting/semihost.h | 29 ++--------------------------- semihosting/stubs-all.c | 6 ++++++ semihosting/stubs-system.c | 6 ------ semihosting/user.c | 20 ++++++++++++++++++++ semihosting/meson.build | 5 +++-- 5 files changed, 31 insertions(+), 35 deletions(-) create mode 100644 semihosting/user.c diff --git a/include/semihosting/semihost.h b/include/semihosting/semihost.h index 97d2a2ba99..b03e637578 100644 --- a/include/semihosting/semihost.h +++ b/include/semihosting/semihost.h @@ -26,32 +26,6 @@ typedef enum SemihostingTarget { SEMIHOSTING_TARGET_GDB } SemihostingTarget; =20 -#ifdef CONFIG_USER_ONLY -static inline bool semihosting_enabled(bool is_user) -{ - return true; -} - -static inline SemihostingTarget semihosting_get_target(void) -{ - return SEMIHOSTING_TARGET_AUTO; -} - -static inline const char *semihosting_get_arg(int i) -{ - return NULL; -} - -static inline int semihosting_get_argc(void) -{ - return 0; -} - -static inline const char *semihosting_get_cmdline(void) -{ - return NULL; -} -#else /* !CONFIG_USER_ONLY */ /** * semihosting_enabled: * @is_user: true if guest code is in usermode (i.e. not privileged) @@ -59,17 +33,18 @@ static inline const char *semihosting_get_cmdline(void) * Return true if guest code is allowed to make semihosting calls. */ bool semihosting_enabled(bool is_user); + SemihostingTarget semihosting_get_target(void); const char *semihosting_get_arg(int i); int semihosting_get_argc(void); const char *semihosting_get_cmdline(void); void semihosting_arg_fallback(const char *file, const char *cmd); + /* for vl.c hooks */ void qemu_semihosting_enable(void); int qemu_semihosting_config_options(const char *optstr); void qemu_semihosting_chardev_init(void); void qemu_semihosting_console_init(Chardev *); -#endif /* CONFIG_USER_ONLY */ void qemu_semihosting_guestfd_init(void); =20 #endif /* SEMIHOST_H */ diff --git a/semihosting/stubs-all.c b/semihosting/stubs-all.c index a2a1fc9c6f..c001c84574 100644 --- a/semihosting/stubs-all.c +++ b/semihosting/stubs-all.c @@ -11,6 +11,12 @@ #include "qemu/osdep.h" #include "semihosting/semihost.h" =20 +/* Queries to config status default to off */ +bool semihosting_enabled(bool is_user) +{ + return false; +} + SemihostingTarget semihosting_get_target(void) { return SEMIHOSTING_TARGET_AUTO; diff --git a/semihosting/stubs-system.c b/semihosting/stubs-system.c index f26cbb7c25..989789f373 100644 --- a/semihosting/stubs-system.c +++ b/semihosting/stubs-system.c @@ -22,12 +22,6 @@ QemuOptsList qemu_semihosting_config_opts =3D { }, }; =20 -/* Queries to config status default to off */ -bool semihosting_enabled(bool is_user) -{ - return false; -} - /* * All the rest are empty subs. We could g_assert_not_reached() but * that adds extra weight to the final binary. Waste not want not. diff --git a/semihosting/user.c b/semihosting/user.c new file mode 100644 index 0000000000..515de3d2c0 --- /dev/null +++ b/semihosting/user.c @@ -0,0 +1,20 @@ +/* + * Semihosting for user emulation + * + * Copyright (c) 2019 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "semihosting/semihost.h" + +bool semihosting_enabled(bool is_user) +{ + return true; +} + +SemihostingTarget semihosting_get_target(void) +{ + return SEMIHOSTING_TARGET_AUTO; +} diff --git a/semihosting/meson.build b/semihosting/meson.build index 86f5004bed..f3d38dda91 100644 --- a/semihosting/meson.build +++ b/semihosting/meson.build @@ -7,8 +7,9 @@ specific_ss.add(when: ['CONFIG_SEMIHOSTING', 'CONFIG_SYSTEM= _ONLY'], if_true: fil 'uaccess.c', )) =20 -common_ss.add(when: ['CONFIG_SEMIHOSTING', 'CONFIG_SYSTEM_ONLY'], if_false= : files('stubs-all.c')) -system_ss.add(when: ['CONFIG_SEMIHOSTING'], if_true: files( +common_ss.add(when: 'CONFIG_SEMIHOSTING', if_false: files('stubs-all.c')) +user_ss.add(when: 'CONFIG_SEMIHOSTING', if_true: files('user.c')) +system_ss.add(when: 'CONFIG_SEMIHOSTING', if_true: files( 'config.c', 'console.c', ), if_false: files( --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350831; cv=none; d=zohomail.com; s=zohoarc; b=RezwnlyJUQXpmLApVcs1iQQPaw5AtTSXOYBkqE4ZXpkyzvhf9oO60PSeR1ZV4YvQyw2w4msBf1jf9GupSkjMgJTqt/WIGp7ybJEY7J4VOXiQl7CUMtj3eJg3zaGMaVnEm35T1fBoDTwK1/QxADVrBTn7GqGg5/QrpXU7Z3HQGPo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350831; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wDV12YwNumASN3qNFcyYdusmdSKLuYlMr1apQ66exto=; b=PoHwt/bRroi/DfA17byX5H0R6X45o4DUD2Dl1VivywkPBoZI+lQg0xKaDxY7FLEJ6nknUAoHF3jkkUsUBt1AKA71bMZtMnWinmv/w0DFjavOGHiWeoJGEWriVpzdHPtSZCgRhvHk1XzShtvDK6FXTc9m4WfD8JfeqZygFCGe4Ns= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350831874476.9577390078862; Tue, 22 Apr 2025 12:40:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JMC-0001Mg-9m; Tue, 22 Apr 2025 15:32:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLX-0000C9-Bw for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:55 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLV-0006bF-5m for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:54 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-2279915e06eso58608945ad.1 for ; Tue, 22 Apr 2025 12:31:52 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:31:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 047/147] semihosting: Assert is_user in user-only semihosting_enabled Date: Tue, 22 Apr 2025 12:26:36 -0700 Message-ID: <20250422192819.302784-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350832277019000 Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- semihosting/user.c | 1 + 1 file changed, 1 insertion(+) diff --git a/semihosting/user.c b/semihosting/user.c index 515de3d2c0..98c144cb45 100644 --- a/semihosting/user.c +++ b/semihosting/user.c @@ -11,6 +11,7 @@ =20 bool semihosting_enabled(bool is_user) { + assert(is_user); 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350313; x=1745955113; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rzfkd84AU4JxIk+n9aK5OlCLgNFIPk0/g2EPPFZ4xP8=; b=loungcGEI/fdCLUZ27oYzqRvZkD+nct9qD23EkI6XM4qpUyjIlf9DJfTWz291zJL5z oAnfPEC3mO+YVYOj4LbKB/nZKxEWpSon9j6yVLdQXFgx549PC380UM8f6QPNnnwYwMj7 O2VQcnOB4FrCWs/+tnjfu84Lxmbn6ZvuT5fYhFIAOETDkgc3i+tUXLVxxqrOu28kdKnH jRracRdyRLdmk2qwsLPIVoGIJsEbNI1FgDsJD8sc5Yo91dr1BghO9CAadUqgZqIUUnnv xbq/H6FM7FA11IO+TS2z0wx4HEC82v4t6B7vOkJnCCmML/m4B9ODfzGMK08iQq2dy5d0 AWxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350313; x=1745955113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rzfkd84AU4JxIk+n9aK5OlCLgNFIPk0/g2EPPFZ4xP8=; b=e0Ee2pXqyURbSYNZdm8p/HPnWKnyWUmgkXb3iwIkWjxhzgzaooLJI0GkI39Rg75DsK B7dA6L7qAS8NFdMLfJXkPYDhyYUUNpGFuRsZqBHnkJbtaUWRO66HiMMFpRct6v+srbTZ fX3aEe0bNk1NqCS+Jn6iEjZ4AKimxy8FGeMBHamPnvGUrWxTr76xLjc4UYEwm5yNWYgr R+KQmqiqCRpxqMSpQiWpvO2ilX5Epi8dZ4xKnuz4Fp3ygcT3nbzXu6IOtJbdw7JIac7F qzHpTqebArcho8/jyLP+CXA3Li40oEOVcEmocP86KAECzp2U8wzwk07QHgGPCsGgetkj kWwA== X-Gm-Message-State: AOJu0YwOrLUaxrz+Bkfr/tR8TgvhA8ofab/AIE/QX1IHFWwigKq1XZNp ju7iId/bZTpxLG3zBNkEANoBUWEBCL9p/ueYQs23peb57MqGZZRhsCmrjVFMBr7WavtsMvs2Ohi G X-Gm-Gg: ASbGnctElsh+asUwjHZq2E9SFgyWgefFS88S6p/sQ1IiMfwZUtETyjzrzf4zwDmj8wo LmyV0xE9/ZbDtTUp+A8rgAG+3jaqbJVulk6apa0YGpBmR3Tny26UB3XExCT2GiIo7KwO5KreEuF TfPd6IhQmbdnpu23M/+sEV7aeiSpiJSoz14pzA0qoLZfMXBbb4/tta4EVpaIAWWZu5W5ls3vF2e P/SZV87ZaJfOJp5V8/DdRmZ0uRx07M3OCyLyyscNelaf8yZPngolggmqHL2ZgBerjep+svVX4dQ ACawy4OmLd7U2xqVCP7pda2/+QkxJ3bcMiLrALVU6ysXQa87lLHLX9gzj0l/BHkzSFroN9ltOJs = X-Google-Smtp-Source: AGHT+IFMAkz9iEWA7wGPXaE/uq3sWtqofxt0sZVDADOLB4wJJDYzZ9/A96JhgZefmhOxQQFUBw3McA== X-Received: by 2002:a17:902:e88f:b0:220:f151:b668 with SMTP id d9443c01a7336-22c535815admr193370365ad.20.1745350312649; Tue, 22 Apr 2025 12:31:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 048/147] include/exec: Split out watchpoint.h Date: Tue, 22 Apr 2025 12:26:37 -0700 Message-ID: <20250422192819.302784-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351094340019000 Content-Type: text/plain; charset="utf-8" Relatively few objects in qemu care about watchpoints, so split out to a new header. Removes an instance of CONFIG_USER_ONLY from hw/core/cpu.h. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/watchpoint.h | 41 +++++++++++++++++++++++++++++ include/hw/core/cpu.h | 30 --------------------- accel/tcg/tcg-accel-ops.c | 1 + system/watchpoint.c | 1 + target/arm/debug_helper.c | 1 + target/i386/cpu.c | 1 + target/i386/machine.c | 2 +- target/i386/tcg/system/bpt_helper.c | 1 + target/ppc/cpu.c | 1 + target/ppc/cpu_init.c | 2 +- target/riscv/debug.c | 1 + target/s390x/helper.c | 1 + target/s390x/tcg/excp_helper.c | 1 + target/xtensa/dbg_helper.c | 1 + 14 files changed, 53 insertions(+), 32 deletions(-) create mode 100644 include/exec/watchpoint.h diff --git a/include/exec/watchpoint.h b/include/exec/watchpoint.h new file mode 100644 index 0000000000..4b6668826c --- /dev/null +++ b/include/exec/watchpoint.h @@ -0,0 +1,41 @@ +/* + * CPU watchpoints + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef EXEC_WATCHPOINT_H +#define EXEC_WATCHPOINT_H + +#if defined(CONFIG_USER_ONLY) +static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr l= en, + int flags, CPUWatchpoint **watchpo= int) +{ + return -ENOSYS; +} + +static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, + vaddr len, int flags) +{ + return -ENOSYS; +} + +static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, + CPUWatchpoint *wp) +{ +} + +static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) +{ +} +#else +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, + int flags, CPUWatchpoint **watchpoint); +int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, + vaddr len, int flags); +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); +void cpu_watchpoint_remove_all(CPUState *cpu, int mask); +#endif + +#endif /* EXEC_WATCHPOINT_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index abd8764e83..37cb7d1531 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1109,36 +1109,6 @@ static inline bool cpu_breakpoint_test(CPUState *cpu= , vaddr pc, int mask) return false; } =20 -#if defined(CONFIG_USER_ONLY) -static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr l= en, - int flags, CPUWatchpoint **watchpo= int) -{ - return -ENOSYS; -} - -static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, - vaddr len, int flags) -{ - return -ENOSYS; -} - -static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, - CPUWatchpoint *wp) -{ -} - -static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) -{ -} -#else -int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - int flags, CPUWatchpoint **watchpoint); -int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, - vaddr len, int flags); -void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); -void cpu_watchpoint_remove_all(CPUState *cpu, int mask); -#endif - /** * cpu_get_address_space: * @cpu: CPU to get address space from diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index d9b662efe3..5c88056157 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -37,6 +37,7 @@ #include "exec/hwaddr.h" #include "exec/tb-flush.h" #include "exec/translation-block.h" +#include "exec/watchpoint.h" #include "gdbstub/enums.h" =20 #include "hw/core/cpu.h" diff --git a/system/watchpoint.c b/system/watchpoint.c index 08dbd8483d..21d0bb36ca 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -21,6 +21,7 @@ #include "qemu/error-report.h" #include "exec/cputlb.h" #include "exec/target_page.h" +#include "exec/watchpoint.h" #include "hw/core/cpu.h" =20 /* Add a watchpoint. */ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index a9a619ba6b..473ee2af38 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -13,6 +13,7 @@ #include "cpregs.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exec/watchpoint.h" #include "system/tcg.h" =20 #ifdef CONFIG_TCG diff --git a/target/i386/cpu.c b/target/i386/cpu.c index dba1b3ffef..af46c7a392 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -35,6 +35,7 @@ #include "standard-headers/asm-x86/kvm_para.h" #include "hw/qdev-properties.h" #include "hw/i386/topology.h" +#include "exec/watchpoint.h" #ifndef CONFIG_USER_ONLY #include "system/reset.h" #include "qapi/qapi-commands-machine-target.h" diff --git a/target/i386/machine.c b/target/i386/machine.c index 70f632a36f..6cb561c632 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -7,7 +7,7 @@ #include "hw/i386/x86.h" #include "kvm/kvm_i386.h" #include "hw/xen/xen.h" - +#include "exec/watchpoint.h" #include "system/kvm.h" #include "system/kvm_xen.h" #include "system/tcg.h" diff --git a/target/i386/tcg/system/bpt_helper.c b/target/i386/tcg/system/b= pt_helper.c index be232c1ca9..08ccd3f5e6 100644 --- a/target/i386/tcg/system/bpt_helper.c +++ b/target/i386/tcg/system/bpt_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exec/watchpoint.h" #include "tcg/helper-tcg.h" =20 =20 diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index bfcc695de7..4d8faaddee 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -22,6 +22,7 @@ #include "cpu-models.h" #include "cpu-qom.h" #include "exec/log.h" +#include "exec/watchpoint.h" #include "fpu/softfloat-helpers.h" #include "mmu-hash64.h" #include "helper_regs.h" diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index f81cb680fc..17f0f3d3ff 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -40,7 +40,7 @@ #include "qemu/cutils.h" #include "disas/capstone.h" #include "fpu/softfloat.h" - +#include "exec/watchpoint.h" #include "helper_regs.h" #include "internal.h" #include "spr_common.h" diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 9db4048523..fea989afe9 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -30,6 +30,7 @@ #include "trace.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exec/watchpoint.h" #include "system/cpu-timers.h" =20 /* diff --git a/target/s390x/helper.c b/target/s390x/helper.c index c689e11b46..e660c69f60 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -27,6 +27,7 @@ #include "target/s390x/kvm/pv.h" #include "system/hw_accel.h" #include "system/runstate.h" +#include "exec/watchpoint.h" =20 void s390x_tod_timer(void *opaque) { diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index ac733f407f..1d51043e88 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "exec/cputlb.h" #include "exec/exec-all.h" +#include "exec/watchpoint.h" #include "s390x-internal.h" #include "tcg_s390x.h" #ifndef CONFIG_USER_ONLY diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 163a1ffc7b..c4f4298a50 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -31,6 +31,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/watchpoint.h" #include "system/address-spaces.h" =20 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350579; cv=none; d=zohomail.com; s=zohoarc; b=bw2xzc12Lv6cLpPS9Z/vZYVjs4CYab2h3DEtYs1JnGvPQneXzctm8SwWpEczbpfqp0J0xlVwVluzC75tJ//8d90XvxoedFrcB5H1oMzFIDVA3lES7Tk4xXpC+CYm2EJj1ZNn0/XXblQwEktxOAkmkbQgx+ZXQTxJpNxisdMS2bc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350579; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fRqDXJHX2zGNybTG6x2KjIY6H1Iy34YPBBK1EJX6qfI=; b=i+yh5MEHuS0i99OjPmCT2TrfWvZ0+4N6nbYmYAq54QK8sAQi/pN5CiiY6vzmdNJj39krDVHhv0pp+GCCXFnCE/LnGJxlNoayZVYkQji9tcZM6DwR0MZKHr4QTacGkDPTkEgeTp5e1F1uq+lnRzI6VAL0u8syIcOYOZ7vYdWHtbA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174535057942742.19825010630143; Tue, 22 Apr 2025 12:36:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JNS-0002Dx-Px; Tue, 22 Apr 2025 15:33:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLZ-0000J7-Lz for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:58 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLX-0006bf-1t for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:56 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-227c7e57da2so49176625ad.0 for ; Tue, 22 Apr 2025 12:31:54 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- hw/core/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/core/meson.build b/hw/core/meson.build index b5a545a0ed..547de6527c 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -26,7 +26,7 @@ system_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('= stream.c')) system_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c')) system_ss.add(when: 'CONFIG_EIF', if_true: [files('eif.c'), zlib, libcbor,= gnutls]) =20 -system_ss.add(files( +libsystem_ss.add(files( 'cpu-system.c', 'fw-path-provider.c', 'gpio.c', @@ -46,7 +46,7 @@ system_ss.add(files( 'vm-change-state-handler.c', 'clock-vmstate.c', )) -user_ss.add(files( +libuser_ss.add(files( 'cpu-user.c', 'qdev-user.c', )) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352943; cv=none; d=zohomail.com; s=zohoarc; b=LvwaDG2X/liX1x2qc/QSaDMRhjJ9kETbuhx8Cy5A9MTwKlubU0Rwloaf+WTUgMTej3aF/Et5zIIYWgIwQKwSWe5WfqtTNP1UUha+ZoJH9smF5Moq/UV+LGCzzaBdbTyTQKtf0oA7QqSZZ9dbwR7Oq1KtbBxRaaPvkMgrEDHsLdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352943; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Xdo84E1iLP/XqDwQy8oaphr3JsZ2BPpRKXEovDmduLc=; b=IrSDG+m5dz7zH4nkwFjfNwt6TMj4JlGTnFnWEO+O0V6FGajo4Y4Z5eggt74z66dLSryGnnBtZWwxK/rP34/bRC/Sj8dujDdOShCWV7qPG/jxZJNny2nlQvnGw5N54MqrFmg3U8DbOWut+M8CJzryCntYXNSuQSiKJnezs57utwA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352943437650.380484162266; Tue, 22 Apr 2025 13:15:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JLt-00014A-Sp; Tue, 22 Apr 2025 15:32:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLZ-0000JB-Kg for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:57 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLX-0006bq-Qr for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:57 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-227cf12df27so2441545ad.0 for ; Tue, 22 Apr 2025 12:31:55 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350314; x=1745955114; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xdo84E1iLP/XqDwQy8oaphr3JsZ2BPpRKXEovDmduLc=; b=oXBfAYW8UITWP4AQQNeoBKHZ1EAnfHRXxVYmGoBYRisAd+qIiSJUxBJdr9NRDM9nRx 3HG+fTVurrbIXGXlIk/u6sfyrLUsiRIBzqaj5UMFgobI6FyBFlQBVp+L7QiKa5jEGKX3 KvN1tM1qmcvU2v8fsJVeRiGUMazlDEtcnkgLMkriDXIyv3J9agrZrP9YojEhRhX/ZP4D yIg64AIVxYG7Ub4XfY8h0Q9NDoqJG2kmCVKWEuseIxc/uve2vyNS85to8kb77gwNZhM6 gAspCiE+NX8gW0TNLYZbvADuneTLuilPaf09/Z2yKVc2IRo2l0W7cI5EBTFJMUQbtqn5 AyRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350314; x=1745955114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xdo84E1iLP/XqDwQy8oaphr3JsZ2BPpRKXEovDmduLc=; b=jWg6XQ1/LuKT4sFStSxArCL6Bh9Oly9b6JE6K7cW5PQLly4sbH2NmWSxbpiPhqCTi/ jcGB9fYYArPWq0su4x2UsQf4U7TnjMGjW7XpAJLRz5BQWA52bPsVWqEq289BBycziCuJ xj4+RJ5Qo59l3IxhiR8Km1fz6Nj0Vuhuutp4pwGCx4bWCZLgZA8Ov4D47rhPri2B09la iod4o/B1wiFsgtGFSvoaylnO3FxIWI1rVKPzSINli3Rw09Hp+xSneIfSwFlhP0BOS+ga c/brII4wqXMic3FyE84HERtT8QlayhMIPZ+NDRte6qsJD6lgx2MFaHOPrTmJ5IZ5lLQH ALnw== X-Gm-Message-State: AOJu0YyncutulB+EMyZhM0hkeXMseTKuqudXJ22ebTTD/Z2punOdygbQ /zgSDlj9IOgH6yXhTmGEsAspu2iZKV2VbSOHNd+VIdQ1U16ugSPvHZ8s/Hv0KN0/62U6EuEgeQS s X-Gm-Gg: ASbGncu054UPuOwcKU/vF0xN3h+WBKhZF0ER6GRO2k/CJgYaxdRF5TPwnd5sasiMt+z 73nhKI1GLNvUVXd10cpPl57aeTcBnFbD2awU/K51Bu6XsySzjDxvf/H3awWg0h7d418Fa/A0lN9 9Po24Lh1qFgSVsivVpZiTYbbTQfUt4ddyrGKuApA4gvuI+JkfZyVtee/3PjfzAUhpSfdHfAyDF6 v46AjQ4Bnjx+NZqIRJ2LoSr5LBKjfZJTyms1s2r6d9LpzBpTNidaYd/ScfS5lATAJ7sHYCYxVVg iS4VYIte2WudWsgYPZDNtMrIHKbw8c4Gft3A/OqwqLCHAyI6a3PdrhQ2etpaSoYLCMjiwQwY118 = X-Google-Smtp-Source: AGHT+IFlnhGb/NDU2Um5UPBIeP5jr+vj4mpyY7ZgCmu/Sgh4mkkRS6LFQJw18TE2a8CqdfyQo9ImHQ== X-Received: by 2002:a17:902:d485:b0:221:89e6:ccb6 with SMTP id d9443c01a7336-22da33725f2mr2888635ad.25.1745350314052; Tue, 22 Apr 2025 12:31:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 050/147] system: Move most files to libsystem_ss Date: Tue, 22 Apr 2025 12:26:39 -0700 Message-ID: <20250422192819.302784-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352944628019100 Some of the headers used require CONFIG_USER_ONLY. Do not move vl.c, because it has other include dependencies that are present in system_ss. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- system/meson.build | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/system/meson.build b/system/meson.build index 063301c3ad..c2f0082766 100644 --- a/system/meson.build +++ b/system/meson.build @@ -4,6 +4,10 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [file= s( )]) =20 system_ss.add(files( + 'vl.c', +), sdl, libpmem, libdaxctl) + +libsystem_ss.add(files( 'balloon.c', 'bootdevice.c', 'cpus.c', @@ -23,9 +27,8 @@ system_ss.add(files( 'runstate-hmp-cmds.c', 'runstate.c', 'tpm-hmp-cmds.c', - 'vl.c', 'watchpoint.c', -), sdl, libpmem, libdaxctl) +)) =20 if have_tpm system_ss.add(files('tpm.c')) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350536; cv=none; d=zohomail.com; s=zohoarc; b=kuoIB8MP63j9nU/YiA+O9utDRD0zoollVi50Sf3jboA5Exf5pYtgyRlm66gebYtNG1x2DhlxRNeFp5pvlk/fTq7khniDvujbCPMVixJW/9DK21SO6uT9zHxzy1CsDFBYegIXhGr3B9Xj8NnIYTfxKIPEWGePsNG4ONGfkM9dr50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350536; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VhN0H72crR7ocnAMdx8d6CUFaK0puwv/7eMWfuXv8/4=; b=B4nQXH/t6zS5ATT+tzXxcoS7ik977lBARAvT/q9ODEs0Rhj3IDfzbwiBmhVRhzd7Hbf9GTvcmEBqv0u2zWYkfBJtNErhDFPKBTYdTGuDFFFgTqUMmWiGchILtSKovmcIDTzIf117fvmPBfo/Zsfi4aiD25rJ+LfgYko3DEMuFic= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350536759650.8737112305853; Tue, 22 Apr 2025 12:35:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JNs-0002XB-0R; Tue, 22 Apr 2025 15:34:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLb-0000Pw-4c for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:59 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLY-0006bw-GT for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:58 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-225477548e1so56979995ad.0 for ; Tue, 22 Apr 2025 12:31:55 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350314; x=1745955114; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VhN0H72crR7ocnAMdx8d6CUFaK0puwv/7eMWfuXv8/4=; b=b0YUwDfauX5GVdda3nQz7lSeuweNyscsaRuFsdmMSzEGyVgiey9ntAfU7mh+IuQrne YJdNrDCFbN9jC5eqCEWH3nvs8t5+Hf9VT5sezPK+ycB9OawoohY1UdiI2CUFVXKulB82 rKMzfRtMoBCOnMnBB3E9hp1SYxWz57crf3Q1IOJRmZHf771gcJbZQA8lU1W7ScXMuHbV tzqkcheBfOZidJLFNJ8Gh6c+8s97DMXs01uRVRUHS8En7CZBE21scmvx8vpHlufYh8Gd y4DYpnayLFenfwOPl+v1674CyrDXXAZZMLim/up3UvGv9V/3vjAqdpyDR9HkGXkpw47B 9lWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350314; x=1745955114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VhN0H72crR7ocnAMdx8d6CUFaK0puwv/7eMWfuXv8/4=; b=foJmSajifQU+kX1Pk/UIZMf1M93zDIqZO4xRKrN7CNhVkIeBINV6Varaq4M3T5idM9 mcoRvsKLN2vjDCVHYth2IAldv9KZlYbKjI8S3bLh8TaDlZC/F2JeWKSzULFRVR2ausPt nbFUhEdfiAqiXMvkS3hRzef+1hWNvNNHYzyBGdMYYVr1l0ZJHphmhd42ujFAJAYQtXB7 qM268xCL9K7HhDnDXQVVxqqaCghIMtPkJDIWnePTmF4goLf5cp3cjirpxg5hXQDWIF8a HIsILHj4I8LmE5DECmnUH57Fy6xlNsQGjPBb44qGhECWUYnBbhLVXVoOc3UNXTAl7xEx 1MMQ== X-Gm-Message-State: AOJu0YzARaCkaTq5kygpTLFCcFnCLD9WBH5L7FT9QI1uMwP5r6caNMGt ZiuruCPZEuktcoBBn4n02JHPHbNO4jloyyvUo9EBC2fsqSxv6rKGOTv0ksQeMYQOLaRXwRqtuYD w X-Gm-Gg: ASbGncspdoukU3WZElURdfR8T8scl0aQQiw749O6S1fHUPTDfNhFVLBG+NyJHfFCdCz mFDkdG4u82YopnkqvDj6j/LYdGi9FXgXMeFRoIBvqRDRMChHkLKy57/agvfSPu/8R1sz/mRnEco z4qMmNgnxnf0FUObIA4FdNkb4ZW2rtX0OoAHd5a9pAv7hHmzrFsJGT08ARu5s3GKVJMlJksugqk XdLJS5SvuZa0wTV0+f4Kg90ISYIAuk8yw9FAP9DJqWH7SqJS7A0DE7MoeoTF6dNgD5C7yI/01Xx Bw0kxcqUADaVjvfccSS7MMr4Eg41GHq3+klS5lmR6qh2tJnlJuyczukt/17gVqvky0sG76wUJC0 = X-Google-Smtp-Source: AGHT+IGOAwVHM5lv/o9dQBfWAdTUz86nYkbss67V50XaWl3GtQgDcW47BB69GTuwsEuVnds2NhrsuA== X-Received: by 2002:a17:903:1ce:b0:223:f9a4:3f9c with SMTP id d9443c01a7336-22c5337ca0cmr223085375ad.9.1745350314633; Tue, 22 Apr 2025 12:31:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 051/147] plugins: Move api.c, core.c to libuser_ss, libsystem_ss Date: Tue, 22 Apr 2025 12:26:40 -0700 Message-ID: <20250422192819.302784-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350539066019100 Content-Type: text/plain; charset="utf-8" Headers used by these files require CONFIG_USER_ONLY. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- plugins/meson.build | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/plugins/meson.build b/plugins/meson.build index 3be8245a69..5383c7b88b 100644 --- a/plugins/meson.build +++ b/plugins/meson.build @@ -61,5 +61,8 @@ endif user_ss.add(files('user.c', 'api-user.c')) system_ss.add(files('system.c', 'api-system.c')) =20 -common_ss.add(files('loader.c', 'api.c', 'core.c')) +libuser_ss.add(files('api.c', 'core.c')) +libsystem_ss.add(files('api.c', 'core.c')) + +common_ss.add(files('loader.c')) =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350663; cv=none; d=zohomail.com; s=zohoarc; b=Yg62QQatG8uRvaWlMuoJVmIeu9LPKdAMGOf1Ho4+NvAzE/CEOGFuSiUzAY5FiRuJk00p3DxwFmspyB3CO6/f42YLkCIRgdadGNJWR0Djg53f9rtTa52e0IK94gG3JVcvMVELPicbV83xjVPaMQYDZ97VhUKJP+CrBF+wpeddj/s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350663; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=irulUe5yhLpB5KcHQZP5AkpEiKTl4QGB2IoJogi1FPE=; b=MOo8PeGX65tVEIhaQCRlqElIBkWeh5YxWlpMOJpxoty7rDG08wShDoNd8V39V43K3sAhsQjmCI52i0erodq25QEdBsu88OJ247Owx9O6Ao/LLQEvCtzbtuV5nRRmFNmQIjp+umSYbaxaXEko9LHNY6qLgEyJOc/J9vhuUxj11lc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350663778998.4300696511502; Tue, 22 Apr 2025 12:37:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JNh-0002VE-IX; Tue, 22 Apr 2025 15:34:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLb-0000Pv-4K for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:59 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLY-0006cC-W8 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:58 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-224019ad9edso79383765ad.1 for ; Tue, 22 Apr 2025 12:31:56 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350315; x=1745955115; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=irulUe5yhLpB5KcHQZP5AkpEiKTl4QGB2IoJogi1FPE=; b=DYqiqaHP77MEVbtYBvLvlLf8iZZTVlcKLN2xVauf+5g5Fj0tYqA760SMXk5L0F2bu7 Jh96z9T2twOJPUmm/5n73OyugDONMuk3jiMnckRLddWWTWRXjkKT2zw00YxnLJ7xgHGK wiIQCc9B7FxvmfBNzUlUVXs9b+lM3NVP04/KWijmQtLaiPvdiYv7RTxSmAexTbUxTTJn 8xowAWhVvHVcJ0eU1LqKxJMjq38V7KC5yyS1T45tjhdKtA8EZ6ktAH7jNV6Gp3t30Q6W C+nSkRpZEqZ+sHPykSIUPDS7+Ux7rYl+f/pr+/POplPR15O3TKRSPn85cgK7w150NsZ3 2KHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350315; x=1745955115; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=irulUe5yhLpB5KcHQZP5AkpEiKTl4QGB2IoJogi1FPE=; b=SkRjGnsjFhSqyz15zYkKT37sWseVyXw1+BpUUQtwyqkFI3yYjheCS8hyAcu5j61lum +NF3+iT3di2RYowrlyjYOPIkkqoEu8glg/UYGleod06iDIDkmiOUcILPRM9hZ5h4AQHX UAkA/CN26JXKhCjGiDLE1yh3ni5zMJnIY40pVDJX0J2cxOec0Z1OpW8eH/nGGqAv98hg 5NL0eddmYNhjuCZR1/K3oMLW6ygEfC7FRM1wYiUuD5BIDs1YeFu+eOIOaH4jkQI2ZK8l 2cYs2IlsaHj2jREfyJf1nJuZjepXW62ArRooxVegGrka9s0pMJevFa4tbEZDN+Qc5EaA xL9g== X-Gm-Message-State: AOJu0Yya3bgfbF4Vu7th45vQpYlLjLemeGu/P8DsY1heF2uZYIeBtwf/ ugh6VEHxe6BUemrY3v7t994o8c3olymCF4fyaIM0lBN+rob3RiPPpJPAEJuAR+alr324zwmhZYI R X-Gm-Gg: ASbGnctMa3RRTAxq9JVu76IQwfmIRKYzXLIn0U8nsgRdZYbt/Lt37oKi/Yv4eyW1JJt RWLgEJ7E0fn6QCC3drnmyjv1/97uCnrmf9NpgIU18xS2JLm4l1GForZuCK76dxCl6oVPzWyAWwW DH99f1iAL+hnI+K9SeuY31s6GYLUzIZCjmSHNZVf7Azqnt3t5COBDVnKx2kP/TGWB6BC8VbpNK/ 0K3jHNAeD9Ukuik6f1gKLVHtOYntLbAZqMSrVX7Ixh6h81pDPkRl4IcXO82nLf8qyD3vgn9hBgC TM/NDtmm84qQkdTlMDdc7j06w1UJLtZ4ysiytqul8co7Vm7L5TcHIZCvwZoRPjhr4JlVeqvPdMc = X-Google-Smtp-Source: AGHT+IHtPj4R7EyOUmnoWoyNWIZO6ISVSVgE8tdqCadX6K9U7y+PugR+syluxoHOZdiSqzLoVLGPBA== X-Received: by 2002:a17:903:19cf:b0:224:5a8:ba2c with SMTP id d9443c01a7336-22c5364ed5cmr227665905ad.52.1745350315268; Tue, 22 Apr 2025 12:31:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 052/147] include/exec: Drop ifndef CONFIG_USER_ONLY from cpu-common.h Date: Tue, 22 Apr 2025 12:26:41 -0700 Message-ID: <20250422192819.302784-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350665359019100 Content-Type: text/plain; charset="utf-8" We were hiding a number of declarations from user-only, although it hurts nothing to allow them. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index be032e1a49..9b83fd7ac8 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -9,9 +9,7 @@ #define CPU_COMMON_H =20 #include "exec/vaddr.h" -#ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" -#endif #include "hw/core/cpu.h" #include "tcg/debug-assert.h" #include "exec/page-protection.h" @@ -40,8 +38,6 @@ int cpu_get_free_index(void); void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); =20 -#if !defined(CONFIG_USER_ONLY) - enum device_endian { DEVICE_NATIVE_ENDIAN, DEVICE_BIG_ENDIAN, @@ -176,8 +172,6 @@ int ram_block_discard_range(RAMBlock *rb, uint64_t star= t, size_t length); int ram_block_discard_guest_memfd_range(RAMBlock *rb, uint64_t start, size_t length); =20 -#endif - /* Returns: 0 on success, -1 on error */ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, void *ptr, size_t len, bool is_write); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352093; cv=none; d=zohomail.com; s=zohoarc; b=Qy3jA5K5Vs3pO5an5/PBVK1VxRxmmWQa6Ak9jpOvRsanj7xShP4abd+V1XnYtGvfOCBhscC028hOJRWoGcocoYuxgK7iyOvWwBYZxOJw9iFvY4TJl6PAnT4gnRaQWuaAKwv5FnM9qrKPmLjKBOwwp5ViABwVmZlmS/HSAex7cb0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352093; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mEj8DRwl0sBMiNx3GlTORUB7tXRrga1o2uCtdvfn7gU=; b=iplcB6ZNuoCINOnkbTbwCjiTwMo821IAtUNcbNzRZyn20FvEzHt4+T6dAEHXgvY7bkYCTCQXlAgww3c+P5wGpB3bhKkObYNPmxHaNxnXXvcHOQI3JtpM+I3pxYz3NtUrr2LMem/at1I1W6/cgrFJ0jRddkKs6jDRaxZ2AlpZZG0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352093180125.60916478286651; Tue, 22 Apr 2025 13:01:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JNU-0002HM-HH; Tue, 22 Apr 2025 15:33:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLb-0000Rj-NG for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:59 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLZ-0006cK-BK for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:31:59 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-22da3b26532so315025ad.0 for ; Tue, 22 Apr 2025 12:31:56 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350316; x=1745955116; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mEj8DRwl0sBMiNx3GlTORUB7tXRrga1o2uCtdvfn7gU=; b=Yb/K2L0m1h9Z2tuhq+7CTFWq+CiIwf838nVo/LARGpP68hITBwX6LRauuN7iwU7T0A ququQLI11cT8Q/gA57IKvEPjKLhSQhJlf2T5/AeiRlKP13D6u9qwmP9d14slZmvuUcfM 9DHIzgCFqQHuYO7gqbQOxx9aJym9FRg7aZR1vpSiTNU4Rxc6qY16HXIxpiVHyGEiyjci V0XSP7OeUnPxljy5NWjBaVpcRiY9RUkIUCQjIilgjEJkhjckmvEKM2k90swojdkVl6QU qSbf7swMRRDcRygZ58WLA3QGQUSmW+TY4a0+8mwFPyZ9sOJjWfdxzzkKkPl2oj2DI52q JLIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350316; x=1745955116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mEj8DRwl0sBMiNx3GlTORUB7tXRrga1o2uCtdvfn7gU=; b=dvdx9jm3Ben71NgpgX4iufNZGRJNxpeFKc2y9g1lG/UHzGTC/UDnHck2Nix9gMxoyy KgLjF4lQ2EIT7zAJG2wCgwg25tbppOB4a/TP8eMQMCxutts+xaFMx/vK2YcY395G5X13 KIESTgZ5IuZS0Q856YCpb9GwcjYn1EU9xfM1eCLd1IsCd/eGz9aqMMjQm2+HTonCZ4r0 +Z2L0GvOReq7YdCKnE/if7KkmalhiQHqgjKWs3ERIkmPRWTcC5rTSPexjSgnHASSsSgL JyiWk3/OuQ8czqOYzK64Y6nz7osDpliK90ykZKg1REalOvYbgxuGvZxi+4e8vQgA5qrT uqLw== X-Gm-Message-State: AOJu0YzrBZOXd8k4m7JmSTqHcmZt9vqZqh5ImseG7pBivJD8o48jvxeE qVTksCGZo+Txq0C73lTJ2ksd1IgFzlUGqKhl5sqdT7yYjdXvYCfcQ210pa5dDtgG8/DOd48udz5 l X-Gm-Gg: ASbGncuY7S5JUsDyXR19bbGKA5+9szcYNKTRubuyrFsTR/4wKOlK3uqU3vWS+LGVFkh gQQDflpb0rm9e+713qKLS+Z4ZwvXvNcyE5oNKn0jN65tbXsn/rddgPCZEsTnqUTY5IvdAFlrr8C TwWsUZF5xTawoWNg2mTiNwhgImdlAhcY5gfkn7OVIai589/KuLDoi9PzFsCJ5uEF37KKrMlzUct kHHRueypexRd0JMrFb83IU50vhFyWhXK8UJez9gUSp5zqvV+MKjN5aFyIPSLG6qRzQER0cErQYx 8ZRKaaxwy+klV4QafIMvjUzFEEKUuAD8eyP8YfkZDBZiVgOvXZgOXMcRSTTGchKiLNCHnrF1Ni8 = X-Google-Smtp-Source: AGHT+IHG8gSzTv2fFDZgH6bG9alPznE0yotHGGv3OMtBDF1FDLg0n3+oz2q/f4QekNA1BoUCaJ0P7w== X-Received: by 2002:a17:903:1a6b:b0:224:c46:d167 with SMTP id d9443c01a7336-22c53581853mr236385015ad.16.1745350315873; Tue, 22 Apr 2025 12:31:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 053/147] include/hw/core: Drop ifndef CONFIG_USER_ONLY from cpu.h Date: Tue, 22 Apr 2025 12:26:42 -0700 Message-ID: <20250422192819.302784-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352095518019000 Content-Type: text/plain; charset="utf-8" We were hiding a number of declarations from user-only, although it hurts nothing to allow them. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 37cb7d1531..6dcee5d0ba 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -614,8 +614,6 @@ extern bool mttcg_enabled; */ bool cpu_paging_enabled(const CPUState *cpu); =20 -#if !defined(CONFIG_USER_ONLY) - /** * cpu_get_memory_mapping: * @cpu: The CPU whose memory mappings are to be obtained. @@ -676,8 +674,6 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, C= PUState *cpu, */ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); =20 -#endif /* !CONFIG_USER_ONLY */ - /** * CPUDumpFlags: * @CPU_DUMP_CODE: @@ -701,7 +697,6 @@ enum CPUDumpFlags { */ void cpu_dump_state(CPUState *cpu, FILE *f, int flags); =20 -#ifndef CONFIG_USER_ONLY /** * cpu_get_phys_page_attrs_debug: * @cpu: The CPU to obtain the physical page address for. @@ -758,8 +753,6 @@ bool cpu_virtio_is_big_endian(CPUState *cpu); */ bool cpu_has_work(CPUState *cpu); =20 -#endif /* CONFIG_USER_ONLY */ - /** * cpu_list_add: * @cpu: The CPU to be added to the list of CPUs. @@ -1136,8 +1129,6 @@ const char *target_name(void); =20 #ifdef COMPILING_PER_TARGET =20 -#ifndef CONFIG_USER_ONLY - extern const VMStateDescription vmstate_cpu_common; =20 #define VMSTATE_CPU() { = \ @@ -1147,7 +1138,6 @@ extern const VMStateDescription vmstate_cpu_common; .flags =3D VMS_STRUCT, = \ .offset =3D 0, = \ } -#endif /* !CONFIG_USER_ONLY */ =20 #endif /* COMPILING_PER_TARGET */ =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351466; cv=none; d=zohomail.com; s=zohoarc; b=QxcHP732GJuo+jbfjKZE42ys+2o7PHixD+klxTQJpYlN2PMl65tnxA/XElrRhU7NheOWyIln6AV72KiiACnw1ApNtB1L3Bh/LESv0xoabJgV+y+XQ8i+OkKmzOeJ3emjKS8s4jC8gfVKDbUkeibPvvT20IkjYWFxORnAHKizbZY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351466; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=u3MzC1SM8/P9FwN0GSrhaTCjx8/yGZnbGlkuu1GEQBw=; b=OQC6eL+qpXiqPZLkA5EoNS7BP1xIWeIXOPEQRgrLYIeten4o6sLNadsT+PvEEmx3kk2gUAaZ5b60N5DpGcH0AMRNIlJkwV4wyTi3pZuNJA9OJFmt7hd6/Ab5qKn503ZGJlAJYMdX1gDYKmZuQQGPMH/isfChBYoClVARi1tf/yY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351466699515.0002523705599; Tue, 22 Apr 2025 12:51:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPJ-0005rb-7U; Tue, 22 Apr 2025 15:35:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLc-0000XT-TK for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:01 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLa-0006cU-1N for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:00 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-224019ad9edso79384125ad.1 for ; Tue, 22 Apr 2025 12:31:57 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350316; x=1745955116; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u3MzC1SM8/P9FwN0GSrhaTCjx8/yGZnbGlkuu1GEQBw=; b=uoYTgjZQiGbphS8dgKp+O7XwTxeOOHkXQGaDJSgQWCJRGNMlWFwK250a5IvLfxQRcj GaDJiFyWGU4ApPK6++62JA5WK5wSxZUhYa1k8DQoTiR2mqgMabq9SIuM0VTC6QFjLgCD LtxcHLDZrQGfRKN19vyCVRudEb/IRgfK2HL9GEhpMX6t84rH+lEsq68gUtfyGvv4nh7T n2DDz4eEmONF1wc8HG60gbOkpd6JVKDG9SAasN+p3jgr5fc9n4tmuM/4JtwX0Av5S9y6 H9XdF9rUoB2lcvpwPKIHvsxCAJcbrAKgCWkG56lSRLfvHI3V2CxqhBX46/iFNYDkVQBR hS8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350316; x=1745955116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u3MzC1SM8/P9FwN0GSrhaTCjx8/yGZnbGlkuu1GEQBw=; b=esb9d3G34EaV9aYEmWAfjgCO0HXV0FARweMf884c7gz4Zu+V6wJxdTmATGst+nhYvf s4NlGtmvwA246DQUgC5jzTcEZPUGvJvY46xmg5Cny4rmzrRxEG5Ebz3YzxOLXckFLLES LbDMxJejTynLmApP3QfA70uQ92z3TlK+xPViChFPMEksDKm4i/RpTczd9VAAwtTFra79 vKADE568S8VPPiQTPW0uEY1dG7ZIqDl7eeUnHPNRx5mZgT4wYl4GGx3YWEzIN+P98d2E oXPK5/MoJqjk2AGXBO/I3Ddh/Rz2YuBKeikCMcTrsWz0XOKfBg9q6GGQEGdmzroQSOw7 60JA== X-Gm-Message-State: AOJu0YyJiH3zWZta12bVvf0u5Bd6JVXnRPi9hyS1Mr+k1JgZWbM7ddwm aF3oMltoGqQAL4iejzQoOzrhR7zXnh34cGWmGlGORkfLpTvibPD2PhpMBLJnDsadhlTCJa+FXLL P X-Gm-Gg: ASbGncs6Yd4GTdYCotl9BsvfzFJLlZ8Ellt6P6WT4y5QZwSrZErittgFWdnHagX4o1/ kGLkwPqVYj9DIGgWcSAIJ2trx7eUBfgkEAAbwy24FvPzwXi3F5Bhx5BRl+EHIinVx+SkKeb3JOo 3OrNg2b9xyA3Y034J4IQHJUzClm1e5p4ApPNUHGYjEaYrwgppdHdBZvCpbKTqIvgBjm3R1pclrm 5LE2Fb4TzBGR5zOzFJw5NfXjm6bUbebep5Sh4WEgjEQtjN7IVY+BLhylwqc9hKKRZQMlYfFxRdz hQlTIxMsXkmyJFiy5FU13bkgVWnV/25SaXc0QzC3avluuhpPoekxvmuwK3+HbNFNI+0MGasLnlI = X-Google-Smtp-Source: AGHT+IEgjAGH/G1ykdDrixRlHejmh0ufMdRscNHAjfO8TRNToLrNz6aXNtbofRrXdJQ43Obo6t3EcQ== X-Received: by 2002:a17:902:db01:b0:223:501c:7581 with SMTP id d9443c01a7336-22c535a4e39mr236434995ad.16.1745350316524; Tue, 22 Apr 2025 12:31:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 054/147] include/hw/intc: Remove ifndef CONFIG_USER_ONLY from armv7m_nvic.h Date: Tue, 22 Apr 2025 12:26:43 -0700 Message-ID: <20250422192819.302784-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351469399019100 Content-Type: text/plain; charset="utf-8" We were hiding a number of declarations from user-only, although it hurts nothing to allow them. The inlines for user-only are unused. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/armv7m_nvic.h | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 89fe8aedaa..7b9964fe7e 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -189,21 +189,7 @@ int armv7m_nvic_raw_execution_priority(NVICState *s); * @secure: the security state to test * This corresponds to the pseudocode IsReqExecPriNeg(). */ -#ifndef CONFIG_USER_ONLY bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); -#else -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secur= e) -{ - return false; -} -#endif -#ifndef CONFIG_USER_ONLY bool armv7m_nvic_can_take_pending_exception(NVICState *s); -#else -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) -{ - return true; -} -#endif =20 #endif --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352549; cv=none; d=zohomail.com; s=zohoarc; b=FPz+EHsERDNZ+0LA5R4ZHOhUb61PNBz5LVgeqU8+9bwwVEnv8EpsQidqM5E7nMWeA8zdFUxbMOhPOVEAxkqegeBYJy/+6C8TT1cbUEON5zj7m+LyFb/ymarWj3c9MwBG2yKN1YjhRWtaw/M7TtF4XXil6xX0XnKfb35OPkKbEek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352549; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BoCYXpmxTadp3XapZ6TJFD3hsb+jhxzWsNPz+aVP0mI=; b=Dl2juXNPj7z+kB1o3TOPdTjLZEpPnfxbcYawWPS7rVQ/kTSwptPOnVlXkmRVsIT54CqmLCxCukWE77GxCZO4+JBMC4PVkKMLQQZGR66pd8IDbdq8llDl9QAptnQx1kmAvL6i6eARTvWULnXF0BtynwPWmhyGXV43i6wBW6sdOtk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352549273734.6737371627901; Tue, 22 Apr 2025 13:09:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JR5-0001I3-4e; Tue, 22 Apr 2025 15:37:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLh-0000fs-E1 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:07 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLb-0006ch-To for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:04 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-227d6b530d8so58374775ad.3 for ; Tue, 22 Apr 2025 12:31:58 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350317; x=1745955117; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BoCYXpmxTadp3XapZ6TJFD3hsb+jhxzWsNPz+aVP0mI=; b=Tzhw8rV1VZT81rseU4N0/CkDeCUE3iZtvSQpLmZZAFb6r2h2aishWrQFW9I4gYz0Yx PR1LSjylz13hyQzMTfBW/8YVFWSCLw6ezMPbZIBnHojzjkBWvGcbUa3nWXEbNuLBNHGz Hvocy3gNgg6N5kzBK7aJgiD/xiIet2I/1PcWwL64T6BFRgrv+755MJPJK1a5vmw4a/AS LbNcKwPl71JZ6hwJ0dBgVghxv0Iq+bIQIw3oO7Ct5OHAAOql6RZUzXIP9cDxAI/Q3cio dRkEsdpHXEst3IuUs+BnN/l6VWATo4wg1PFusP9/R93PjOs0eScM+Ot85zhErZnCh4N2 RFYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350317; x=1745955117; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BoCYXpmxTadp3XapZ6TJFD3hsb+jhxzWsNPz+aVP0mI=; b=IQAEDvmuWGo2G45YvtLaj/aWVFlnVDXVj1TeoTUHWIevJKgpBCujjDCmRaY8ET8lbN zE16uU5axeM2SKuAWR0AhYM5+ucvQ9/CsSZKCB0z1J5538QlGvUZZ9HATRI6cuMC6CwV 9Rl3zEl7phyyHPUsisxjpE3JRV+02GBzMoEjC8yD8eGribzpO1TP7xT0QXqiGAV5w9uU 88uax9jmRcntJwaPmldP3XUVVSlWJN0nQhL8g99s8LD3r5UFEnvHVrq1Jx9Zwfc0cqQA gMLtOz5hWqaItqBYwEH07CFFewT3ocJ/zjgjXxBarWCDQ/ux5ldIy6EiefJP7e8f8Rzy yFLA== X-Gm-Message-State: AOJu0Yx/Sn4fHSehpzoKAqTT/lh+D3dwPwCYN7udk7BrX++WhN+MltgX uSiqbhzTgrsP0yXaXgyz/oRLeG2q2cLW49CGmbPUEB4GHoOMRj0WShtLVWVO4428C/h4XbeTlX9 g X-Gm-Gg: ASbGncscakFSEbuNIPATDoouiRP0J3FLu3fIDTsa2C6KSm3VCUneh8DcoxsFSR9lzwa LorW20TTEuIQ4hfjSOJsVcJVPHAKNG0m/ubmCSas3WIldIXu3r3h/VrlbWFTZuVBW1RHtMvPUsK 7j1Kmk3A1vUT/Ihn/4QYkAhdalt1Cc0B/AsZBUbU3XCzD9CmN9SjeSjdbN54IW0d7B5gLQAf+dd h65XhfYyxUtRfh430C7PkuxkEbeIS1VlsfBZGPn1sG5ls2Mn7eRNk1jW9nlfhqDpxHv0lnIB9cx HSFziuXzjiWvDhFydGFYcFKJcKs34bdyaeqHLNY9X3gAScoWvz/gDGMaGDArG+Ls+Ls1g+SOKCW vSJQZe2lL1w== X-Google-Smtp-Source: AGHT+IGytOSzE39M6wuHRJfpbJwRfmWFee/iQzjpKNry0zQgeAi4DtPzAIWLzjW6mdTTmtvcn3Bo0A== X-Received: by 2002:a17:902:ced0:b0:224:26fd:82e5 with SMTP id d9443c01a7336-22c536272b1mr249454495ad.48.1745350317117; Tue, 22 Apr 2025 12:31:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 055/147] include/hw/s390x: Remove ifndef CONFIG_USER_ONLY in css.h Date: Tue, 22 Apr 2025 12:26:44 -0700 Message-ID: <20250422192819.302784-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352551307019000 Content-Type: text/plain; charset="utf-8" We were hiding a number of declarations from user-only, although it hurts nothing to allow them. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/hw/s390x/css.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/hw/s390x/css.h b/include/hw/s390x/css.h index cd97e2b707..965545ce73 100644 --- a/include/hw/s390x/css.h +++ b/include/hw/s390x/css.h @@ -238,7 +238,6 @@ uint32_t css_get_adapter_id(CssIoAdapterType type, uint= 8_t isc); void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maska= ble, uint8_t flags, Error **errp); =20 -#ifndef CONFIG_USER_ONLY SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid); bool css_subch_visible(SubchDev *sch); @@ -262,7 +261,6 @@ int css_enable_mss(void); IOInstEnding css_do_rsch(SubchDev *sch); int css_do_rchp(uint8_t cssid, uint8_t chpid); bool css_present(uint8_t cssid); -#endif =20 extern const PropertyInfo css_devid_ro_propinfo; =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352138; cv=none; d=zohomail.com; s=zohoarc; b=XWJkwvhTI4iK+30xayYbCNccoCqFNuzJtUe5aZ745+RlxWHBFlVMO4q98mpZnZozJ3yIEH0NfVh/FTTO0X1udXqN8aNzMd9+i64/qd60PfCXxY1HqH28Ky9hFaW9vMGwK3a2imZ9L+ye0dT4xtEtN/BgyHarZw5dxrn4EwLqdsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352138; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=0uxfEtRPulhqCz9P8lMUWCBJIGVs2GTvcMpeRpiAY+Y=; b=amk2HI2/dzC4AsFuAF+/3hfMXUl8aQNtToHHSpVHePiFqTY5qc/+3ujuxWbN3xcYFUaxF3zjMNkc7i5n2jQX+N/soDr3dJEL5yeXNQ9neQoXsw+bRRnkVWtuLGHIWeKprPml4BMFQsgcw0xp1I/Va8dTuB/K2jD9rTqq454Fbdw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352138506742.9371478748876; Tue, 22 Apr 2025 13:02:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPN-00069z-9U; Tue, 22 Apr 2025 15:35:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLf-0000fi-Jf for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:07 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLc-0006cv-HB for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:03 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-224019ad9edso79384415ad.1 for ; Tue, 22 Apr 2025 12:31:58 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350318; x=1745955118; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0uxfEtRPulhqCz9P8lMUWCBJIGVs2GTvcMpeRpiAY+Y=; b=aNp4S9AM0PUl7r5GivGSMABo6MhjI/2/FZZ83C3wgNcJUmAmLSFtzKPP1BJL/GWlxm ERxDZs9to4Chfo598X1yrDKikMHQHCQMbRRXRcl0u21vW4r/PlheUgbClmjUYU9QbnaZ zY7i9tLmay4NGru//x2um9gRfOsoiMLVxbxF8EH0kzMF8uM3LYKCuHbOPsfk2bLUm/iy kMcWSAzR/q7whv8ExrneJp8Z/LoDI2ma9GYgI2TB9cj58hsJ4gz/Xe2Z+1xFT0E9r550 n0FQPGanwL/LVUDSq+U0UBNOIKDysiPgvMGrdJUX9/+4BYLUHiwiMaOzaP4a4/gzsVuw UGXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350318; x=1745955118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0uxfEtRPulhqCz9P8lMUWCBJIGVs2GTvcMpeRpiAY+Y=; b=FZ2d0m8Yn5UiMKSw6h3fGBGQyzXtNjsVldIYraF9nX5Sw8q1YVR5kbn3JiO3jeq052 ogBumaDt/yjalPJJ4xWYgyPQsi2hW0SePMlRGnfYyNl8Y+WwSD1FcdOTfGNhV6ZhQKIo MT6MBJwCXhmw+Rww/9GC8amr08ELaO+XJF49UxiFoKC18fVR5wggOVhq9rIasggR0x5T VurzH5TPvv0MaFI5Jqvawp4kKRhvsguGjVypu06zKKB2NTSAgdgV6psvN4c8xN+b8jAa mY7RIyy0ORBoEYQ0XgrpGVbVD9fdSpEMnDpPme95HLkN4kHAb72tVRTaCpVEFNmEqYkV IGEQ== X-Gm-Message-State: AOJu0YzE58pglAUgPuWfkvlOj19nEAXGngO3rpn+7cUulf0uerPY1Pwr YnPh7rK3aD7ngCHrD/XY1VzkvWfyo81rjguvHjKwIXdR9qy2NUA1Z/3+lHD8oIieDNbaCLKBqcD 2 X-Gm-Gg: ASbGncuYdV6Gtn1yAgo+6wjEpMoph8IN7diANpJ3q8aA4GHXU4a7uQNkHNMeSMhBFFx qC3LpAyh16txyIR80hPq4LQHQNJs2sySfiHVlTETKsqfruCsE8R8UWEv5JHOw7gVINKdN/5ZIS0 MsvIa75pMBpTsMg9YNGHQqkkdyWqOxh9KkIBmjqSUz0C9Ph/em/noddILHcF31b/ab+jGfalTmk kD0gdqbjEQ6xI06zQ5iPsuyB/P2dYHUdYx6XNVsolBUfBq3mwTcFdwp0BtSPm8WDpxLPifLRRDA grkPU8CQ46PQVJx6G+PMf0BONVTynVihOSjg1N3toPtDsfOx1uvmiOv1D/bexSSAHraoBT16JIA = X-Google-Smtp-Source: AGHT+IFTQXpaqW2sKBZlhBXLXrJtmoL9BeumQ9lWsq9kWsirlKdFzdreKl4POt14rO3SZqxu1uXdKw== X-Received: by 2002:a17:903:990:b0:223:f408:c3dc with SMTP id d9443c01a7336-22c5357a703mr246169795ad.9.1745350317743; Tue, 22 Apr 2025 12:31:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 056/147] include/exec: Split out icount.h Date: Tue, 22 Apr 2025 12:26:45 -0700 Message-ID: <20250422192819.302784-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352141819019100 Content-Type: text/plain; charset="utf-8" Split icount stuff from system/cpu-timers.h. There are 17 files which only require icount.h, 7 that only require cpu-timers.h, and 7 that require both. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/icount.h | 68 ++++++++++++++++++++++++++++++++ include/system/cpu-timers.h | 58 --------------------------- accel/tcg/cpu-exec.c | 2 +- accel/tcg/icount-common.c | 2 +- accel/tcg/monitor.c | 1 + accel/tcg/tcg-accel-ops-icount.c | 2 +- accel/tcg/tcg-accel-ops-mttcg.c | 2 +- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/tcg-accel-ops.c | 2 +- accel/tcg/tcg-all.c | 2 +- accel/tcg/translate-all.c | 2 +- hw/core/ptimer.c | 2 +- replay/replay.c | 2 +- stubs/icount.c | 2 +- system/cpu-timers.c | 1 + system/dma-helpers.c | 2 +- system/vl.c | 1 + target/arm/helper.c | 1 + target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/debug.c | 1 + target/riscv/machine.c | 2 +- target/riscv/pmu.c | 2 +- util/async.c | 2 +- util/main-loop.c | 1 + util/qemu-timer.c | 1 + 26 files changed, 92 insertions(+), 75 deletions(-) create mode 100644 include/exec/icount.h diff --git a/include/exec/icount.h b/include/exec/icount.h new file mode 100644 index 0000000000..4964987ae4 --- /dev/null +++ b/include/exec/icount.h @@ -0,0 +1,68 @@ +/* + * icount - Instruction Counter API + * CPU timers state API + * + * Copyright 2020 SUSE LLC + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef EXEC_ICOUNT_H +#define EXEC_ICOUNT_H + +/** + * ICountMode: icount enablement state: + * + * @ICOUNT_DISABLED: Disabled - Do not count executed instructions. + * @ICOUNT_PRECISE: Enabled - Fixed conversion of insn to ns via "shift" o= ption + * @ICOUNT_ADAPTATIVE: Enabled - Runtime adaptive algorithm to compute shi= ft + */ +typedef enum { + ICOUNT_DISABLED =3D 0, + ICOUNT_PRECISE, + ICOUNT_ADAPTATIVE, +} ICountMode; + +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) +extern ICountMode use_icount; +#define icount_enabled() (use_icount) +#else +#define icount_enabled() ICOUNT_DISABLED +#endif + +/* + * Update the icount with the executed instructions. Called by + * cpus-tcg vCPU thread so the main-loop can see time has moved forward. + */ +void icount_update(CPUState *cpu); + +/* get raw icount value */ +int64_t icount_get_raw(void); + +/* return the virtual CPU time in ns, based on the instruction counter. */ +int64_t icount_get(void); +/* + * convert an instruction counter value to ns, based on the icount shift. + * This shift is set as a fixed value with the icount "shift" option + * (precise mode), or it is constantly approximated and corrected at + * runtime in adaptive mode. + */ +int64_t icount_to_ns(int64_t icount); + +/** + * icount_configure: configure the icount options, including "shift" + * @opts: Options to parse + * @errp: pointer to a NULL-initialized error object + * + * Return: true on success, else false setting @errp with error + */ +bool icount_configure(QemuOpts *opts, Error **errp); + +/* used by tcg vcpu thread to calc icount budget */ +int64_t icount_round(int64_t count); + +/* if the CPUs are idle, start accounting real time to virtual clock. */ +void icount_start_warp_timer(void); +void icount_account_warp_timer(void); +void icount_notify_exit(void); + +#endif /* EXEC_ICOUNT_H */ diff --git a/include/system/cpu-timers.h b/include/system/cpu-timers.h index 64ae54f6d6..a1abed0d7a 100644 --- a/include/system/cpu-timers.h +++ b/include/system/cpu-timers.h @@ -15,64 +15,6 @@ /* init the whole cpu timers API, including icount, ticks, and cpu_throttl= e */ void cpu_timers_init(void); =20 -/* icount - Instruction Counter API */ - -/** - * ICountMode: icount enablement state: - * - * @ICOUNT_DISABLED: Disabled - Do not count executed instructions. - * @ICOUNT_PRECISE: Enabled - Fixed conversion of insn to ns via "shift" o= ption - * @ICOUNT_ADAPTATIVE: Enabled - Runtime adaptive algorithm to compute shi= ft - */ -typedef enum { - ICOUNT_DISABLED =3D 0, - ICOUNT_PRECISE, - ICOUNT_ADAPTATIVE, -} ICountMode; - -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) -extern ICountMode use_icount; -#define icount_enabled() (use_icount) -#else -#define icount_enabled() ICOUNT_DISABLED -#endif - -/* - * Update the icount with the executed instructions. Called by - * cpus-tcg vCPU thread so the main-loop can see time has moved forward. - */ -void icount_update(CPUState *cpu); - -/* get raw icount value */ -int64_t icount_get_raw(void); - -/* return the virtual CPU time in ns, based on the instruction counter. */ -int64_t icount_get(void); -/* - * convert an instruction counter value to ns, based on the icount shift. - * This shift is set as a fixed value with the icount "shift" option - * (precise mode), or it is constantly approximated and corrected at - * runtime in adaptive mode. - */ -int64_t icount_to_ns(int64_t icount); - -/** - * icount_configure: configure the icount options, including "shift" - * @opts: Options to parse - * @errp: pointer to a NULL-initialized error object - * - * Return: true on success, else false setting @errp with error - */ -bool icount_configure(QemuOpts *opts, Error **errp); - -/* used by tcg vcpu thread to calc icount budget */ -int64_t icount_round(int64_t count); - -/* if the CPUs are idle, start accounting real time to virtual clock. */ -void icount_start_warp_timer(void); -void icount_account_warp_timer(void); -void icount_notify_exit(void); - /* * CPU Ticks and Clock */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 372b876604..034c2ded6b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -35,7 +35,7 @@ #include "exec/log.h" #include "qemu/main-loop.h" #include "exec/cpu-all.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "exec/replay-core.h" #include "system/tcg.h" #include "exec/helper-proto-common.h" diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index 402d3e3f4e..d6471174a3 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -35,7 +35,7 @@ #include "system/replay.h" #include "system/runstate.h" #include "hw/core/cpu.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "system/cpu-timers-internal.h" =20 /* diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c index eeb38a4d9c..1c182b6bfb 100644 --- a/accel/tcg/monitor.c +++ b/accel/tcg/monitor.c @@ -14,6 +14,7 @@ #include "qapi/qapi-commands-machine.h" #include "monitor/monitor.h" #include "system/cpu-timers.h" +#include "exec/icount.h" #include "system/tcg.h" #include "tcg/tcg.h" #include "internal-common.h" diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-ico= unt.c index 27cf1044c7..d0f7b410fa 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -25,7 +25,7 @@ =20 #include "qemu/osdep.h" #include "system/replay.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "hw/core/cpu.h" diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index bdcc385ae9..dfcee30947 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -26,7 +26,7 @@ #include "qemu/osdep.h" #include "system/tcg.h" #include "system/replay.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index f62cf24e1d..6eec5c9eee 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -27,7 +27,7 @@ #include "qemu/lockable.h" #include "system/tcg.h" #include "system/replay.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 5c88056157..ccdb781eef 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -29,7 +29,7 @@ #include "system/accel-ops.h" #include "system/tcg.h" #include "system/replay.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "qemu/timer.h" diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index c1a30b0121..7a5b810b88 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -26,7 +26,7 @@ #include "qemu/osdep.h" #include "system/tcg.h" #include "exec/replay-core.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "tcg/startup.h" #include "qapi/error.h" #include "qemu/error-report.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 167535bcb1..bb161ae61a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -55,7 +55,7 @@ #include "qemu/cacheinfo.h" #include "qemu/timer.h" #include "exec/log.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "system/tcg.h" #include "qapi/error.h" #include "accel/tcg/cpu-ops.h" diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index 7f63d17ca1..0aeb10fb53 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -11,7 +11,7 @@ #include "migration/vmstate.h" #include "qemu/host-utils.h" #include "exec/replay-core.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "system/qtest.h" #include "block/aio.h" #include "hw/clock.h" diff --git a/replay/replay.c b/replay/replay.c index 3adc387b3d..a3e24c967a 100644 --- a/replay/replay.c +++ b/replay/replay.c @@ -11,7 +11,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "system/replay.h" #include "system/runstate.h" #include "replay-internal.h" diff --git a/stubs/icount.c b/stubs/icount.c index edbf60cbfa..ceb73b4fc2 100644 --- a/stubs/icount.c +++ b/stubs/icount.c @@ -1,6 +1,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" =20 /* icount - Instruction Counter API */ =20 diff --git a/system/cpu-timers.c b/system/cpu-timers.c index 23dd82b465..cb35fa62b8 100644 --- a/system/cpu-timers.c +++ b/system/cpu-timers.c @@ -36,6 +36,7 @@ #include "hw/core/cpu.h" #include "system/cpu-timers.h" #include "system/cpu-timers-internal.h" +#include "exec/icount.h" =20 /* clock and ticks */ =20 diff --git a/system/dma-helpers.c b/system/dma-helpers.c index 6bad75876f..0d592f6468 100644 --- a/system/dma-helpers.c +++ b/system/dma-helpers.c @@ -13,7 +13,7 @@ #include "trace.h" #include "qemu/thread.h" #include "qemu/main-loop.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "qemu/range.h" =20 /* #define DEBUG_IOMMU */ diff --git a/system/vl.c b/system/vl.c index ec93988a03..c17945c493 100644 --- a/system/vl.c +++ b/system/vl.c @@ -89,6 +89,7 @@ #include "audio/audio.h" #include "system/cpus.h" #include "system/cpu-timers.h" +#include "exec/icount.h" #include "migration/colo.h" #include "migration/postcopy-ram.h" #include "system/kvm.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index 0454b06a6c..becbbbd0d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -24,6 +24,7 @@ #include "exec/translation-block.h" #include "hw/irq.h" #include "system/cpu-timers.h" +#include "exec/icount.h" #include "system/kvm.h" #include "system/tcg.h" #include "qapi/error.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6c4391d96b..0dd8645994 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -31,7 +31,7 @@ #include "accel/tcg/cpu-ops.h" #include "trace.h" #include "semihosting/common-semi.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "cpu_bits.h" #include "debug.h" #include "pmp.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7948188356..c52c87faae 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -27,7 +27,7 @@ #include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/tb-flush.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "qemu/guest-random.h" #include "qapi/error.h" #include diff --git a/target/riscv/debug.c b/target/riscv/debug.c index fea989afe9..7fc9e121e1 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -32,6 +32,7 @@ #include "exec/helper-proto.h" #include "exec/watchpoint.h" #include "system/cpu-timers.h" +#include "exec/icount.h" =20 /* * The following M-mode trigger CSRs are implemented: diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 889e2b6570..a1f70cc955 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -21,7 +21,7 @@ #include "qemu/error-report.h" #include "system/kvm.h" #include "migration/cpu.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "debug.h" =20 static bool pmp_needed(void *opaque) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 0408f96e6a..a68809eef3 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -22,7 +22,7 @@ #include "qemu/timer.h" #include "cpu.h" #include "pmu.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "system/device_tree.h" =20 #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ diff --git a/util/async.c b/util/async.c index 863416dee9..2719c629ae 100644 --- a/util/async.c +++ b/util/async.c @@ -35,7 +35,7 @@ #include "block/raw-aio.h" #include "qemu/coroutine_int.h" #include "qemu/coroutine-tls.h" -#include "system/cpu-timers.h" +#include "exec/icount.h" #include "trace.h" =20 /***********************************************************/ diff --git a/util/main-loop.c b/util/main-loop.c index acad8c2e6c..42bd75c193 100644 --- a/util/main-loop.c +++ b/util/main-loop.c @@ -27,6 +27,7 @@ #include "qemu/cutils.h" #include "qemu/timer.h" #include "system/cpu-timers.h" +#include "exec/icount.h" #include "system/replay.h" #include "qemu/main-loop.h" #include "block/aio.h" diff --git a/util/qemu-timer.c b/util/qemu-timer.c index 788466fe22..1fb48be281 100644 --- a/util/qemu-timer.c +++ b/util/qemu-timer.c @@ -27,6 +27,7 @@ #include "qemu/timer.h" #include "qemu/lockable.h" #include "system/cpu-timers.h" +#include "exec/icount.h" #include "system/replay.h" #include "system/cpus.h" =20 --=20 2.43.0 From nobody Thu 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350318; x=1745955118; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/uK/6e74nn8Fot5LvCS7tmplWHujswrlAKxdO1vG4SM=; b=pqMS3LgFjVnlb7oJ4Zg71pITDQq+FrAzFiY2kUAWZLFcWeMTcb+oIwn6LBw2X+Pofn OGh5/8ZGIY67yTxcL3RQNzmM0kk82VD7AiaKbhSp6Tx1TUvXa6LxTpCdmnSaBRDmydID fYtFg2lzcBd7aJtBP6TXb+Qi0gvtWBG3VnIO8FdpV4dIejjZLzWmPJC6J3bcdW24m4fw F2Gxrt9M16vJiLOy+ToixW9VnVm9E5Vn8ETwEbHkEDf97BwN2bTAU/UCH2xyXk/gavC9 7DENKwUNHCjrnPb1Gzsef2AsPCtxmBV88dZm+lCLmllEw6T//4VrcLPHbWpy1KQO3uPE DduQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350318; x=1745955118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/uK/6e74nn8Fot5LvCS7tmplWHujswrlAKxdO1vG4SM=; b=H1CRzSg//IGHaD+959axekFfn6V/HhynzvtrFC1WGApnimF3x9nMq5XVbv/qW4JTmJ W2qQ3fui0VjhXkwjJ2ouI3uWaohk7cSMD0QotIOC3c4Fi1TeSs2XwSAfHW1iESvtitwF dEwddYLG06drXy88pjve1H0ptosZqKHR2Dhoh1LdsieZAGb4iu9HWq17OEB6BSjYBXkF kb9pLRyLbdK+5foD4fFTi0lh3bLsEeOjac8cHytKZWrkF5Ca1TX0oREGFc5DH5lrJqES 6v9PWGFJizEQ5LizWwJzYQO2llpmc9y/g61nNzD5K7X6vt+GJSs97mD1Sgf9jnNKdOQh 2LVQ== X-Gm-Message-State: AOJu0YyZxwmcLVtGrSmk2tP8BUUKPUSSQkugqJWl9o+fF1Vp1TPlMbVG tk0q53XqzTT8tNXkypPLNCde2NImvMvO86Eq6kBPEmjXGPQQ6zUMB0ouML7H0YloMTqJKTAjQQs G X-Gm-Gg: ASbGncuiRTK2AnD77yLVMAdMBECT28cuAPesBoKXcbHJ56tIYKlgGhhkTE8ig8MLQb9 s6ldaYmOM8ExquUVD59GO4I/agRzNcPV85l8qOsYVRCofypUJqFXBdZtH6TfhcRee1lWu/FMMsV Yw+285GaTg8E8JmaSrlMfNUM+mnsBQ9UEE59UIenep/pauEc2c+HYjN4y00twuSUI+fXj6TnjzL /DakB+DJ3GidCuXHCtZYlY6EipZSgYwLCx5ma4pYDLsVRS96OrRcPkUAvz/wbUMAiKdiymjOdA6 edckC2nuqqEWYOUDua1RwkDmxrazU50f8jb1NIjrNHsOWf4YM+ZCsAaK3KdTeZkeXbaFCcZSkMY = X-Google-Smtp-Source: AGHT+IFyMAnr3n8Qri4/q7uvsoq2AvNHasCCWieoVTPkN6YKfgR7EJBb6G1AuHRET8f1DiXyyS0HJA== X-Received: by 2002:a17:903:1aa8:b0:223:607c:1d99 with SMTP id d9443c01a7336-22da304bff3mr3947885ad.0.1745350318305; Tue, 22 Apr 2025 12:31:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 057/147] include/exec: Protect icount_enabled from poisoned symbols Date: Tue, 22 Apr 2025 12:26:46 -0700 Message-ID: <20250422192819.302784-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352874227019000 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/exec/icount.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/exec/icount.h b/include/exec/icount.h index 4964987ae4..7a26b40084 100644 --- a/include/exec/icount.h +++ b/include/exec/icount.h @@ -22,13 +22,21 @@ typedef enum { ICOUNT_ADAPTATIVE, } ICountMode; =20 -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) +#ifdef CONFIG_TCG extern ICountMode use_icount; #define icount_enabled() (use_icount) #else #define icount_enabled() ICOUNT_DISABLED #endif =20 +/* Protect the CONFIG_USER_ONLY test vs poisoning. */ +#if defined(COMPILING_PER_TARGET) || defined(COMPILING_SYSTEM_VS_USER) +# ifdef CONFIG_USER_ONLY +# undef icount_enabled +# define icount_enabled() ICOUNT_DISABLED +# endif +#endif + /* * Update the icount with the executed instructions. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/system/qtest.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/system/qtest.h b/include/system/qtest.h index 6ddddc501b..84b1f8c6ee 100644 --- a/include/system/qtest.h +++ b/include/system/qtest.h @@ -23,7 +23,6 @@ static inline bool qtest_enabled(void) return qtest_allowed; } =20 -#ifndef CONFIG_USER_ONLY void G_GNUC_PRINTF(2, 3) qtest_sendf(CharBackend *chr, const char *fmt, ..= .); void qtest_set_command_cb(bool (*pc_cb)(CharBackend *chr, gchar **words)); bool qtest_driver(void); @@ -33,6 +32,5 @@ void qtest_server_init(const char *qtest_chrdev, const ch= ar *qtest_log, Error ** void qtest_server_set_send_handler(void (*send)(void *, const char *), void *opaque); void qtest_server_inproc_recv(void *opaque, const char *buf); -#endif =20 #endif --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351427; cv=none; d=zohomail.com; s=zohoarc; b=MCdzkGY6ZRtobBbyV078t2bjw0++WR8D/HeqiHQCeqqfwDmibtgVujGXhcjvTwLXsu9Br89R6MWI/Lh5qlpYR8vs5MGY2K09HzSgUwVeUe3i4pzgLF47frGSjbkmeERpA6KDFXRB0U3AAVl5KHYwgVg5G12ocNH/EqaRY/4Gijg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351427; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Z/d4Opsx2QmpRYGlTe7zbsmEBVXLmlU0lp+CJtYfxNc=; b=AA8ZSYvwP9GoBbaMF4sAq//xnQCVjmfaCJ+fkRdpsW43vJo/XPtiF32r+7qFph28GDRSYtko/UBBeRJ3F00y036uskDmriYg7bEA0+C+UIsKHhbRgvSV7qFKdK0Jwd7aQKXEC7PS5CwyaySlXwdJJQv39oKpV0NB8/K+G2mzzIA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174535142743897.99268256767641; Tue, 22 Apr 2025 12:50:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPd-0006rh-JE; Tue, 22 Apr 2025 15:36:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLf-0000fh-Bx for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:07 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLd-0006dT-6X for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:03 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-227b828de00so60223265ad.1 for ; Tue, 22 Apr 2025 12:32:00 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350319; x=1745955119; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z/d4Opsx2QmpRYGlTe7zbsmEBVXLmlU0lp+CJtYfxNc=; b=qArbqv9qhealEbU49rmICwASJDtX0nzy3OVOGPTGpKcmAfrN2cWYyVIm6vX3L5m2JM ZuN74IKRMkSUP6ECKihZ2R9D5dVflnfxejR+XSoFeBBbHC8BZB4Zci5NkBYQ6UGZ1Nto efmU/KLq1SyAjjeT/GIv7bHl+3T71SaOb9TM2xI56bdgvUgLObtQ9ZXf8Qen4Uh0Xv6H /0E0iwTijiPA5IMLwMhdbawGZdCaxrPHGKqdGag3VRZRW2cjxxgdEpgJ8/yKCK1fTq/W E2/zhEY8ajhP4QZzZQOZr2DQv18O4nX2OWfvm1l8hoyJKqGBkdXxhCj3Slw+vmTWiZD9 L7Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350319; x=1745955119; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z/d4Opsx2QmpRYGlTe7zbsmEBVXLmlU0lp+CJtYfxNc=; b=dvqFqUMLBWsysns3FZss/pEwKBC6/84qpcTeXo8orKncCDqZPxHADyvHUrrcIUC0FP jUJ/EfPmuJa6mtr/b4UxztHT/KKBKOwqZRpHrHS8qwguLlBgHVPxeQOdxlGUnRkJObAM NmUpj88RGTR2+2Hp6eq/VtdTW8KTELhC3P6ZNKbn2TiuQsilTb3F3EOiyzZTsbMDN6BL NHgWc8qlhMSGXUAIXCAXl20FPMaRbIWHismim0PH8X7yqC+KAeCpkLOe9OVvBCOOw3e7 ZXWtJofXRBi3rDe4zYtawvg5pOeRpOKv3cb1oxjT4h15gg/oUHml0Z1xf+/vN7PJfp8p 30+g== X-Gm-Message-State: AOJu0YwFhrDMOvhery9yUQCEKWQXKZq8//Xhr/m2dGPYwql6G+3lXDhi CcDafjihDLKt6jZONElaD0KfV0/xWjJXe2Xbdxuh7wtz6TayIhiPdjXgS7AZ1eW4Mjo1zLGQGs0 j X-Gm-Gg: ASbGncvQEg5WhJmGu0Lg2qbXG5WpxCM/XrBC2UIc0gAtOetI/AbU6T1Xt3Fo/y5DkID nmcJvwlN4O4rN1ME499IE8cm2wnqZrhmTMoBB8HjNwJL5mnHwsbfZTZEnNZzaeiiOfYYBRoRLiz 9sElTqw8nZyVyzoguxm4x2NSDxqB0bLIlMrkctw0C5UXM3dYNSu3lFnq6ML8mZ10Ngo1I94WrVE vgiZ6LkARr/ZmIrVzdYq7jUkg4H68w7bRNdbwjtTqOpX3EqQtLA/OBGnZx0Kzl5sPqm/ZsUUiQ/ vKgbomUMesuDkN2+trdZuMKG5C+Y3nFlJlz9s/cLZ0hDn/CRqhdD9A9c1ZzHq878dKEGutHTaec = X-Google-Smtp-Source: AGHT+IHjnKRLmZUR+58ST303qB5aoXrghQNSd03NpNk6U2n/d5xrHPVsbrPkY1+RO/oXdbW4TkBUCw== X-Received: by 2002:a17:903:2344:b0:223:3396:15e8 with SMTP id d9443c01a7336-22c535834bfmr267115525ad.22.1745350319573; Tue, 22 Apr 2025 12:31:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 059/147] include/qemu: Remove ifndef CONFIG_USER_ONLY from accel.h Date: Tue, 22 Apr 2025 12:26:48 -0700 Message-ID: <20250422192819.302784-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351429380019100 Content-Type: text/plain; charset="utf-8" While setup_post and has_memory will not be used for CONFIG_USER_ONLY, let the struct have constant layout. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/qemu/accel.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/include/qemu/accel.h b/include/qemu/accel.h index 972a849a2b..fbd3d897fe 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -38,13 +38,13 @@ typedef struct AccelClass { =20 const char *name; int (*init_machine)(MachineState *ms); -#ifndef CONFIG_USER_ONLY + bool (*cpu_common_realize)(CPUState *cpu, Error **errp); + void (*cpu_common_unrealize)(CPUState *cpu); + + /* system related hooks */ void (*setup_post)(MachineState *ms, AccelState *accel); bool (*has_memory)(MachineState *ms, AddressSpace *as, hwaddr start_addr, hwaddr size); -#endif - bool (*cpu_common_realize)(CPUState *cpu, Error **errp); - void (*cpu_common_unrealize)(CPUState *cpu); =20 /* gdbstub related hooks */ int (*gdbstub_supported_sstep_flags)(void); @@ -78,12 +78,10 @@ const char *current_accel_name(void); =20 void accel_init_interfaces(AccelClass *ac); =20 -#ifndef CONFIG_USER_ONLY int accel_init_machine(AccelState *accel, MachineState *ms); =20 /* Called just before os_setup_post (ie just before drop OS privs) */ void accel_setup_post(MachineState *ms); -#endif /* !CONFIG_USER_ONLY */ =20 /** * accel_cpu_instance_init: --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351127; cv=none; d=zohomail.com; s=zohoarc; b=MGfKWQ41pLXBOx4rK6OFouwr9vHHHqjnvFl5wRsIMyJoYfD42in5p/6FBaYslQKNaL8RsvE/5y4WgxbM4tmzFL/s9RZneq11nbcQJ33o+dUuISzi8v7HdQgk0UVbhx8l3OBWMYPNQITL3K3KNXMwUCQkz9S82qO/a3W25y4syVA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351127; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=N/LWI/F8VdrNv0zLmIvQDUtowepeiN+2e5bv51DEBF8=; b=Bd3o0f7aZEZfp3Ffx25zVrGfzI0YN4avOP7GQzlLKj2AUjC/B25BR3RyMzZc2uZHHBAO+nbXkb9MJ4BuMcmbbWLvTYjB0xzUsdo06bz00tTkEJ4CsvyH/y5H1vf5l7LsiRCCDIb86hpXAfiQXWLOdaAGt5Ndr55pJjluFJtWOLU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351127669810.5854916067854; Tue, 22 Apr 2025 12:45:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPL-00061X-3f; Tue, 22 Apr 2025 15:35:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLf-0000fj-Ky for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:07 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLd-0006de-NT for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:03 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2241053582dso78276595ad.1 for ; Tue, 22 Apr 2025 12:32:01 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.31.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:31:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350320; x=1745955120; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N/LWI/F8VdrNv0zLmIvQDUtowepeiN+2e5bv51DEBF8=; b=F+3wQiHxGIC1kO2+3MBQ16NW/ggM9rc1SupvJLbw6EB1Yy7EAkYcpVLYqTn/wOPyJv 6McwzRtzNk2unbbDh7MQAvfgbtA84oAfaW2pUZ2K3/Ng5HZFxYsdvMHN2ABAviluyMJy m/OwXa/Zu89kC9iG+dXLAdZp4c0GDo71NZnhAUe6WDZpIZvUCHcw1o2VfB+4d8M5S0p4 4Cs+W3BnLvdANdQhTSa/D4km0cOYX2+jBIBCc44OYYwEipxiQ6e7iy6y6jSKAIJw5Dlj /2TvjkWKGY+JAA5RTdt/1tVNsD7S42D5Go0hrAJdyYQmPEhL3aCEhVyz787ljBZZobkL eZGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350320; x=1745955120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N/LWI/F8VdrNv0zLmIvQDUtowepeiN+2e5bv51DEBF8=; b=rSUAkt6RcHBpDDfIlZ50kgSQYvX+LrP6IFYkzXBexcX+dt2xdFsZobCOJNl2isc3GK 3Sd5CZmWLu6zNT41XLofbmSqS7HL2F1ywUERiFKxTRUpL4OViYTdpT205BWmH6fDDCXq m/wbLOZUezOSCR7ZUdUy4I5vtp6a9MFEmLwskTYz8ub/EJH+X1fyuWBw3Ro44K8UFWqy 89t/areSRlRphCKx7rzYf8xf1B8BuaelJhOp09zetdBca8Q0op+REeJcLrFl7vD0o+lm tgl52Y6T+jwDJaPI+a2XWQFH1fv7ABMEAp4iq4Mwfsvqzc6Q/wjr+oufBo3tymS2642Q g61A== X-Gm-Message-State: AOJu0YzqU7GTf3CY/CqX41xCsNSY61NjTzf7Z/fBkRmhkXTxYokCXJ5w K4g4TWzCHgUDp8xoSErF1//+GIHohf7D7g0SFxUg7z7iPL2v0kF0rGydtoN2Y+9CMyeWhHiYVza f X-Gm-Gg: ASbGncs2R1KoXjL4JI5xml1BsiVZrSI0lGJLBxJ126mbjKlMZPxu4jlyaL7RUP21t4A rrG5xOgXSDFAeXWu4yd2ZxC/wVTEOsIWhPuLiuIcO5SYcPBrE+DJEJdH3xRDTP2QcxTtNC4dIbY K4937BgavG+ollCH279hP41QyjJP9k7yG+WrunZJgmcMXwQ+mb0BmBnqQAPdE50+UbNGvlgiEW2 9FNrqFHjbiNQXm7s7xwkB7aISSEuLxW/3W3ALB3Z+MJS6o538d1yywIF8A2Ma5WzonoGs/Nhvbw o65TiDCMEflKYxYZhAXMSyIv/yO4L9PuEMKH2J+KgwzrnneDjE+8yJq1Yr/ZRGjqIqYvoJ5k/im D/6dmfMs9sA== X-Google-Smtp-Source: AGHT+IGJIgRF5vm0b8DMOQFMrPRxD+1jrTl1pVTjLQ/PntK9tXS9rWqrmN6akH0IEC/D6iW6wga7yA== X-Received: by 2002:a17:903:2410:b0:220:be86:a421 with SMTP id d9443c01a7336-22c536050f6mr274714465ad.38.1745350320207; Tue, 22 Apr 2025 12:32:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Alistair Francis , Pierrick Bouvier Subject: [PATCH 060/147] target/riscv: Remove ifndef CONFIG_USER_ONLY from cpu_cfg.h Date: Tue, 22 Apr 2025 12:26:49 -0700 Message-ID: <20250422192819.302784-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351130645019100 Content-Type: text/plain; charset="utf-8" While RISCVCPUConfig.satp_mode is unused for user-only, this header is used from disas/riscv.h, whose users are only built once. The savings of 4 bytes isn't worth it. Reviewed-by: Alistair Francis Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/riscv/cpu_cfg.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 8a843482cc..cfe371b829 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -196,9 +196,7 @@ struct RISCVCPUConfig { =20 bool short_isa_string; =20 -#ifndef CONFIG_USER_ONLY RISCVSATPMap satp_mode; -#endif }; =20 typedef struct RISCVCPUConfig RISCVCPUConfig; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352095; cv=none; d=zohomail.com; s=zohoarc; b=mmjuH2BLhbu5qaOhroastwtF7D2J5uKkWmkMMnWBIxMakeNrQx/ImWxgBdAMlDVg8Yyo7cSc/V+5XfwdiA3AMhdZsaUgGRHmGC9wGXxQZSLcCyY5Ijl0Cc5O4tzufTwh7yjPNVRZmFJ0iiROzQ3LLvcYkdZ12K4vXtfpD6N+u1g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352095; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LeENUlDVgehwxdXE0XXPfIIxCZLEhLec/NmTrOg0uCg=; b=f9O7M0Q81ld6CNoZzAltXeSl4fKMpZFF4u8hjFb7IZfH0DbWFvAOk2KIjSAzQzk7QK002CsUsDzIAjYc3PwN2Cr61vR1gM/cf+FpsK21Brfeiv4vB1qc0JSGYX1PW0J2AYShPZ7q7hyHSJy3dAUm4G8yiKwHjfRNN9YX7AgLifI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352095421111.75303740015522; Tue, 22 Apr 2025 13:01:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JQg-0000Zy-Nx; Tue, 22 Apr 2025 15:37:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLh-0000fr-DR for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:07 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLe-0006dm-AM for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:04 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2243803b776so87046045ad.0 for ; Tue, 22 Apr 2025 12:32:01 -0700 (PDT) Received: from stoup.. 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This is intended to prevent files being incorrectly added to common_ss. Remove #ifndef CONFIG_USER_ONLY / #error / #endif blocks. All they do is trigger the poison error. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/poison.h | 5 +++++ include/hw/hw.h | 4 ---- include/system/confidential-guest-support.h | 4 ---- include/system/replay.h | 4 ---- include/system/xen.h | 4 ---- meson.build | 6 ++++-- 6 files changed, 9 insertions(+), 18 deletions(-) diff --git a/include/exec/poison.h b/include/exec/poison.h index 2c151fd1e0..4180a5a489 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -66,4 +66,9 @@ #pragma GCC poison CONFIG_WHPX #pragma GCC poison CONFIG_XEN =20 +#ifndef COMPILING_SYSTEM_VS_USER +#pragma GCC poison CONFIG_USER_ONLY +#pragma GCC poison CONFIG_SOFTMMU +#endif + #endif diff --git a/include/hw/hw.h b/include/hw/hw.h index 045c1c8b09..1b33d12b7f 100644 --- a/include/hw/hw.h +++ b/include/hw/hw.h @@ -1,10 +1,6 @@ #ifndef QEMU_HW_H #define QEMU_HW_H =20 -#ifdef CONFIG_USER_ONLY -#error Cannot include hw/hw.h from user emulation -#endif - G_NORETURN void hw_error(const char *fmt, ...) G_GNUC_PRINTF(1, 2); =20 #endif diff --git a/include/system/confidential-guest-support.h b/include/system/c= onfidential-guest-support.h index b68c4bebbc..ea46b50c56 100644 --- a/include/system/confidential-guest-support.h +++ b/include/system/confidential-guest-support.h @@ -18,10 +18,6 @@ #ifndef QEMU_CONFIDENTIAL_GUEST_SUPPORT_H #define QEMU_CONFIDENTIAL_GUEST_SUPPORT_H =20 -#ifdef CONFIG_USER_ONLY -#error Cannot include system/confidential-guest-support.h from user emulat= ion -#endif - #include "qom/object.h" =20 #define TYPE_CONFIDENTIAL_GUEST_SUPPORT "confidential-guest-support" diff --git a/include/system/replay.h b/include/system/replay.h index 8926d8cf4b..1c87c97fdd 100644 --- a/include/system/replay.h +++ b/include/system/replay.h @@ -11,10 +11,6 @@ #ifndef SYSTEM_REPLAY_H #define SYSTEM_REPLAY_H =20 -#ifdef CONFIG_USER_ONLY -#error Cannot include this header from user emulation -#endif - #include "exec/replay-core.h" #include "qapi/qapi-types-misc.h" #include "qapi/qapi-types-run-state.h" diff --git a/include/system/xen.h b/include/system/xen.h index 5f41915732..c2f283d1c2 100644 --- a/include/system/xen.h +++ b/include/system/xen.h @@ -10,10 +10,6 @@ #ifndef SYSTEM_XEN_H #define SYSTEM_XEN_H =20 -#ifdef CONFIG_USER_ONLY -#error Cannot include system/xen.h from user emulation -#endif - #include "exec/cpu-common.h" =20 #ifdef COMPILING_PER_TARGET diff --git a/meson.build b/meson.build index 7e22afe135..657949326b 100644 --- a/meson.build +++ b/meson.build @@ -4050,7 +4050,8 @@ common_ss.add_all(when: 'CONFIG_USER_ONLY', if_true: = user_ss) libuser_ss =3D libuser_ss.apply({}) libuser =3D static_library('user', libuser_ss.sources() + genh, - c_args: '-DCONFIG_USER_ONLY', + c_args: ['-DCONFIG_USER_ONLY', + '-DCOMPILING_SYSTEM_VS_USER'], dependencies: libuser_ss.dependencies(), build_by_default: false) libuser =3D declare_dependency(objects: libuser.extract_all_objects(recurs= ive: false), @@ -4060,7 +4061,8 @@ common_ss.add(when: 'CONFIG_USER_ONLY', if_true: libu= ser) libsystem_ss =3D libsystem_ss.apply({}) libsystem =3D static_library('system', libsystem_ss.sources() + genh, - c_args: '-DCONFIG_SOFTMMU', + c_args: ['-DCONFIG_SOFTMMU', + '-DCOMPILING_SYSTEM_VS_USER'], dependencies: libsystem_ss.dependencies(), build_by_default: false) libsystem =3D declare_dependency(objects: libsystem.extract_all_objects(re= cursive: false), --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351515; cv=none; d=zohomail.com; s=zohoarc; b=KmpctENakrhTGDKiCAV9zY/GlTFnrLLjT6BrnkJJuRUX0KeOPBRhW/vdP32QIWYnjbCkZOsZ8a2a9HkuwUV65Dw4WauVl1b644IwQFyVYjC4G9zKRcWyDDZ9Q70ItiRqP9LAcTV++z4eHpGKN0HXYif0Ggf0fj+KmxvJBDfZ+kU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351515; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Ov1D5DRp2B1Vosai0+UfYupVFAv3Pz5JSReUzKCYE4s=; b=jTp/VQOuaPVsCWCLxrR4c6Oqbv8IvRBrt2m2p2a4/kxNm9R7Ggx8wsPTvBwc25GWWDtEbwWKsvFaeEdBdbzve1OHUvU1/s8+a8foWVF/jd/ei08HGc4w1zSzSZqWFX7g83d/kosmX4EAVBdj663ovAyI2UqxA1cCcz+fKScLWYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351515487979.806256270415; Tue, 22 Apr 2025 12:51:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JR3-0001EQ-ER; Tue, 22 Apr 2025 15:37:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLk-0000mA-Bg for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:09 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLe-0006e1-W8 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:05 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-22c33ac23edso56325245ad.0 for ; Tue, 22 Apr 2025 12:32:02 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:32:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 062/147] exec/cpu-all: extract tlb flags defines to exec/tlb-flags.h Date: Tue, 22 Apr 2025 12:26:51 -0700 Message-ID: <20250422192819.302784-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351517022019000 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250320223002.2915728-3-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 63 -------------------- include/exec/tlb-flags.h | 89 ++++++++++++++++++++++++++++ accel/tcg/cputlb.c | 1 + accel/tcg/user-exec.c | 1 + semihosting/uaccess.c | 1 + target/arm/ptw.c | 1 + target/arm/tcg/helper-a64.c | 1 + target/arm/tcg/mte_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/i386/tcg/system/excp_helper.c | 1 + target/riscv/op_helper.c | 1 + target/riscv/vector_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/sparc/mmu_helper.c | 1 + 14 files changed, 101 insertions(+), 63 deletions(-) create mode 100644 include/exec/tlb-flags.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4395fd08af..5c4379f0d0 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -35,69 +35,6 @@ CPUArchState *cpu_copy(CPUArchState *env); =20 #include "cpu.h" =20 -#ifdef CONFIG_USER_ONLY - -/* - * Allow some level of source compatibility with softmmu. We do not - * support any of the more exotic features, so only invalid pages may - * be signaled by probe_access_flags(). - */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) -#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) -#define TLB_WATCHPOINT 0 - -#else - -/* - * Flags stored in the low bits of the TLB virtual address. - * These are defined so that fast path ram access is all zeros. - * The flags all must be between TARGET_PAGE_BITS and - * maximum address alignment bit. - * - * Use TARGET_PAGE_BITS_MIN so that these bits are constant - * when TARGET_PAGE_BITS_VARY is in effect. - * - * The count, if not the placement of these bits is known - * to tcg/tcg-op-ldst.c, check_max_alignment(). - */ -/* Zero if TLB entry is valid. */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) -/* Set if TLB entry references a clean RAM page. The iotlb entry will - contain the page physical address. */ -#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) -/* Set if TLB entry is an IO callback. */ -#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) -/* Set if TLB entry writes ignored. */ -#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) -/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ -#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) - -/* - * Use this mask to check interception with an alignment mask - * in a TCG backend. - */ -#define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) - -/* - * Flags stored in CPUTLBEntryFull.slow_flags[x]. - * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. - */ -/* Set if TLB entry requires byte swap. */ -#define TLB_BSWAP (1 << 0) -/* Set if TLB entry contains a watchpoint. */ -#define TLB_WATCHPOINT (1 << 1) -/* Set if TLB entry requires aligned accesses. */ -#define TLB_CHECK_ALIGNED (1 << 2) - -#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGN= ED) - -/* The two sets of flags must not overlap. */ -QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); - -#endif /* !CONFIG_USER_ONLY */ - /* Validate correct placement of CPUArchState. */ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) !=3D sizeof(CPUState)); diff --git a/include/exec/tlb-flags.h b/include/exec/tlb-flags.h new file mode 100644 index 0000000000..a0e51a4b37 --- /dev/null +++ b/include/exec/tlb-flags.h @@ -0,0 +1,89 @@ +/* + * TLB flags definition + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#ifndef TLB_FLAGS_H +#define TLB_FLAGS_H + +#include "exec/cpu-defs.h" + +#ifdef CONFIG_USER_ONLY + +/* + * Allow some level of source compatibility with softmmu. We do not + * support any of the more exotic features, so only invalid pages may + * be signaled by probe_access_flags(). + */ +#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) +#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) +#define TLB_WATCHPOINT 0 + +#else + +/* + * Flags stored in the low bits of the TLB virtual address. + * These are defined so that fast path ram access is all zeros. + * The flags all must be between TARGET_PAGE_BITS and + * maximum address alignment bit. + * + * Use TARGET_PAGE_BITS_MIN so that these bits are constant + * when TARGET_PAGE_BITS_VARY is in effect. + * + * The count, if not the placement of these bits is known + * to tcg/tcg-op-ldst.c, check_max_alignment(). + */ +/* Zero if TLB entry is valid. */ +#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) +/* + * Set if TLB entry references a clean RAM page. The iotlb entry will + * contain the page physical address. + */ +#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) +/* Set if TLB entry is an IO callback. */ +#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) +/* Set if TLB entry writes ignored. */ +#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) +/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) + +/* + * Use this mask to check interception with an alignment mask + * in a TCG backend. + */ +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ + | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) + +/* + * Flags stored in CPUTLBEntryFull.slow_flags[x]. + * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. + */ +/* Set if TLB entry requires byte swap. */ +#define TLB_BSWAP (1 << 0) +/* Set if TLB entry contains a watchpoint. */ +#define TLB_WATCHPOINT (1 << 1) +/* Set if TLB entry requires aligned accesses. */ +#define TLB_CHECK_ALIGNED (1 << 2) + +#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGN= ED) + +/* The two sets of flags must not overlap. */ +QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); + +#endif /* !CONFIG_USER_ONLY */ + +#endif /* TLB_FLAGS_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 613f919fff..b2db49e305 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -34,6 +34,7 @@ #include "qemu/error-report.h" #include "exec/log.h" #include "exec/helper-proto-common.h" +#include "exec/tlb-flags.h" #include "qemu/atomic.h" #include "qemu/atomic128.h" #include "tb-internal.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index ebc7c3ecf5..667c5e0354 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -21,6 +21,7 @@ #include "disas/disas.h" #include "exec/vaddr.h" #include "exec/exec-all.h" +#include "exec/tlb-flags.h" #include "tcg/tcg.h" #include "qemu/bitops.h" #include "qemu/rcu.h" diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index 2e33596428..ccb0c96070 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -11,6 +11,7 @@ #include "exec/cpu-all.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" +#include "exec/tlb-flags.h" #include "semihosting/uaccess.h" =20 void *uaccess_lock_user(CPUArchState *env, target_ulong addr, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4330900348..8d4e9e07a9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -12,6 +12,7 @@ #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/tlb-flags.h" #include "cpu.h" #include "internals.h" #include "cpu-features.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 9244848efe..fa79d19425 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -31,6 +31,7 @@ #include "exec/cpu-common.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/tlb-flags.h" #include "qemu/int128.h" #include "qemu/atomic128.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 80164a8050..888c670754 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -31,6 +31,7 @@ #endif #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" #include "qapi/error.h" #include "qemu/guest-random.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index d786b4b111..e3bed77b48 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" +#include "exec/tlb-flags.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index 6876329de2..b0b74df72f 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -22,6 +22,7 @@ #include "exec/cpu_ldst.h" #include "exec/cputlb.h" #include "exec/page-protection.h" +#include "exec/tlb-flags.h" #include "tcg/helper-tcg.h" =20 typedef struct TranslateParams { diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 72dc48e58d..f3d26b6b95 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -25,6 +25,7 @@ #include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" +#include "exec/tlb-flags.h" #include "trace.h" =20 /* Exceptions processing helpers */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 67b3bafebb..83978be060 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" +#include "exec/tlb-flags.h" #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" #include "internals.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 8187b917ba..0ff2e10d81 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -29,6 +29,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" +#include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" #include "qemu/int128.h" #include "qemu/atomic128.h" diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 78cb24a8e2..249b1f6c4c 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" +#include "exec/tlb-flags.h" #include "qemu/qemu-print.h" #include "trace.h" =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350322; x=1745955122; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xgU73YOfMEflbLqLNoDMX+RVctfg0fSpdUj7bFm7Lqc=; b=gYrU+NJjTwRm+rPXDBwaEjSQbuEpz5jAhRjaEfZMjgHa9e9x7D6XGTACI3r1UFTAIU ti0cm6Zi1nVR/COE0egnSlHtDiiIKmBumiOHBkN1Ba7IvrfnSz9/uhyzJQImb1viuir7 cN8jnN+8vV1XOpZUP/pPyQuvyvM9R/H1ZJAeFE1+2BXJt0KcCCokxnNElsbYSzKUs9IR m8dlnFFGx/yH+8dMV6uC7oij6Ve8D+m+G8XBvugzU8sS0iXKVO4Bk0Wsa9fuDNEX2GoN EEfaNfe2+ZQjdoDcso+LsM7wgVS/KrR4vYWI7V3SkUkAvPeKZ8I3kmZteTpOBBAn9Mjc 9hWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350322; x=1745955122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xgU73YOfMEflbLqLNoDMX+RVctfg0fSpdUj7bFm7Lqc=; b=mhXmfL3gxBIfj1bzLUZiu5zRKr9McLKecTQCXdyJ20EW+XRKbs/wrvPqMQfwaTB9Zh SzvisuxZ4Z/4x6pXfPpygZYlE2KOBRhpdG+Sf5X7uhQom2gL/jrloiHAUL5mHSvZNhwq uSoRtaj/U1QouSDJDPLtqmqjdpYOl0mvqCyQEn8pmIlK+ypsJBkQFdRXIbuGXwm5+u1G 2UYMoeZcXhuz0g3md17us7dq4SY+xwOydevLZKNvC/JkVjMfC3KkrM/dL4Su6LF0WMQi xJPJ2/kz7meq+tWwHcDKwkzVzSzRCD/BSzr4NmIk+46Vj+8vmtAXzsZW1BqBhLt/AcQf ve6A== X-Gm-Message-State: AOJu0YytsCLJw3yHEiu5ubfPIfYyZYir9NJcHe6qqgg/eEivsz78P134 S817djPPncLqEu+ncyN6sPmz4Th2hQGdOhHaSggHIkaiPy67wWUnBnSl71Lnlu7MYsBDi7sPPD6 B X-Gm-Gg: ASbGnct5+41RW812gEyWVlvKQtOVJQBP1EaoTKQIHMhYTzv3/4U+4JWahaJi4MVpiUG Otn4apEPhhPtuwvHYFQnbg/7ZNIpuI8Jyc04dIKoIL/08hiDLhYZsZLOsIXYLhxtLb26XpU/ihc n2MHTrcvMb4x+bvSvtvZgBGuDVfKYRB/1b4Xw5dvJQceJ837ARlFUWLROpsTVdN0TotX1sC9afC 7RvLUDTbUvIhU7U/DYwqAzwxQ0NgKJetomylSge5Cu4hEPHqEkVAi6VLjRbVmEMFX0kTdqdECa0 2Dv/mMxQYlHBfFNQa6qmWkmmX1VDFz/ePWYxb46MNWwGu+HZ46FA8XVoKr1zboEKfKIXiXeIXpA = X-Google-Smtp-Source: AGHT+IGu1VapgOEfYgynacBU0pOJ6+VaXmA1lGetjRfxNFbim34rQHlmJ2Q9oOyLzhUkRgE4+kxV0w== X-Received: by 2002:a17:903:2983:b0:224:1781:a947 with SMTP id d9443c01a7336-22c53580c35mr263978735ad.21.1745350322148; Tue, 22 Apr 2025 12:32:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 063/147] accel/tcg: Fix argument types of tlb_reset_dirty Date: Tue, 22 Apr 2025 12:26:52 -0700 Message-ID: <20250422192819.302784-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351101326019000 Content-Type: text/plain; charset="utf-8" The arguments to tlb_reset_dirty are host pointers. The conversion from ram_addr_t was done in the sole caller, tlb_reset_dirty_range_all. Fixes: e554861766d ("exec: prepare for splitting") Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 2 +- accel/tcg/cputlb.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 8125f6809c..03ed7e2165 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -31,7 +31,7 @@ void tlb_unprotect_code(ram_addr_t ram_addr); #endif =20 #ifndef CONFIG_USER_ONLY -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); +void tlb_reset_dirty(CPUState *cpu, uintptr_t start, uintptr_t length); void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); #endif =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b2db49e305..10090067f7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -912,7 +912,7 @@ static inline void copy_tlb_helper_locked(CPUTLBEntry *= d, const CPUTLBEntry *s) * We must take tlb_c.lock to avoid racing with another vCPU update. The o= nly * thing actually updated is the target TLB entry ->addr_write flags. */ -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) +void tlb_reset_dirty(CPUState *cpu, uintptr_t start, uintptr_t length) { int mmu_idx; =20 @@ -923,12 +923,12 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1= , ram_addr_t length) =20 for (i =3D 0; i < n; i++) { tlb_reset_dirty_range_locked(&cpu->neg.tlb.f[mmu_idx].table[i], - start1, length); + start, length); } =20 for (i =3D 0; i < CPU_VTLB_SIZE; i++) { tlb_reset_dirty_range_locked(&cpu->neg.tlb.d[mmu_idx].vtable[i= ], - start1, length); + start, length); } } qemu_spin_unlock(&cpu->neg.tlb.c.lock); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351390; cv=none; d=zohomail.com; s=zohoarc; b=Lit10N2aD3AHyfLVhG7tnYNSJjV+6dnXoSYt4sST7ztFLB/Tl1QoAvvOdTXEJGR3+gU897HBgbDS17NYo1xj1mBlSrghHTJnqVLu3Dm6/jCN/LgWo80YgdLa7bzybCZbdWtwDJLepzAJz53Sc3nmf1Plr85zxIUI21+JTxDYvTI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351390; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7VCm6mlHRL+Ejn4ewBmyxmL8FXzxR8z3K0tghqh0r4s=; b=IziifMVuDNIDfGQCeEa3S/8RiKAs68YjdgXr4DIkrJrM9OlD6EHfKYB5P/CcbEa8eYsUT982phaHPMitsSu5yqqGy626M8OPIl6OZNh+NoRLSFgNXlq7T6mmlxj4TEFKdTcc+2TCSon7pvuERHxY4ROOkSihC1CvMNu/rv9uowI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351390261563.6324678352444; Tue, 22 Apr 2025 12:49:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPe-0006t2-Iv; Tue, 22 Apr 2025 15:36:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLk-0000mB-B1 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:09 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLg-0006eK-8l for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:06 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-224019ad9edso79385985ad.1 for ; Tue, 22 Apr 2025 12:32:03 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350323; x=1745955123; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7VCm6mlHRL+Ejn4ewBmyxmL8FXzxR8z3K0tghqh0r4s=; b=NGPlTD7hrYGOuG4Allx3iBhaoCJDTKDzTE3Tojee9v3iqigxw34G1IdbBhNnPnmszz mT3QwkGHNiK4v3QNR5lGunHkr5u5bQaq+nBA8uXOY2IZFWeNg5pxXkquLsiVKObR5Ict 2SolhP1kfzsEvpryNNTF4caPqrU4Mb0LxJ95TmvXQxFUxgdJ5olqmfOtMyD7l/brsNXB 0qOyikPaAoL2VMQX+gpDG47d7tk1yEFWJVNcHuusx2yxUIAh38s5BNr6LzQ2vfNq8JY3 WEJ1dQvZTbsIq3g7QsC9UUUhHgVb3Pn8iqe58vEwhI/mRK8Q6iKugAHzPzY8CF8tmKmg sWCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350323; x=1745955123; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7VCm6mlHRL+Ejn4ewBmyxmL8FXzxR8z3K0tghqh0r4s=; b=ksoIibSlhfWM9a1QvlTL/qwAcFDcQHR3QgEEcUfCnXkFn3Nro7xlEMmjVnuXFmEEHF pxn3ckZ/V+62ikTW97R5UJL5j3tTmeUhRSs451v1RjZg7nJ6JFH1lh3noNFQwHpomnqW cbAKNI/r5k0DcIMjhD+O6D0eZkUKdhMDGK4RW5+RehrzhwZ45NXYEOzIn0VzqrvBzSLz PsQHg5AmHPvSBttuNMrJnqMMI51JHtCWE7qwyilXnYZ5yeIUtPJuBAnMuATHCjSekPJh /4MwbAUwIu3Lu5qqCk6TVwaQ861xgFY+3P6V4RjrD0Y8lCir9fuWbk8fQ4CyyBkZ9Oot hBsQ== X-Gm-Message-State: AOJu0YwEMftQckHcKjDl0j+By5NjO+jI6ycnseF8333nHYEC8jekPtH8 LGoKMypWftF9rpER0kMEe59Ll+Lp1OlwDu+GWa7sV2ZPJ4EpvcXG6IGTwipbEVa/zyAj4OGAmfK 0 X-Gm-Gg: ASbGncuJOADx/STXgC/eFrHNkAZ+K842QORbFPLmd/LJhOpZT2Z2XTv7jKDmRbCKjsa 9B7eqUt09VL5+cBsFo5udWpgkadkLjHuPkIu1FlrvvZqv9fWkZ1MtQ41MbUuJV/EQ2lwDqd8rNL s2K1hqjeK518bfaoHtsApGjjjiCzygfNDruaiMo3xK7xsEjYJ3bsry+o2JXKOpuIcNYxiO6XlEu c6HwPbFFGQchlQ1Sh87wtD/j2cNB6rBJNwcZF2jsx7YWLYjAGH8dTKptbz8Za/6hU6uHiKfkkyO OW6JyLI6zL6xTORyjZtpO3XPt+8RyTeqZKTIttbVmwadZhwDw/bCec8AEzNf0hOrEXTE/A2i6lU = X-Google-Smtp-Source: AGHT+IGItKZjDl+HJUif+XBUeE3HHp6dQITkPixJIERk2XYFs7tYuznvoKa0CE9SaioY7sI755yrrQ== X-Received: by 2002:a17:903:166f:b0:223:397f:46be with SMTP id d9443c01a7336-22c536423f9mr234234805ad.47.1745350322832; Tue, 22 Apr 2025 12:32:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 064/147] accel/tcg: Pass CPUTLBEntryFull to tlb_reset_dirty_range_locked Date: Tue, 22 Apr 2025 12:26:53 -0700 Message-ID: <20250422192819.302784-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351390474019000 Content-Type: text/plain; charset="utf-8" While we're renaming things, don't modify addr; save it for reuse in the qatomic_set. Compute the host address into a new local variable. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 10090067f7..5df98d93d0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -882,18 +882,16 @@ void tlb_unprotect_code(ram_addr_t ram_addr) * * Called with tlb_c.lock held. */ -static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, +static void tlb_reset_dirty_range_locked(CPUTLBEntryFull *full, CPUTLBEntr= y *ent, uintptr_t start, uintptr_t length) { - uintptr_t addr =3D tlb_entry->addr_write; + const uintptr_t addr =3D ent->addr_write; =20 if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_DISCARD_WRITE | TLB_NOTDIRTY)) =3D=3D 0) { - addr &=3D TARGET_PAGE_MASK; - addr +=3D tlb_entry->addend; - if ((addr - start) < length) { - qatomic_set(&tlb_entry->addr_write, - tlb_entry->addr_write | TLB_NOTDIRTY); + uintptr_t host =3D (addr & TARGET_PAGE_MASK) + ent->addend; + if ((host - start) < length) { + qatomic_set(&ent->addr_write, addr | TLB_NOTDIRTY); } } } @@ -918,16 +916,18 @@ void tlb_reset_dirty(CPUState *cpu, uintptr_t start, = uintptr_t length) =20 qemu_spin_lock(&cpu->neg.tlb.c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + CPUTLBDesc *desc =3D &cpu->neg.tlb.d[mmu_idx]; + CPUTLBDescFast *fast =3D &cpu->neg.tlb.f[mmu_idx]; + unsigned int n =3D tlb_n_entries(fast); unsigned int i; - unsigned int n =3D tlb_n_entries(&cpu->neg.tlb.f[mmu_idx]); =20 for (i =3D 0; i < n; i++) { - tlb_reset_dirty_range_locked(&cpu->neg.tlb.f[mmu_idx].table[i], + tlb_reset_dirty_range_locked(&desc->fulltlb[i], &fast->table[i= ], start, length); } =20 for (i =3D 0; i < CPU_VTLB_SIZE; i++) { - tlb_reset_dirty_range_locked(&cpu->neg.tlb.d[mmu_idx].vtable[i= ], + tlb_reset_dirty_range_locked(&desc->vfulltlb[i], &desc->vtable= [i], start, length); } } --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350700; cv=none; d=zohomail.com; s=zohoarc; b=nbzEtZMrl+1eRPxA9TaSjb/lqw+yKeEGdagchvhqKq5FQ738fczcq0CzANLOCrxpmt6KdM1M7EJyHkXRVxQxDVSK7ccwzrDyaS/szIkYJDEzOCRfYVHXSS2sbA8IccRDY9DJh7X3pbhdlYxTZ03114Q98pF96xDrF+d7vwyAl10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350700; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IIU1fG3v2ti6ddjpGI+Ep7ZP7ka1a1iDtVAhhJuSr6o=; b=SnlhxbLBnvbOY19dfQ9bNfBDKENhcE5oK+oLQYF+SUF5mPscGX0BZjXX3ZJKfGiUBVVfB/0E0RuttM6VB8E3SQAThOgJNlL9sDy90iCUZUI2zjDLeL5tsU6BHgLH4GQUbfYC+M39+bt0oILnJpW0HXmtaRchlTayu4HrPGX/MW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350700170584.725618004573; Tue, 22 Apr 2025 12:38:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JOS-0003sp-5k; Tue, 22 Apr 2025 15:34:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLm-0000q8-68 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:11 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLh-0006eX-7U for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:09 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2243803b776so87046905ad.0 for ; Tue, 22 Apr 2025 12:32:04 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350323; x=1745955123; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IIU1fG3v2ti6ddjpGI+Ep7ZP7ka1a1iDtVAhhJuSr6o=; b=Pgct6mzGy7n4/vNCtUPaLEVVsX6V3iTGvIzoYfiXmX+6/oTiNA+skT4ev0KMOW6YdO EppwNM8uxz9fdQ/dz24Y2ydDIPf9CBrICjkgcv+tmYHk9jXbXMvTpJtGt3hwtOa/bMfc 5onf8PRWT6SZTfo/5pFmPC5cWXDygTgzl8f9eUcdwPuLwThIt/ehFYMRZawibGN40yMF rQuliQojlxvVIkJyFij7fnlZweFi+bQXMGU4IkCeED3+J+DViZnrT5et5Sq7qhGYQp8E IyzdSRKrkUAcmvEqP/4+4SZdRR/hTUludh8p7W89tRvhAegqCQRqreGlIOS6sscgVLhr /HGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350323; x=1745955123; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IIU1fG3v2ti6ddjpGI+Ep7ZP7ka1a1iDtVAhhJuSr6o=; b=m5xqeda00oa+fKRylUoSUmLX0NNv3W1kYzW95vtZscvxz+Kqm29FdNwGGdqGh7apKE vqO55xe+6HmPni5yprVBYYwnoMaBrRFS/+LkN/voMRFXZ7mIfU9eZPvVrCkPPJ3Tphce sJSi3st1EapHBtQRNdRijPmuKEID7OnFOuqpZDm+EQYGus4Bkt0jvnrAB0QRAVIA2HUm Vqamubvm3yJGHAdJS7YtkksNyc5seBldqI8CIyinzxujoKEstdd69BwQlyY3NE63au7H y5hDig2VyASPx4QUZ77zRHwJTjAjVUtoH/BOUpLqT1jNUO5MQHmgXdkIiIXIPoTTbLRD ARWA== X-Gm-Message-State: AOJu0YwUA73xk9Yf3sH6Vqkq8Nm3EcCiUe+S1w72q9X+6EyxIIhwaBrY mnbSVcyhX6PQcCWxiMRHjfw4rJLpMdgMxHfOdFNJwupYxZiRLpMYuC21eZ3cVVKzkDWXDyuWKrv x X-Gm-Gg: ASbGnctyHP6VLfElPivrqkFDYAm90jpeIK7EtgaOdOVWiZhBkoVnW+TKiO2wQxqjsDW VJGepzndqflvv0ZvZlOvfZxkEEq+kGAsDk8zrzSxm+ZTlapGgwPmPgPLU20csXpVIG8O9iBjZo1 oSuFXzsht1C2ARWXPB5cl7n8a0FTdxzW/2EXJ7swqUklWdyStK9qcRIBusnDS8gXL/S6OsOAFrb M/74+5drk75TQDf7Q8Q9nTre/FjKiqcWjBY1GQl40IXg8brBcKMJgT324lj6ZNxBSh5PcpAwFTK 6gSuxAMcBfWFwBk3R9Y5t820E4BA3pD3UTDechl69Zy4LBHttAX+FwvLoYPr+CarOtx0wXDBGws = X-Google-Smtp-Source: AGHT+IEXIjwxRcCLel6K3nCgtqqDsI4237rjSZpO9q0mzhlkMkRcFQYLY4l+WROpKm3Xtf9dO5MZ2A== X-Received: by 2002:a17:902:d4cd:b0:224:910:23f0 with SMTP id d9443c01a7336-22c53642323mr214658235ad.49.1745350323431; Tue, 22 Apr 2025 12:32:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 065/147] accel/tcg: Rebuild full flags in tlb_reset_dirty_range_locked Date: Tue, 22 Apr 2025 12:26:54 -0700 Message-ID: <20250422192819.302784-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350700683019000 Content-Type: text/plain; charset="utf-8" Undo the split between inline and slow flags before masking. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5df98d93d0..28c47d4872 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -886,9 +886,10 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntryFu= ll *full, CPUTLBEntry *ent uintptr_t start, uintptr_t length) { const uintptr_t addr =3D ent->addr_write; + int flags =3D addr | full->slow_flags[MMU_DATA_STORE]; =20 - if ((addr & (TLB_INVALID_MASK | TLB_MMIO | - TLB_DISCARD_WRITE | TLB_NOTDIRTY)) =3D=3D 0) { + flags &=3D TLB_INVALID_MASK | TLB_MMIO | TLB_DISCARD_WRITE | TLB_NOTDI= RTY; + if (flags =3D=3D 0) { uintptr_t host =3D (addr & TARGET_PAGE_MASK) + ent->addend; if ((host - start) < length) { qatomic_set(&ent->addr_write, addr | TLB_NOTDIRTY); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352187; cv=none; d=zohomail.com; s=zohoarc; b=BYN1e7wLG7S5XL8SK4U1U4o+oQvTX5zuwRcJf3HEsm5pRTkXsd75JM6YxUHVo/W3kIIofF7PcNrMnnBtQSALSWysnu4QHqr4Kz8QrsjltT2kGT6ibpyn7MaKMFGGQGFJg5hVzbw4YnuMGOGsoAlfIb88Sykr7FUFIsXSkB8/dlA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352187; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Qcu//0jyv2Qr1qgAsqv3VCUMABiA/lbrLzTg9MZVJM8=; b=Zjeq7zwV7jV9IlYGpFf62/VP5RIsek7C6Z6/YK+Pg5b/HSLIaKYzMLet3+t1KyGhUD0g1MSrQnM4v1Kp0F89aTvUnxQzJTXQ6xKZJzBhBTn/aHHWIs7w5wcvB2xafNKwdf/vXIRBX1bVG2RyYYJlAMoA3ij04P+WuibxYF2Yiec= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174535218709537.257872195395294; Tue, 22 Apr 2025 13:03:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPa-0006fs-DD; Tue, 22 Apr 2025 15:36:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLm-0000px-37 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:11 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLh-0006eb-9l for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:09 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-225477548e1so56981595ad.0 for ; Tue, 22 Apr 2025 12:32:04 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350324; x=1745955124; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Qcu//0jyv2Qr1qgAsqv3VCUMABiA/lbrLzTg9MZVJM8=; b=J9jIEFZLGUE05wOPugN/O+RcLybABgTewAFHojtpbze+lBOaGBcAni7jGV/Im5Q9Ea 0f68hPyOm+Bfy4rFL2ljUgG6mfjMAtoJJuvrmx/1jqBB+ms2faWZ5sTFb+MYW/piPw/a 6TNcj5jfltU0kQvF/AUM95Dll4VHaw7e4MyyQK9X33ctB2PXF27gV5ty5Idrq2yjTF5q uXUhtnW/k0PGJ2kras8R1QqDAWwrvqIqJ/cAK9M/KPCdxta7KVbQuPcAd2TDhWJYlL2h nJdYgrLZSVJl7saWjZ42sXZdlC0S5esVzB3Zp5xcesIQk7o7yawAdGYtirMGBUBR4q8r 1wFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350324; x=1745955124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qcu//0jyv2Qr1qgAsqv3VCUMABiA/lbrLzTg9MZVJM8=; b=XEPtux623av8x5V32N0DeXfX8X0yrefoxrgQUy86Q7zfkmJyIMN5Dk6loUk+NUOa+O /ZunV8hfA1Pn41uKJ7mdFDLdlq12CFkPbaQJG775a2IB8Dn3yjB+NjwUzD9BFNuQ9zje JyHqRGUHVKWJS8zCbz2WGX8WVI/AbCPEPOtTIbTx+1atmO4XHYiDu1ZcmEIroUCXnOFm ZGPEsB37dvVhApD9iejPPZ31ci17eeHxZG/6q1SKwhitzmHN9DK0mkCz+dNfdJnNI4sk hK7mFHhCueBOUfGpLNMF+1Ekkd8zZOughqrjeMInn33WYWCiKd+MtEiLe/IXDZKOr4tT 27BQ== X-Gm-Message-State: AOJu0Yw4VTh7EVj1nwf8E0aFc5nXHD82oMNNSek5aOxteutQEHT0MhdA hQzvHpfqf0cz0wWfTZDDFq7tusAGtkw5dX4O8WANS/cF7+k6ixlWuWqahaHkCLVv5Gv0dgQBqt7 z X-Gm-Gg: ASbGncuj6l9oVdpIthwR5yvVsNEsQt2ESqEbmh03rLr1Xgcr2BDmk401ZzUj1sonQyM 2OWsetLBCsA4rr+uVUtbOEgSnmhigb+M1u29cdrGRJ3on0RSu0a8bOhmbTCwdX+P+vmTcJCbocN ZuqaNURiSLSihXGHx4yZMaaBCjWz2lXhFrCpyAgoZFmNKchp9fsGm7ypvWp9Zzs+YFT+ScULppJ gyGdJKeq9A4Ri+3IS9oWpl2qDVt/hVUqPbrFT7MybC2Id/dNaF9c8knDskHcvfEIQXMEgescmd8 Ez3RR1LssRIF+iNJjJ6nbS/xYwjD7P9XgzhNN8ji6p5wzyT4x1EW0LXpKKItYT/5ljrHtIAFSyY = X-Google-Smtp-Source: AGHT+IHlH0OsaiT6N+otkf5NVhKPfosNhoHWqhsvLNMUobIIfYLUrWUi7DO2HvmZ+aoNCObZI7r66Q== X-Received: by 2002:a17:902:d58e:b0:223:2aab:462c with SMTP id d9443c01a7336-22c53580c26mr251616435ad.15.1745350323972; Tue, 22 Apr 2025 12:32:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 066/147] include/exec: Move TLB_MMIO, TLB_DISCARD_WRITE to slow flags Date: Tue, 22 Apr 2025 12:26:55 -0700 Message-ID: <20250422192819.302784-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352189106019100 Content-Type: text/plain; charset="utf-8" Recover two bits from the inline flags. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/exec/tlb-flags.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/include/exec/tlb-flags.h b/include/exec/tlb-flags.h index a0e51a4b37..54a6bae768 100644 --- a/include/exec/tlb-flags.h +++ b/include/exec/tlb-flags.h @@ -53,20 +53,15 @@ * contain the page physical address. */ #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) -/* Set if TLB entry is an IO callback. */ -#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) -/* Set if TLB entry writes ignored. */ -#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ -#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 3)) =20 /* * Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_FORCE_SLOW) =20 /* * Flags stored in CPUTLBEntryFull.slow_flags[x]. @@ -78,8 +73,14 @@ #define TLB_WATCHPOINT (1 << 1) /* Set if TLB entry requires aligned accesses. */ #define TLB_CHECK_ALIGNED (1 << 2) +/* Set if TLB entry writes ignored. */ +#define TLB_DISCARD_WRITE (1 << 3) +/* Set if TLB entry is an IO callback. */ +#define TLB_MMIO (1 << 4) =20 -#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGN= ED) +#define TLB_SLOW_FLAGS_MASK \ + (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED | \ + TLB_DISCARD_WRITE | TLB_MMIO) =20 /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350579894262.0763266454669; Tue, 22 Apr 2025 12:36:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JP7-0005MI-HA; Tue, 22 Apr 2025 15:35:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLo-0000vk-KQ for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:13 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLj-0006el-QN for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:12 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2260c91576aso48793155ad.3 for ; Tue, 22 Apr 2025 12:32:05 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350325; x=1745955125; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tlaPgaqu+RlzrqR3gxsyz4cZtfxx2Xq8XD/b6ALmxlQ=; b=So8RjdNCEuhDHGV0jbz9Xe2lVdTC7ANH7d20hpebGNL5lH8j9HL004xeFK/H+weJQB nAIe7vsBvJTvLLmffz17KEMfNo8FYTe7RhJxkpMUsA90QgcSlwtvIOD7VdjEVNOybYlR QdsXyiUX1K+55fb2kRDET+j10AxnjJhVZPlAKgi+VBEtQ0+ecbvnHWdYztGEzC8wq/67 ES3NLJEX3OHm9VHWzo+SNzaKxwIGZvWMpaZnVYw0V1pq+eFRljCL3sO3jgylhKIipGfm ckfMgV2zNL1nz7NiTHQ0hqY1ThkGQdWAOLGAbRXiQZm23ssFmb08pbKICEcza6a2X/xs azbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350325; x=1745955125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tlaPgaqu+RlzrqR3gxsyz4cZtfxx2Xq8XD/b6ALmxlQ=; b=QF9hsso117gerLquWdR5H9oQaQ73iinE0wc2tnFmTtxmcPSw89VmqQzWVH0EU0D02m 3qYoPiQKdfMUMPIsDCWHBCwediMlokoN1JjSIQM16k91rrE4lIf1RmVxgKSwNz7GJMLI 7ubj7d0a+gZ13AmYGyKCxccxBIo+FbzWOQcmeGQ0khzl03EZ6vFxrRstWt5vA53YMGXZ 5nKO7h5BIBUQbj0c1qag18o+LftDcPDZ/FEQJUgtuNkon9awAm7KHwExbY5JJeNtZnXM 9WYGP9EkbuauAGg49CrHJasAnswZuMTuaVuGPrYG0NCvE+Cg5mDowqYeMvSZ3b7gZU11 SzgQ== X-Gm-Message-State: AOJu0YwjYhfNjzKR+2EWF6AwvEnfctGt88e42UO+RGw2iqmqYNXW7QvM 0HgHUMhDhE4sphXpCnyovgfL6qdQUDVCa/weOmJkSYg5AIGgU7P3o9K/x3VtkdZyAnrVle9PqsL j X-Gm-Gg: ASbGncupy2opdbGXniWOuVuNlpodBnhcEB05+QoZzQOBhlwNMhPrj+/yYmLuwKWZpql 9wpf708PyxCOxYlaoAl/Ce53sCHcKMBIuKnL/DS0YKL5ljv5SZP8c6FwxTfqqwyzTbRQCnKN/9D GuuWXroqw+yzbTGdMZOdc6LTaXvLa4q1gpjYp0vQJ8WCgsCT9T6c4bareUh386bM3mvOJijpzpw iE/8ewGbeJJzcS/pvxuzBiIpw6sJrVsXaGIu1VMo7ik42GeD1iGkFthbKuLejECm9voyRBuzgHc 2fAQGwFLRMBjamfsqEp7pSg0XIx4WPu6+aBVEabPX34TbrSK23/x6Xosh4LfsEzIBrP+OGZ3HXE = X-Google-Smtp-Source: AGHT+IE4EXj8VIYNumDC8LF3F/EdCzynvTTR5LbiwZlRM+e8P/bKy1FV2/YFZfAGh5NXfwufIR1Orw== X-Received: by 2002:a17:903:98c:b0:224:1780:c1ec with SMTP id d9443c01a7336-22c5360dc12mr294007565ad.35.1745350324702; Tue, 22 Apr 2025 12:32:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 067/147] include/exec: Move tb_{, set_}page_addr[01] to translation-block.h Date: Tue, 22 Apr 2025 12:26:56 -0700 Message-ID: <20250422192819.302784-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1745350581268019100 Content-Type: text/plain; charset="utf-8" Move the accessor functions for TranslationBlock into the header related to the structure. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 49 ------------------------------- include/exec/translation-block.h | 50 ++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 49 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 19b0eda44a..fcad3446fe 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -123,55 +123,6 @@ int probe_access_full_mmu(CPUArchState *env, vaddr add= r, int size, #endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 -static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb) -{ -#ifdef CONFIG_USER_ONLY - return tb->itree.start; -#else - return tb->page_addr[0]; -#endif -} - -static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb) -{ -#ifdef CONFIG_USER_ONLY - tb_page_addr_t next =3D tb->itree.last & TARGET_PAGE_MASK; - return next =3D=3D (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next; -#else - return tb->page_addr[1]; -#endif -} - -static inline void tb_set_page_addr0(TranslationBlock *tb, - tb_page_addr_t addr) -{ -#ifdef CONFIG_USER_ONLY - tb->itree.start =3D addr; - /* - * To begin, we record an interval of one byte. When the translation - * loop encounters a second page, the interval will be extended to - * include the first byte of the second page, which is sufficient to - * allow tb_page_addr1() above to work properly. The final corrected - * interval will be set by tb_page_add() from tb->size before the - * node is added to the interval tree. - */ - tb->itree.last =3D addr; -#else - tb->page_addr[0] =3D addr; -#endif -} - -static inline void tb_set_page_addr1(TranslationBlock *tb, - tb_page_addr_t addr) -{ -#ifdef CONFIG_USER_ONLY - /* Extend the interval to the first byte of the second page. See abov= e. */ - tb->itree.last =3D addr; -#else - tb->page_addr[1] =3D addr; -#endif -} - /* TranslationBlock invalidate API */ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 3c69bc71a9..8b8e730561 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -13,6 +13,7 @@ #include "exec/vaddr.h" #ifdef CONFIG_USER_ONLY #include "qemu/interval-tree.h" +#include "exec/target_page.h" #endif =20 /* @@ -157,4 +158,53 @@ static inline uint32_t tb_cflags(const TranslationBloc= k *tb) bool tcg_cflags_has(CPUState *cpu, uint32_t flags); void tcg_cflags_set(CPUState *cpu, uint32_t flags); =20 +static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb) +{ +#ifdef CONFIG_USER_ONLY + return tb->itree.start; +#else + return tb->page_addr[0]; +#endif +} + +static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb) +{ +#ifdef CONFIG_USER_ONLY + tb_page_addr_t next =3D tb->itree.last & TARGET_PAGE_MASK; + return next =3D=3D (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next; +#else + return tb->page_addr[1]; +#endif +} + +static inline void tb_set_page_addr0(TranslationBlock *tb, + tb_page_addr_t addr) +{ +#ifdef CONFIG_USER_ONLY + tb->itree.start =3D addr; + /* + * To begin, we record an interval of one byte. When the translation + * loop encounters a second page, the interval will be extended to + * include the first byte of the second page, which is sufficient to + * allow tb_page_addr1() above to work properly. The final corrected + * interval will be set by tb_page_add() from tb->size before the + * node is added to the interval tree. + */ + tb->itree.last =3D addr; +#else + tb->page_addr[0] =3D addr; +#endif +} + +static inline void tb_set_page_addr1(TranslationBlock *tb, + tb_page_addr_t addr) +{ +#ifdef CONFIG_USER_ONLY + /* Extend the interval to the first byte of the second page. See abov= e. */ + tb->itree.last =3D addr; +#else + tb->page_addr[1] =3D addr; +#endif +} + #endif /* EXEC_TRANSLATION_BLOCK_H */ --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350904; cv=none; d=zohomail.com; s=zohoarc; b=lSGf3iW0JhDNq3KhQ+KgBxeldsEbysgmkcW582XGx4VKOqDR1lR1eWPp7uGFzb1aZOl1oSD5cRJG2F52imx+mFFCnC8/zV2MD78DcMkVZHNwW4Ux8hIeC6F0ecAVr5qqvW2DUeFx8s/jKVcbKC44URS3LVUaWEssWGO854/xTG0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350904; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Mym6I21VutfSQahS1cIV8VVwJqeJPoQQbXrANWwquXs=; b=mmdbDL4zLUtWqgP3BZKJyXbBu7TOmdeGmlGNZvEgAjN95datEb45ar3qM6iHtxCwQwW6mV5jZ5XBZ1z66z5vI2egfpq65CN36MnWma9OwD5kRUB1kciprYNgKRYrMTsVSS2Hp91ab+k3+5Cqo9PRBoebmGl5OOcRB8BqVCms8Z8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350904737400.4879533298731; Tue, 22 Apr 2025 12:41:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JOf-0004HP-4L; Tue, 22 Apr 2025 15:35:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLp-00010q-D8 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:13 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLj-0006ex-Uv for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:12 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-2295d78b45cso88962875ad.0 for ; Tue, 22 Apr 2025 12:32:06 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350325; x=1745955125; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mym6I21VutfSQahS1cIV8VVwJqeJPoQQbXrANWwquXs=; b=Iw/hVEvOmqyJJQshqXecZe2kQHvTtnM0mKg1j27hkzQuM8uy0tBUpz/dI9mjXeDpPb 23qZuaSK2WWHz2XGf5ebJiwyEScNzT3RpcZpt/5p3xpZ2kBnHMX7HCpdJcOxTvQhmN6x uUT8KaawqcnfTSPweJpvuZA8NE4XVSJyUV9jRkt+DfcXNc8GWw1fhA/5Y9JRYifG41YD XVA8g/UwEbPvbVDRH17wD9hmo4q8iQTmaeyiQiP5rW+ViXpiIos2AEHbhn+xDjqXW4d4 tczgvqnvhsaGNjXGsfsfVZmbZtcC2YBV2Xshm5zLpxgwU9c0byBrbxpY2wsJkxHdsn2l 8kNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350325; x=1745955125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mym6I21VutfSQahS1cIV8VVwJqeJPoQQbXrANWwquXs=; b=wrPK0C8nSMO4Tm1WDnN9Yly6G4s+jhXdDz2FzS63L66j8DoeHO8GLhIbiZ2jitePB4 3H8AS4D+tddxjVizYNzF+Ad4LdoT3MiHTTnz2wnzHGpHDNOeY9s+2Wxbr3KtnPDeQ4SC DX9m+OtgEAlXC27Hm80PA0g7L1aGyUPTyEHIufsa0DgVDPe/wi0yWz5JpYU4/3LP+mz5 8bOHB86atjgKMvKgQwqNCPD5NIFgp3v5CH0pRKxa6HdmKWm1PQVbIpX3+D5X/XXAlLOE usOqnjls6atafDJBOStAQU1pZivZfndugPx2TjwDFNshOVujGuU6hVmctaLb3TtJK1hL hL0g== X-Gm-Message-State: AOJu0Yz54BX9xz5m5o7cKtTzSgm+GWnr4af7mc4X236nlfFKejjORw8I /KrwYSQ5JqyENXYhfXFSI1A7Nbvhln6ZtMK/7831E+7ywFDhnM8V3jQkg9cLMl7rG7YhaT1Cmam x X-Gm-Gg: ASbGncvnAg3VT3N1RgxwlSNFwfSBrkT3PooFzfeeiWL3OR+l7ruOMuiBvIOiWT4aD6r OjMSdsqMoFouX4BPpsTk1dHmxlA6+hVVjXE9j33rDEQiJ1ntg/rhUSOtdog3Ev/qFVFHOmcUvro k+c7TVlP7xOxDAy9x3Ql1cvq8dB+3pEEz0tjk6sjZh1jgMzPE75Jtu1kejF//NR3vKZlORkKQ2S R8PsH2zvnQggftcnX0NbQz4SXyNjgJ/yCeZQYO5EbQxiHJr1UeQ07im+3IQjq7UtV9FXeGH9i9q zZLpTLPncTBuJP1gIMvqwFnXS6fJ9Omi4+NqlfWRUBOLSpq+Nl9T3RgwIJSrSBRj2xW43b7RCoI = X-Google-Smtp-Source: AGHT+IG478TXFH3/5dMzncHLz7g1If1T6fQN2MZsl69pFDsvUVA74ZGLRQW9yt3TVNCqCma2nYFvPQ== X-Received: by 2002:a17:902:e2ca:b0:227:e74a:a063 with SMTP id d9443c01a7336-22c53605110mr193726305ad.37.1745350325296; Tue, 22 Apr 2025 12:32:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 068/147] accel/tcg: Move get_page_addr_code* declarations Date: Tue, 22 Apr 2025 12:26:57 -0700 Message-ID: <20250422192819.302784-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350906726019000 Content-Type: text/plain; charset="utf-8" Move the declarations from exec/exec-all.h to the private accel/tcg/internal-common.h. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/internal-common.h | 34 ++++++++++++++++++++++++++++++++++ include/exec/exec-all.h | 34 ---------------------------------- accel/tcg/translator.c | 1 + 3 files changed, 35 insertions(+), 34 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 9b6ab3a8cc..2f00560d10 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -74,4 +74,38 @@ uint32_t curr_cflags(CPUState *cpu); =20 void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); =20 +/** + * get_page_addr_code_hostp() + * @env: CPUArchState + * @addr: guest virtual address of guest code + * + * See get_page_addr_code() (full-system version) for documentation on the + * return value. + * + * Sets *@hostp (when @hostp is non-NULL) as follows. + * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp + * to the host address where @addr's content is kept. + * + * Note: this function can trigger an exception. + */ +tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, + void **hostp); + +/** + * get_page_addr_code() + * @env: CPUArchState + * @addr: guest virtual address of guest code + * + * If we cannot translate and execute from the entire RAM page, or if + * the region is not backed by RAM, returns -1. Otherwise, returns the + * ram_addr_t corresponding to the guest code at @addr. + * + * Note: this function can trigger an exception. + */ +static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, + vaddr addr) +{ + return get_page_addr_code_hostp(env, addr, NULL); +} + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index fcad3446fe..f52a680f42 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -143,40 +143,6 @@ struct MemoryRegionSection *iotlb_to_section(CPUState = *cpu, hwaddr index, MemTxAttrs attr= s); #endif =20 -/** - * get_page_addr_code_hostp() - * @env: CPUArchState - * @addr: guest virtual address of guest code - * - * See get_page_addr_code() (full-system version) for documentation on the - * return value. - * - * Sets *@hostp (when @hostp is non-NULL) as follows. - * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp - * to the host address where @addr's content is kept. - * - * Note: this function can trigger an exception. - */ -tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, - void **hostp); - -/** - * get_page_addr_code() - * @env: CPUArchState - * @addr: guest virtual address of guest code - * - * If we cannot translate and execute from the entire RAM page, or if - * the region is not backed by RAM, returns -1. Otherwise, returns the - * ram_addr_t corresponding to the guest code at @addr. - * - * Note: this function can trigger an exception. - */ -static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, - vaddr addr) -{ - return get_page_addr_code_hostp(env, addr, NULL); -} - #if !defined(CONFIG_USER_ONLY) =20 MemoryRegionSection * diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 2ab081b95f..5f0aa9d56a 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -17,6 +17,7 @@ #include "exec/translator.h" #include "exec/plugin-gen.h" #include "tcg/tcg-op-common.h" +#include "internal-common.h" #include "internal-target.h" #include "disas/disas.h" #include "tb-internal.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351279; cv=none; d=zohomail.com; s=zohoarc; b=UqZnpdWUpgic6rULi/vHz9kLkOReoLdBssNIQjfevnB+kuHjGDeLUHWawllxjJRBwWkQOuATLqSM8RiEsfCrj+dca2ui8tTg48wAAf80ELnnU61mBPSAVUL9fl/e4cn4jJndb1bR/4BrpQE4q+OLcAkvjzJqgVEdOTqn8YNfJXo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351279; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FNsYq0CLsO6lFu+oOVVyImJDoiCdKLFU/pHo4cHTdc0=; b=SW3h04iQVMJZsZhnGfbTaFh/0HePLrC1F5bmvgJ6+1BUwKm/n94z000QxgummhzMu7vFv8ytarSc10aPXg5bZQ8fm71bOwfSUlJJ7V6QXNiZ+lYeQbFeCdjF3zS5YU+dCyRM1ZfqkHJLuYOmw5aeS9lf0hgtVQL/4IjtI6M78GM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351279981184.43905412479637; Tue, 22 Apr 2025 12:47:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPP-0006Kd-SJ; Tue, 22 Apr 2025 15:35:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLn-0000sS-W1 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:12 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLj-0006f3-Ts for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:10 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-225477548e1so56981905ad.0 for ; Tue, 22 Apr 2025 12:32:06 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350326; x=1745955126; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FNsYq0CLsO6lFu+oOVVyImJDoiCdKLFU/pHo4cHTdc0=; b=ILG8taac1OfMepSdtGLz5MfYvotv6r/uaz8W625e6R3Sm4LfUljQx1wB8KScQZWYP3 ign3wF+b0ZIKTl8Mew9s+0QtAErR/CRJPypElolxbSYVFAf5gt0X6+di9TiJX51OBHv1 I4VApXUpHz/JgvaDRpJgkk1EMmqbX0JCqUKzH+xA5J4AAbGY2fU9e4Rp1tT/DB8b1WeP 6V/uZAp0uBBkf95pFInPuCSj27RLiXwsHINzX56sE7YWp3Yl7ly5D2luSFLvCLKyHFDG egnV5CYP00mRpgXHXTqpScVcndLrurkvowKMZFonEj9QbUfhtebg/7sL89x/86pnO/XR cxGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350326; x=1745955126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FNsYq0CLsO6lFu+oOVVyImJDoiCdKLFU/pHo4cHTdc0=; b=g4VYgFMj70uXGGpAT1M5PYSnRcnwzIv9KGUdTApzZKiFNPusyLUKBf80xW+TAKjJIJ WMNJPLeg3hI21vAUD1Lgd53vU7j4jxfivd+E5OOZgETke0tjxpScKuvMMnn+dvZqTxjM W7tJfe9hlVogQ062misWN4Q4CC0ua12f5BJpYdUwrKhsXdVBJ9lcUWYXSuuvCKZeq4QX 6KQ20a+fqrOQiIwdFAYNkrbaycA2C7D+vPEuI/tXw/C0H6KRLJzYVuSeLmH6oipMBdhv sJC63+DWMjteBEftm2MWM6ztC0ueRbDCzTxOO5sXKJs/Gs3VbkVPjBYBgelMIvM+vn9U ypIQ== X-Gm-Message-State: AOJu0YxxE1fSrdmAqqTNYwGaM2W6xcVrCGZr02BJGcL/bS/QzNiu+6yK +96Cp2/MSj7qJiLe9lXXnVWkLyvUIg+CsN+3ZH+aUi8HMStZdPf3qvhE1E/I6hN+Mghk/2f4PuN G X-Gm-Gg: ASbGnctRFJOeMHPvtA7iCufvIlLuit3Ij1dP8nQUNDxOSXDQC0WEd4kHyKb4yRTeCQ3 6XZ43ZK2jVsgOTPV6UiPu3wNfLZ9tLlb9Y9RTRftR/BQ1tSPVQGchutTHbOiNrO1BVtSol2OS7x 9ItPPWDS1+q2kN/3RMlai2nfWljsh8ouQBfLA2+nNbCH2/Oh8fN1+3yuFh1vWqtXZMD0hd/rVmZ O4tiAl7By7iW1l143GUJJFcMhimKQzP1f5EmqO3ADl+IPFFxG0b53/RfAz20JtBH0xQiybIjlc2 NYjKf6SAxVdxiyTro7pQZ+ovuQdZS1euoBABSMtXr0IBSARvXMXtElVi6DFEXiWisGJp9eoTbd0 = X-Google-Smtp-Source: AGHT+IH8tyNJAPlcoThH61nxsi9AvyxPX8UEI+4Dxg66XlIu1kNlAAMzTLQdh21BOn/uRh2xR9Y9+w== X-Received: by 2002:a17:902:ef0a:b0:22c:35c5:e30a with SMTP id d9443c01a7336-22c53580d0dmr229724425ad.16.1745350325938; Tue, 22 Apr 2025 12:32:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 069/147] accel/tcg: Remove page_protect Date: Tue, 22 Apr 2025 12:26:58 -0700 Message-ID: <20250422192819.302784-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351282063019000 Content-Type: text/plain; charset="utf-8" Merge the user-only page_protect function with the user-only implementation of tb_lock_page0. This avoids pulling page-protection.h into tb-internal.h. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tb-internal.h | 11 +++-------- include/user/page-protection.h | 1 - accel/tcg/user-exec.c | 2 +- 3 files changed, 4 insertions(+), 10 deletions(-) diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index 68aa8d17f4..f7c2073e29 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -51,28 +51,23 @@ =20 #endif /* CONFIG_SOFTMMU */ =20 +void tb_lock_page0(tb_page_addr_t); + #ifdef CONFIG_USER_ONLY -#include "user/page-protection.h" /* * For user-only, page_protect sets the page read-only. * Since most execution is already on read-only pages, and we'd need to * account for other TBs on the same page, defer undoing any page protecti= on * until we receive the write fault. */ -static inline void tb_lock_page0(tb_page_addr_t p0) -{ - page_protect(p0); -} - static inline void tb_lock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { - page_protect(p1); + tb_lock_page0(p1); } =20 static inline void tb_unlock_page1(tb_page_addr_t p0, tb_page_addr_t p1) {= } static inline void tb_unlock_pages(TranslationBlock *tb) { } #else -void tb_lock_page0(tb_page_addr_t); void tb_lock_page1(tb_page_addr_t, tb_page_addr_t); void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t); void tb_unlock_pages(TranslationBlock *); diff --git a/include/user/page-protection.h b/include/user/page-protection.h index 51daa18648..d5c8748d49 100644 --- a/include/user/page-protection.h +++ b/include/user/page-protection.h @@ -16,7 +16,6 @@ #include "exec/target_long.h" #include "exec/translation-block.h" =20 -void page_protect(tb_page_addr_t page_addr); int page_unprotect(tb_page_addr_t address, uintptr_t pc); =20 int page_get_flags(target_ulong address); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 667c5e0354..72a9809c2d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -657,7 +657,7 @@ target_ulong page_find_range_empty(target_ulong min, ta= rget_ulong max, } } =20 -void page_protect(tb_page_addr_t address) +void tb_lock_page0(tb_page_addr_t address) { PageFlagsNode *p; target_ulong start, last; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351163; cv=none; d=zohomail.com; s=zohoarc; b=C5915Dvs2/vO7HRJH1IdasG+6IzNnHGjaUQ4VCT5XyKQTOYzTpr3/IqjoeVDxvkusVW2MNjmAHzxWzn9Zl5uxbl/2i1YzfTpvpbSjsuRn14JMePX048IEx/0J8jv8uE8eTYvUH10rJVljqZ66tXjxKTm9pAkZhf1wyMFqXD7eVQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351163; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZSAf1+HedmWB7UB003Jb743ifjZ0UvEme3TNs+0ZvNA=; b=nSPaevuQ2nd2h/d67/7dAWimFkSH+WnF+lDCpGpI/TK/jFsgsPGBG8l2fCMKDolu1dEs8BMoiIXzHLZ+eJzLLm9DIGvFCzu2kDS5YYq3WY/koK41ost9Yu1pBGLugyB0+l1v1LJl2Wk9LRnXPMhc8NbFA7ziwBAbRUH1c5IxTx0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351163312409.9087967780366; Tue, 22 Apr 2025 12:46:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JO0-0003Dl-Q9; Tue, 22 Apr 2025 15:34:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLo-0000sR-0i for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:12 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLj-0006f6-Uv for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:10 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-225df540edcso2861915ad.0 for ; Tue, 22 Apr 2025 12:32:07 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350326; x=1745955126; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZSAf1+HedmWB7UB003Jb743ifjZ0UvEme3TNs+0ZvNA=; b=SOy5jfIydsv5bnXRjxMaCR/GwPFG9lH46AniRisHWJOgbSHGwx4GgZgnPv32Oa0KZo kb0Af9aUmE+n2p904Jhj78U/imsNHY+j7+2Wz3SRrjx5ZRbYAqU+VYV1FS2MxDF7QIKT tqSyzndpd8xFDJw1Hc865h/YyUgUY37tVL6qmslcqzoWgU3uLkIjmglC9YqXmBgWPCsK tUNKB7V8Vsn6O8jLyosbAeKZuXtrSXgnWsUJoKvhD5uFZytQwlQchvXsZ5h9IpbMpEwF 7sCdppfEKHOgZuWrqBVqh2zCaxfRysldRuONdLohDiYfTsYkhu9aJcxPeE5K01QsgKOq gD0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350326; x=1745955126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZSAf1+HedmWB7UB003Jb743ifjZ0UvEme3TNs+0ZvNA=; b=PlB/TaGIxjpQNqPpSxxFqVxwVxcQ+QLxy00PaGPBCahhTsQ4XGVMXtZwrZMDpeM29A BkKdZ5J93gWxlknfiAvGoa7/iJFKlwuYrIVjuHdwTvvTCA2ZnyuT4PGwEMT8RswxNYoE hjOhVkEde0PzJo5D7t32Qnzr3O0FMJDipibza1l2eA7uwbsM9cudx2vC5Y5XpJE7RtaD iw55lR56QzV+iStsEeWfDtubYW65auLkC80EwgZCnQWetj2Q1bxA/ZJqmfRwS2tZj/t6 M6FHI1lwwDsch/pBv+VU0WbV2OPVUelaEds2JAXUAoJ3sBL1KSOxVLa0SOZgOEqGm4Tk yCCw== X-Gm-Message-State: AOJu0YwzFKjkNiO1wiE1Ygo3YcQ6OP5W5Ipk1yu3nF/kRmCg5G/nssX1 MSGgctG3wH0HMCGV8VqCFVQM9vBAZ3iv1JsZJzppIKw3wA5m3Qum0HrjJfH3kjhTm5m/uLMZNqb w X-Gm-Gg: ASbGnct/op5KcH3kjS/qwv1UGeTC9U8S+aWIsZOdbU7FoLsRGhEa1tEM4kWqWp3rdQh s2n9vYO7oubTVXY3rVoiRq7zBdH3Rk2m2pEr13Qn5h6iLzQDqmZNKxZ/O+Hae9A+9OP3taM3Xuj WbaHN4whaPyBrmS7N4dDq+rNjbMMQ650KbSEk2rpObvxeJ3NvSgr3j+Dv3OEaItTNrBZw0hWmSv 8TTz9t3ioR9SoB/dz/or0bMgrhqe0ZP8rt7JEvtidUZYr0uV5GwCTx2St8EeaHpLzCo2+FeSwW+ 7QIB0/2djmU+voL2t2fCaKbgCM+VHY5gA5gpG+JKcLKi91A0rdPbmvFK+uqR/fzobadiuCw/X4s = X-Google-Smtp-Source: AGHT+IH2Z2pF4fOoUkVEctNzQnT8DhdXcokGsj4N5z6LOy0X3ZhTNUmQ++7Ke0NI/AySXFHznrRb+g== X-Received: by 2002:a17:903:904:b0:216:271d:e06c with SMTP id d9443c01a7336-22da3183acdmr2420475ad.4.1745350326552; Tue, 22 Apr 2025 12:32:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 070/147] accel/tcg: Remove cpu-all.h, exec-all.h from tb-internal.h Date: Tue, 22 Apr 2025 12:26:59 -0700 Message-ID: <20250422192819.302784-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351164742019100 Content-Type: text/plain; charset="utf-8" Not used by tb-internal.h, but add an include for target_page.h in tb-maint.c. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tb-internal.h | 2 -- accel/tcg/tb-maint.c | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index f7c2073e29..f9a06bcbab 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -9,8 +9,6 @@ #ifndef ACCEL_TCG_TB_INTERNAL_TARGET_H #define ACCEL_TCG_TB_INTERNAL_TARGET_H =20 -#include "exec/cpu-all.h" -#include "exec/exec-all.h" #include "exec/translation-block.h" =20 /* diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index d5899ad047..df3438e190 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -26,6 +26,7 @@ #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "exec/tb-flush.h" +#include "exec/target_page.h" #include "tb-internal.h" #include "system/tcg.h" #include "tcg/tcg.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351509; cv=none; d=zohomail.com; s=zohoarc; b=Enas3k2VQJr5lS2AOZGNOLsm4nuq4w+CE9Wc06cr5U7drSW8aAGvLzdjNCGmKm1yL8Wi6uvtidXxLADAlRAGZtp/62BydaszbYN30IUK+XdEnDo1op57lq0KfMNCpzeGbNAKtGnpAxjMdmNp8syLuxnP402XyScssA45/JkM2Gc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351509; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BPrUJL2Wwt5H6m+qbEougiZhbCqsapatk+AvGECCLZ0=; b=kHYjItntNC5mwG7xIlS5pbxnmnais9XGi1TVpJoKfPcFxBIJ4zMxWVz78dt7+BcuzAlkai6g1MRP90eB0D09ojJV1YQm4ZnlOQ7jZz4sqeSGtYgvE1jj9dkqS3LMTYrCNyBXQflYjHV6BsclbytN+gAifsFEuk59i68wCQWRwPs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351509496534.1354767041805; Tue, 22 Apr 2025 12:51:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPi-0007Ee-Nz; Tue, 22 Apr 2025 15:36:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLp-00010F-6G for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:13 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLk-0006fD-Qk for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:12 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-22928d629faso54246575ad.3 for ; Tue, 22 Apr 2025 12:32:08 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350327; x=1745955127; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BPrUJL2Wwt5H6m+qbEougiZhbCqsapatk+AvGECCLZ0=; b=xFOWXr/pAX60p4nMfpHEy/oKhjM3UbrdWyxzzpg/Qnqav87TU0iZgjp6XJyGqG6LOV aeqRy5mGl9l9xCBYG1fuKuZCIPkAILzgWzrxJdR3Y0ocA3vV9PCc5kwPO2CrI8dLz4Zy 02SCaBk7QYZbNX62Xzu+PXf50aJorN1s2YyW18pZN8aOuZPQhsOYDhe74dRXGzxztNxE X5SFWBsd9HxSchnBobUZ4I9iHvri6uzu3XPEGtXoNv8oDmFh/G8jsIJ/sLeDX/4xiiT2 9MPwTcEIX3+gp5B8JOKTU3r0IMBrEJZDY6/XOvSFZiPzhFydr5wrj92ZkMSq5TdlLIGh NSXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350327; x=1745955127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BPrUJL2Wwt5H6m+qbEougiZhbCqsapatk+AvGECCLZ0=; b=C/yfYBDlqGiWtZVPIXvbIXU72yyiTg2Stjg3wuRiwKeXrMiA27QTHLn3d2cbRaiSW+ 5bQqAPtcfpIGkkn2AGyZX+XzXYXhdv+ANq0mDcN1slA/E1+Sn7sO3IsEgApOSYZA69DK prN4T9wYOXpzXpx6bDUX/YNULfVBcAczeT0Jyxtbn9kHxdRnzMYuWAd/ztn8MPSTRHDU aZskakewvzB+puSLsCMEgADGALH0TUCdncprjxxywvZTPUMYE+4H76Fxt+HwGshb6Mk5 sW0onlp5Z3n5B5hRqoRA+15vxHLqGMS+pXTjf/zoPa+qx/66Edl1iZRqLTqKYiYv25or Ngzg== X-Gm-Message-State: AOJu0Yx6kYsloV4QTerPN0wlmEAGOFpC7+ADry24UCQjQMBygDuDyoIH er6JdaEzk5hMrDPkQbyDkCNdNcn2qVA0LSEGb8WponJuUf/yW5EvtaGEltld3/yPLfJOjbo8rPo l X-Gm-Gg: ASbGnctHgRuQzx96yxpfMo4OxTgY31e2M2qhXsKxJ8WbbEZldT1onuwnLACzoSGvt7+ ZuIALMfDA/9052UgivVzm36+FDUr3TTFdOOMkBaIPzRi4+RH1POTFimFQpGTAV6UJIcW6AI9bl8 RLKwn+FMT0TKd2F6/0YbdwwSL+NkPmjy6V2DQvzi8Uk+hhT7x3C2GlddZNMg0sKmQwaut568UCE MKQgMwZTnV83hn8LNDklQqBYiBy6RNtmqgPpwVZNRHaSJL+OPf9xEb0tPypnhTbgRYUnSZakvL1 GTZ/8LJOxKCYosv7pWeT1bmibmHd4ad8CyExIdwOqtpQ5NjfrmfETHUF5ju6blTrDkdaELrZoe4 = X-Google-Smtp-Source: AGHT+IFt/p5BWHLdwSq+AVfN0dwEW5BAWTMNnu6NWbABk9RIACRT1M2ON8stnOmPrzs9KbYqsOhdaw== X-Received: by 2002:a17:903:287:b0:223:33cb:335f with SMTP id d9443c01a7336-22c5337a07fmr210733565ad.3.1745350327132; Tue, 22 Apr 2025 12:32:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 071/147] target/rx: Fix copy/paste typo (riscv -> rx) Date: Tue, 22 Apr 2025 12:27:00 -0700 Message-ID: <20250422192819.302784-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351512115019000 From: Philippe Mathieu-Daud=C3=A9 Rename riscv_cpu_mmu_index() -> rx_cpu_mmu_index(). Fixes: ef5cc166da1 ("target/rx: Populate CPUClass.mmu_index") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401072052.25892-1-philmd@linaro.org> --- target/rx/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 0ba0d55ab5..a240b3b3ce 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -66,7 +66,7 @@ static bool rx_cpu_has_work(CPUState *cs) (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } =20 -static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc) +static int rx_cpu_mmu_index(CPUState *cs, bool ifunc) { return 0; } @@ -227,7 +227,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) &rcc->parent_phases); =20 cc->class_by_name =3D rx_cpu_class_by_name; - cc->mmu_index =3D riscv_cpu_mmu_index; + cc->mmu_index =3D rx_cpu_mmu_index; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; cc->get_pc =3D rx_cpu_get_pc; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352334; cv=none; d=zohomail.com; s=zohoarc; b=S5weFPfvIEpgAuKgVcV36WDcjIJf93r0heTce1En847mv5qL69kt6mIq/io6bonjOxRITMvlkY2pIzRp4FRQ8jhdbqGdKFOUClda9W8jiwHS9hvwYNBovOWRu/o0ggPT083h17D0uCt169nS8VSBTdJylCJT9nLherMQEdS3Ii4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352334; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KE33KBayr4dnRr7Xrs3VkN2rsoJvmDMI/IpM1PhpEq8=; b=a5ZJlsXV0XVsG0byYxu+Bvmb+qChWb7fpp5RsNqa0p7c0Z/wk3zdav95fjj7qxlFJis6QNQcn/TlxsMA9FOvIwsIXui8c4AlYxNFuWUdrTzKzGsg3dre7ebMz1AcaYhCHfxNxN3WebYgonlinwKHHNfwSVyehItil4WPYPaiqMA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174535233410938.934995206227995; Tue, 22 Apr 2025 13:05:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JO5-0003MC-V2; Tue, 22 Apr 2025 15:34:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLp-00010I-62 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:13 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLl-0006fS-Pf for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:12 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-22409077c06so78042095ad.1 for ; Tue, 22 Apr 2025 12:32:09 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350328; x=1745955128; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KE33KBayr4dnRr7Xrs3VkN2rsoJvmDMI/IpM1PhpEq8=; b=Vv86iRyEEpElgb1j8QcFjS54Uup+H1RGpfGbONKivSrKbcXjQue/RYLQF5yDRQOZCU xVlhMU/Fx2ZO4rbgn1joc1jSok5zA3ohHbHPz+AtYaW33O16Nxt2yoXG6vzSaUom4LFD ur5YJtcVpglqiA3RRT8IgQkhqUEYJu4DdYYzvcSHHGpAwW1p/xBJWoSsXPWEjgA/lrR7 lF7yKCZnYifzAhohe0eFEGHXcEeydIHhcqWs/l1K9RHcqt6IxR410xRF2klqCVeTVEwF zDh+/2HKe7kGlI+9mu1hnkGaCvnAsw2hTqsKj26vtR9rZ5zeZH3AEyYrOG3oJzMF1vJm EauQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350328; x=1745955128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KE33KBayr4dnRr7Xrs3VkN2rsoJvmDMI/IpM1PhpEq8=; b=QtQiiFjdLtR4+yJnU2kqtLufkmcrYxcVsboICsCzbpxRCm/mnMLXAg/W+6M3ceDogr 7bLGu3b+dFldHgJ3EGlzsQVl8pj3fNygVUgmTtpl9smKRF186xoSWBMP++Ijm8IAnL3T 6JzbJx9xb62jl1dFuZu6qdsYZtn8ODNa4Z696JJtYz218fNyRTEEsCrAUvPF71pjUP2I BTyy85Xh88m+J5Aw4E5Fj9hZhOCWzMAwek0emheDLjSmBBD6zxZyfwL2M8m816mSADN7 J6NzA8Ql/IJcPBrkxZAfTd70k0Yv5/vC8OKHkUNxFFI5k4E5V8XehT9AW41mcwkQmGv/ zM4w== X-Gm-Message-State: AOJu0YzsthOijIlY6/llARTp4TMSoRmP1bOgMUxeU4QBcJtz7Sg22OGK qXmrX/FcvFXH/dVOtUfp2G5fKrT642sg/KpsklOLH9crUA78+spgrWvzFHPeY36bX2Uj9xJ4WZb Q X-Gm-Gg: ASbGnctA3bOOxscJY+9Ojlf0By4QmXEdh30G+yzkuVP20zccln4gv5qWxNw7z3xI/pk g8dUtCIOeHTjBVua+DJsWg1ejEHgnBezmd3z29B6jbbvywE8man/LCHQpZpY7c4LlY2/NDPomUn NeO3VagNQit+CZqzJ8STc4xyE9JMZ8DGlRyfDN41lkB2waVi1qIRgXe7bREaVHjEX4NCCEV2Zdd 9sNU237RuwvpL3hBpBpWJ47NfY9AuGt1UHPn5hHEoGtgw6m9JV3O1s5hjsaQsIuIz1Wm/9BfW1k F5LatXbOeWIrBOjFY1ZX0yEAxTaqXJHueBg9gq74UsI9GqMZDf9SBFq1KNVC3/zRmiyzNbL2vO0 = X-Google-Smtp-Source: AGHT+IFeFiI6+ksHq5yFSBGyRmRjKuBP4m9BKYK6WYqm/iC3564b8uc1QgjGGv1bPxnWlX08XQOvIA== X-Received: by 2002:a17:903:40cc:b0:223:5c33:56b4 with SMTP id d9443c01a7336-22c53583807mr215608565ad.20.1745350327964; Tue, 22 Apr 2025 12:32:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 072/147] hw/core/cpu: Update CPUClass::mmu_index docstring Date: Tue, 22 Apr 2025 12:27:01 -0700 Message-ID: <20250422192819.302784-73-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352334411019000 From: Philippe Mathieu-Daud=C3=A9 Since commits 32a8ea12fab..90b7022e698 (target: "Split out TARGET_env_mmu_index"), target's memory_rw_debug() callbacks use the target's TARGET_env_mmu_index(), not the generic CPUClass::mmu_index() callback. Update the documentation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-2-philmd@linaro.org> --- include/hw/core/cpu.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6dcee5d0ba..29f6419050 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -104,8 +104,7 @@ struct SysemuCPUOps; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @mmu_index: Callback for choosing softmmu mmu index; - * may be used internally by memory_rw_debug without TCG. + * @mmu_index: Callback for choosing softmmu mmu index. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350581; cv=none; d=zohomail.com; s=zohoarc; b=Gsh6kl430oyfh+lSoW4AtUqH9LjMjyt/5xHt67t9iSHmjPZXB5Gc1s3iv2ZxcPw15huHjSSz96Zch2jH4LJSjSvEvpBSME0uzJH0fMSPR8/Q7hdCzN7Hpydq8g3HiMqCyGGyNnyunUZihYVuTSdjZVUVVnMA0IDF34nMR/wgsh8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350581; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eY3tVR1Ho6nb9UcI2ivFSVueJvDpQEAHEetuLect7PU=; b=KSj1NeMhmFn65+xK6/M+XZ1kLAmJ45y8ttBqR361yRtN4AFSINM+y/zJZapY92UH17jhxhVhonkeuiZdOSSTD9jyhwE3FBBXE35ekeXCaqdnRmTcSLkJ+KyICElCsx5At4fC37QQ9D2AbHCtMI+ztux6r1r5pMV1JV+86S8kAsM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350581201912.3478681103452; Tue, 22 Apr 2025 12:36:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JOS-0003v9-P3; Tue, 22 Apr 2025 15:34:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLp-00010i-8r for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:13 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLm-0006fZ-3f for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:12 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-227914acd20so1911595ad.1 for ; Tue, 22 Apr 2025 12:32:09 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350328; x=1745955128; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eY3tVR1Ho6nb9UcI2ivFSVueJvDpQEAHEetuLect7PU=; b=CaOs1zQrLP3GO7sYjr9yaBEghwWrb/Bj14b9xeMF/2vWBcpP85AZtbMF5AZybMkhj4 edSgyARnkLMaG7hyJe3W2vYk4H0tc2PYSvewPc4o0IjSWnRxJZIdMWEc4mctJFlrP93g /NZFC5b2OCSzdviRojvcHLA2i3Z3negpNO8JTx3nESX8ve8iFi+zTmQMr2ATZZYUgiuZ 3oi0GoZkEhE6pyUYTU+sNicGopWByIoXfr0CJIxqiOYoBCjFg20uive67Nh93K77pZaA k0nyh+q27Ss7hxyYIDYkF+AudEkBfUJYz7ZL/BGiwi9IP5moqHsrGPaqSUSo49EAClj7 P3Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350328; x=1745955128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eY3tVR1Ho6nb9UcI2ivFSVueJvDpQEAHEetuLect7PU=; b=w5b3vriDcfJ2OM1p/dOc2O5Mv8eK1t7jTS9nDlYfR22c+9wGqFO282aE47TJmQSdCK vFW4vL88EeAOuwmQ03moC7wYZjHVEGC1pmO1qPYSvVt/z388ci36WnbVGFhuxgvorbVL v4B+ukLiHHgmRpCcTTpsu4lYkJcb+MGt/t2/KlIIz0r5WdZGHQAhyXujWpFdWRN8NZq9 BottDw+UCARrm4nIEALZpUWHDE/+P5LgihOfR9OSC4GJ6U1O2T5vDMyLCu4opmsA8xtG gXUtIoXYKK1WITG81jA0pOHTNChFIg7Jug9uqVZ10dMDgzY6TrVRUuk99Z3qmkV/19ju Elgg== X-Gm-Message-State: AOJu0YwN9fmPG3i4EB49ELbRp/b0+CYVcZ679K+wR0AZJGavN4V2YH3l WxMF0BRpWI2mP1wfE0aehXJQfmfBwcJ66nOdRWRmtFigb0XaaB/V0E2rJRIUXkqLJjirPVLhzes t X-Gm-Gg: ASbGnctxY13//Eym23aCZyjL0V6Vrbh8hjMYTlqVrAmHlP5LZDisFXSEy+Z/lVVJ9yS H4HnRxmdkl1LJqY/tvIjLGmt3F4uJeUrncEhMSrA4GD92zVuR87Cad87+UuqygDeNfewkD+FGT+ J73ZETH4l4iiFlR09yeAj69i/lYumstY+jyDdWVoQcVFuMf8PXh6R0w9LMSDZc9HYSHr/kIgpgt dy9mNlyoACJ2mSzdmpfNK9JL4MBFdzOqn4GkBF2H3QG2B2mOvEW06hD1ODisPM9S+w0DNIasEJm MGta0i8al0HqiMtnYOuHYm4CD2bkPOUBl42PwzDHFuhoMO+YqtCOYGXlS0+QhqXAkgkBmBckvsY = X-Google-Smtp-Source: AGHT+IH1XuUKH/7K74RZSmdZPTIXr5pf8eKtb+uwN4z92vtHO05QFOG7gvQy0q/tgjGsfrqyJB1HZg== X-Received: by 2002:a17:902:fc4b:b0:21f:7078:4074 with SMTP id d9443c01a7336-22da31974c3mr2742595ad.7.1745350328569; Tue, 22 Apr 2025 12:32:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 073/147] accel/tcg: Introduce TCGCPUOps::mmu_index() callback Date: Tue, 22 Apr 2025 12:27:02 -0700 Message-ID: <20250422192819.302784-74-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350582274019000 From: Philippe Mathieu-Daud=C3=A9 We'll move CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-3-philmd@linaro.org> --- include/accel/tcg/cpu-mmu-index.h | 5 ++++- include/accel/tcg/cpu-ops.h | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/accel/tcg/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-= index.h index 8d1cb53bfa..f1ca385d3c 100644 --- a/include/accel/tcg/cpu-mmu-index.h +++ b/include/accel/tcg/cpu-mmu-index.h @@ -10,6 +10,7 @@ #define ACCEL_TCG_CPU_MMU_INDEX_H =20 #include "hw/core/cpu.h" +#include "accel/tcg/cpu-ops.h" #include "tcg/debug-assert.h" #ifdef COMPILING_PER_TARGET # ifdef CONFIG_USER_ONLY @@ -33,7 +34,9 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) # endif #endif =20 - int ret =3D cs->cc->mmu_index(cs, ifetch); + const TCGCPUOps *tcg_ops =3D cs->cc->tcg_ops; + int ret =3D tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch) + : cs->cc->mmu_index(cs, ifetch); tcg_debug_assert(ret >=3D 0 && ret < NB_MMU_MODES); return ret; } diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index f60e5303f2..106a0688da 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -67,6 +67,9 @@ struct TCGCPUOps { /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); =20 + /** @mmu_index: Callback for choosing softmmu mmu index */ + int (*mmu_index)(CPUState *cpu, bool ifetch); + #ifdef CONFIG_USER_ONLY /** * @fake_user_interrupt: Callback for 'fake exception' handling. --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350834; cv=none; d=zohomail.com; s=zohoarc; b=NwekaHtA529GQW+5xHAxcv6TWmB9tzTPLvwVR5fvHAcuT2ROVEqjeDoxjXNttx+P1sPISkkfTPP06sKh6Td042vhlCXvfBLOKl2ss9N8SEJ3dCeVGc6exWDEUFlACInvkHVf13/jfusPZvqZ/24Hes0sAct0Sh8g0IHAcBG7UNI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350834; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oVGDH0zXbPh1XWGLwpF7fHPSsEZ5O5FckAiSLdeKleA=; b=joauYy9SvviF/XisOSQe248FFmRcT+WK14A4mROVrNIb7cREORuz3aUJE6gGR5m6iwgPmOmtBs5gUWkyt80xEkGvq6svVeHnXw2D9XRRf4qgoZU4Gn5LfOrBfPENI17QNnWS2dv8hccjvJtRZG92ETQEVYHVfwT5SH0Pud/2dpE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350834809684.9415250896079; Tue, 22 Apr 2025 12:40:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPY-0006Yt-Fg; Tue, 22 Apr 2025 15:36:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLq-000141-Ji for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:16 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLm-0006fe-GE for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:14 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2240b4de12bso83068005ad.2 for ; Tue, 22 Apr 2025 12:32:10 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:32:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 074/147] target/alpha: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:03 -0700 Message-ID: <20250422192819.302784-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350836337019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-4-philmd@linaro.org> --- target/alpha/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 584c2aa76b..56c96b1c4d 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -238,6 +238,7 @@ static const TCGCPUOps alpha_tcg_ops =3D { .translate_code =3D alpha_translate_code, .synchronize_from_tb =3D alpha_cpu_synchronize_from_tb, .restore_state_to_opc =3D alpha_restore_state_to_opc, + .mmu_index =3D alpha_cpu_mmu_index, =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D alpha_cpu_record_sigsegv, @@ -262,7 +263,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) &acc->parent_realize); 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-5-philmd@linaro.org> --- target/arm/internals.h | 1 + target/arm/cpu.c | 13 +++++++------ target/arm/tcg/cpu-v7m.c | 1 + 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 28585c0755..8756c24c08 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -373,6 +373,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, const Tr= anslationBlock *tb); =20 /* Our implementation of TCGCPUOps::cpu_exec_halt */ bool arm_cpu_exec_halt(CPUState *cs); +int arm_cpu_mmu_index(CPUState *cs, bool ifetch); #endif /* CONFIG_TCG */ =20 typedef enum ARMFPRounding { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01786ac787..21e8cf1400 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -121,6 +121,12 @@ void arm_restore_state_to_opc(CPUState *cs, env->exception.syndrome =3D data[2] << ARM_INSN_START_WORD2_SHIFT; } } + +int arm_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return arm_env_mmu_index(cpu_env(cs)); +} + #endif /* CONFIG_TCG */ =20 #ifndef CONFIG_USER_ONLY @@ -144,11 +150,6 @@ static bool arm_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int arm_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - return arm_env_mmu_index(cpu_env(cs)); -} - void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) { @@ -2674,6 +2675,7 @@ static const TCGCPUOps arm_tcg_ops =3D { .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, .restore_state_to_opc =3D arm_restore_state_to_opc, + .mmu_index =3D arm_cpu_mmu_index, =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D arm_cpu_record_sigsegv, @@ -2708,7 +2710,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) &acc->parent_phases); =20 cc->class_by_name =3D arm_cpu_class_by_name; - cc->mmu_index =3D arm_cpu_mmu_index; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; cc->get_pc =3D arm_cpu_get_pc; diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index c4dd309272..1a913faa50 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -237,6 +237,7 @@ static const TCGCPUOps arm_v7m_tcg_ops =3D { .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .debug_excp_handler =3D arm_debug_excp_handler, .restore_state_to_opc =3D arm_restore_state_to_opc, + .mmu_index =3D arm_cpu_mmu_index, =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D arm_cpu_record_sigsegv, --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351107; cv=none; d=zohomail.com; s=zohoarc; b=Q02e6oCFhZB4piisR/RNoIwkVXtia2GtlJpKUpNefEND0CJg3h7ou58OfJdGlZ+wX7hdWV4Ep1TMCOxehLgRCTlfXI/2CiFbiy9c69WhjOkDkAwtj+rE+yoNQoKmQer30P8BRnIzlzRipbS+ZP6mbfP5QIEb/2QFSi1kC9Il4uU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351107; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WONVWesSZ8uE3+nlVXH925QeCM8w4OWegE2KeFmY578=; b=XIPlYFB9jjWwCnA5y2hir8um++WuKoe3s3MztpiSbuzcoak5coRU1jXSu4/gWOjCbuW1akCY9WHUe40838f1hTnDyeSxw2XdRjuK5JBMT6OEOtZIU1Q86nNCpwo0IapTSIaHU26jdAAi2BZbFPQpELlKlHOeySLuxbf/yFvURhU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351107748815.4495620831367; Tue, 22 Apr 2025 12:45:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JO0-0003D0-74; Tue, 22 Apr 2025 15:34:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JLq-000143-Jf for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:16 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JLo-0006g3-1n for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:32:14 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-227d6b530d8so58377845ad.3 for ; Tue, 22 Apr 2025 12:32:11 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:32:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 076/147] target/avr: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:05 -0700 Message-ID: <20250422192819.302784-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351110630019100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-6-philmd@linaro.org> --- target/avr/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 1121822470..feb73e722b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -228,6 +228,7 @@ static const TCGCPUOps avr_tcg_ops =3D { .translate_code =3D avr_cpu_translate_code, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .restore_state_to_opc =3D avr_restore_state_to_opc, + .mmu_index =3D avr_cpu_mmu_index, .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, .cpu_exec_halt =3D avr_cpu_has_work, .tlb_fill =3D avr_cpu_tlb_fill, @@ -250,7 +251,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) =20 cc->class_by_name =3D avr_cpu_class_by_name; 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Tue, 22 Apr 2025 12:32:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 077/147] target/hppa: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:06 -0700 Message-ID: <20250422192819.302784-78-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350667334019100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-7-philmd@linaro.org> --- target/hppa/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2a85495d02..09a6aaa3dd 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -256,6 +256,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { .translate_code =3D hppa_translate_code, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, .restore_state_to_opc =3D hppa_restore_state_to_opc, + .mmu_index =3D hppa_cpu_mmu_index, =20 #ifndef CONFIG_USER_ONLY .tlb_fill_align =3D hppa_cpu_tlb_fill_align, @@ -281,7 +282,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) &acc->parent_phases); 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Tue, 22 Apr 2025 12:32:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 078/147] target/i386: Remove unused cpu_(ldub, stb)_kernel macros Date: Tue, 22 Apr 2025 12:27:07 -0700 Message-ID: <20250422192819.302784-79-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352741910019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-8-philmd@linaro.org> --- target/i386/tcg/seg_helper.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h index ebf1035277..6b8606cd6d 100644 --- a/target/i386/tcg/seg_helper.h +++ b/target/i386/tcg/seg_helper.h @@ -35,8 +35,6 @@ * TODO: Convert callers to compute cpu_mmu_index_kernel once * and use *_mmuidx_ra directly. */ -#define cpu_ldub_kernel_ra(e, p, r) \ - cpu_ldub_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_lduw_kernel_ra(e, p, r) \ cpu_lduw_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_ldl_kernel_ra(e, p, r) \ @@ -44,8 +42,6 @@ #define cpu_ldq_kernel_ra(e, p, r) \ cpu_ldq_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) =20 -#define cpu_stb_kernel_ra(e, p, v, r) \ - cpu_stb_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stw_kernel_ra(e, p, v, r) \ cpu_stw_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stl_kernel_ra(e, p, v, r) \ @@ -53,12 +49,10 @@ #define cpu_stq_kernel_ra(e, p, v, r) \ cpu_stq_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) =20 -#define cpu_ldub_kernel(e, p) cpu_ldub_kernel_ra(e, p, 0) #define cpu_lduw_kernel(e, p) cpu_lduw_kernel_ra(e, p, 0) #define cpu_ldl_kernel(e, p) cpu_ldl_kernel_ra(e, p, 0) #define cpu_ldq_kernel(e, p) cpu_ldq_kernel_ra(e, p, 0) =20 -#define cpu_stb_kernel(e, p, v) cpu_stb_kernel_ra(e, p, v, 0) #define cpu_stw_kernel(e, p, v) cpu_stw_kernel_ra(e, p, v, 0) #define cpu_stl_kernel(e, p, v) cpu_stl_kernel_ra(e, p, v, 0) #define cpu_stq_kernel(e, p, v) cpu_stq_kernel_ra(e, p, v, 0) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50bdda3bsm89312635ad.27.2025.04.22.12.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:32:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350332; x=1745955132; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XHzIFD1toGdj6HYrHyt+UU2Mbk/NX+AyaF0biHg+m+k=; b=fXB0kVn/aVd24jiOX+rs4Ly8P0Pl2bcvxN+uLwtzJTI5kLLSlXZAr9tGqmUPm7bDwf qhx/1DPeXgk+/WT3fbUU6jYzQgk/MjMsi4enw0j0Xrn1SapwhPmWAw9KgE3A572k2ebE bYHwp3EK/qJcnqlxekGKWTPphQR9c22dWlfE6d9zbcEzhJy5EEp0MwJkq4jgmZYJUqZo trGIVSIIrHeUnLFFc7g9JBtGFcq1MOSJB4eE2bFYffXN5vK1nLVuqfFy7/rZEGvErxeH 2Q4bPhNYJWsT+N2UhcIiKJd3SaP8IlpuJjd1rIxYyorARqynTc9B6QShcKYCcyK7RwQQ yFbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350332; x=1745955132; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XHzIFD1toGdj6HYrHyt+UU2Mbk/NX+AyaF0biHg+m+k=; b=m9Zu3h3DBAEg54X5hY+59F+wB8loI5vcmJ7+CqXQbCWpORhQNTG+7Tg0jCRBuF1tLN E/rG2H9Nyid4OL7rGnVtS2z9XMftHe1Y541rrDkAt6xpWJANWXDJyWB7BHUKwaQ6+So+ yoRyw168iopIidgIWuxocb4kbmvzfGCYf9MRxNcqEAL8dKTNtkm9Ir9pT3qK/idhl0CB bHLq0Hnboh+/08NQ8/0m0Yg2soNL0Kqcq761yFBH9tMrXGPmuQ7+0et504WYfbxRAoma FIZFHhmHwAue5UcsP8shM8z1jetIxfGYQJ448FByDSWIleXXWorey4bNydagqebGBd17 JzDw== X-Gm-Message-State: AOJu0Yxlvige+TffcRtaWrn2PD/YnjDRAKKoNhka7mnOSGNEI2EIfidk uJO39baQ17cd8WSPBT0y3RezbVP+PqrIvcqyHoGUWKCxlpc9mSZE6zTF9nvD9l41axjGdVpE+1v m X-Gm-Gg: ASbGncvqpcQvhUwQe+9qMuOu0Hb8qVHCHQRZ0vGrFXEsJxdr5pewkY56dd6/Hdtqxi2 uhuoXDWDhGjg54yUlZXEqIAmEKzl+2AlZejMtqCpwBwHKKER81hw1f6QjUYuSEJMXyuUPxOmWPu xA+GmSxExZFEnoPG4Xy96YUIzAzL5esTfl/tQWIHHb5uG/ROq1l4SjnhWE8IcXevCtSkaxRIUCp W2QsRVFnFJTI9qEDznDJTdcYmgvGNUon4dVGqqN88Jm8kT18lP1glJLlIkqpr1CzbHG0XinmV8V 49geyZW/ehvUKwGPPnRV1EDQZqn2QGJU25FUHCPXsrjcrX5zsrkOnER6UY7lJGjUpeGkIm3lqlU = X-Google-Smtp-Source: AGHT+IG1jfX66ZydW0eiqvrfGJTshjrTNE4+dTZTUx285nMH2wIIaYZcnI4EMBxQeZAgZSCsa83NnQ== X-Received: by 2002:a17:902:f60a:b0:223:60ce:2451 with SMTP id d9443c01a7336-22c5359c344mr234896925ad.15.1745350332479; Tue, 22 Apr 2025 12:32:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 079/147] target/i386: Restrict cpu_mmu_index_kernel() to TCG Date: Tue, 22 Apr 2025 12:27:08 -0700 Message-ID: <20250422192819.302784-80-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351095312019000 From: Philippe Mathieu-Daud=C3=A9 Move cpu_mmu_index_kernel() to seg_helper.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-9-philmd@linaro.org> --- target/i386/cpu.h | 1 - target/i386/tcg/seg_helper.h | 4 ++++ target/i386/cpu.c | 16 ---------------- target/i386/tcg/seg_helper.c | 16 ++++++++++++++++ 4 files changed, 20 insertions(+), 17 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 76f24446a5..db9f01a11b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2598,7 +2598,6 @@ static inline bool is_mmu_index_32(int mmu_index) } =20 int x86_mmu_index_pl(CPUX86State *env, unsigned pl); -int cpu_mmu_index_kernel(CPUX86State *env); =20 #define CC_DST (env->cc_dst) #define CC_SRC (env->cc_src) diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h index 6b8606cd6d..ea98e1a98e 100644 --- a/target/i386/tcg/seg_helper.h +++ b/target/i386/tcg/seg_helper.h @@ -20,6 +20,8 @@ #ifndef SEG_HELPER_H #define SEG_HELPER_H =20 +#include "cpu.h" + //#define DEBUG_PCALL =20 #ifdef DEBUG_PCALL @@ -31,6 +33,8 @@ # define LOG_PCALL_STATE(cpu) do { } while (0) #endif =20 +int cpu_mmu_index_kernel(CPUX86State *env); + /* * TODO: Convert callers to compute cpu_mmu_index_kernel once * and use *_mmuidx_ra directly. diff --git a/target/i386/cpu.c b/target/i386/cpu.c index af46c7a392..0b74b9a375 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8669,22 +8669,6 @@ static int x86_cpu_mmu_index(CPUState *cs, bool ifet= ch) return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); } =20 -static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) -{ - int mmu_index_32 =3D (env->hflags & HF_LMA_MASK) ? 0 : 1; - int mmu_index_base =3D - !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : - (pl < 3 && (env->eflags & AC_MASK) - ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); - - return mmu_index_base + mmu_index_32; -} - -int cpu_mmu_index_kernel(CPUX86State *env) -{ - return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); -} - static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu =3D X86_CPU(cs); diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 71962113fb..f4370202fe 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -128,6 +128,22 @@ int get_pg_mode(CPUX86State *env) return pg_mode; } =20 +static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) +{ + int mmu_index_32 =3D (env->hflags & HF_LMA_MASK) ? 0 : 1; + int mmu_index_base =3D + !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : + (pl < 3 && (env->eflags & AC_MASK) + ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); + + return mmu_index_base + mmu_index_32; +} + +int cpu_mmu_index_kernel(CPUX86State *env) +{ + return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); +} + /* return non zero if error */ static inline int load_segment_ra(CPUX86State *env, uint32_t *e1_ptr, uint32_t *e2_ptr, int selector, --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351953; cv=none; d=zohomail.com; s=zohoarc; b=IDm8tXcsf6adcSDWXc2Yvvwc5EJjnJbOu1C0pue+Y+BnIT9uue1i5VhCY6/g9tRUzyh+Q/xSYJKjUfT3J86llla6NFdLKRx/1XMfOZnsjizIYXogBpNufcgk2xOGF2jo9dJJOhar5r0dGpK/uDIh07O5qfGYrKZKmEek2ufMAi8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351953; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dSsKhIFR7U782mMw16oJTtddZogsTKruKpBxDjg9WE0=; b=HBaf5XCrcva1ULvfsvO/tfIQlBoo5nhz2g1r19fCs7V60RWcdRv0ILIt6+OscqGpxdf+PsSYuuN2qy1WgDOND7sVHpk3bqAEIYER7y3NsHkuyLx1pqyd24Wth35laKTj6+eWL14P3EZl/dAqi/naY09fFZ7JSsQXrDczdzC7TgQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351953738914.0792644118839; Tue, 22 Apr 2025 12:59:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JR9-0001Sz-Gv; Tue, 22 Apr 2025 15:37:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOp-00053t-Mw for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:25 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOm-000717-7f for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:18 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2255003f4c6so63586215ad.0 for ; Tue, 22 Apr 2025 12:35:14 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350513; x=1745955313; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dSsKhIFR7U782mMw16oJTtddZogsTKruKpBxDjg9WE0=; b=oerO1tZVaMf34yX/J7eiwa1OYPWlnpVr7aKctDtEt+QhNFZvMqma0f15/h62wi5+XX ajGy/VSflvKNkNXTtIn4vNXHBYlgyyN8IIrnkIeEysRGubRMJXyh+hqZmq20bx+aS/hf h5OlWnAU/QIkz3bkS7IHrJgV27Qhe6HjlLJOlbvwz4QfJUSD+WfSIX/HT7MKFxVn09t9 l9lTujPD80LBr231DeIz28c/SwcV62kbHdwnHhE2Raf1bkoGrbhNkVVcffnVHzbobOZN zXMVD8Zh1berJbhA9ngrnFO5KNTRfzf89DtTZUkY3Eeuj2pt89ESKR6XThTa6mIwBJ4j EFWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350513; x=1745955313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dSsKhIFR7U782mMw16oJTtddZogsTKruKpBxDjg9WE0=; b=pl/byG9PzwvSMRipdkXcgVug/OwLza98nZl6j7w0J+TAmil9jYvUkfsvWw8Ntk16U8 uVkV7Y6M/9DgiQ7vGf3WuUFPxbh0cbvayTHpvy7GSxH1SFF5c4uy0bIDTX9fd9oUCe+3 wEjRpBKgzJznnPr37lEcTjDHzWMstS1V8E/tWjbsA7rKwZdCnqQpcQ8IQ5pjZs85HL8J 1FXxF0ZaAvgYtvuxA1CcyXvqGlCavAtluROT3ZTRTn4Uhjf1oe5i04WX+RB6DsN80X9d F2jLyyCdlBXdThuQpYF68orOPkytWwSXfHHyNu247ouxFufxEvmcOq+hOlPW2jPY/8ns MO1w== X-Gm-Message-State: AOJu0YyAwpKHh/0rcA+CXRQ7yFyI07/TxUn+JkVJ490T0rAQ+ut63t2c iaDAl3yQDdRHSE7wad2pWhYhPj7A1yg22DrTk/TOFrLMMKMuMDdfwz24H1385Z7BsZfBbm2teMf t X-Gm-Gg: ASbGncvwjeRbBiDPJTjw4POwZOitYnWsoBg33Xye+CqWJtgcfkWZgnV4uDxGyZvP8Ue PCWw7U6aDRkicl2FJNPUBkxIJNIj/KeX0MMNw+ccwkzoGPhYJIp095jxpfl10SuMn6gvgmiKIxZ U8xjsR8vT+mPexxyValoXykv3bbCfca83gBbSxnm3OJNbuSOL72fDiGLqAXqqjydVSpuy15ilBV rWKugpnOdJPk/WluupTRHRQE8ivqr+RpYgZL1Ut7q69I/locel+E2T5/2hxQXvKALAlDdRO3Jfi XHMjmxE1PE2FKcM32CzlHZ2cCWhrS+UEP2chUpe3fptoQ6JfyaT+aQ8IJW+GpeAX0VP91AFSfTD tJ2OGuG72yw== X-Google-Smtp-Source: AGHT+IGjQm0GKWw570XVulBwAzB6pftW75kzjSpnZQPFipm06E/R/8PY+CYJUd7pLEG2A/lIExx4+g== X-Received: by 2002:a17:902:d58c:b0:224:1579:5e8e with SMTP id d9443c01a7336-22c5356e19fmr281295735ad.1.1745350513441; Tue, 22 Apr 2025 12:35:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 080/147] target/i386: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:09 -0700 Message-ID: <20250422192819.302784-81-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351954660019000 From: Philippe Mathieu-Daud=C3=A9 Move x86_cpu_mmu_index() to tcg-cpu.c, convert CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-10-philmd@linaro.org> --- target/i386/cpu.h | 2 -- target/i386/tcg/tcg-cpu.h | 2 ++ target/i386/cpu.c | 18 ------------------ target/i386/tcg/seg_helper.c | 1 + target/i386/tcg/tcg-cpu.c | 18 ++++++++++++++++++ 5 files changed, 21 insertions(+), 20 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index db9f01a11b..9b8b962e0a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2597,8 +2597,6 @@ static inline bool is_mmu_index_32(int mmu_index) return mmu_index & 1; } =20 -int x86_mmu_index_pl(CPUX86State *env, unsigned pl); - #define CC_DST (env->cc_dst) #define CC_SRC (env->cc_src) #define CC_SRC2 (env->cc_src2) diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h index 53a8494455..7580f8afb4 100644 --- a/target/i386/tcg/tcg-cpu.h +++ b/target/i386/tcg/tcg-cpu.h @@ -78,4 +78,6 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=3D= XSAVE_PKRU_OFFSET); =20 bool tcg_cpu_realizefn(CPUState *cs, Error **errp); =20 +int x86_mmu_index_pl(CPUX86State *env, unsigned pl); + #endif /* TCG_CPU_H */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0b74b9a375..d930ebd262 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8652,23 +8652,6 @@ static bool x86_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -int x86_mmu_index_pl(CPUX86State *env, unsigned pl) -{ - int mmu_index_32 =3D (env->hflags & HF_CS64_MASK) ? 0 : 1; - int mmu_index_base =3D - pl =3D=3D 3 ? MMU_USER64_IDX : - !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : - (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; - - return mmu_index_base + mmu_index_32; -} - -static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - CPUX86State *env =3D cpu_env(cs); - return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); -} - static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu =3D X86_CPU(cs); @@ -8910,7 +8893,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; - cc->mmu_index =3D x86_cpu_mmu_index; cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; cc->get_pc =3D x86_cpu_get_pc; diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index f4370202fe..9dfbc4208c 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -28,6 +28,7 @@ #include "helper-tcg.h" #include "seg_helper.h" #include "access.h" +#include "tcg-cpu.h" =20 #ifdef TARGET_X86_64 #define SET_ESP(val, sp_mask) \ diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index b8aff825ee..818653ee6d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -94,6 +94,23 @@ static void x86_restore_state_to_opc(CPUState *cs, } } =20 +int x86_mmu_index_pl(CPUX86State *env, unsigned pl) +{ + int mmu_index_32 =3D (env->hflags & HF_CS64_MASK) ? 0 : 1; + int mmu_index_base =3D + pl =3D=3D 3 ? MMU_USER64_IDX : + !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : + (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; + + return mmu_index_base + mmu_index_32; +} + +static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + CPUX86State *env =3D cpu_env(cs); + return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); +} + #ifndef CONFIG_USER_ONLY static bool x86_debug_check_breakpoint(CPUState *cs) { @@ -112,6 +129,7 @@ static const TCGCPUOps x86_tcg_ops =3D { .translate_code =3D x86_translate_code, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .restore_state_to_opc =3D x86_restore_state_to_opc, + .mmu_index =3D x86_cpu_mmu_index, .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, #ifdef CONFIG_USER_ONLY --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351346; cv=none; d=zohomail.com; s=zohoarc; b=Px9DTToRT6gPU3gpElmBEwq0cbYaPittETcQBqo58f27w/iVinqJmO/6nmHgXV3NRpeoi6MiGR6No+uWUd4IeRuRmFOtkgmoxRcuc5bl7i3iztx48Omb+kE0VVFmefvbY1cASBKb2q8UMwe6mQo0FH4PIPP1ahCHEFToM/R4L/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351346; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=s+vJSXjRAVXeTwmKub0ZXgQhIZDI7tyX9VxiyklcrIY=; b=UxMffl0hjjZDW6lSOw2N09SFfvA4Fh+AGr2rFnEHfGDo8bX1XDFiD2Zz1htuzOhNMt4jssi9cX/2MJJHMqVhjeeHIQQR+nlTosufCUlv2NK7QIh9prFDXYMvyXYmG6jLBlvTJHO4OG6CpvwP1er283MsqJUMr1jg/1dwEv7xW14= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351346889452.15305252909786; Tue, 22 Apr 2025 12:49:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JR6-0001Le-Qk; Tue, 22 Apr 2025 15:37:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOp-00053s-NL for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:25 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOm-000719-IH for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:18 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-223fb0f619dso64457265ad.1 for ; Tue, 22 Apr 2025 12:35:14 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:35:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 081/147] target/loongarch: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:10 -0700 Message-ID: <20250422192819.302784-82-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351348350019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-11-philmd@linaro.org> --- target/loongarch/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ea1665e270..cb96b17911 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -868,6 +868,7 @@ static const TCGCPUOps loongarch_tcg_ops =3D { .translate_code =3D loongarch_translate_code, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, .restore_state_to_opc =3D loongarch_restore_state_to_opc, + .mmu_index =3D loongarch_cpu_mmu_index, =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D loongarch_cpu_tlb_fill, @@ -919,7 +920,6 @@ static void loongarch_cpu_class_init(ObjectClass *c, vo= id *data) &lacc->parent_phases); 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Tue, 22 Apr 2025 12:35:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 082/147] target/m68k: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:11 -0700 Message-ID: <20250422192819.302784-83-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351952525019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-12-philmd@linaro.org> --- target/m68k/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 0065e1c1ca..4409d8941c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -592,6 +592,7 @@ static const TCGCPUOps m68k_tcg_ops =3D { .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, .restore_state_to_opc =3D m68k_restore_state_to_opc, + .mmu_index =3D m68k_cpu_mmu_index, =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D m68k_cpu_tlb_fill, @@ -615,7 +616,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) &mcc->parent_phases); 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Tue, 22 Apr 2025 12:35:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 083/147] target/microblaze: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:12 -0700 Message-ID: <20250422192819.302784-84-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351382397019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-13-philmd@linaro.org> --- target/microblaze/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f3bebea856..88baeb6807 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -431,6 +431,7 @@ static const TCGCPUOps mb_tcg_ops =3D { .translate_code =3D mb_translate_code, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, .restore_state_to_opc =3D mb_restore_state_to_opc, + .mmu_index =3D mb_cpu_mmu_index, =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D mb_cpu_tlb_fill, @@ -455,7 +456,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) &mcc->parent_phases); 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Tue, 22 Apr 2025 12:35:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 084/147] target/mips: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:13 -0700 Message-ID: <20250422192819.302784-85-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351128671019100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-14-philmd@linaro.org> --- target/mips/cpu.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 47df563e12..cb0d6dde0e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -182,11 +182,6 @@ static bool mips_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) -{ - return mips_env_mmu_index(cpu_env(cs)); -} - #include "cpu-defs.c.inc" =20 static void mips_cpu_reset_hold(Object *obj, ResetType type) @@ -549,11 +544,18 @@ static const Property mips_cpu_properties[] =3D { =20 #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" + +static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) +{ + return mips_env_mmu_index(cpu_env(cs)); +} + static const TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, .restore_state_to_opc =3D mips_restore_state_to_opc, + .mmu_index =3D mips_cpu_mmu_index, =20 #if !defined(CONFIG_USER_ONLY) .tlb_fill =3D mips_cpu_tlb_fill, @@ -581,7 +583,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) &mcc->parent_phases); =20 cc->class_by_name =3D mips_cpu_class_by_name; - cc->mmu_index =3D mips_cpu_mmu_index; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->get_pc =3D mips_cpu_get_pc; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 22 Apr 2025 12:35:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 085/147] target/openrisc: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:14 -0700 Message-ID: <20250422192819.302784-86-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351006414019100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-15-philmd@linaro.org> --- target/openrisc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e8abf1f8b5..dc55594a7d 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -247,6 +247,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { .translate_code =3D openrisc_translate_code, .synchronize_from_tb =3D openrisc_cpu_synchronize_from_tb, .restore_state_to_opc =3D openrisc_restore_state_to_opc, + .mmu_index =3D openrisc_cpu_mmu_index, =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D openrisc_cpu_tlb_fill, @@ -269,7 +270,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) &occ->parent_phases); =20 cc->class_by_name =3D openrisc_cpu_class_by_name; - cc->mmu_index =3D openrisc_cpu_mmu_index; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->get_pc =3D openrisc_cpu_get_pc; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352403; cv=none; d=zohomail.com; s=zohoarc; b=cIHf71C16OXN54v5BjmvmsRAXvBCCgMI7LQcMFs1K5ssZyX/8WbeFd+tqACHHNDbFfAHG44DpYh9CRCIS+NCzdGf9pE2sRGaTYMltnq4ShFqW3CpfhzK0xGHIvszJjSbouDpVVI8nZgKfEUD0Bb7sz+T1HnhrjJ+//kl+BVApjw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352403; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350517; x=1745955317; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wTTbJUYSutthRAHWERBfaY61+pWxicGlAYRiaD9+MBo=; b=JGp1UPR5fuVG0BgFgXe8uCm5cwUZgggBydyYsfxu/W4y03k7ZAAMwUkwpDnl1dknIN X2vDn0tt3oi7fchVWrSNi8/tE2v4sauzz/kna1yFU4x962UFmhvXVokd+Khil5SJ6VGf evwX5iQ6r2ae3rDZq2BuLz8cqBpIasDsC1ZQFDRzr/OPoDAYbi39WaTNl3l2oEtHidYP tHR6cr10kxZQwhNVCKiyoOmpTTaR8Izm4T0rkRMZBH6flMFNPdii2ZubO9JdfaLrfWJ7 XQGteDn29gZSvzO5mU1y8mzCH9FCC9cp5BOkSJRzGFSGnoucKlrf4/6k/XFuuEX8vWVe V49A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350517; x=1745955317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wTTbJUYSutthRAHWERBfaY61+pWxicGlAYRiaD9+MBo=; b=bmMlsPFgb8feTJy28XBfPcaXnZ1mR6yEc4RKU29D4XNBCb7iHzR/ytfVt0eHhZ13VH wPe2zBX9fJYf7mDp8BZYEaMFfexVrhoxp3jf1ux9y1BNSsugZT5Cn/VKkldRFS7Vc1Pz 2pYMfJTXGF/ECerfHn+Wmux3ebQGnloUbjWVuEyvu8RuB4vHsNvgY3Rh2ryrWZW2yLA5 YMWsq6R0E7CxOX3dyu7aRB8ZD7bvvpqKYgDoP19BFXPLD0PsFHWrO4mHJeUfD5sNQuDg OYPCy+9nfvvO++Ao27bQHr4JtDPWqZeXzx18uz48ouCLpHKEpj3q1B/sWBUdb30fDrxT 9niw== X-Gm-Message-State: AOJu0Yx3JfwpaOeEjNvtiwkgJeerf10kDChgsNVVgPW5Amo7vfYq9MU3 GMiPFBLQAzeW1UucJoS/GOdkC+d89IwyaXaUyEVvTqRYtnvurC35nR4qoUb9yUwxz4Lb/O9pYN7 l X-Gm-Gg: ASbGncuS2zpRtMHtvf+Uk2+XBJHQSVlmJ0FU+neOtcMpG0rEM2tM1KTYj1WRazs/DJi m5Fo341CVZj94dWRxROgMtcmqYZ190VbBcB4H9xRohfu6F3Y5HYdM6gMBYPq9L0WZaaDj3urDfG jwCGEU0NjX1dgqsuJj/TmMbXAIes0TNt7n0Wckg/C6fDawE7fF9/8JaMaCVYQFpc3DN3ZQajJ1S r3pe9T5e0/S67tlVhKWNnqPPamGoPXldw6YsqsfivAQ/0ECSx8urxo4EOTol4zTkdWp924DloC+ SWIglZB471gf0PRYhJnabcRgX/5DbNGcIpjFwfDsEq6YnqPxeE6usFPLCPzr+dsqOrw49BHwEc4 = X-Google-Smtp-Source: AGHT+IEN79ZnpXd2WZW7/CzCrQkflbbXtTzueXTzCs/wdF0KezWejwERUMQ0tNOjK7obHYuugMgF4A== X-Received: by 2002:a17:902:ce01:b0:223:569d:9a8b with SMTP id d9443c01a7336-22c53580d1dmr207953245ad.18.1745350517215; Tue, 22 Apr 2025 12:35:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 086/147] target/ppc: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:15 -0700 Message-ID: <20250422192819.302784-87-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352405504019100 From: Philippe Mathieu-Daud=C3=A9 Convert CPUClass::mmu_index() to TCGCPUOps::mmu_index(), restricting ppc_cpu_mmu_index() to TCG #ifdef. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-16-philmd@linaro.org> --- target/ppc/cpu_init.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 17f0f3d3ff..fd8c42069e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7216,6 +7216,11 @@ static void ppc_restore_state_to_opc(CPUState *cs, =20 cpu->env.nip =3D data[0]; } + +static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return ppc_env_mmu_index(cpu_env(cs), ifetch); +} #endif /* CONFIG_TCG */ =20 #ifndef CONFIG_USER_ONLY @@ -7225,11 +7230,6 @@ static bool ppc_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - return ppc_env_mmu_index(cpu_env(cs), ifetch); -} - static void ppc_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); @@ -7482,6 +7482,7 @@ static const TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, .restore_state_to_opc =3D ppc_restore_state_to_opc, + .mmu_index =3D ppc_cpu_mmu_index, =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D ppc_cpu_record_sigsegv, @@ -7518,7 +7519,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) &pcc->parent_phases); =20 cc->class_by_name =3D ppc_cpu_class_by_name; - cc->mmu_index =3D ppc_cpu_mmu_index; cc->dump_state =3D ppc_cpu_dump_state; cc->set_pc =3D ppc_cpu_set_pc; cc->get_pc =3D ppc_cpu_get_pc; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351807; cv=none; d=zohomail.com; s=zohoarc; b=a0SKeh7OyG7gt5X6SY1bqOqOLR5JbDLtaAECFBoYXla4UjQ/KDAixcZGxdN5s3zfGViffxY7AFJb6xxk0GSQLQHnHKETrV+wmbkFfuVMzTunSVGVn77O6mjb0k1iGMOrOefyfz7g0WeD4TW+yDm0iHQ/kFO8ynWWYQkSiSCjLpw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351807; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CTmftL2su6jwrf+15dG9AUJcmzSAFqQvTSHtk/3sj+U=; b=G4kGmT/wa2in9JPIkZlX6wSh6NXxXvYsBTUmXxz+4FcC92+XNW6M2UUdYoKwLkquwAlCULb86DrLDWa0LIO8uKbSZ+51TNGOO2erFI9/alDG2GY/MDnDcVr9eqWrJ5VhBniyo3+ddBuzcSmPxzN3S9UyDG1DYlSK9iS/4k5FY0c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351807083286.7630355744168; Tue, 22 Apr 2025 12:56:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JRM-0001jP-KZ; Tue, 22 Apr 2025 15:37:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOs-00054X-78 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:30 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOp-00071j-Or for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:21 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-223fd89d036so69452925ad.1 for ; Tue, 22 Apr 2025 12:35:18 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-17-philmd@linaro.org> --- target/riscv/cpu.c | 6 ------ target/riscv/tcg/tcg-cpu.c | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 09ded6829a..430b02d2a5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1021,11 +1021,6 @@ bool riscv_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - return riscv_env_mmu_index(cpu_env(cs), ifetch); -} - static void riscv_cpu_reset_hold(Object *obj, ResetType type) { #ifndef CONFIG_USER_ONLY @@ -3049,7 +3044,6 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, void *data) &mcc->parent_phases); =20 cc->class_by_name =3D riscv_cpu_class_by_name; - cc->mmu_index =3D riscv_cpu_mmu_index; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; cc->get_pc =3D riscv_cpu_get_pc; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5aef9eef36..bee7dfd803 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -91,6 +91,11 @@ static const char *cpu_priv_ver_to_str(int priv_ver) return priv_spec_str; } =20 +static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return riscv_env_mmu_index(cpu_env(cs), ifetch); +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -138,6 +143,7 @@ static const TCGCPUOps riscv_tcg_ops =3D { .translate_code =3D riscv_translate_code, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .restore_state_to_opc =3D riscv_restore_state_to_opc, + .mmu_index =3D riscv_cpu_mmu_index, =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D riscv_cpu_tlb_fill, --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351949; cv=none; d=zohomail.com; s=zohoarc; b=E89YAuwfckbMXncvJxJeURC1Fc4riWm8UJnjaSFEDDlkk2F0D6GlFD0M6Ydz2yAaRpweBch348h+iDJQxoAPcMThKLi2mcvFW24izOaPUPDzBxjdT5QM0xqddbjWMGSfYTQktXTWSUmT8I9nZrLgQ+rS8UK/NS9Tff3s7j4/F+U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351949; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NMqpwELVZjRand5YykheI0qauU6tLGMgrXCPuO0m4X0=; b=dfTvscycSswn0Y9hFWf0DuumMIRQ/8YI80F6htXpmRtcvbBmtgnRZT3zsWkVGviet3YXZ+mfB1Yb9cfPuYQDAn2RvX+GdMJ3KvWSOEJRre3Lznwa2qa7e26oluf1K0epUQ0z3LvEu4jHb85P3YTzYX6wJM7Ze76jTiej2xEfsOw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351949819951.8934513352472; Tue, 22 Apr 2025 12:59:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPM-00062V-23; Tue, 22 Apr 2025 15:35:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOu-00056Z-5B for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:29 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOq-00071r-Et for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:22 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-2240b4de12bso83112275ad.2 for ; Tue, 22 Apr 2025 12:35:19 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:35:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 088/147] target/rx: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:17 -0700 Message-ID: <20250422192819.302784-89-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351950571019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-18-philmd@linaro.org> --- target/rx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index a240b3b3ce..51743020d4 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -207,6 +207,7 @@ static const TCGCPUOps rx_tcg_ops =3D { .translate_code =3D rx_translate_code, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, .restore_state_to_opc =3D rx_restore_state_to_opc, + .mmu_index =3D rx_cpu_mmu_index, .tlb_fill =3D rx_cpu_tlb_fill, =20 .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, @@ -227,7 +228,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) &rcc->parent_phases); =20 cc->class_by_name =3D rx_cpu_class_by_name; - cc->mmu_index =3D rx_cpu_mmu_index; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; cc->get_pc =3D rx_cpu_get_pc; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352537; cv=none; d=zohomail.com; s=zohoarc; b=AJmYIlTBb7YB6XJX4XgKCnEeMLLQa5BS/vMUreQ7pQHlxuoyPfUgvjsRX2E4Q++lxrlMcWHmQOUF0gOUCXUnbsh0MsDuutHB59pfnVJn8g3EHINnT9GJJpP7rx7lNJnwzjWqhVpfPGGnm/B5h01mxuMKc7JSz8dtlfKIdorwySg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352537; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-19-philmd@linaro.org> --- target/s390x/cpu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 1f75629ddc..d15b1943e0 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -126,11 +126,6 @@ static vaddr s390_cpu_get_pc(CPUState *cs) return cpu->env.psw.addr; } =20 -static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - return s390x_env_mmu_index(cpu_env(cs), ifetch); -} - static void s390_query_cpu_fast(CPUState *cpu, CpuInfoFast *value) { S390CPU *s390_cpu =3D S390_CPU(cpu); @@ -308,6 +303,11 @@ static const Property s390x_cpu_properties[] =3D { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" =20 +static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return s390x_env_mmu_index(cpu_env(cs), ifetch); +} + void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) { @@ -348,6 +348,7 @@ static const TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, .restore_state_to_opc =3D s390x_restore_state_to_opc, + .mmu_index =3D s390x_cpu_mmu_index, =20 #ifdef CONFIG_USER_ONLY .record_sigsegv =3D s390_cpu_record_sigsegv, @@ -378,7 +379,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) &scc->parent_phases); =20 cc->class_by_name =3D s390_cpu_class_by_name; - cc->mmu_index =3D s390x_cpu_mmu_index; cc->dump_state =3D s390_cpu_dump_state; cc->query_cpu_fast =3D s390_query_cpu_fast; cc->set_pc =3D s390_cpu_set_pc; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351126; cv=none; d=zohomail.com; s=zohoarc; b=R18dp/DNYUznLtQkLmzMZpUKMZnVrxJI2cS0wdmYT6jFE32DavP9+hKCDGmASFmzRH2kIe6xFYNibWm85MObY/v3w8NxjnI6YGO8wzC+XHGJmLq+aKcZae7V/8n3NPHAEgHTa5zWnVxtGIxCXzTXQaFUbQnu+O0kb46cwj0MuHI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351126; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZMFyoxMcqEJbFer+UYr/caW6q12pnT/2IbFSElSLN88=; b=KhxMSDAkgVPLwFvNbgK2jHU/273qLCXAFaOqPRONXA3kas3+5W85PHKqPZNfupOkoqaHBaoLw3F9Ic8REwvNYOiwdOcToe3mrPKOjPqXI9CNAFSHfJ/k81MJKb3DQUukuiaY9ZvEQYo5KJ8qdBKGEruseScVLcLOa2oIL0VHu+w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174535112651656.61538696983962; Tue, 22 Apr 2025 12:45:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JR6-0001Kq-CI; Tue, 22 Apr 2025 15:37:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOu-00056c-9v for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:29 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOr-00072K-Ey for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:23 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-224019ad9edso79433685ad.1 for ; Tue, 22 Apr 2025 12:35:20 -0700 (PDT) Received: from stoup.. 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Tue, 22 Apr 2025 12:35:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 090/147] target/sh4: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:19 -0700 Message-ID: <20250422192819.302784-91-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351127525019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-20-philmd@linaro.org> --- target/sh4/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ce84bdf539..df093988cb 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -266,6 +266,7 @@ static const TCGCPUOps superh_tcg_ops =3D { .translate_code =3D sh4_translate_code, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, .restore_state_to_opc =3D superh_restore_state_to_opc, + .mmu_index =3D sh4_cpu_mmu_index, =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D superh_cpu_tlb_fill, @@ -291,7 +292,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) &scc->parent_phases); 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Tue, 22 Apr 2025 12:35:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 091/147] target/sparc: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:20 -0700 Message-ID: <20250422192819.302784-92-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352105296019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-21-philmd@linaro.org> --- target/sparc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 57fbf16ad2..af3cec43e7 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1005,6 +1005,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { .translate_code =3D sparc_translate_code, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, .restore_state_to_opc =3D sparc_restore_state_to_opc, + .mmu_index =3D sparc_cpu_mmu_index, =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D sparc_cpu_tlb_fill, @@ -1033,7 +1034,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, voi= d *data) =20 cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; - cc->mmu_index =3D sparc_cpu_mmu_index; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351952; cv=none; d=zohomail.com; s=zohoarc; b=EoHUU0g2HjX+3BqSPeFpkc52cSYEn3tVv3SNb7O99mdyZrX7KVvY6LK+tXjJXhpbhX34FEHikOVX4FC/p2WTQ5A/cSas/TIp8amw6+IUJMtuA1qCgb4nP8Xgp6ns+YTGBLwfTmwVk+WzFwwJjUGdlkiVP1B0wVWNQcl1K7uts9E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351952; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 22 Apr 2025 12:35:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 092/147] target/tricore: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:21 -0700 Message-ID: <20250422192819.302784-93-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351952532019000 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-22-philmd@linaro.org> --- target/tricore/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 16acc4ecb9..833a93d37a 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -176,6 +176,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .translate_code =3D tricore_translate_code, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .restore_state_to_opc =3D tricore_restore_state_to_opc, + .mmu_index =3D tricore_cpu_mmu_index, .tlb_fill =3D tricore_cpu_tlb_fill, .cpu_exec_interrupt =3D tricore_cpu_exec_interrupt, .cpu_exec_halt =3D tricore_cpu_has_work, @@ -194,7 +195,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, N= ULL, &mcc->parent_phases); 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Tue, 22 Apr 2025 12:35:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 093/147] target/xtensa: Restrict SoftMMU mmu_index() to TCG Date: Tue, 22 Apr 2025 12:27:22 -0700 Message-ID: <20250422192819.302784-94-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351623713019100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-23-philmd@linaro.org> --- target/xtensa/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index ec6a0a8b66..51f9ee9e89 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -236,6 +236,7 @@ static const TCGCPUOps xtensa_tcg_ops =3D { .translate_code =3D xtensa_translate_code, .debug_excp_handler =3D xtensa_breakpoint_handler, .restore_state_to_opc =3D xtensa_restore_state_to_opc, + .mmu_index =3D xtensa_cpu_mmu_index, =20 #ifndef CONFIG_USER_ONLY .tlb_fill =3D xtensa_cpu_tlb_fill, @@ -262,7 +263,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) &xcc->parent_phases); =20 cc->class_by_name =3D xtensa_cpu_class_by_name; - cc->mmu_index =3D xtensa_cpu_mmu_index; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; cc->get_pc =3D xtensa_cpu_get_pc; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351280; cv=none; d=zohomail.com; s=zohoarc; b=TWGSRuxnsKEn+cbhHZiquj/IuWokOB/jLPn3oU7pKLfCsFuEg1Kf+ElIJ6ro89Tj6KJ54vxrTlgNsBe55hP9iW3cvatqc0hhU0LaZrI5cbSVuffKpz8DapyahwI+0OlmwS6H5H6bHYc9DtC46FNisWwf7LRW/i5dFhN9pET2/YA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351279; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350522; x=1745955322; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N1UQyMwl8FkxNsbxCkJPrCVn5egihsCexcKX6axRuSQ=; b=w/Rd9550GuDf1Vy53JUa71n7Q29FlJ53TVw5cLaLt6l+5DvSbEltJaiAH1jjafVlHC IjHlzGqaccYCZ3TtNamHrw7izhR+fyvVFMkt8jfthkQ5DW/ZLyzMVIOZ07wzpegxbhEW +TMgK2lymKDlmR1sqGNMKywx3oLsoFMo5FS2d25f6NyERDMOPmVdS5r9cA55kD87M52t tH+Gb4p2vio/aQKE+Msbp3fJ01DEinbqhaC0UFwkippZ7xwcXGk0uzXKXrvm9QMg5P78 u1ma02U3elZOnzon+j2WwpBK5ltSpXfeaA5Ye2D108Smp74HTVmuhfwh85g1XaQlYWC3 By/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350522; x=1745955322; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N1UQyMwl8FkxNsbxCkJPrCVn5egihsCexcKX6axRuSQ=; b=kcC8V33oix6p5yWui0dkjgGErtJqf7RMyJ+07nyZhlp92yzIffttHZkRVNQ7VMFQEQ qPx3IUkmVRRfhc2KYdUnYoBD5vOADlsuhgjn9uT0GC+VgaqAIf8thfMZ4Ak87Wmq4+hb AhnWVEMO5o1P6Tig1/OGnWevog3FG90uEi5WqojzHqwYau/kRJ9h1a3dMFriTBmDV6K7 wlGzwBLrZeSgnVGohfqPrWT3BxjJLpJ9dplvjPi6j2RneP5Oq4PxKG2jiBk0vHn8x113 74wJuI/3K1ul1mGroGSpVqFzncglHJee1gpvohX7G/bZa86J8K7er2C4VDHwdD7Pr/RV RsZg== X-Gm-Message-State: AOJu0YxxQQeoloVrhoQYDVy6c3rC/UKXJfeuro8tktBM7Cq8o7pgqabf oLP+kuPcMChEIMlztXFSl0+6+pNVz/G+K+XjPMn7uGvKXtNocbWIsemIOuduTTZtlZwaajUvQcl O X-Gm-Gg: ASbGncs4DsjTwyAESeVNdiq8AaLaJITfxV5FBa20uvt35mv1Lub4LRO3Jh/XrMEbQIe aIC6wkzGyPuiqBVw/Tee9iSmrqT9oklaph7yLPYW1epJc7+rpIg63bBwzE4SNDlttJ07ujfNkgG 3AU9pytGAwbsXTQ+rG2pn80mkBk+4HeujvKGcyD4dqLn3ius56OxmYltLjz3ImYmsgR3FRDYKjP R7af2nhZvG3OU7d98xYGvyStCCZ4D/Bs22RDQmYr8jET7PpOH6DkmqszR2QLQSOt/7NPoERMUR0 3zA0cvfuu6Hp6tS2MLtHZRpNdeh7A+bHVbh1iC4dTsAJvyTs0FfTfFd9EIVp8MJGJ2JO9IWdlL4 = X-Google-Smtp-Source: AGHT+IGGxPcWKl9L+xU5eTuU7M5qZ+c+b6ToAsTd10A/BiAnYeBINB5Bf/KWVhemRYJkTx4cAjs2HQ== X-Received: by 2002:a17:902:dac7:b0:21f:98fc:8414 with SMTP id d9443c01a7336-22da3387b8dmr2623995ad.26.1745350522225; Tue, 22 Apr 2025 12:35:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Brian Cain Subject: [PATCH 094/147] target/hexagon: Implement TCGCPUOps.mmu_index Date: Tue, 22 Apr 2025 12:27:23 -0700 Message-ID: <20250422192819.302784-95-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351282036019000 This hook is about to become mandatory. Since hexagon is still user-only, the implementation is trivial. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Brian Cain Signed-off-by: Richard Henderson --- target/hexagon/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 766b678651..ad1f303fbc 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -313,6 +313,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Erro= r **errp) mcc->parent_realize(dev, errp); } =20 +static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return MMU_USER_IDX; +} + static void hexagon_cpu_init(Object *obj) { } @@ -324,6 +329,7 @@ static const TCGCPUOps hexagon_tcg_ops =3D { .translate_code =3D hexagon_translate_code, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, .restore_state_to_opc =3D hexagon_restore_state_to_opc, + .mmu_index =3D hexagon_cpu_mmu_index, }; =20 static void hexagon_cpu_class_init(ObjectClass *c, void *data) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351328; cv=none; d=zohomail.com; s=zohoarc; b=JVbOdxBVzRtfhxM9+5Y+exaJg6CAKO1Go/s/TzlmUjB+ovTeZ5lTEegyrj7cPzpmG6RLkB8ZwGkgnfoEPGKHKQ9h9TRxhuotrvtddLV8Nf0C1WF8BzPkLVMlTW2B8AMhhqBdRyIwpRrq3vPIYPs9DwB0OUy43tmCMJVerrX5ocg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351328; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sWIZdxiQwNCWQMc8BJaWdVB87by5vfdybCIjbCIrMGM=; b=BNUFswz6ueZPhBCbDrmOAIctt5B9QElExGZsiCTFYs6I+SFluimqWeX+AxNmuy+pD6iR5Z3dpIV+4zsso/MjCL0C0tANHb+fanKuNf0ZZ+jV537o4+hDAmu/ojH+qrXJ0GkzEUvdYE7H7U5LxxqGH4UiqflD/Pak7m7AdI/UTJI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351328597654.2885971149599; Tue, 22 Apr 2025 12:48:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JR8-0001Oq-LK; Tue, 22 Apr 2025 15:37:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOw-0005AI-BJ for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:30 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOu-00073J-Fl for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:26 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2241053582dso78326205ad.1 for ; Tue, 22 Apr 2025 12:35:23 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-ID: <20250401080938.32278-24-philmd@linaro.org> --- include/accel/tcg/cpu-mmu-index.h | 4 +--- include/hw/core/cpu.h | 2 -- accel/tcg/cpu-exec.c | 1 + 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/include/accel/tcg/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-= index.h index f1ca385d3c..e681a90844 100644 --- a/include/accel/tcg/cpu-mmu-index.h +++ b/include/accel/tcg/cpu-mmu-index.h @@ -34,9 +34,7 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) # endif #endif =20 - const TCGCPUOps *tcg_ops =3D cs->cc->tcg_ops; - int ret =3D tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch) - : cs->cc->mmu_index(cs, ifetch); + int ret =3D cs->cc->tcg_ops->mmu_index(cs, ifetch); tcg_debug_assert(ret >=3D 0 && ret < NB_MMU_MODES); return ret; } diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 29f6419050..28bd27b8ed 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -104,7 +104,6 @@ struct SysemuCPUOps; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @mmu_index: Callback for choosing softmmu mmu index. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: @@ -151,7 +150,6 @@ struct CPUClass { ObjectClass *(*class_by_name)(const char *cpu_model); void (*parse_features)(const char *typename, char *str, Error **errp); =20 - int (*mmu_index)(CPUState *cpu, bool ifetch); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, size_t len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 034c2ded6b..9e15105533 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1075,6 +1075,7 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp) assert(tcg_ops->cpu_exec_interrupt); #endif /* !CONFIG_USER_ONLY */ assert(tcg_ops->translate_code); + assert(tcg_ops->mmu_index); tcg_ops->initialize(); tcg_target_initialized =3D true; } --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351934; cv=none; d=zohomail.com; s=zohoarc; b=nYuL1Uy+oS7l9wNwSgzXNKvvyI4Kx3oHihfKeyjt8jn1/qhxu2zWv3JUkLbKYhps0mk/HJYawAE6DwPcCBT+PMnS7OR1tyf9PTd8N9EV0aLAiRGlIuS9Qrb3wdu0NUdUH29RkLQV+h/kttSUL0QcZs/PDO+pCcBfYi79qy+emus= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351934; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=B2dng6uyh/TVtKzBLSnew6/1cI3Pxi8Kdl7ghuagDjo=; b=S/zR9dyT+jbGbzb1nEopDlJVVGyDnhMgYCPKFu9BjyI4XWYFsHUrRI93WtUAswVgZsQyLTZfAEqA3iN64feX9HB22rsdV30yg7/vp9VdU75Q1Uvt8HCoAWJjxf6uM3hLckKDWvXhRmBK5M9Znim3K4iFKPUBdhxhBFcuIUEg6jA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351934130114.83380417294427; Tue, 22 Apr 2025 12:58:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JQZ-0000NS-PW; Tue, 22 Apr 2025 15:37:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOy-0005AP-MD for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:31 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOu-00073a-VU for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:28 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-225477548e1so57017145ad.0 for ; Tue, 22 Apr 2025 12:35:24 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350523; x=1745955323; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B2dng6uyh/TVtKzBLSnew6/1cI3Pxi8Kdl7ghuagDjo=; b=AUbGAmacNLauXAn7sy+sGXnofPcI2DGfXvYWeGU+tldxYog9WaUTFKBQcaVHHWT/az 9vm6ZSx6ym+J/aDyYWYwf2f6EGkHDoVBG1+C8ovy6jXjK+j/ccvTtq3qPS2PibSYls5W HW83tr6R08i/PYMN8xBeTP6jj79ZHXvlaglqGIx4tkNRQNh350NL5h497meD60AdG/Lw G5LJKYNlJQh/qyq3zfEg2/1/8e+rdhsiXVqwcdq9YFa5GUpOVmIkLRHZ5edhTZtmUmpR F4aagJYGhGGR4xkquFijZpVoRQpu86NyB2oUAl5UpzehIG4/JvAMJzyX2Uu6lBAkNk7Q Uh8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350523; x=1745955323; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B2dng6uyh/TVtKzBLSnew6/1cI3Pxi8Kdl7ghuagDjo=; b=K9wxich1bJU+tCX8EcMv+j2c2WIDQLYmggWd4tkpaoy61AbMLXhSFU8ByoBh9CGpc5 BeIyaMn/EFWCY90PV820WDnrohJS9pRYmlRNGyCQXVH2ES7TObfKWLTcayofucNWROAu GvIwlpgnZjCTFSQFKOntheOywdkj+eceEmjCFVavI9tOUQG801NsF8PPDFIXf7Ez5lko M9SjpN/J2F6WaH02hjFIY4q0AsS3hW3dDUAsv1QXhKuEu1JOat7z8W1MXYMHrgPeqDrr pEuY7fUtDRAkHZ8Lg6Mk/tQN6qY9Iz8fUMQ6kaTtpScqwErgpZGTufKVc+pV/BYymatq rWXw== X-Gm-Message-State: AOJu0YzXMdBj60Rf/P2Dj4Nxl3oEXpyh5gTPV3mLYyFI71gHfGjLT3hu y7FDq5citZ7WH/4r5qG8sNBc+3VedH0xhv0dQ82+7hea18i0nXjmYKn0mNSQGIxkjnVokW1GEFt i X-Gm-Gg: ASbGncu+xCi1I14+OqDBt9wkYXVXO7GG7qbMTajxqeQu3Rwko045yDzzKnWDVqsM+xJ D7swEt4GR/KWAfv4B0Pgt/y1R6W98iIx9sYr7v50XhWJKvzGP2aQLVCwsXoCNePuyWNyMhzWtV1 rIST/ycoryYh1Qy1qV58m3Zh8UiiR5CihN1r+HhlR6lwgMQeHcPUXsqHb1DWXh0QYnmlDjl5xQK f/6Xr++jsrgv6dE1e/7H9rBiUCZxIJgK56Eo5S02HmZenltuPjYuj5nbPJD4pJXodNzflvEPzIh HRBtr6EavgDjwNwTyeuWEjUDmTyZrFTUVnMjbvxsU8SkV4OaeaxEyNtkAppb/KagMa+AXT+KZ3u DmAsL4K/Eqw== X-Google-Smtp-Source: AGHT+IF3sdvzjsJfy29xB/uspueerctkoEaCAGZM3yxLzzLRofKiWDKEadLKu8Ad0U+4LN9QwDcYtg== X-Received: by 2002:a17:902:ef0a:b0:22c:35c5:e30a with SMTP id d9443c01a7336-22c53580d0dmr229853135ad.16.1745350523568; Tue, 22 Apr 2025 12:35:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 096/147] accel/tcg: Build translator.c twice Date: Tue, 22 Apr 2025 12:27:25 -0700 Message-ID: <20250422192819.302784-97-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351934514019000 Drop some unnecessary includes. Change the offsetof expressions to be based on CPUState instead of ArchCPU. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/translator.c | 14 ++++++-------- accel/tcg/meson.build | 2 +- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 5f0aa9d56a..c53bbdef99 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -11,14 +11,13 @@ #include "qemu/bswap.h" #include "qemu/log.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" #include "exec/cpu-ldst-common.h" #include "accel/tcg/cpu-mmu-index.h" +#include "exec/target_page.h" #include "exec/translator.h" #include "exec/plugin-gen.h" #include "tcg/tcg-op-common.h" #include "internal-common.h" -#include "internal-target.h" #include "disas/disas.h" #include "tb-internal.h" =20 @@ -26,8 +25,7 @@ static void set_can_do_io(DisasContextBase *db, bool val) { QEMU_BUILD_BUG_ON(sizeof_field(CPUState, neg.can_do_io) !=3D 1); tcg_gen_st8_i32(tcg_constant_i32(val), tcg_env, - offsetof(ArchCPU, parent_obj.neg.can_do_io) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.can_do_io) - sizeof(CPUState)); } =20 bool translator_io_start(DisasContextBase *db) @@ -50,8 +48,8 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t= cflags) if ((cflags & CF_USE_ICOUNT) || !(cflags & CF_NOIRQ)) { count =3D tcg_temp_new_i32(); tcg_gen_ld_i32(count, tcg_env, - offsetof(ArchCPU, parent_obj.neg.icount_decr.u32) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.icount_decr.u32) - + sizeof(CPUState)); } =20 if (cflags & CF_USE_ICOUNT) { @@ -80,8 +78,8 @@ static TCGOp *gen_tb_start(DisasContextBase *db, uint32_t= cflags) =20 if (cflags & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, tcg_env, - offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.= low) - - offsetof(ArchCPU, env)); + offsetof(CPUState, neg.icount_decr.u16.low) - + sizeof(CPUState)); } =20 return icount_start_insn; diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 72d4acfe5e..047afa49a2 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -8,6 +8,7 @@ tcg_ss.add(files( 'cpu-exec-common.c', 'tcg-runtime.c', 'tcg-runtime-gvec.c', + 'translator.c', )) if get_option('plugins') tcg_ss.add(files('plugin-gen.c')) @@ -22,7 +23,6 @@ tcg_specific_ss.add(files( 'cpu-exec.c', 'tb-maint.c', 'translate-all.c', - 'translator.c', )) tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'= )) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350813; cv=none; d=zohomail.com; s=zohoarc; b=c+6kOdCY16ndeHUVPv7MtH9U+scsx0POwf63PM0p9WGecci6yck2O6qA6I7LP6lrnzQhwfryZtb34958MHE/yVJjLTo2pO4boQF6dq3GFvKcqiL64KzCW4XTH88PI/C7fnArfTwlgytycMCFXyXC3y7H+DUFUQ5Af1mo6lwJjCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350813; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ggbOR76BAcyXgvavB4mZvfqZnt/5CtPguoo3NLh6PJU=; b=DtXmJohQHAL3ASBtvzBI3Gko3TvQ22Rkz6FAM5IZ+p1S3R5aiarswpV9cPzS7Tq1d9Ke0mvb12Cib2dKbo2QvQ1PeLZoQK6+M9uYgdCXRe+EKBkVj7CeuirySXOa32+hlXS6SNDHF05v4Casux621ENnfn8BU3uPafh0K3JkAec= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350813538139.5070896290605; Tue, 22 Apr 2025 12:40:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPw-0008Ci-GE; Tue, 22 Apr 2025 15:36:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOx-0005AK-Cy for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:31 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOv-00073w-GL for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:27 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-22435603572so60089515ad.1 for ; Tue, 22 Apr 2025 12:35:25 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350524; x=1745955324; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ggbOR76BAcyXgvavB4mZvfqZnt/5CtPguoo3NLh6PJU=; b=u8hmPKYT7fvzpSHlZTbaVudiOODJC42ahyABcxxpK0rq/oI5nlqopFAaHbofMNoYlb LRhZr0jtRd5y9LF6/bTP8ioGxNneB3NXwV3VedpHUufATYHGqz4WLSOU14vV0sKzlcUl oAliFNz2tG93Cqz4l2+Z6oQQZ7Z0w8yO6Yvd1BZqfrf5e/mt/omrR+Pj1m7bmZlF2TEb bXgWyPp8zai08POShSZuFHWqQ4MyJiDX6I4lykslSou+keGkAKcEOHAqKEK/RxTzijUH hpGJABdiLNVJx5obEnnZSV5WLDe84cawha+uXF7b6x/ula3PnKQh4Dci2JWOMiIZ15Dm 7ReA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350524; x=1745955324; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ggbOR76BAcyXgvavB4mZvfqZnt/5CtPguoo3NLh6PJU=; b=MFP39QIocS3r8jLPtrPTy5OUM83jhAm0f3QAeQjLIQA/Fwo44wBdvtJQWKVinskG0K LGiMI3twC+rk9RuZ2NvBt4nhH3PgC1q9qXU8p8M2UN48/bPzBGwGvec9j1Q9XWZJKEBR UNM7GQllT3xbRFdN3XVo2g4sMA0bfhcwALzrMOKmnb3MZ2PXwLd0MjcoEzJPzAcEnZCW FILX4o3GkjDTY2zBKxQudk+Xg3C7GcwIxdYT0mByQW8lUX825443Eq+9sXO5vOKHuwU7 AvxQyHrjmI0nSPk08u2IgaqzQToCoKApZUBQ0qgb6Iz9kZocR3RklqWEXf9/dixaw4ze 62dw== X-Gm-Message-State: AOJu0YzV55uAzZB6XAA8qtEBLpDoqm1Cb0MBxSwfzRQ9J8X+q2sONAxC OsfELt/rOImbFsF2+Y9yd8Ungh5M+UxRFHICU8hiOuwelr6tTod/mOHojPNUvvndZL224+4yhga f X-Gm-Gg: ASbGncs6l6gW0P1+a7TnclUbAJ81y/XVBX19hYzSh3g3bpFAsJk5a73lE9Au7JC5Qlg 7NgLZDk/Rv51+As94PaBbK1wquqcrHuTF1+i7zs59TFH2LpZiS6y+Rv9dTNyjdAA/8d27d7BkUV D8r8JmAbuHHK1zpgXULrBjHXgN2TGRk3gBv2c8xfRnjOICGoXVpPy9A2edsAdPQviWz46VDOCU+ WSr7o609ae/NzPIHo0iQ/wo/iHZQor5RHIpzhm6Zo5LRv/rh99ozJew6e1vtaGsUGLCU8OYbuxW j8hY1TkOpHCGPWepuQPdcvs4myMl9PQy3/xhZH8OgGnApL5zKINY+8vinWAbDI9XQe5LZTr2OcY = X-Google-Smtp-Source: AGHT+IHQ5G/Uz3gsObG6PveHqWI147CwQFLiTqGfqBTYuOHqLAAHEQ4et/oHp3TnjcFHck56UV4HUw== X-Received: by 2002:a17:903:40cc:b0:223:39ae:a98 with SMTP id d9443c01a7336-22c53581510mr278314625ad.22.1745350524180; Tue, 22 Apr 2025 12:35:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 097/147] accel/tcg: Split out tlb-bounds.h Date: Tue, 22 Apr 2025 12:27:26 -0700 Message-ID: <20250422192819.302784-98-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350815371019000 The CPU_TLB_DYN_{MIN,MAX}_BITS definitions are not required outside of cputlb.c and translate-all.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tb-internal.h | 27 --------------------------- accel/tcg/tlb-bounds.h | 32 ++++++++++++++++++++++++++++++++ accel/tcg/cputlb.c | 1 + accel/tcg/translate-all.c | 1 + 4 files changed, 34 insertions(+), 27 deletions(-) create mode 100644 accel/tcg/tlb-bounds.h diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index f9a06bcbab..08538e2896 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -22,33 +22,6 @@ */ #define GETPC_ADJ 2 =20 -#ifdef CONFIG_SOFTMMU - -#define CPU_TLB_DYN_MIN_BITS 6 -#define CPU_TLB_DYN_DEFAULT_BITS 8 - -# if HOST_LONG_BITS =3D=3D 32 -/* Make sure we do not require a double-word shift for the TLB load */ -# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) -# else /* HOST_LONG_BITS =3D=3D 64 */ -/* - * Assuming TARGET_PAGE_BITS=3D=3D12, with 2**22 entries we can cover 2**(= 22+12) =3D=3D - * 2**34 =3D=3D 16G of address space. This is roughly what one would expec= t a - * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel - * Skylake's Level-2 STLB has 16 1G entries. - * Also, make sure we do not size the TLB past the guest's address space. - */ -# ifdef TARGET_PAGE_BITS_VARY -# define CPU_TLB_DYN_MAX_BITS \ - MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# else -# define CPU_TLB_DYN_MAX_BITS \ - MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) -# endif -# endif - -#endif /* CONFIG_SOFTMMU */ - void tb_lock_page0(tb_page_addr_t); =20 #ifdef CONFIG_USER_ONLY diff --git a/accel/tcg/tlb-bounds.h b/accel/tcg/tlb-bounds.h new file mode 100644 index 0000000000..efd34d4793 --- /dev/null +++ b/accel/tcg/tlb-bounds.h @@ -0,0 +1,32 @@ +/* + * softmmu size bounds + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_TLB_BOUNDS_H +#define ACCEL_TCG_TLB_BOUNDS_H + +#define CPU_TLB_DYN_MIN_BITS 6 +#define CPU_TLB_DYN_DEFAULT_BITS 8 + +# if HOST_LONG_BITS =3D=3D 32 +/* Make sure we do not require a double-word shift for the TLB load */ +# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) +# else /* HOST_LONG_BITS =3D=3D 64 */ +/* + * Assuming TARGET_PAGE_BITS=3D=3D12, with 2**22 entries we can cover 2**(= 22+12) =3D=3D + * 2**34 =3D=3D 16G of address space. This is roughly what one would expec= t a + * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel + * Skylake's Level-2 STLB has 16 1G entries. + * Also, make sure we do not size the TLB past the guest's address space. + */ +# ifdef TARGET_PAGE_BITS_VARY +# define CPU_TLB_DYN_MAX_BITS \ + MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) +# else +# define CPU_TLB_DYN_MAX_BITS \ + MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) +# endif +# endif + +#endif /* ACCEL_TCG_TLB_BOUNDS_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 28c47d4872..a717f357d5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -41,6 +41,7 @@ #include "trace.h" #include "tb-hash.h" #include "tb-internal.h" +#include "tlb-bounds.h" #include "internal-common.h" #include "internal-target.h" #ifdef CONFIG_PLUGIN diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bb161ae61a..87fb6c51d3 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -47,6 +47,7 @@ #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "tb-internal.h" +#include "tlb-bounds.h" #include "exec/translator.h" #include "exec/tb-flush.h" #include "qemu/bitmap.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350920; cv=none; d=zohomail.com; s=zohoarc; b=JlcZohgqSFQK+CnjKQ4xEu6VmjULDMOwoJ0TMA1KLCfhJ1pvtP7XIetnWUMYjy7vll4APYRLtiNtYVcvjFUHqF41iIeUz7g90DSdX+qdn9wIsx1Hl9Rj7dqciqnWL9eWvojbure9v/lCcEgMiK9T+eExFZ5rDvhwqADJSNcjmXs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350920; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=F+jTPRxzefHutS8rakDU7HuiolaxKbTM9MImwBgIvjk=; b=VB5lm+P0BkO+jicO1qSbh1cMZaKkNuKcCIy44H4FZfXXF5Xd6AQlVPv1LP/iSEuhmOkrqTIiYOscjc3Mi6yDQyyW9GnFJ3PhnU1cVtCIoFT+gODbxZ1HhjSGRcmBxyQuV6f1qdJEk2eStyiB8AnCvGMkoIArJhob0P/f/XNL8LE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350920665399.031134900383; Tue, 22 Apr 2025 12:42:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JQc-0000S1-NC; Tue, 22 Apr 2025 15:37:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOy-0005AO-LU for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:31 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOw-000744-5C for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:28 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-223fd89d036so69454475ad.1 for ; Tue, 22 Apr 2025 12:35:25 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350525; x=1745955325; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F+jTPRxzefHutS8rakDU7HuiolaxKbTM9MImwBgIvjk=; b=qjxfzInsVCRSEyrhhf0fZx+hXJg4VP6RVkVJbQ6+DtEziTQNwCpatSEdZfNmtu1+cy 6rY0Fz3UxA1BsE42ddzkj6iqx9WRA4de3i2ZI1O9PQ4UgakD8vEbYiyMNLNkF5Qvmq5C WItH1pfWXvC0c3yJrX35lChBPVMfllcys590TpEDASSRtFyYpzmemawpA5S8VYGKCLRl v4p3x4j7Z9LLIPK3yMRmo7N55rejfN5pHiybYjExaMwJx0ctJ/5ERCvljSJriUf/NJgk bnyKi/ajxo89FO9rLXchEgVLWzTWOuCfv9eLL2VNK4FY+7m6hKZk1m+0GFKQJM/6gwBT Z0Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350525; x=1745955325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F+jTPRxzefHutS8rakDU7HuiolaxKbTM9MImwBgIvjk=; b=H/4rdhXMlt6b0ux1jrXq2E+TcRSs3tzjk7GUNF9JT8nCbMbnWlqYpR3n7hbnhOqUXl pBoICZv1+zPh3NilbHsxe8vW4r7peJ+hRpY1XmVL4cYj3aWh0kACHLHpS607UjQPetU0 odnSXXydnsvs6tJaUYN0R9CDpEorlJn7B3faWJ5G04cQsDdbFBR+555Y0hasgg3IV4m5 JrSQfDzs+2aT6yr0u2Wa3YeTgEhQr2JZ5s7lOVmR/FfoyBKPy1QfJJ+sDbj2Qi/smHBx QHfzvbMzc8FSQWzLKG3q79e3dRZ0h8DuMI4t05P4egakwQnIx87W3J+3arQLiaLdOcwG cX3Q== X-Gm-Message-State: AOJu0YxuJNO/8awk1dPnf+jhxFv5Jjvk4WrXhPJzIDqGniGEMj/lfqhU jaeCiy6OBilSCSrsI0YhuRVsdI0rprf9JUrMBe2M4ptkyIZWU6BtCl0eaV1YBUPW+P4YxbFj3VL a X-Gm-Gg: ASbGnctweIHgNJufIqG3axqqgH4h29U4u8f1s/+5IJI1R/PlHQJsQoRgZKLM9UBebv1 o9hAsxKOtAItRJTxE2NUnuKslJWeDMK4HXfefXYBPZtrpbYfHn7OoKsljHwv4+Pzi6snb2J2eW8 qNEUb5GcswlRMr7NZ/XBnlpSn2MPNim00ichkx/A0XXicPl5Hhk7XWoJfHkh5lZHxAt/tDmiJVy wkiTrmoWWBQSiJH05JT1u1TTWOUwK4yGPsjWXMGFUPJvHD5vg82IB02SgZf/r0Vr26JSQgMpE4x F/6uZcS4A6KkPhib646dLAmwzTpAtaeOBq6W9c/dBMYdIoEME8RvvPtmLFhmKeOGqobbDTwxkjk = X-Google-Smtp-Source: AGHT+IHNQAIqC/9clq17SVx904+csE/jL0cA+lGCrwDPaPh4vKO1sgGSBAK9cpmroGLrDMmtKzuv9g== X-Received: by 2002:a17:902:cf0d:b0:21f:2a2:3c8b with SMTP id d9443c01a7336-22c5337ce31mr257595055ad.11.1745350524788; Tue, 22 Apr 2025 12:35:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 098/147] include/exec: Redefine tlb-flags with absolute values Date: Tue, 22 Apr 2025 12:27:27 -0700 Message-ID: <20250422192819.302784-99-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350922455019100 Content-Type: text/plain; charset="utf-8" Don't base the values on TARGET_PAGE_BITS_MIN, but do verify that TLB_FLAGS_MASK does not overlap minimum page size. All targets now have the same placement for these flags, simplifying mmu management when we enable heterogenus systems. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/tlb-flags.h | 68 +++++++++++++++++++--------------------- accel/tcg/cputlb.c | 2 ++ 2 files changed, 34 insertions(+), 36 deletions(-) diff --git a/include/exec/tlb-flags.h b/include/exec/tlb-flags.h index 54a6bae768..357e79095c 100644 --- a/include/exec/tlb-flags.h +++ b/include/exec/tlb-flags.h @@ -19,54 +19,29 @@ #ifndef TLB_FLAGS_H #define TLB_FLAGS_H =20 -#include "exec/cpu-defs.h" +/* + * Flags returned for lookup of a TLB virtual address. + */ =20 #ifdef CONFIG_USER_ONLY =20 /* - * Allow some level of source compatibility with softmmu. We do not - * support any of the more exotic features, so only invalid pages may - * be signaled by probe_access_flags(). + * Allow some level of source compatibility with softmmu. + * Invalid is set when the page does not have requested permissions. + * MMIO is set when we want the target helper to use the functional + * interface for load/store so that plugins see the access. */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) -#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) -#define TLB_WATCHPOINT 0 +#define TLB_INVALID_MASK (1 << 0) +#define TLB_MMIO (1 << 1) +#define TLB_WATCHPOINT 0 =20 #else =20 -/* - * Flags stored in the low bits of the TLB virtual address. - * These are defined so that fast path ram access is all zeros. - * The flags all must be between TARGET_PAGE_BITS and - * maximum address alignment bit. - * - * Use TARGET_PAGE_BITS_MIN so that these bits are constant - * when TARGET_PAGE_BITS_VARY is in effect. - * - * The count, if not the placement of these bits is known - * to tcg/tcg-op-ldst.c, check_max_alignment(). - */ -/* Zero if TLB entry is valid. */ -#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) -/* - * Set if TLB entry references a clean RAM page. The iotlb entry will - * contain the page physical address. - */ -#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) -/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ -#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 3)) - -/* - * Use this mask to check interception with an alignment mask - * in a TCG backend. - */ -#define TLB_FLAGS_MASK \ - (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_FORCE_SLOW) - /* * Flags stored in CPUTLBEntryFull.slow_flags[x]. * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. */ + /* Set if TLB entry requires byte swap. */ #define TLB_BSWAP (1 << 0) /* Set if TLB entry contains a watchpoint. */ @@ -82,6 +57,27 @@ (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED | \ TLB_DISCARD_WRITE | TLB_MMIO) =20 +/* + * Flags stored in CPUTLBEntry.addr_idx[x]. + * These must be above the largest alignment (64 bytes), + * and below the smallest page size (1024 bytes). + * This leaves bits [9:6] available for use. + */ + +/* Zero if TLB entry is valid. */ +#define TLB_INVALID_MASK (1 << 6) +/* Set if TLB entry references a clean RAM page. */ +#define TLB_NOTDIRTY (1 << 7) +/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ +#define TLB_FORCE_SLOW (1 << 8) + +/* + * Use this mask to check interception with an alignment mask + * in a TCG backend. + */ +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_FORCE_SLOW) + /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a717f357d5..39314e86f3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -49,6 +49,8 @@ #endif #include "tcg/tcg-ldst.h" =20 +QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & ((1u < TARGET_PAGE_BITS_MIN) - 1)); + /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ /* #define DEBUG_TLB_LOG */ --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352794; cv=none; d=zohomail.com; s=zohoarc; b=eXxvj77Ppnn/GDREtajSd+yCg9L5nOuivipG7l7jyF8lbru7R4+W4ggRZnJjxfZ1BVxoEYRrOYJ1Bbcj/TDKHWmMghrHEFwGcoCHEDyoJj5/yjx63tm4LN1m8Hlth9PWOUFrYLDrk9zfpUD0eMEhomBCbsfkAfxz8/0EQLoqSUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352794; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2WoakTEoTh5W+Edqv/m7cqa7TN4j7HTie5YrJRYbIMU=; b=BaNbfIPX8Xm+2vyZV7B7e0vzJwEUrr3nN0KMgWwH+Xp7nd2eOC5FV8tqX9UVuPheslM3V3PsiNTDBcQW5JUDZ44nqIJJ2uRbX14LREtzAHLr/sqkFv5VoqYbNCrGH9q9RY6couC1Kil+vAdSMN4b7IRHLa9ZqKx2zVcFb7IKMQI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352794881823.9445242095513; Tue, 22 Apr 2025 13:13:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JPZ-0006eB-BD; Tue, 22 Apr 2025 15:36:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JOy-0005AQ-Oa for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:31 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOw-00074O-MZ for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:28 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-22438c356c8so59119215ad.1 for ; Tue, 22 Apr 2025 12:35:26 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350525; x=1745955325; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2WoakTEoTh5W+Edqv/m7cqa7TN4j7HTie5YrJRYbIMU=; b=CX+RGNphhqJ8AHWCwBqGlOhZ1suuubvGlDYDLZu5NjwfdOWDownPUc2JScikSfCn/K Ezbi8TKR/PZnrS2fDpX3XZjHD1YFnurBXzqJQsS8QARYJHIZYmKH/ymy8DBbw+CaoOD2 OGdySFlv4+WmTAVgVxPhvjsmNljYrk25EuYc1rKQjcY7CqTczqd71I4ePQleLlfCLiIT KtLWtBMbubLvoEiA7O7Bkdp4IT97olrB/RRLAYGco5qfZoXmluFJuH9+67r7YR0U2Wdz AvP8ilCcPcgOxJ3FsfiRI+YWuuMOrLuNm+/QBQIQNtxgJZw7dsX2WQpeQb8RjKs65xrb l34Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350525; x=1745955325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2WoakTEoTh5W+Edqv/m7cqa7TN4j7HTie5YrJRYbIMU=; b=sa1nJHCU8fZlp11/dIzFtbHsHMruvbLoIZ855e9E8V80dusHzIJHuzjcltOLtxujCu Ucg2/rPCp/H92mgyzY9f3MBbZSGxtoaAI0wUsCtLpSOayKyO/I2LM7yxSK4DPoQgu2RG fHR7blkx4CBEpRhSVwAvMPHXt512bhp1Qdx6NuFqj6b0/ACFPxNfG0j41s+XKRZAv8Se MqUzZFfmTF2XY26zC8bxWbbXME/t/b9XSQgMK3jfGkBQJBMTD1vvWEQyqYsXrj7ShWvp rex71XLfIHGYH3Xl8jXJFhLxmIUYQO0+ZtJRrqrnkknG64qspZAgYMTVqLdms30NNMuG 1tew== X-Gm-Message-State: AOJu0YwExeeN17RP0CSAiWkubW+PfYB/uX4YsUMRAtOYbZHcR3Sb/r97 67n6fBAIdpCsAxr+oXCzCICySlde4NIyA8Szh1aNXQ7WHS1p1B2Ywoi/XFD7JodBDkUhTdfboiN C X-Gm-Gg: ASbGnctNvsiQy70DJCt9OLLelCyCB6qvE/4a6Qzjl9yU6mxEKUXooXBfh/mvmBQvrQY q0e2ZaKGKpj8UAzg8f5dXxO+5L+9R1OfwhXmhhhKdlofqxV91dVvJsW6RR1NUdTlVOr2fSJBbfF FP0ccoODwm1l/jd8uhE+rXQARulcPVBQ1GW/DLOGjeo2wHXS/iByYg7hS0yIW38OGPrjHseDsnw 0gWywyjcB53VrKhOg7slMym7NQl/MeCwfHL7q4oAlb1kLkAoHFHhtklpNmGRWE2PB1MNZtga8Z6 9UNQpo5/Fc/Qb+OK5O+S3ePbr+OHQIHoXCjn/7P0PmpLM+u8wtPmuIRJF2cTs+gUxjKtXyV9Ie0 = X-Google-Smtp-Source: AGHT+IHiq5c+Jgc1MaQGq2iVWsxlcznD0hNaGcc9YATWMePpBp6h5ERo/3Ie8NGm4tvoEE+RCzaYuA== X-Received: by 2002:a17:902:dac5:b0:224:826:279e with SMTP id d9443c01a7336-22c53630377mr225992365ad.50.1745350525406; Tue, 22 Apr 2025 12:35:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 099/147] page-vary: Move and rename qemu_target_page_bits_min Date: Tue, 22 Apr 2025 12:27:28 -0700 Message-ID: <20250422192819.302784-100-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352796012019000 Content-Type: text/plain; charset="utf-8" Rename to migration_legacy_page_bits, to make it clear that we cannot change the value without causing a migration break. Move to page-vary.h and page-vary-target.c. Define via TARGET_PAGE_BITS if not TARGET_PAGE_BITS_VARY. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/page-vary.h | 9 +++++++++ include/exec/target_page.h | 1 - migration/savevm.c | 6 +++--- page-target.c | 5 ----- page-vary-target.c | 9 +++++++++ 5 files changed, 21 insertions(+), 9 deletions(-) diff --git a/include/exec/page-vary.h b/include/exec/page-vary.h index 54ddde308a..101c25911c 100644 --- a/include/exec/page-vary.h +++ b/include/exec/page-vary.h @@ -49,4 +49,13 @@ bool set_preferred_target_page_bits(int bits); */ void finalize_target_page_bits(void); =20 +/** + * migration_legacy_page_bits + * + * For migration compatibility with qemu v2.9, prior to the introduction + * of the configuration/target-page-bits section, return the value of + * TARGET_PAGE_BITS that the target had then. + */ +int migration_legacy_page_bits(void); + #endif /* EXEC_PAGE_VARY_H */ diff --git a/include/exec/target_page.h b/include/exec/target_page.h index 8e89e5cbe6..e4bd7f7767 100644 --- a/include/exec/target_page.h +++ b/include/exec/target_page.h @@ -63,7 +63,6 @@ static inline int qemu_target_page_bits(void) return TARGET_PAGE_BITS; } =20 -int qemu_target_page_bits_min(void); size_t qemu_target_pages_to_MiB(size_t pages); =20 #endif diff --git a/migration/savevm.c b/migration/savevm.c index c33200a33f..0c12e373b4 100644 --- a/migration/savevm.c +++ b/migration/savevm.c @@ -50,6 +50,7 @@ #include "system/cpus.h" #include "system/memory.h" #include "exec/target_page.h" +#include "exec/page-vary.h" #include "trace.h" #include "qemu/iov.h" #include "qemu/job.h" @@ -339,7 +340,7 @@ static int configuration_pre_load(void *opaque) * predates the variable-target-page-bits support and is using the * minimum possible value for this CPU. */ - state->target_page_bits =3D qemu_target_page_bits_min(); + state->target_page_bits =3D migration_legacy_page_bits(); return 0; } =20 @@ -462,8 +463,7 @@ static const VMStateInfo vmstate_info_capability =3D { */ static bool vmstate_target_page_bits_needed(void *opaque) { - return qemu_target_page_bits() - > qemu_target_page_bits_min(); + return qemu_target_page_bits() > migration_legacy_page_bits(); } =20 static const VMStateDescription vmstate_target_page_bits =3D { diff --git a/page-target.c b/page-target.c index 321e43d06f..8fcd5443b5 100644 --- a/page-target.c +++ b/page-target.c @@ -9,11 +9,6 @@ #include "qemu/osdep.h" #include "exec/target_page.h" =20 -int qemu_target_page_bits_min(void) -{ - return TARGET_PAGE_BITS_MIN; -} - /* Convert target pages to MiB (2**20). */ size_t qemu_target_pages_to_MiB(size_t pages) { diff --git a/page-vary-target.c b/page-vary-target.c index 84ddeb7c26..6251d948cf 100644 --- a/page-vary-target.c +++ b/page-vary-target.c @@ -23,6 +23,15 @@ #include "exec/page-vary.h" #include "exec/target_page.h" =20 +int migration_legacy_page_bits(void) +{ +#ifdef TARGET_PAGE_BITS_VARY + return TARGET_PAGE_BITS_MIN; +#else + return TARGET_PAGE_BITS; +#endif +} + bool set_preferred_target_page_bits(int bits) { #ifdef TARGET_PAGE_BITS_VARY --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350526; x=1745955326; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XyKtevNAmC2eZUOXDG2VlAgB8+znbswT4cFJTBgj39o=; b=bZJFr79w4boekFPjMKLY2mvuyr+RjISeO/Drdn+Hu/pe+9U3o0t5Ref/5ZRAfCBC1E WsPamYgkzgadMIwec+Bl4t8DhEnwX0S4CGxasB5GMiTHkUQOnuXXymYTj7LufMb5JRgj UPgMqoy4S3qvb0f3X6593XAnSJmE7flm19jH9yn5cNXYF1PPz39n1GWa27brjuSKPErL 2dCvkZtP9LngHCt1D1KwE9eKQudLzIP0/eaH1hvmuEOAnHA8UFp+z2RnMIv0pgRvfKvA SPKY7YgXn1ol2bsEZ0VaBas6qJweXirtpB0OA436x4sg2ik22U6LBjYI9/v+WmVoZOUd +q+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350526; x=1745955326; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XyKtevNAmC2eZUOXDG2VlAgB8+znbswT4cFJTBgj39o=; b=MAr0njnGuSIlAVEBTJoVxGPAGQ3H3lerFGrPAl9YxaWKzuDBQr6f6pLFyBgwCyxLyk agJ4SKD4vYjxdUkmZKJ8vJhHGpXIfLibS1t/rGI+6BYPGjwPUCOAz+6svtvHWlyqQ/Wy 7EowIfwAwCzkiRPGZFHqfdtU6LiJKOpUR3X+yBachBQw/UYFAFHcLbS9UOvZ9aARss5X hXz2E76C9F8dKOsCsY+vSHhZNtfjtsddU7wYesiYaT/blVWEfjhQrkl2+VmCQs9nVkcb hHai0Mk968EG/QrLhFo0JlJ8lsM7Er3ve7f9A7AYFpS1b4ivmP8AH24KeQzrZDJhfHL6 Ankg== X-Gm-Message-State: AOJu0YwKN1ErujXlDBu0KvZAHH7HFtdMVlQvHCCMz5LCym3ZCGpd+/h6 KnOWDns994GuseRXoLmESklt46toOjxpGApovLY+6+BqJbqu+n/qBVykOI1e0WAknZjVL8tnm84 n X-Gm-Gg: ASbGncuGZpEDixW6OYm0V3462VbT7Wdy81o75otZcv3o25wvBtjuDPLoIT5qiI33iXu FlLkzk+ir5v5pk0/oOuB1ByeK0Vog0SX2Hhj3VdAs2doOYYKpRPh4ExXPUAACtSzW+mqUuOMXap xmcEIBqiE6mZBJZGPbpB4RGi4K/b36iV28136Xcv1Lww9eYW4BbBqwkjc7XJnJ9CNLBtraZNNes DyX7uz2Lxz1AcDkgjyoJSsln1RChOfL5xQN7PdgcwDWXETPwKDNT3ddlANsAEVV6vUNUijsIG9H enbeT1l/oTPL5m8pH9rt95DKyzCHfh7ytDnPNH4OF9+IjupS61kekWJqeTFbY27rYh691xPA5D8 = X-Google-Smtp-Source: AGHT+IFJ54L200hTGpkePGGV3r7BnF6R8RDsNMcgyQGtv82Q3FKUD0UOQN1VjGrrDU4m0OQnFh2tCA== X-Received: by 2002:a17:903:2410:b0:220:be86:a421 with SMTP id d9443c01a7336-22c536050f6mr274854035ad.38.1745350526017; Tue, 22 Apr 2025 12:35:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 100/147] page-vary: Restrict scope of TARGET_PAGE_BITS_MIN Date: Tue, 22 Apr 2025 12:27:29 -0700 Message-ID: <20250422192819.302784-101-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352780417019100 Content-Type: text/plain; charset="utf-8" The only place we really need to know the minimum is within page-vary-target.c. Rename the target/arm TARGET_PAGE_BITS_MIN to TARGET_PAGE_BITS_LEGACY to emphasize what it really means. Move the assertions related to minimum page size as well. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 10 ++-------- include/exec/target_page.h | 1 - target/alpha/cpu-param.h | 1 - target/arm/cpu-param.h | 3 +-- target/ppc/cpu-param.h | 1 - accel/tcg/cputlb.c | 1 - page-vary-target.c | 39 +++++++++++++++++++++++++++++++++++--- 7 files changed, 39 insertions(+), 17 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 9f955f53fd..e01acb7c90 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -34,14 +34,8 @@ #ifndef TARGET_VIRT_ADDR_SPACE_BITS # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h #endif -#ifndef TARGET_PAGE_BITS -# ifdef TARGET_PAGE_BITS_VARY -# ifndef TARGET_PAGE_BITS_MIN -# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h -# endif -# else -# error TARGET_PAGE_BITS must be defined in cpu-param.h -# endif +#if !defined(TARGET_PAGE_BITS) && !defined(TARGET_PAGE_BITS_VARY) +# error TARGET_PAGE_BITS must be defined in cpu-param.h #endif =20 #include "exec/target_long.h" diff --git a/include/exec/target_page.h b/include/exec/target_page.h index e4bd7f7767..ca0ebbc8bb 100644 --- a/include/exec/target_page.h +++ b/include/exec/target_page.h @@ -41,7 +41,6 @@ extern const TargetPageBits target_page; # endif # define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) #else -# define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS # define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) # define TARGET_PAGE_MASK ((TARGET_PAGE_TYPE)-1 << TARGET_PAGE_BITS) #endif diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index ff06e41497..63989e71c0 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -18,7 +18,6 @@ * a 4k minimum to match x86 host, which can minimize emulation issues. */ # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 12 # define TARGET_VIRT_ADDR_SPACE_BITS 63 #else # define TARGET_PAGE_BITS 13 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 896b35bd6d..a7ae42d17d 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -24,7 +24,6 @@ # else /* Allow user-only to vary page size from 4k */ # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 12 # endif # else # define TARGET_PAGE_BITS 12 @@ -35,7 +34,7 @@ * have to support 1K tiny pages. */ # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 10 +# define TARGET_PAGE_BITS_LEGACY 10 #endif /* !CONFIG_USER_ONLY */ =20 /* ARM processors have a weak memory model */ diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 6c4525fdf3..553ad2f4c6 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -33,7 +33,6 @@ #ifdef CONFIG_USER_ONLY /* Allow user-only to vary page size from 4k */ # define TARGET_PAGE_BITS_VARY -# define TARGET_PAGE_BITS_MIN 12 #else # define TARGET_PAGE_BITS 12 #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 39314e86f3..0de46903dd 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -49,7 +49,6 @@ #endif #include "tcg/tcg-ldst.h" =20 -QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & ((1u < TARGET_PAGE_BITS_MIN) - 1)); =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ diff --git a/page-vary-target.c b/page-vary-target.c index 6251d948cf..49a32b4fe5 100644 --- a/page-vary-target.c +++ b/page-vary-target.c @@ -23,19 +23,45 @@ #include "exec/page-vary.h" #include "exec/target_page.h" =20 + +/* + * For system mode, the minimum comes from the number of bits + * required for maximum alignment (6) and the number of bits + * required for TLB_FLAGS_MASK (3). + * + * For user mode, TARGET_PAGE_BITS_VARY is a hack to allow the target + * page size to match the host page size. Mostly, this reduces the + * ordinary target page size to run on a host with 4KiB pages (i.e. x86). + * There is no true minimum required by the implementation, but keep the + * same minimum as for system mode for sanity. + * See linux-user/mmap.c, mmap_h_lt_g and mmap_h_gt_g. + */ +#define TARGET_PAGE_BITS_MIN 9 + +#ifndef TARGET_PAGE_BITS_VARY +QEMU_BUILD_BUG_ON(TARGET_PAGE_BITS < TARGET_PAGE_BITS_MIN); +#endif + +#ifndef CONFIG_USER_ONLY +#include "exec/tlb-flags.h" + +QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & ((1u < TARGET_PAGE_BITS_MIN) - 1)); + int migration_legacy_page_bits(void) { #ifdef TARGET_PAGE_BITS_VARY - return TARGET_PAGE_BITS_MIN; + QEMU_BUILD_BUG_ON(TARGET_PAGE_BITS_LEGACY < TARGET_PAGE_BITS_MIN); + return TARGET_PAGE_BITS_LEGACY; #else return TARGET_PAGE_BITS; #endif } +#endif =20 bool set_preferred_target_page_bits(int bits) { -#ifdef TARGET_PAGE_BITS_VARY assert(bits >=3D TARGET_PAGE_BITS_MIN); +#ifdef TARGET_PAGE_BITS_VARY return set_preferred_target_page_bits_common(bits); #else return true; @@ -44,5 +70,12 @@ bool set_preferred_target_page_bits(int bits) =20 void finalize_target_page_bits(void) { - finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN); +#ifndef TARGET_PAGE_BITS_VARY + finalize_target_page_bits_common(TARGET_PAGE_BITS); +#elif defined(CONFIG_USER_ONLY) + assert(target_page.bits !=3D 0); + finalize_target_page_bits_common(target_page.bits); +#else + finalize_target_page_bits_common(TARGET_PAGE_BITS_LEGACY); +#endif } --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351949; cv=none; d=zohomail.com; s=zohoarc; b=PnIkLySSCUSYeC+0fTn1Nt47e5ixcpoO7CB3+yTdPTB+qkYURNKaBsWSxIGIxmLBy/Il4XLRuvDUaL1B4Gs613xBlSKPXMEQ4Uat4JnEwmmzjICL5W0ncw1Y/XuVXDux93gf9PIoEBNcSDyQiTm5kYt0N8ZbX2EPGoF53yOEb4s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351949; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Uk2ZrawXZYiOMoISYC3G3yGzQ++x7vjYflwSfXkzRVo=; b=D/x0ZyLTkh/bufh2SX5jrjqy1Yj7v+um1ebsjaSvYx2VNBPDqvHROdgjMnDKrd74UuzeXiC8mpDshxE1tAOuRtNncEUzeCi3Gfqrc7ntDbZ2QN8xuqAbSJ/8gV8ei0VqY+50fg+h3mU/5XC8tfXhI2WGv7miAUkGrUETstRgBkE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351949680191.96793375849245; Tue, 22 Apr 2025 12:59:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JRU-0002AJ-9Y; Tue, 22 Apr 2025 15:38:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JP1-0005B3-DK for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:31 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JOy-00074f-Ho for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:30 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2255003f4c6so63588525ad.0 for ; Tue, 22 Apr 2025 12:35:27 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350526; x=1745955326; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Uk2ZrawXZYiOMoISYC3G3yGzQ++x7vjYflwSfXkzRVo=; b=ALi5vwPqYr3cHuZKemP9+QGASB/90ShuMYUGXn2YswkM2FPoo1z2z2fw71pXGPlzza Wd4BuFQrsKTuDKES78x3jrI0zq6vEDrtvpmn2qc+CinKikgjny7wySoFWzakMoV7mAWp KQBplEl0BybX8PeoR7mPwIuid8pdUYxgV5CC2fA5xLuXoMVbNw3lzGw5d8YinIUriS84 BrDCR8rJY+sVw4zFbxxCD0aWXVKCthkxraOqy94leW4P8I850BGD3vOo3/mZu+oaqUOZ m5R1YJV7ehzS7hI4ewPfewacvqox82Ijf6w0LloVF8Q5DgGO577rZtsMl/rlJs8654TW rkbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350526; x=1745955326; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uk2ZrawXZYiOMoISYC3G3yGzQ++x7vjYflwSfXkzRVo=; b=LqW9PbTq5++8vOwOQfvqsQOJxWOCO5FKlT9nCYAKIPq33PuhADxoD7+wVm+e8JtyHq leGN2ZJkjAzXBKWk+u5pz3CkHzcELHZ74YUjLxTWylngBL0SudcCjNwc+14bPnzmw4mZ cakYPh793AUYAQQGyMIgNUQZBZb+Dlm+RBnNL3IdYMo+euS2dZlmG+Nf8ZLG8JTgItCP +7d5km+8OEka0Luau17FgYlonYC09X26fCOI0kv7dpbFmeggO2zzx3329+aAus5xjJYn fn4mHn7h42x6KJjYd7OUdtp8zbnP+3WrcJp6Ui2fBM8DZn/Aju9bKMRy+CN9zx4IQlZV qbzQ== X-Gm-Message-State: AOJu0YwtIewePReSkCjJ10WS70QqqJoGQqXblsUMWqatH/AFD8VWO876 suxQp9lxxTaFiVmLFRHd/5asRL+athwp5cBW5QmyjEX0ik5Z5ukW3TncUz/SKINDC0Thkm037FP b X-Gm-Gg: ASbGncuA4r5xM0W+wXXW4NkWL4vR+hH0aej9Rr7+MycYFUFw/bPSLrPpmJLKL6mOxJ4 jYRKA7q44QnWqLVSZVvyLcyVbLoKOBnQzA3Xch9kwjQqcG6woyxUIVJyKQaQkYZ6uik2y4y10P0 itO7oyJcZVJKHzqSHfhtySeWhmwiDbXuKFrLboe7HAJ2Upi1fPTqMG/uP7LimE6+p9j6a3kJe/i GJWAvDQiUm/1n5CvRaE1PB7Iuo6SUt9+K3yLr6+bRYEAe67szFGFqCWVZtecJeuaztl6ClgRnZN UDVZ6EiNH3XBYNwYEYiLePvhnYPI6pxH2fhlLbF1utKoK8C9qbR3ZED0cxHPdgkNsIoTxvniAsU = X-Google-Smtp-Source: AGHT+IH7WMAJRlPRMEw/0aNBxQE02SPMnBWKDXOONk2f7iOo9BnqdHywyjXGKM4UGS4n54APAsk2Hg== X-Received: by 2002:a17:903:947:b0:223:517c:bfa1 with SMTP id d9443c01a7336-22c5360c7admr276939285ad.38.1745350526622; Tue, 22 Apr 2025 12:35:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 101/147] exec/cpu-all: move cpu_copy to linux-user/qemu.h Date: Tue, 22 Apr 2025 12:27:30 -0700 Message-ID: <20250422192819.302784-102-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351950479019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-3-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 2 -- linux-user/qemu.h | 3 +++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5c4379f0d0..2aaaf0548d 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -31,8 +31,6 @@ #endif =20 =20 -CPUArchState *cpu_copy(CPUArchState *env); - #include "cpu.h" =20 /* Validate correct placement of CPUArchState. */ diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 5f00750151..948de8431a 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -362,4 +362,7 @@ void *lock_user_string(abi_ulong guest_addr); #define unlock_user_struct(host_ptr, guest_addr, copy) \ unlock_user(host_ptr, guest_addr, (copy) ? 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Tue, 22 Apr 2025 12:35:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 102/147] include/exec/cpu-all: move compile time check for CPUArchState to cpu-target.c Date: Tue, 22 Apr 2025 12:27:31 -0700 Message-ID: <20250422192819.302784-103-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352328347019000 From: Pierrick Bouvier Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-4-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 4 ---- cpu-target.c | 5 +++++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 2aaaf0548d..be462c4410 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -33,8 +33,4 @@ =20 #include "cpu.h" =20 -/* Validate correct placement of CPUArchState. */ -QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) !=3D 0); -QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) !=3D sizeof(CPUState)); - #endif /* CPU_ALL_H */ diff --git a/cpu-target.c b/cpu-target.c index 519b0f8900..7f3b244ed1 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" @@ -29,6 +30,10 @@ #include "accel/accel-cpu-target.h" #include "trace/trace-root.h" =20 +/* Validate correct placement of CPUArchState. */ +QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) !=3D 0); +QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) !=3D sizeof(CPUState)); + char *cpu_model_from_type(const char *typename) { const char *suffix =3D "-" CPU_RESOLVING_TYPE; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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When includes set already have ifdef CONFIG_USER_ONLY, we add it here, else, we don't condition the include. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-5-pierrick.bouvier@linaro.org> --- hw/s390x/ipl.h | 1 + include/exec/cpu-all.h | 5 ----- target/arm/internals.h | 1 + target/hppa/cpu.h | 1 + target/i386/hvf/vmx.h | 1 + target/ppc/mmu-hash32.h | 2 ++ hw/ppc/spapr_ovec.c | 1 + target/alpha/helper.c | 1 + target/arm/hvf/hvf.c | 1 + target/i386/arch_memory_mapping.c | 1 + target/i386/helper.c | 1 + target/i386/tcg/system/misc_helper.c | 1 + target/i386/tcg/system/tcg-cpu.c | 1 + target/m68k/helper.c | 1 + target/ppc/excp_helper.c | 1 + target/ppc/mmu-book3s-v3.c | 1 + target/ppc/mmu-hash64.c | 1 + target/ppc/mmu-radix64.c | 1 + target/riscv/cpu_helper.c | 1 + target/sparc/ldst_helper.c | 1 + target/sparc/mmu_helper.c | 1 + target/xtensa/mmu_helper.c | 1 + target/xtensa/op_helper.c | 1 + 23 files changed, 23 insertions(+), 5 deletions(-) diff --git a/hw/s390x/ipl.h b/hw/s390x/ipl.h index c6ecb3433c..6557ac3be5 100644 --- a/hw/s390x/ipl.h +++ b/hw/s390x/ipl.h @@ -15,6 +15,7 @@ =20 #include "cpu.h" #include "system/address-spaces.h" +#include "system/memory.h" #include "hw/qdev-core.h" #include "hw/s390x/ipl/qipl.h" #include "qom/object.h" diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index be462c4410..399fcbb9d1 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -26,11 +26,6 @@ #include "hw/core/cpu.h" #include "exec/cpu-defs.h" #include "exec/target_page.h" -#ifndef CONFIG_USER_ONLY -#include "system/memory.h" -#endif - - #include "cpu.h" =20 #endif /* CPU_ALL_H */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 8756c24c08..01408e40a3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -28,6 +28,7 @@ #include "exec/breakpoint.h" #include "hw/registerfields.h" #include "tcg/tcg-gvec-desc.h" +#include "system/memory.h" #include "syndrome.h" #include "cpu-features.h" =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 8b36642b59..f6bf068776 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "system/memory.h" #include "qemu/cpu-float.h" #include "qemu/interval-tree.h" #include "hw/registerfields.h" diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index 87a478f7fd..3ddf7982ff 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -34,6 +34,7 @@ #include "system/hvf_int.h" =20 #include "system/address-spaces.h" +#include "system/memory.h" =20 static inline uint64_t rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg) { diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index 2838de031c..04c23ea75e 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -3,6 +3,8 @@ =20 #ifndef CONFIG_USER_ONLY =20 +#include "system/memory.h" + bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_t= ype, hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, bool guest_visible); diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_ovec.c index 6d6eaf67cb..75ab4fe262 100644 --- a/hw/ppc/spapr_ovec.c +++ b/hw/ppc/spapr_ovec.c @@ -16,6 +16,7 @@ #include "migration/vmstate.h" #include "qemu/bitmap.h" #include "system/address-spaces.h" +#include "system/memory.h" #include "qemu/error-report.h" #include "trace.h" #include diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 57cefcba14..f6261a3a53 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -25,6 +25,7 @@ #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" +#include "system/memory.h" =20 =20 #define CONVERT_BIT(X, SRC, DST) \ diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 93a3f9b53d..34ca36fab5 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -23,6 +23,7 @@ #include =20 #include "system/address-spaces.h" +#include "system/memory.h" #include "hw/boards.h" #include "hw/irq.h" #include "qemu/main-loop.h" diff --git a/target/i386/arch_memory_mapping.c b/target/i386/arch_memory_ma= pping.c index ced199862d..a2398c2173 100644 --- a/target/i386/arch_memory_mapping.c +++ b/target/i386/arch_memory_mapping.c @@ -14,6 +14,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "system/memory_mapping.h" +#include "system/memory.h" =20 /* PAE Paging or IA-32e Paging */ static void walk_pte(MemoryMappingList *list, AddressSpace *as, diff --git a/target/i386/helper.c b/target/i386/helper.c index c07b1b16ea..64d9e8ab9c 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -25,6 +25,7 @@ #include "system/runstate.h" #ifndef CONFIG_USER_ONLY #include "system/hw_accel.h" +#include "system/memory.h" #include "monitor/monitor.h" #include "kvm/kvm_i386.h" #endif diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/= misc_helper.c index 0555cf2604..67896c8c87 100644 --- a/target/i386/tcg/system/misc_helper.c +++ b/target/i386/tcg/system/misc_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "system/address-spaces.h" +#include "system/memory.h" #include "exec/cputlb.h" #include "tcg/helper-tcg.h" #include "hw/i386/apic.h" diff --git a/target/i386/tcg/system/tcg-cpu.c b/target/i386/tcg/system/tcg-= cpu.c index ab1f3c7c59..0538a4fd51 100644 --- a/target/i386/tcg/system/tcg-cpu.c +++ b/target/i386/tcg/system/tcg-cpu.c @@ -24,6 +24,7 @@ #include "system/system.h" #include "qemu/units.h" #include "system/address-spaces.h" +#include "system/memory.h" =20 #include "tcg/tcg-cpu.h" =20 diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 0bf574830f..8251272219 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -25,6 +25,7 @@ #include "exec/page-protection.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" +#include "system/memory.h" #include "gdbstub/helpers.h" #include "fpu/softfloat.h" #include "qemu/qemu-print.h" diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index c941c89806..da8b525a41 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "qemu/log.h" +#include "system/memory.h" #include "system/tcg.h" #include "system/system.h" #include "system/runstate.h" diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c index a812cb5113..3865556310 100644 --- a/target/ppc/mmu-book3s-v3.c +++ b/target/ppc/mmu-book3s-v3.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "system/memory.h" #include "cpu.h" #include "mmu-hash64.h" #include "mmu-book3s-v3.h" diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 5ca4faee2a..3ba4810497 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -25,6 +25,7 @@ #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "system/hw_accel.h" +#include "system/memory.h" #include "kvm_ppc.h" #include "mmu-hash64.h" #include "exec/log.h" diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 461eda4a3d..4ab5f3bb92 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -23,6 +23,7 @@ #include "exec/page-protection.h" #include "qemu/error-report.h" #include "system/kvm.h" +#include "system/memory.h" #include "kvm_ppc.h" #include "exec/log.h" #include "internal.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0dd8645994..ca58094fb5 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -26,6 +26,7 @@ #include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "system/memory.h" #include "instmap.h" #include "tcg/tcg-op.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 45882e25db..8890d2b119 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -27,6 +27,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" +#include "system/memory.h" #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 249b1f6c4c..c5d82a0854 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -24,6 +24,7 @@ #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" #include "exec/tlb-flags.h" +#include "system/memory.h" #include "qemu/qemu-print.h" #include "trace.h" =20 diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 40b02f0a2c..1ce125794d 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -36,6 +36,7 @@ #include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "system/memory.h" =20 #define XTENSA_MPU_SEGMENT_MASK 0x0000001f #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 028d4e0a1c..c125fa4946 100644 --- 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Tue, 22 Apr 2025 12:35:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 104/147] exec/cpu-all: remove exec/page-protection include Date: Tue, 22 Apr 2025 12:27:33 -0700 Message-ID: <20250422192819.302784-105-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351553674019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-6-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 399fcbb9d1..957c86886e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -19,7 +19,6 @@ #ifndef CPU_ALL_H #define CPU_ALL_H =20 -#include "exec/page-protection.h" #include "exec/cpu-common.h" #include "exec/cpu-interrupt.h" #include "exec/tswap.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352741; cv=none; d=zohomail.com; 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Tue, 22 Apr 2025 12:35:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 105/147] exec/cpu-all: remove tswap include Date: Tue, 22 Apr 2025 12:27:34 -0700 Message-ID: <20250422192819.302784-106-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352744409019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-7-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 1 - target/ppc/mmu-hash64.h | 2 ++ target/i386/tcg/system/excp_helper.c | 1 + target/i386/xsave_helper.c | 1 + target/riscv/vector_helper.c | 1 + 5 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 957c86886e..bfa039ab76 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -21,7 +21,6 @@ =20 #include "exec/cpu-common.h" #include "exec/cpu-interrupt.h" -#include "exec/tswap.h" #include "hw/core/cpu.h" #include "exec/cpu-defs.h" #include "exec/target_page.h" diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index ae8d4b37ae..b8fb12a970 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -1,6 +1,8 @@ #ifndef MMU_HASH64_H #define MMU_HASH64_H =20 +#include "exec/tswap.h" + #ifndef CONFIG_USER_ONLY =20 #ifdef TARGET_PPC64 diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index b0b74df72f..4badd73943 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/tlb-flags.h" +#include "exec/tswap.h" #include "tcg/helper-tcg.h" =20 typedef struct TranslateParams { diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index 996e9f3bfe..24ab7be8e9 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -5,6 +5,7 @@ #include "qemu/osdep.h" =20 #include "cpu.h" +#include "exec/tswap.h" =20 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 83978be060..7fffa23bc8 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -26,6 +26,7 @@ #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" +#include "exec/tswap.h" #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" #include "internals.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 22 Apr 2025 12:35:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 106/147] exec/cpu-all: remove exec/cpu-interrupt include Date: Tue, 22 Apr 2025 12:27:35 -0700 Message-ID: <20250422192819.302784-107-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351788033019000 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-8-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 1 - target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/avr/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/loongarch/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 1 + target/mips/cpu.h | 1 + target/openrisc/cpu.h | 1 + target/ppc/cpu.h | 1 + target/riscv/cpu.h | 1 + target/rx/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/xtensa/cpu.h | 1 + accel/tcg/cpu-exec.c | 1 + hw/alpha/typhoon.c | 1 + hw/m68k/next-cube.c | 1 + hw/ppc/ppc.c | 1 + hw/xtensa/pic_cpu.c | 1 + 23 files changed, 22 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index bfa039ab76..7b712b2556 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -20,7 +20,6 @@ #define CPU_ALL_H =20 #include "exec/cpu-common.h" -#include "exec/cpu-interrupt.h" #include "hw/core/cpu.h" #include "exec/cpu-defs.h" #include "exec/target_page.h" diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 80562adfb5..42788a6a0b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" =20 #define ICACHE_LINE_SIZE 32 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a8177c6c2e..958a921490 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -25,6 +25,7 @@ #include "hw/registerfields.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "exec/gdbstub.h" #include "exec/page-protection.h" #include "qapi/qapi-types-common.h" diff --git a/target/avr/cpu.h b/target/avr/cpu.h index b0518a1f60..c2cc2daa66 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "system/memory.h" =20 #ifdef CONFIG_USER_ONLY diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index f6bf068776..dab58c227f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "system/memory.h" #include "qemu/cpu-float.h" #include "qemu/interval-tree.h" diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9b8b962e0a..ce55a5a654 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -24,6 +24,7 @@ #include "cpu-qom.h" #include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "exec/memop.h" #include "hw/i386/topology.h" #include "qapi/qapi-types-common.h" diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 02ef6ddecb..a924aa01d7 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -10,6 +10,7 @@ =20 #include "qemu/int128.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "fpu/softfloat-types.h" #include "hw/registerfields.h" #include "qemu/timer.h" diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index ddb0f29f4a..451644a05a 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -22,6 +22,7 @@ #define M68K_CPU_H =20 #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" #include "cpu-qom.h" =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e44ddd5307..d29681abed 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -23,6 +23,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" +#include "exec/cpu-interrupt.h" =20 typedef struct CPUArchState CPUMBState; #if !defined(CONFIG_USER_ONLY) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9ef72a95d7..29362498ec 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -3,6 +3,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #ifndef CONFIG_USER_ONLY #include "system/memory.h" #endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b97d2ffdd2..c153823b62 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "fpu/softfloat-types.h" =20 /** diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3ee83517dc..7489ba9564 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -23,6 +23,7 @@ #include "qemu/int128.h" #include "qemu/cpu-float.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "cpu-qom.h" #include "qom/object.h" #include "hw/registerfields.h" diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51e49e03de..556eda57e9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,6 +24,7 @@ #include "hw/registerfields.h" #include "hw/qdev-properties.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "exec/gdbstub.h" #include "qemu/cpu-float.h" #include "qom/object.h" diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 349d61c4e4..5f2fcb6656 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -24,6 +24,7 @@ #include "cpu-qom.h" =20 #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" =20 #ifdef CONFIG_USER_ONLY diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 5b7992deda..0a32ad4c61 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,6 +28,7 @@ #include "cpu-qom.h" #include "cpu_models.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" #include "qapi/qapi-types-machine-common.h" =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index d536d5d715..18557d8c38 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" =20 /* CPU Subtypes */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 68f8c21e7c..c0aab69b61 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,6 +4,7 @@ #include "qemu/bswap.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" =20 #if !defined(TARGET_SPARC64) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 8d70bfc0cd..6684631478 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -31,6 +31,7 @@ #include "cpu-qom.h" #include "qemu/cpu-float.h" #include "exec/cpu-defs.h" +#include "exec/cpu-interrupt.h" #include "hw/clock.h" #include "xtensa-isa.h" =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 9e15105533..d388be83d0 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -26,6 +26,7 @@ #include "trace.h" #include "disas/disas.h" #include "exec/cpu-common.h" +#include "exec/cpu-interrupt.h" #include "exec/page-protection.h" #include "exec/mmap-lock.h" #include "exec/translation-block.h" diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index e8711ae16a..9718e1a579 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/module.h" #include "qemu/units.h" +#include "exec/cpu-interrupt.h" #include "qapi/error.h" #include "hw/pci/pci_host.h" #include "cpu.h" diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 0570e4a76f..4ae5668331 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -12,6 +12,7 @@ =20 #include "qemu/osdep.h" #include "exec/hwaddr.h" +#include "exec/cpu-interrupt.h" #include "system/system.h" #include "system/qtest.h" #include "hw/irq.h" diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 3a80931538..43d0d0e755 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -27,6 +27,7 @@ #include "hw/ppc/ppc.h" #include "hw/ppc/ppc_e500.h" #include "qemu/timer.h" +#include "exec/cpu-interrupt.h" #include "system/cpus.h" #include "qemu/log.h" #include "qemu/main-loop.h" diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c index 8cef88c61b..e388531610 100644 --- a/hw/xtensa/pic_cpu.c +++ b/hw/xtensa/pic_cpu.c @@ -27,6 +27,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "exec/cpu-interrupt.h" #include "hw/irq.h" #include "qemu/log.h" #include "qemu/timer.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-12-pierrick.bouvier@linaro.org> --- accel/tcg/internal-target.h | 1 + include/exec/poison.h | 1 + accel/tcg/translate-all.c | 1 + 3 files changed, 3 insertions(+) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index c88f007ffb..05abaeb8e0 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -9,6 +9,7 @@ #ifndef ACCEL_TCG_INTERNAL_TARGET_H #define ACCEL_TCG_INTERNAL_TARGET_H =20 +#include "cpu-param.h" #include "exec/exec-all.h" #include "exec/translation-block.h" #include "tb-internal.h" diff --git a/include/exec/poison.h b/include/exec/poison.h index 4180a5a489..8ec02b40e8 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -37,6 +37,7 @@ #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN +#pragma GCC poison TCG_GUEST_DEFAULT_MO =20 #pragma GCC poison TARGET_LONG_BITS #pragma GCC poison TARGET_FMT_lx diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 87fb6c51d3..ed41fc5d0c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -43,6 +43,7 @@ #include "system/ram_addr.h" #endif =20 +#include "cpu-param.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/mmap-lock.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351302; cv=none; d=zohomail.com; s=zohoarc; b=miDBf8UEBxI/UfIM4PJdT3OTU7b0Dg7PBuW4KUYj6vMgx8DwGIGMin2NGq7b6c/0HAUQ0T6Pe0YoiH34x0VwoPG0TNf/tb61SQVqLOPBG3uv7Hqi7hlHKOKvLdmxeM67BrZ4g8etLD/AME5UVG9QthsGNS0KNIavLVARCVpSB1w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351302; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dQfBujJU7UIXTPefdL2D/GAfXKoyN3ifbh/HgiWO374=; b=FeQ9V25b+H8UHlvDdxVRDYr/Vhi3eSLlxNOZvcTgf8uAz5/h1iRbJVUUoNSZt33w3uurCe2XKUSq43X0oLJfY4zz+HhSPw3vHLjk8owSI4dyZvWSMDSVoNNn7pZ+K7ip8CV2wmOZgrwQL0uI5aUN4qPBJXv6nh88rUug5pmziBo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351302601197.02196756970488; Tue, 22 Apr 2025 12:48:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JQv-00010H-2q; Tue, 22 Apr 2025 15:37:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JP7-0005Y1-Uq for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:39 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JP3-00075z-1I for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:37 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-2279915e06eso58647115ad.1 for ; Tue, 22 Apr 2025 12:35:32 -0700 (PDT) Received: from stoup.. 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Note: this was caught by a test regression for s390x-softmmu. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-13-pierrick.bouvier@linaro.org> --- include/exec/poison.h | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/user-exec.c | 1 + 3 files changed, 3 insertions(+) diff --git a/include/exec/poison.h b/include/exec/poison.h index 8ec02b40e8..f267da6083 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -38,6 +38,7 @@ #pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN #pragma GCC poison TCG_GUEST_DEFAULT_MO +#pragma GCC poison TARGET_HAS_PRECISE_SMC =20 #pragma GCC poison TARGET_LONG_BITS #pragma GCC poison TARGET_FMT_lx diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index df3438e190..d479f53ae0 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/interval-tree.h" #include "qemu/qtree.h" +#include "cpu.h" #include "exec/cputlb.h" #include "exec/log.h" #include "exec/exec-all.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 72a9809c2d..7f57d8f1af 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "accel/tcg/cpu-ops.h" #include "disas/disas.h" +#include "cpu.h" #include "exec/vaddr.h" #include "exec/exec-all.h" #include "exec/tlb-flags.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350813; cv=none; d=zohomail.com; s=zohoarc; b=TyZsbbxpIUIPcO4YKLQMTpipYd5PVp+7oexmgTTs6GK7NuELwkB95QASeYbszFg7lJ7A0QONrXK9eJ5Q25ix4VWx36le7Xvv6F/jzCclgTmZuBkyqx60aNol6rGqR9wWDLrgLLm4wD4n5AJy8uWbXB7a+RibU4Nl2XGNXX1jfKA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350813; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kHsAIp23EWRdufSrcLbCASuKqIf9fO9vwVBtAt7EmVA=; b=ZZS+CZw2NdNoGUEMmwasxnJuRz2lox69rgknecpQzchghPei7X3/+n8vcu3VBw4nEsD5Q0V2D1dS/ywZDtzTrqV4P5CW24QORac+nNZzdqATw/kbCcyh+gbMq5XFCGbD1CZLU3kC2vrbmW7pBz9vifS6k22b/b0JvDSCoNNfu18= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745350813207654.7319798913417; Tue, 22 Apr 2025 12:40:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JR4-0001HC-Hh; Tue, 22 Apr 2025 15:37:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JP5-0005RB-NA for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:38 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JP3-00076a-Mn for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:35 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-225477548e1so57019255ad.0 for ; Tue, 22 Apr 2025 12:35:33 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-14-pierrick.bouvier@linaro.org> --- include/exec/cpu-all.h | 1 - accel/tcg/cpu-exec.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 7b712b2556..dae4fbcea8 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -23,6 +23,5 @@ #include "hw/core/cpu.h" #include "exec/cpu-defs.h" #include "exec/target_page.h" -#include "cpu.h" =20 #endif /* CPU_ALL_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d388be83d0..8d2b957a3b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -36,6 +36,7 @@ #include "exec/log.h" #include "qemu/main-loop.h" #include "exec/cpu-all.h" +#include "cpu.h" #include "exec/icount.h" #include "exec/replay-core.h" #include "system/tcg.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351552; cv=none; d=zohomail.com; s=zohoarc; b=Mw1XQ7mkWcUY/ohjj8y2kv+ikMnOnwCSZSUENUvr+F87rEYaIlg5o9lYuFvDoYDgJaoMkzFpff92/ZmMibzt1PvlzEztppFjxqvdJmoF15u58vWp8IlgYQ3G7wMgrk0PMvOg0dGQbQ3Q9qhsVAj4OV/lcucIW5Nyj+S3pOF3Sbs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351552; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=t9/fRgkcvhfGfqwtp9FaRYG3/zOFCQrW6Y3T1GaLUNg=; b=UPsoQVbnMicggLYSuuBGbGWybWFM2+xwigfYXPyNgHf38MiWnG2BnFuhfrWH7N6GfAiBr5HPiqWPvISpFMsWmVNHJXAtnq0+X/PjRriaCLSozDTU2K1nRHB1giLGhsT018aDje0kG6Pa6kTJajQrTkDF3ap2FfqhhxERw00gzoY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351552737485.7539507353831; Tue, 22 Apr 2025 12:52:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JR0-00019C-IX; Tue, 22 Apr 2025 15:37:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JPB-0005iN-9u for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:42 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JP4-000776-Kd for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:39 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-22928d629faso54274195ad.3 for ; Tue, 22 Apr 2025 12:35:34 -0700 (PDT) Received: from stoup.. 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client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351553333019000 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/tb-hash.h | 1 + hw/s390x/ipl.h | 1 + include/exec/cpu-all.h | 1 - hw/alpha/dp264.c | 1 + hw/arm/boot.c | 1 + hw/arm/smmuv3.c | 1 + hw/avr/atmega.c | 1 + hw/hppa/machine.c | 1 + hw/hyperv/hyperv.c | 1 + hw/hyperv/syndbg.c | 1 + hw/hyperv/vmbus.c | 1 + hw/i386/multiboot.c | 1 + hw/i386/pc.c | 1 + hw/i386/pc_sysfw_ovmf.c | 1 + hw/i386/vapic.c | 1 + hw/loongarch/virt.c | 1 + hw/m68k/q800.c | 1 + hw/m68k/virt.c | 1 + hw/openrisc/boot.c | 1 + hw/pci-host/astro.c | 1 + hw/ppc/e500.c | 1 + hw/ppc/mac_newworld.c | 1 + hw/ppc/mac_oldworld.c | 1 + hw/ppc/ppc_booke.c | 1 + hw/ppc/prep.c | 1 + hw/ppc/spapr_hcall.c | 1 + hw/riscv/riscv-iommu-pci.c | 1 + hw/riscv/riscv-iommu.c | 1 + hw/s390x/s390-pci-bus.c | 1 + hw/s390x/s390-pci-inst.c | 1 + hw/s390x/s390-skeys.c | 1 + hw/sparc/sun4m.c | 1 + hw/sparc64/sun4u.c | 1 + monitor/hmp-cmds-target.c | 1 + semihosting/uaccess.c | 1 + target/alpha/cpu.c | 1 + target/alpha/helper.c | 1 + target/alpha/translate.c | 1 + target/arm/cpu.c | 1 + target/arm/gdbstub64.c | 1 + target/arm/ptw.c | 1 + target/arm/tcg/helper-a64.c | 1 + target/arm/tcg/op_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/arm/tcg/tlb-insns.c | 1 + target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate.c | 1 + target/avr/helper.c | 1 + target/avr/translate.c | 1 + target/hppa/cpu.c | 1 + target/hppa/mem_helper.c | 1 + target/hppa/translate.c | 1 + target/i386/helper.c | 1 + target/i386/kvm/hyperv.c | 1 + target/i386/kvm/kvm.c | 1 + target/i386/kvm/xen-emu.c | 1 + target/i386/sev.c | 1 + target/i386/tcg/access.c | 1 + target/i386/tcg/mpx_helper.c | 1 + target/i386/tcg/system/excp_helper.c | 1 + target/i386/tcg/tcg-cpu.c | 2 +- target/i386/tcg/translate.c | 1 + target/loongarch/cpu_helper.c | 1 + target/loongarch/tcg/tlb_helper.c | 1 + target/loongarch/tcg/translate.c | 1 + target/m68k/helper.c | 1 + target/m68k/translate.c | 1 + target/microblaze/helper.c | 1 + target/microblaze/mmu.c | 1 + target/microblaze/translate.c | 1 + target/mips/tcg/msa_helper.c | 1 + target/mips/tcg/system/cp0_helper.c | 1 + target/mips/tcg/system/tlb_helper.c | 1 + target/mips/tcg/translate.c | 1 + target/openrisc/mmu.c | 1 + target/openrisc/sys_helper.c | 1 + target/openrisc/translate.c | 2 +- target/ppc/mem_helper.c | 1 + target/ppc/mmu-hash32.c | 1 + target/ppc/mmu_common.c | 1 + target/ppc/mmu_helper.c | 1 + target/ppc/translate.c | 1 + target/riscv/cpu_helper.c | 1 + target/riscv/pmp.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/riscv/translate.c | 2 +- target/riscv/vector_helper.c | 1 + target/rx/cpu.c | 1 + target/s390x/helper.c | 1 + target/s390x/ioinst.c | 1 + target/s390x/mmu_helper.c | 1 + target/s390x/tcg/excp_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/s390x/tcg/misc_helper.c | 1 + target/sh4/helper.c | 1 + target/sh4/translate.c | 1 + target/sparc/ldst_helper.c | 1 + target/sparc/mmu_helper.c | 1 + target/sparc/translate.c | 1 + target/tricore/helper.c | 1 + target/tricore/translate.c | 1 + target/xtensa/helper.c | 1 + target/xtensa/mmu_helper.c | 1 + target/xtensa/translate.c | 1 + target/xtensa/xtensa-semi.c | 1 + 105 files changed, 104 insertions(+), 5 deletions(-) diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h index a5382f460d..3bc5042d9d 100644 --- a/accel/tcg/tb-hash.h +++ b/accel/tcg/tb-hash.h @@ -22,6 +22,7 @@ =20 #include "exec/cpu-defs.h" #include "exec/exec-all.h" +#include "exec/target_page.h" #include "exec/translation-block.h" #include "qemu/xxhash.h" #include "tb-jmp-cache.h" diff --git a/hw/s390x/ipl.h b/hw/s390x/ipl.h index 6557ac3be5..cb55101f06 100644 --- a/hw/s390x/ipl.h +++ b/hw/s390x/ipl.h @@ -14,6 +14,7 @@ #define HW_S390_IPL_H =20 #include "cpu.h" +#include "exec/target_page.h" #include "system/address-spaces.h" #include "system/memory.h" #include "hw/qdev-core.h" diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index dae4fbcea8..e7c8b8672f 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -22,6 +22,5 @@ #include "exec/cpu-common.h" #include "hw/core/cpu.h" #include "exec/cpu-defs.h" -#include "exec/target_page.h" =20 #endif /* CPU_ALL_H */ diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 570ea9edf2..19562b5967 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "exec/target_page.h" #include "elf.h" #include "hw/loader.h" #include "alpha_sys.h" diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e296b62fa1..d3811b896f 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -14,6 +14,7 @@ #include #include "hw/arm/boot.h" #include "hw/arm/linux-boot-if.h" +#include "exec/target_page.h" #include "system/kvm.h" #include "system/tcg.h" #include "system/system.h" diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 1a96287ba9..4362ae6aa1 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -25,6 +25,7 @@ #include "hw/qdev-core.h" #include "hw/pci/pci.h" #include "cpu.h" +#include "exec/target_page.h" #include "trace.h" #include "qemu/log.h" #include "qemu/error-report.h" diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 2e8b8e8c67..c105d2a97c 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -12,6 +12,7 @@ #include "qemu/module.h" #include "qemu/units.h" #include "qapi/error.h" +#include "exec/target_page.h" #include "system/memory.h" #include "system/address-spaces.h" #include "system/system.h" diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index c5f247633e..c430bf28dd 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -11,6 +11,7 @@ #include "elf.h" #include "hw/loader.h" #include "qemu/error-report.h" +#include "exec/target_page.h" #include "system/reset.h" #include "system/system.h" #include "system/qtest.h" diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c index d21e428eae..c487f13e2f 100644 --- a/hw/hyperv/hyperv.c +++ b/hw/hyperv/hyperv.c @@ -25,6 +25,7 @@ #include "target/i386/kvm/hyperv-proto.h" #include "target/i386/cpu.h" #include "exec/cpu-all.h" +#include "exec/target_page.h" =20 struct SynICState { DeviceState parent_obj; diff --git a/hw/hyperv/syndbg.c b/hw/hyperv/syndbg.c index d3e3917077..a410b55b9a 100644 --- a/hw/hyperv/syndbg.c +++ b/hw/hyperv/syndbg.c @@ -15,6 +15,7 @@ #include "hw/qdev-properties.h" #include "hw/loader.h" #include "cpu.h" +#include "exec/target_page.h" #include "hw/hyperv/hyperv.h" #include "hw/hyperv/vmbus-bridge.h" #include "hw/hyperv/hyperv-proto.h" diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c index 12a7dc4312..06649b2a2e 100644 --- a/hw/hyperv/vmbus.c +++ b/hw/hyperv/vmbus.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "exec/target_page.h" #include "qapi/error.h" #include "migration/vmstate.h" #include "hw/qdev-properties.h" diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index cd07a05861..6e6b96bc34 100644 --- a/hw/i386/multiboot.c +++ b/hw/i386/multiboot.c @@ -29,6 +29,7 @@ #include "multiboot.h" #include "hw/loader.h" #include "elf.h" +#include "exec/target_page.h" #include "system/system.h" #include "qemu/error-report.h" =20 diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 01d0581f62..3b98089e90 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -24,6 +24,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" +#include "exec/target_page.h" #include "hw/i386/pc.h" #include "hw/char/serial-isa.h" #include "hw/char/parallel.h" diff --git a/hw/i386/pc_sysfw_ovmf.c b/hw/i386/pc_sysfw_ovmf.c index 07a4c267fa..da947c3ca4 100644 --- a/hw/i386/pc_sysfw_ovmf.c +++ b/hw/i386/pc_sysfw_ovmf.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "hw/i386/pc.h" +#include "exec/target_page.h" #include "cpu.h" =20 #define OVMF_TABLE_FOOTER_GUID "96b582de-1fb2-45f7-baea-a366c55a082d" diff --git a/hw/i386/vapic.c b/hw/i386/vapic.c index 26aae64e5d..347431eeef 100644 --- a/hw/i386/vapic.c +++ b/hw/i386/vapic.c @@ -11,6 +11,7 @@ =20 #include "qemu/osdep.h" #include "qemu/module.h" +#include "exec/target_page.h" #include "system/system.h" #include "system/cpus.h" #include "system/hw_accel.h" diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index f1eb42c2c1..39ea5cadd6 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -8,6 +8,7 @@ #include "qemu/units.h" #include "qemu/datadir.h" #include "qapi/error.h" +#include "exec/target_page.h" #include "hw/boards.h" #include "hw/char/serial-mm.h" #include "system/kvm.h" diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index aeed4c8ddb..c2e365a820 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -24,6 +24,7 @@ #include "qemu/units.h" #include "qemu/datadir.h" #include "qemu/guest-random.h" +#include "exec/target_page.h" #include "system/system.h" #include "cpu.h" #include "hw/boards.h" diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c index d967bdd743..b738cb7e75 100644 --- a/hw/m68k/virt.c +++ b/hw/m68k/virt.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qemu/guest-random.h" +#include "exec/target_page.h" #include "system/system.h" #include "cpu.h" #include "hw/boards.h" diff --git a/hw/openrisc/boot.c b/hw/openrisc/boot.c index 0a5881be31..c81efe8138 100644 --- a/hw/openrisc/boot.c +++ b/hw/openrisc/boot.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cpu-defs.h" +#include "exec/target_page.h" #include "elf.h" #include "hw/loader.h" #include "hw/openrisc/boot.h" diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 039cc3ad01..c6f2d4f494 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -35,6 +35,7 @@ #include "target/hppa/cpu.h" #include "trace.h" #include "qom/object.h" +#include "exec/target_page.h" =20 /* * Helper functions diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 69269aa24c..809078a2c3 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -18,6 +18,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/guest-random.h" +#include "exec/target_page.h" #include "qapi/error.h" #include "e500.h" #include "e500-ccsr.h" diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 2d5309d6f5..21b2fc569a 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -50,6 +50,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qapi/error.h" +#include "exec/target_page.h" #include "hw/ppc/ppc.h" #include "hw/qdev-properties.h" #include "hw/nvram/mac_nvram.h" diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index b5814690f5..0d34e6bfda 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -28,6 +28,7 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "qapi/error.h" +#include "exec/target_page.h" #include "hw/ppc/ppc.h" #include "hw/qdev-properties.h" #include "hw/boards.h" diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index 925e670ba0..3872ae2822 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -24,6 +24,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "exec/target_page.h" #include "hw/ppc/ppc.h" #include "qemu/timer.h" #include "system/reset.h" diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 3e68d8e6e2..739526335c 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -39,6 +39,7 @@ #include "hw/rtc/mc146818rtc.h" #include "hw/isa/pc87312.h" #include "hw/qdev-properties.h" +#include "exec/target_page.h" #include "system/kvm.h" #include "system/reset.h" #include "trace.h" diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 406aea4ecb..a4f399c4ff 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -9,6 +9,7 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "exec/tb-flush.h" +#include "exec/target_page.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" #include "hw/ppc/spapr.h" diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c index 12451869e4..a795464803 100644 --- a/hw/riscv/riscv-iommu-pci.c +++ b/hw/riscv/riscv-iommu-pci.c @@ -17,6 +17,7 @@ */ =20 #include "qemu/osdep.h" +#include "exec/target_page.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/pci/pci_bus.h" diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 76e0fcd873..65411b3e4c 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -18,6 +18,7 @@ =20 #include "qemu/osdep.h" #include "qom/object.h" +#include "exec/target_page.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_device.h" #include "hw/qdev-properties.h" diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 2591ee49c1..4365f8ed1e 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -14,6 +14,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qapi/visitor.h" +#include "exec/target_page.h" #include "hw/s390x/s390-pci-bus.h" #include "hw/s390x/s390-pci-inst.h" #include "hw/s390x/s390-pci-kvm.h" diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index b4e003c19c..b5dddb22b8 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -13,6 +13,7 @@ =20 #include "qemu/osdep.h" #include "exec/memop.h" +#include "exec/target_page.h" #include "system/memory.h" #include "qemu/error-report.h" #include "system/hw_accel.h" diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c index 425e3e4a87..de0af12649 100644 --- a/hw/s390x/s390-skeys.c +++ b/hw/s390x/s390-skeys.c @@ -11,6 +11,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" +#include "exec/target_page.h" #include "hw/s390x/s390-virtio-ccw.h" #include "hw/qdev-properties.h" #include "hw/s390x/storage-keys.h" diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 5aaafb40da..edbf19d958 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -27,6 +27,7 @@ #include "qapi/error.h" #include "qemu/datadir.h" #include "cpu.h" +#include "exec/target_page.h" #include "hw/sysbus.h" #include "qemu/error-report.h" #include "qemu/timer.h" diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index d3cb7270ff..becdf3ea98 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -28,6 +28,7 @@ #include "qapi/error.h" #include "qemu/datadir.h" #include "cpu.h" +#include "exec/target_page.h" #include "hw/irq.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bridge.h" diff --git a/monitor/hmp-cmds-target.c b/monitor/hmp-cmds-target.c index 011a367357..8eaf70d9c9 100644 --- a/monitor/hmp-cmds-target.c +++ b/monitor/hmp-cmds-target.c @@ -31,6 +31,7 @@ #include "qapi/error.h" #include "qobject/qdict.h" #include "system/hw_accel.h" +#include "exec/target_page.h" =20 /* Set the current CPU defined by the user. Callers must hold BQL. */ int monitor_set_cpu(Monitor *mon, int cpu_index) diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index ccb0c96070..f51a253626 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -11,6 +11,7 @@ #include "exec/cpu-all.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" +#include "exec/target_page.h" #include "exec/tlb-flags.h" #include "semihosting/uaccess.h" =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 56c96b1c4d..99d839a279 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "fpu/softfloat.h" =20 =20 diff --git a/target/alpha/helper.c b/target/alpha/helper.c index f6261a3a53..096eac3445 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/cputlb.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" #include "qemu/qemu-print.h" diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 2156c02214..7f3195a5dc 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -27,6 +27,7 @@ #include "exec/helper-gen.h" #include "exec/translator.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "exec/log.h" =20 #define HELPER_H "helper.h" diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 21e8cf1400..c9e043bc9b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -34,6 +34,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/exec-all.h" +#include "exec/target_page.h" #include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index be38016fc7..64ee9b3b56 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -29,6 +29,7 @@ #endif #ifdef CONFIG_TCG #include "accel/tcg/cpu-mmu-index.h" +#include "exec/target_page.h" #endif =20 int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8d4e9e07a9..e0e82ae507 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -12,6 +12,7 @@ #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/tlb-flags.h" #include "cpu.h" #include "internals.h" diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index fa79d19425..507dbc1a44 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -31,6 +31,7 @@ #include "exec/cpu-common.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/target_page.h" #include "exec/tlb-flags.h" #include "qemu/int128.h" #include "qemu/atomic128.h" diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 30786fd1ff..71ba406782 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -20,6 +20,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "exec/target_page.h" #include "internals.h" #include "cpu-features.h" #include "exec/exec-all.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index e3bed77b48..9b0d40c9e1 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" +#include "exec/target_page.h" #include "exec/tlb-flags.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index 630a481f0f..0407ad5542 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "exec/cputlb.h" +#include "exec/target_page.h" #include "cpu.h" #include "internals.h" #include "cpu-features.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 39014325df..43408c71bb 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -17,8 +17,8 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" - #include "exec/exec-all.h" +#include "exec/target_page.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index d280018138..273b860d57 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -27,6 +27,7 @@ #include "semihosting/semihost.h" #include "cpregs.h" #include "exec/helper-proto.h" +#include "exec/target_page.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/target/avr/helper.c b/target/avr/helper.c index f23fa3e8ba..32cbf17919 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -26,6 +26,7 @@ #include "accel/tcg/getpc.h" #include "exec/cputlb.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" =20 diff --git a/target/avr/translate.c b/target/avr/translate.c index 0490936cd5..b9c592c899 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -29,6 +29,7 @@ #include "exec/helper-gen.h" #include "exec/log.h" #include "exec/translator.h" +#include "exec/target_page.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 09a6aaa3dd..51bff0c5d6 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -26,6 +26,7 @@ #include "qemu/module.h" #include "exec/exec-all.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" #include "hw/hppa/hppa_hardware.h" diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index a1ade9079e..554d7bf4d1 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -24,6 +24,7 @@ #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" #include "trace.h" diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 0d0d1bc99b..14f3833322 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -28,6 +28,7 @@ #include "exec/helper-gen.h" #include "exec/translator.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "exec/log.h" =20 #define HELPER_H "helper.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 64d9e8ab9c..197fdac7dd 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/cputlb.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "system/runstate.h" #ifndef CONFIG_USER_ONLY #include "system/hw_accel.h" diff --git a/target/i386/kvm/hyperv.c b/target/i386/kvm/hyperv.c index 70b89cacf9..9865120cc4 100644 --- a/target/i386/kvm/hyperv.c +++ b/target/i386/kvm/hyperv.c @@ -13,6 +13,7 @@ =20 #include "qemu/osdep.h" #include "qemu/main-loop.h" +#include "exec/target_page.h" #include "hyperv.h" #include "hw/hyperv/hyperv.h" #include "hyperv-proto.h" diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6c749d4ee8..c9a3c02e3e 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -67,6 +67,7 @@ #include "hw/pci/msix.h" #include "migration/blocker.h" #include "exec/memattrs.h" +#include "exec/target_page.h" #include "trace.h" =20 #include CONFIG_DEVICES diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c index b23010374f..284c5ef6f6 100644 --- a/target/i386/kvm/xen-emu.c +++ b/target/i386/kvm/xen-emu.c @@ -13,6 +13,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "qemu/error-report.h" +#include "exec/target_page.h" #include "hw/xen/xen.h" #include "system/kvm_int.h" #include "system/kvm_xen.h" diff --git a/target/i386/sev.c b/target/i386/sev.c index ba88976e9f..878dd20f2c 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -26,6 +26,7 @@ #include "qemu/uuid.h" #include "qemu/error-report.h" #include "crypto/hash.h" +#include "exec/target_page.h" #include "system/kvm.h" #include "kvm/kvm_i386.h" #include "sev.h" diff --git a/target/i386/tcg/access.c b/target/i386/tcg/access.c index e68b73a24b..5a4721dcee 100644 --- a/target/i386/tcg/access.c +++ b/target/i386/tcg/access.c @@ -5,6 +5,7 @@ #include "cpu.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "exec/target_page.h" #include "access.h" =20 =20 diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index 22423eedcd..b942665adc 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "exec/target_page.h" #include "helper-tcg.h" =20 =20 diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index 4badd73943..a563c9b35e 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -22,6 +22,7 @@ #include "exec/cpu_ldst.h" #include "exec/cputlb.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/tlb-flags.h" #include "exec/tswap.h" #include "tcg/helper-tcg.h" diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 818653ee6d..35b17f2b18 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -23,7 +23,7 @@ #include "qemu/accel.h" #include "accel/accel-cpu-target.h" #include "exec/translation-block.h" - +#include "exec/target_page.h" #include "tcg-cpu.h" =20 /* Frob eflags into and out of the CPU temporary format. */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e000073459..ca49f8d6dc 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -26,6 +26,7 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/translator.h" +#include "exec/target_page.h" #include "fpu/softfloat.h" =20 #include "exec/helper-proto.h" diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index f8965cd155..bb343078bf 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "accel/tcg/cpu-mmu-index.h" +#include "exec/target_page.h" #include "internals.h" #include "cpu-csr.h" =20 diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 70d1b5cf99..0d6c9844a6 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -15,6 +15,7 @@ #include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "cpu-csr.h" diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index e59e4ed25b..53a0b4c3ce 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -11,6 +11,7 @@ #include "tcg/tcg-op-gvec.h" #include "exec/translation-block.h" #include "exec/translator.h" +#include "exec/target_page.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/log.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 8251272219..f73e0def23 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "system/memory.h" diff --git a/target/m68k/translate.c b/target/m68k/translate.c index dec2967fce..b1266a7875 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/qemu-print.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 022c98f0c3..9203192483 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "qemu/host-utils.h" #include "exec/log.h" =20 diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 2d18659b99..95a12e16f8 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -24,6 +24,7 @@ #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" +#include "exec/target_page.h" =20 static unsigned int tlb_decode_size(unsigned int f) { diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b54e5ac4b2..4bb867c969 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -27,6 +27,7 @@ #include "exec/helper-gen.h" #include "exec/translator.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "qemu/qemu-print.h" =20 #include "exec/log.h" diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 74fb80cc25..969dd34b3e 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/memop.h" +#include "exec/target_page.h" #include "fpu/softfloat.h" #include "fpu_helper.h" =20 diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/c= p0_helper.c index 78e422b0ca..101b1e65fd 100644 --- a/target/mips/tcg/system/cp0_helper.c +++ b/target/mips/tcg/system/cp0_helper.c @@ -28,6 +28,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" +#include "exec/target_page.h" =20 =20 /* SMP helpers. */ diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index df80301a41..d239fa9353 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -24,6 +24,7 @@ #include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 78b848a6d9..8658315f93 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -27,6 +27,7 @@ #include "internal.h" #include "exec/helper-proto.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "semihosting/semihost.h" #include "trace.h" #include "fpu_helper.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 47ac783c52..acea50c41e 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "exec/cputlb.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "hw/loader.h" diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 21bc137ccc..92badf017f 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/cputlb.h" +#include "exec/target_page.h" #include "exec/helper-proto.h" #include "exception.h" #ifndef CONFIG_USER_ONLY diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index da033bffff..d4ce60188b 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -28,7 +28,7 @@ #include "qemu/qemu-print.h" #include "exec/translator.h" #include "exec/translation-block.h" - +#include "exec/target_page.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" =20 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 51b137febd..0967624afe 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/target_page.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "helper_regs.h" diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 1f791a7f2f..5bd3efe70e 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "system/kvm.h" #include "kvm_ppc.h" #include "internal.h" diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index fb62b947f1..394a0c9bb6 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -26,6 +26,7 @@ #include "mmu-hash32.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ad9ba8294c..c90ceb7d60 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -27,6 +27,7 @@ #include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a52cbc869a..399107d319 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internal.h" #include "exec/exec-all.h" +#include "exec/target_page.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "qemu/host-utils.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ca58094fb5..619c76cc00 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -26,6 +26,7 @@ #include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "system/memory.h" #include "instmap.h" #include "tcg/tcg-op.h" diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index b0841d44f4..c13a117e3f 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -26,6 +26,7 @@ #include "trace.h" #include "exec/cputlb.h" #include "exec/page-protection.h" +#include "exec/target_page.h" =20 static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index bee7dfd803..710449d17e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -22,6 +22,7 @@ #include "exec/translation-block.h" #include "tcg-cpu.h" #include "cpu.h" +#include "exec/target_page.h" #include "internals.h" #include "pmu.h" #include "time_helper.h" diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d6651f244f..cef61b5b29 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -23,7 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" - +#include "exec/target_page.h" #include "exec/translator.h" #include "exec/translation-block.h" #include "exec/log.h" diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7fffa23bc8..7de6cbae5c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -26,6 +26,7 @@ #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" +#include "exec/target_page.h" #include "exec/tswap.h" #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 51743020d4..e14d9cbef9 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -24,6 +24,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" diff --git a/target/s390x/helper.c b/target/s390x/helper.c index e660c69f60..3c57c32e47 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -27,6 +27,7 @@ #include "target/s390x/kvm/pv.h" #include "system/hw_accel.h" #include "system/runstate.h" +#include "exec/target_page.h" #include "exec/watchpoint.h" =20 void s390x_tod_timer(void *opaque) diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c index a944f16c25..fe62ba5b06 100644 --- a/target/s390x/ioinst.c +++ b/target/s390x/ioinst.c @@ -12,6 +12,7 @@ #include "qemu/osdep.h" =20 #include "cpu.h" +#include "exec/target_page.h" #include "s390x-internal.h" #include "hw/s390x/ioinst.h" #include "trace.h" diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index b079d120db..0e133cb9a5 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -25,6 +25,7 @@ #include "system/tcg.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "hw/hw.h" #include "hw/s390x/storage-keys.h" #include "hw/boards.h" diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 1d51043e88..6cd813e1ab 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "exec/cputlb.h" #include "exec/exec-all.h" +#include "exec/target_page.h" #include "exec/watchpoint.h" #include "s390x-internal.h" #include "tcg_s390x.h" diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0ff2e10d81..d5eece4384 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -29,6 +29,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" +#include "exec/target_page.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" #include "qemu/int128.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 31266aeda4..e02f443850 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -29,6 +29,7 @@ #include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/cpu_ldst.h" +#include "exec/target_page.h" #include "qapi/error.h" #include "tcg_s390x.h" #include "s390-tod.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 7567e6c8b6..b41d14d5d7 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/log.h" =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index bcdd558818..5ce477d0ad 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -25,6 +25,7 @@ #include "exec/helper-gen.h" #include "exec/translation-block.h" #include "exec/translator.h" +#include "exec/target_page.h" #include "exec/log.h" #include "qemu/qemu-print.h" =20 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 8890d2b119..3fa5e78816 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -26,6 +26,7 @@ #include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/cpu_ldst.h" #include "system/memory.h" #ifdef CONFIG_USER_ONLY diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index c5d82a0854..217580a4d8 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -23,6 +23,7 @@ #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "exec/tlb-flags.h" #include "system/memory.h" #include "qemu/qemu-print.h" diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bfe63649db..adebddf27b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/target_page.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/helper-gen.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index b1ee126112..e4c53d453d 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -22,6 +22,7 @@ #include "exec/cputlb.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" =20 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 6819b77668..5c7ed395ca 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -31,6 +31,7 @@ #include "tricore-opcodes.h" #include "exec/translator.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "exec/log.h" =20 #define HELPER_H "helper.h" diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 4824b97e37..d02d16f9ec 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -29,6 +29,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/cputlb.h" +#include "exec/target_page.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 1ce125794d..a7dd810055 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -36,6 +36,7 @@ #include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/target_page.h" #include "system/memory.h" =20 #define XTENSA_MPU_SEGMENT_MASK 0x0000001f diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index cb817b3119..5ebd4a512c 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -37,6 +37,7 @@ #include "qemu/qemu-print.h" #include "exec/translator.h" #include "exec/translation-block.h" +#include "exec/target_page.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/log.h" diff --git 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Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-15-pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 1 - include/exec/cpu_ldst.h | 1 + target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/avr/cpu.h | 1 + target/hexagon/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/loongarch/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 1 + target/mips/cpu.h | 1 + target/openrisc/cpu.h | 1 + target/ppc/cpu.h | 1 + target/riscv/cpu.h | 1 + target/rx/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/tricore/cpu.h | 1 + target/xtensa/cpu.h | 1 + cpu-target.c | 1 + 22 files changed, 21 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index e7c8b8672f..5122fdbee3 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -19,7 +19,6 @@ #ifndef CPU_ALL_H #define CPU_ALL_H =20 -#include "exec/cpu-common.h" #include "hw/core/cpu.h" #include "exec/cpu-defs.h" =20 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 77dc5ac61c..63847f6e61 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -66,6 +66,7 @@ #error Can only include this header with TCG #endif =20 +#include "exec/cpu-common.h" #include "exec/cpu-ldst-common.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/abi_ptr.h" diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 42788a6a0b..fb1d63527e 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -21,6 +21,7 @@ #define ALPHA_CPU_H =20 #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 958a921490..ee92476814 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -24,6 +24,7 @@ #include "qemu/cpu-float.h" #include "hw/registerfields.h" #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "exec/gdbstub.h" diff --git a/target/avr/cpu.h b/target/avr/cpu.h index c2cc2daa66..a0fb40141a 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -22,6 +22,7 @@ #define QEMU_AVR_CPU_H =20 #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "system/memory.h" diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index f78c8f9c2a..e4fc35b112 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -21,6 +21,7 @@ #include "fpu/softfloat-types.h" =20 #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "hex_regs.h" #include "mmvec/mmvec.h" diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index dab58c227f..4e72ab025b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -21,6 +21,7 @@ #define HPPA_CPU_H =20 #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "system/memory.h" diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ce55a5a654..1f30129e40 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -23,6 +23,7 @@ #include "system/tcg.h" #include "cpu-qom.h" #include "kvm/hyperv-proto.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "exec/memop.h" diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index a924aa01d7..69117c602a 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -9,6 +9,7 @@ #define LOONGARCH_CPU_H =20 #include "qemu/int128.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "fpu/softfloat-types.h" diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 451644a05a..5347fbe397 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -21,6 +21,7 @@ #ifndef M68K_CPU_H #define M68K_CPU_H =20 +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d29681abed..90d820b90c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -21,6 +21,7 @@ #define MICROBLAZE_CPU_H =20 #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" #include "exec/cpu-interrupt.h" diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 29362498ec..79f8041ced 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -2,6 +2,7 @@ #define MIPS_CPU_H =20 #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #ifndef CONFIG_USER_ONLY diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c153823b62..f16a070ef6 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -21,6 +21,7 @@ #define OPENRISC_CPU_H =20 #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "fpu/softfloat-types.h" diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 7489ba9564..aa5df47bda 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -22,6 +22,7 @@ =20 #include "qemu/int128.h" #include "qemu/cpu-float.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "cpu-qom.h" diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 556eda57e9..14a6779b4c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -23,6 +23,7 @@ #include "hw/core/cpu.h" #include "hw/registerfields.h" #include "hw/qdev-properties.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "exec/gdbstub.h" diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 5f2fcb6656..e2ec78835e 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -23,6 +23,7 @@ #include "hw/registerfields.h" #include "cpu-qom.h" =20 +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 0a32ad4c61..83d01d5c4e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -27,6 +27,7 @@ =20 #include "cpu-qom.h" #include "cpu_models.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 18557d8c38..7581f5eecb 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -21,6 +21,7 @@ #define SH4_CPU_H =20 #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index c0aab69b61..b87351a666 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -3,6 +3,7 @@ =20 #include "qemu/bswap.h" #include "cpu-qom.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index cf9dbc6df8..abb9cba136 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "hw/registerfields.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" #include "tricore-defs.h" diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6684631478..c5d2042de1 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -30,6 +30,7 @@ =20 #include "cpu-qom.h" #include "qemu/cpu-float.h" +#include "exec/cpu-common.h" #include "exec/cpu-defs.h" #include "exec/cpu-interrupt.h" #include "hw/clock.h" diff --git a/cpu-target.c b/cpu-target.c index 7f3b244ed1..14cd623bff 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -24,6 +24,7 @@ #include "qemu/qemu-print.h" #include "system/accel-ops.h" #include "system/cpus.h" +#include "exec/cpu-common.h" #include "exec/tswap.h" #include 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Tue, 22 Apr 2025 12:35:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 112/147] exec/cpu-all: remove this header Date: Tue, 22 Apr 2025 12:27:41 -0700 Message-ID: <20250422192819.302784-113-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351555947019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-16-pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 25 ------------------------- include/hw/core/cpu.h | 2 +- include/qemu/bswap.h | 2 +- target/alpha/cpu.h | 2 -- target/arm/cpu.h | 2 -- target/avr/cpu.h | 2 -- target/hexagon/cpu.h | 2 -- target/hppa/cpu.h | 2 -- target/i386/cpu.h | 1 - target/loongarch/cpu.h | 2 -- target/m68k/cpu.h | 2 -- target/microblaze/cpu.h | 2 -- target/mips/cpu.h | 2 -- target/openrisc/cpu.h | 2 -- target/ppc/cpu.h | 2 -- target/riscv/cpu.h | 2 -- target/rx/cpu.h | 2 -- target/s390x/cpu.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu.h | 2 -- target/tricore/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- accel/tcg/cpu-exec.c | 1 - hw/hyperv/hyperv.c | 1 - semihosting/uaccess.c | 1 - tcg/tcg-op-ldst.c | 2 +- 26 files changed, 3 insertions(+), 68 deletions(-) delete mode 100644 include/exec/cpu-all.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h deleted file mode 100644 index 5122fdbee3..0000000000 --- a/include/exec/cpu-all.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * defines common to all virtual CPUs - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#ifndef CPU_ALL_H -#define CPU_ALL_H - -#include "hw/core/cpu.h" -#include "exec/cpu-defs.h" - -#endif /* CPU_ALL_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 28bd27b8ed..10b6b25b34 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -579,7 +579,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=3D =20 static inline CPUArchState *cpu_env(CPUState *cpu) { - /* We validate that CPUArchState follows CPUState in cpu-all.h. */ + /* We validate that CPUArchState follows CPUState in cpu-target.c */ return (CPUArchState *)(cpu + 1); } =20 diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index b915835bea..8782056ae4 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -206,7 +206,7 @@ CPU_CONVERT(le, 64, uint64_t) * (except for byte accesses, which have no endian infix). * * The target endian accessors are obviously only available to source - * files which are built per-target; they are defined in cpu-all.h. + * files which are built per-target; they are defined in system/memory.h. * * In all cases these functions take a host pointer. * For accessors that take a guest address rather than a diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index fb1d63527e..849f673489 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -289,8 +289,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 -#include "exec/cpu-all.h" - enum { FEATURE_ASN =3D 0x00000001, FEATURE_SPS =3D 0x00000002, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ee92476814..ea9956395c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2968,8 +2968,6 @@ static inline bool arm_sctlr_b(CPUARMState *env) =20 uint64_t arm_sctlr(CPUARMState *env, int el); =20 -#include "exec/cpu-all.h" - /* * We have more than 32-bits worth of state per TB, so we split the data * between tb->flags and tb->cs_base, which is otherwise unused for ARM. diff --git a/target/avr/cpu.h b/target/avr/cpu.h index a0fb40141a..d6666175a9 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -259,6 +259,4 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, extern const MemoryRegionOps avr_cpu_reg1; extern const MemoryRegionOps avr_cpu_reg2; =20 -#include "exec/cpu-all.h" - #endif /* QEMU_AVR_CPU_H */ diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index e4fc35b112..c065fa8ddc 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -158,6 +158,4 @@ void hexagon_translate_init(void); void hexagon_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); =20 -#include "exec/cpu-all.h" - #endif /* HEXAGON_CPU_H */ diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 4e72ab025b..da5f8adcd5 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -306,8 +306,6 @@ struct HPPACPUClass { ResettablePhases parent_phases; }; =20 -#include "exec/cpu-all.h" - static inline bool hppa_is_pa20(const CPUHPPAState *env) { return env->is_pa20; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1f30129e40..b5d68c796b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2604,7 +2604,6 @@ static inline bool is_mmu_index_32(int mmu_index) #define CC_SRC2 (env->cc_src2) #define CC_OP (env->cc_op) =20 -#include "exec/cpu-all.h" #include "svm.h" =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 69117c602a..ad8b0ed235 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -504,8 +504,6 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchSta= te *env, vaddr *pc, *flags |=3D is_va32(env) * HW_FLAGS_VA32; } =20 -#include "exec/cpu-all.h" - #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU =20 void loongarch_cpu_post_init(Object *obj); diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 5347fbe397..0b70e8c6ab 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -596,8 +596,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif =20 -#include "exec/cpu-all.h" - /* TB flags */ #define TB_FLAGS_MACSR 0x0f #define TB_FLAGS_MSR_S_BIT 13 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 90d820b90c..2bfa396c96 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -411,8 +411,6 @@ void mb_translate_code(CPUState *cs, TranslationBlock *= tb, #define MMU_USER_IDX 2 /* See NB_MMU_MODES in cpu-defs.h. */ =20 -#include "exec/cpu-all.h" - /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 79f8041ced..20f31370bc 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1258,8 +1258,6 @@ static inline int mips_env_mmu_index(CPUMIPSState *en= v) return hflags_mmu_index(env->hflags); } =20 -#include "exec/cpu-all.h" - /* Exceptions */ enum { EXCP_NONE =3D -1, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index f16a070ef6..19ee85ff5a 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -334,8 +334,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); =20 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU =20 -#include "exec/cpu-all.h" - #define TB_FLAGS_SM SR_SM #define TB_FLAGS_DME SR_DME #define TB_FLAGS_IME SR_IME diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index aa5df47bda..3c02f7f7d4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1704,8 +1704,6 @@ void ppc_compat_add_property(Object *obj, const char = *name, uint32_t *compat_pvr, const char *basedesc); #endif /* defined(TARGET_PPC64) */ =20 -#include "exec/cpu-all.h" - /*************************************************************************= ****/ /* CRF definitions */ #define CRF_LT_BIT 3 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 14a6779b4c..867e539b53 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -634,8 +634,6 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *en= v, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#include "exec/cpu-all.h" - FIELD(TB_FLAGS, MEM_IDX, 0, 3) FIELD(TB_FLAGS, FS, 3, 2) /* Vector flags */ diff --git a/target/rx/cpu.h b/target/rx/cpu.h index e2ec78835e..5c19c83219 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -147,8 +147,6 @@ void rx_translate_code(CPUState *cs, TranslationBlock *= tb, int *max_insns, vaddr pc, void *host_pc); void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); =20 -#include "exec/cpu-all.h" - #define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0 #define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1 =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 83d01d5c4e..940eda8dd1 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -948,6 +948,4 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); =20 -#include "exec/cpu-all.h" - #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 7581f5eecb..7752a0c2e1 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -288,8 +288,6 @@ void cpu_load_tlb(CPUSH4State * env); /* MMU modes definitions */ #define MMU_USER_IDX 1 =20 -#include "exec/cpu-all.h" - /* MMU control register */ #define MMUCR 0x1F000010 #define MMUCR_AT (1<<0) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index b87351a666..734dfdb1d3 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -729,8 +729,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, = int pil) #endif } =20 -#include "exec/cpu-all.h" - #ifdef TARGET_SPARC64 /* sun4u.c */ void cpu_tick_set_count(CPUTimer *timer, uint64_t count); diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index abb9cba136..c76e65f818 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -251,8 +251,6 @@ void fpu_set_state(CPUTriCoreState *env); =20 #define MMU_USER_IDX 2 =20 -#include "exec/cpu-all.h" - FIELD(TB_FLAGS, PRIV, 0, 2) =20 void cpu_state_reset(CPUTriCoreState *s); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c5d2042de1..c03ed71c94 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -733,8 +733,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPU= XtensaState *env) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 =20 -#include "exec/cpu-all.h" - static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8d2b957a3b..5ced3879ac 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -35,7 +35,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#include "exec/cpu-all.h" #include "cpu.h" #include "exec/icount.h" #include "exec/replay-core.h" diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c index c487f13e2f..8f193fd0bd 100644 --- a/hw/hyperv/hyperv.c +++ b/hw/hyperv/hyperv.c @@ -24,7 +24,6 @@ #include "qom/object.h" #include "target/i386/kvm/hyperv-proto.h" #include "target/i386/cpu.h" -#include "exec/cpu-all.h" #include "exec/target_page.h" =20 struct SynICState { diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c index f51a253626..81ffecaaba 100644 --- a/semihosting/uaccess.c +++ b/semihosting/uaccess.c @@ -8,7 +8,6 @@ */ =20 #include "qemu/osdep.h" -#include "exec/cpu-all.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/exec-all.h" #include "exec/target_page.h" diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 73838e2701..3b073b4ce0 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -37,7 +37,7 @@ static void check_max_alignment(unsigned a_bits) { /* * The requested alignment cannot overlap the TLB flags. - * FIXME: Must keep the count up-to-date with "exec/cpu-all.h". + * FIXME: Must keep the count up-to-date with "exec/tlb-flags.h". */ if (tcg_use_softmmu) { tcg_debug_assert(a_bits + 5 <=3D tcg_ctx->page_bits); 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Add more visibility to kvm_arch_on_sigbus_vcpu() to allow removing this define from any header. The architectures defining KVM_HAVE_MCE_INJECTION are i386, x86_64 and aarch64. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-18-pierrick.bouvier@linaro.org> --- include/system/kvm.h | 2 -- target/arm/cpu.h | 4 ---- target/i386/cpu.h | 2 -- accel/kvm/kvm-all.c | 5 +++++ 4 files changed, 5 insertions(+), 8 deletions(-) diff --git a/include/system/kvm.h b/include/system/kvm.h index 21da3b8b05..18811cad6f 100644 --- a/include/system/kvm.h +++ b/include/system/kvm.h @@ -390,9 +390,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id); /* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */ unsigned long kvm_arch_vcpu_id(CPUState *cpu); =20 -#ifdef KVM_HAVE_MCE_INJECTION void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); -#endif =20 void kvm_arch_init_irq_routing(KVMState *s); =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ea9956395c..a8a1a8faf6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -33,10 +33,6 @@ #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" =20 -#ifdef TARGET_AARCH64 -#define KVM_HAVE_MCE_INJECTION 1 -#endif - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b5d68c796b..35c16302bd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -35,8 +35,6 @@ =20 #define XEN_NR_VIRQS 24 =20 -#define KVM_HAVE_MCE_INJECTION 1 - /* support for self modifying code even if the modified instruction is close to the modifying instruction */ #define TARGET_HAS_PRECISE_SMC diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 0723a3933b..7c5d1a98bc 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -57,6 +57,11 @@ #include #endif =20 +#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__) +# define KVM_HAVE_MCE_INJECTION 1 +#endif + + /* KVM uses PAGE_SIZE in its definition of KVM_COALESCED_MMIO_MAX. We * need to use the real host PAGE_SIZE, as that's what KVM will use. */ --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352186; cv=none; d=zohomail.com; s=zohoarc; b=ifhJBjhMHU+dilxsdJbTQZJW96vIN0h7R8oxezbDuEFQ7Du9xe+rJxiBIdZxfyM5e3Yi1rVyRtlOFxEZASuo8ALA9rJqlikhDPu1UnA1QM7ypS/7eqBz+TLQPsdRVjNZtdts+oWojCUe0pt4bEJYiBBYPXgICblUKmGpNAvaavM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352186; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=e/M+JJq6ZWP2W3rE9cY5JRLQzGEcLqDNY6NmbDaK7f0=; b=OAA8Pu+DdxJ9083tmSmLWuhvmps0pq5qNz+kQYnMhvB1aoSpMLvGvjvNIyw8l8MTXxWBH8B32aQmbhNoUYfuLiOK+KdPlxmk+5TXyLdF9vi77YpZ9XTKNL8Pvl6E3EI+5C1JtdODPblhoOWFwNSPrUoPyQ4PEagsgXx4KYTD19o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352186445994.1179210935463; Tue, 22 Apr 2025 13:03:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JQo-0000rT-O5; Tue, 22 Apr 2025 15:37:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JP9-0005bw-3j for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:41 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JP6-00077i-O6 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:38 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-22c33677183so65837385ad.2 for ; Tue, 22 Apr 2025 12:35:36 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350535; x=1745955335; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e/M+JJq6ZWP2W3rE9cY5JRLQzGEcLqDNY6NmbDaK7f0=; b=ifF3VsRg9o4JZn1AvHwmciwP1+jhSFbPrUOqhiOv4u4DGIGOPJSzaLd909DI9KLwsZ NIn1mOgqLY1r8uWpiAb9FEYLeyY/GnIUiBtifsSvoieBMj6U+rPfAMSsBwaCiInrApp5 Vc17Li7QB760gnIR5vo6cZLFdBNOLV8H/z3G5rt6H7FUrpwUkuJ1jXPe01UKGkOU3pxj 22KfzR2SuHDIw9dgIoxuLiD8442ZxByxLsgpnLd54yEJKdIR7aTu6mqwxAbXqf94e+SS mjvl2KNSkczBFDvRxi2Ls9HnSQ6b4AiH57vG03qP1oBIz0dAeqNw1X1TWSJlfa5Rjfme KqGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350535; x=1745955335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e/M+JJq6ZWP2W3rE9cY5JRLQzGEcLqDNY6NmbDaK7f0=; b=E0pma3OPrUNW7s7xcSpN5obM7uzLhJhswOdcgeQ6RlvAfptgzjU10LpdAqPM5lxbFo pdoYJWFicjx9HIdVD4Mf89RlMtBxn9pZjR9IwTwzEJEqnYsVCKRJEndXdM9tSTTPBrqf rKbAq+ZhHwdyVH6PlobpHXmtjeP/TtABjUYamDdL+Uj8JSZL//bhs0oXrelOl/BBSS+B rG5rt4LjVNByyNuGMnPUCGOZog/hz0s2vyzGmhW40gmFePfgkVq22EKRaV2ZZTGBu17H XeLHl3T9XlOYt1mn69NcqoYLHdkpiagOMNaSw0acFDKln2slqGr0PVg3sAoepPyjk21x cpFQ== X-Gm-Message-State: AOJu0YwD2pbHWwEyprnmMoqp+AhqCpnJ6xh8+F6u7ptmq21+1mfLrtYB Y78SNTXM0ggRbVH3PzAV5RAWGTv4be75SKTzFlyPGIiAFK/1Y9ufuDWGEAjc1+kHz8dc2qeLfgp X X-Gm-Gg: ASbGncuVNf8NAHxCbkgoWCAFxqcDR0PMLidbaFfR6i6B22vJl8KeXIv4IaA2lqvBJwi +srjb89qFY256dAmonD8EEYo+UBIOW6KvXa4LyKKipfIm6FPCAvvzfolcGB9xfT5HidngJCNPVA ARj0j23rTkQ4pQc5IW2UMV49IFJP+J5D82e7bG3DpZyyLSiNyzOEYOQW8kRaQxqRA3YswwYA63c SORng1q5umyFx9xdMzHcnIJNsTuASKqVEl8oXhvA+GiU65AB72FIvedDNKA5Y39CNenu59g4z/z uVU2l5X/Z8lqVr4tH6jXDaPmCoGOHLxKJK3b6Px6WVXQV6uKDhzXFx/zNq73FxQiOE6b9OVxlEQ = X-Google-Smtp-Source: AGHT+IEPu4jJP6fIwNDnMXwqqy6Vlj3JPtM0CeUjHQWSMdg0R8uDfezC/UQ1plwTM9S+fgpl3EW8EA== X-Received: by 2002:a17:903:2c9:b0:224:2717:7992 with SMTP id d9443c01a7336-22c5360deb2mr247730255ad.33.1745350535233; Tue, 22 Apr 2025 12:35:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 114/147] exec/poison: KVM_HAVE_MCE_INJECTION can now be poisoned Date: Tue, 22 Apr 2025 12:27:43 -0700 Message-ID: <20250422192819.302784-115-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352189065019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier We prevent common code to use this define by mistake. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-19-pierrick.bouvier@linaro.org> --- include/exec/poison.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/exec/poison.h b/include/exec/poison.h index f267da6083..a09e0c1263 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -73,4 +73,6 @@ #pragma GCC poison CONFIG_SOFTMMU #endif =20 +#pragma GCC poison KVM_HAVE_MCE_INJECTION + #endif --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352741; cv=none; d=zohomail.com; s=zohoarc; b=XUhqljKd7hwrhdsfM5sGteiUuQ+WoyGmDDo6VrLlM2zY5/XFaMdAmpp8S5YBsRmJbOaLkfJ5Liymjph8gqrxUViLRAu95uAyNz+lDjx2lr/Of/LhNasSVCS1a7GHlhh0gDw8lN/1fUBYE/rhvLtpaz/OXjDQhkX5d0V6+U3By5A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352741; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fw918qmxQalPO99dinob5iJyGANUib3+dTX4jzZTubw=; b=keKe5Ml3L2bTNX6ac9DzpucL37R6/57BWHwDDkw4vVonQWviFirsHJNM7Vxevqqz3eybDoCKfnxqNAeRJPQoowVHBPuGD/rMZhoRLwtlxnKUYxKCxGKu2vQIIkOigOgzEiAWRcHQavZKxN6u63q7YW7Ug7CVV/S/O0yh/qzq6RM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352741067601.1704275974828; Tue, 22 Apr 2025 13:12:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JR9-0001Tl-VG; Tue, 22 Apr 2025 15:37:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JP9-0005bx-Bt for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:41 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JP7-00077p-9j for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:39 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-22435603572so60092595ad.1 for ; Tue, 22 Apr 2025 12:35:36 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-20-pierrick.bouvier@linaro.org> --- target/arm/cpu.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a8a1a8faf6..ab7412772b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -971,7 +971,6 @@ struct ArchCPU { */ uint32_t kvm_target; =20 -#ifdef CONFIG_KVM /* KVM init features for this CPU */ uint32_t kvm_init_features[7]; =20 @@ -984,7 +983,6 @@ struct ArchCPU { =20 /* KVM steal time */ OnOffAuto kvm_steal_time; -#endif /* CONFIG_KVM */ =20 /* Uniprocessor system with MP extensions */ bool mp_is_up; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351622; cv=none; d=zohomail.com; s=zohoarc; b=luBzwRBsp/ZL3HttELav5Ej4TVy5IaWbe/81/6mv15rRL7emkpab0MOBroIEOgNoFEX3GzkKpDJLDVKJ8uAgBhUHBvVBsUTqjiCEs4dwyIi8gvf41gApR3TD/fnxGj5WmUnB3e2YB1aPns68IQAoJNxgcCVDmMjLClVEhmVzrF4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351622; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0pNZiYfei49mNgpV0jBnyPLCIko49eVtkxL+ip5wtaU=; b=DdiaGxFBQ588qITK1VvC2ZbTmR8fZF5FnA+z2pDzLlvfE8ACY8ukHVunMg/3RojRpDJDfgICxVqr+R92qU0pf5+ZisL6Brja8e8Tdjpb4ubFwKisBssRxPzIX+x0rlwiJBx9rCeAa093mykM81R5MAhlYTi5RrZ9WuWlrpn8JH0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351622174377.2396870314608; Tue, 22 Apr 2025 12:53:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JRJ-0001gy-VM; Tue, 22 Apr 2025 15:37:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JPA-0005gO-1E for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:42 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JP8-00077v-3p for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:39 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2254e0b4b79so85259735ad.2 for ; Tue, 22 Apr 2025 12:35:37 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50fdf1f1sm88996795ad.237.2025.04.22.12.35.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:35:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350537; x=1745955337; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0pNZiYfei49mNgpV0jBnyPLCIko49eVtkxL+ip5wtaU=; b=Si3sFgLCwwZ/TT0eI7EgmGV1bYKHaUjEptL6bsQzTawg1LykusKkReIVxgcBBDReW8 DyXdfwS7XkFgBp9Cw/5cUGjctEJvNGPfg7E4UW9yIF8h8DUuZsXnF3l7vIFE5K1IZjGZ ftkw4XCkDuPpWo2wPCfkEzsl3f7YlBmK4cLv0u2PtqBGDnQz42jtUDIulg+Hdqa3UEJG Kg6hOL+ePzAKJLF7IsccPQ6H8jRD8Wb2kk8VgG5EWIQOWzzLzauB50G++niTY9VFHtVM 3YMEDgykOoGjAZe2nzzOZODkewPovVvqG3muR8Va/56g+xAmmEm46LWeIL2W/ZKadEP/ l8Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350537; x=1745955337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0pNZiYfei49mNgpV0jBnyPLCIko49eVtkxL+ip5wtaU=; b=sRbDMe+LdL4d8h4oP/kE2DLq+97J7n1xg7Ls2jbMdUisoIJ/7QY/eqZ7yrdXtR0O/F YXwGfqI7FDx6JTmKZU/SmRsyFqszedPL4Wlzqfm1skBiOiDPsyUE2hI06mty4DpbWh9N 5S1Yei1TSX2RvpU7dECp8CtodgEPaX5HolxyHD3KH8tKn6UfQ6iV7kRrbqJNSZ/dVmqG l3ornJBhLl99lt2TJTbjngesJxw0RaaHYSuXK/TRkPdtxlH8RVxaykSDC05WR/ikJYPW Hv+LBJ7eGAbADDsEkpVBfWHDoT9H7LctO82FgCTYA6WddHOMnUBOUlCmuHi02ErRu8Ae M/LA== X-Gm-Message-State: AOJu0YylzqK/n3x8Lx3eJxXG7OgsQ7wdo/IIP17Vx4UGAjGowZr9SEQ2 lsTo3xlkCgdWx56aJ3xSbWBItgzDb8ItyuaLb1pijkfUgKvPBmgkFKvQ7KdxREbpSf7q8wofkJD S X-Gm-Gg: ASbGnctg2vYa5TvUFvLrcLzspoA7PDyGR/RPJnKsGzy/Bnq81CCV7zpwSx2eycvYLRP K5M55DnDbUdhrHcKw/b/qOBDiQYeEhcA9aUyBVUnJxaI0dVMK3RScsNN2o130qhTlnFtDqQs0X7 nobuO2mf+6oJDwqMzjJ1sIiCyBXIYlrs1fFFS2J4nA8wgsbsyUGBiAhDhoVL+1SZrzpZy4DA4uP RaCyaSX94/+R5j+3LCNWpJdMH6ZuEWgZdJiOWtaybyhzv7xb5gHYcWmfkkbbSCq6TIKZipKr9Xx OJgcHmdxTejw520LsnE/6Cj3OxE4IY8FpuZ+mM9Y9KzfxcbT7WhIQ9qeOQBRo0lQmh/WCU28b5U = X-Google-Smtp-Source: AGHT+IGKO0lS6MmlVukS2kjxI+/y4wMCSvnucGmYgnjwyvOlTSFB/qDy91Kwyjneyu1HbTjNBxunqA== X-Received: by 2002:a17:903:191:b0:21b:b3c9:38ff with SMTP id d9443c01a7336-22c53607e15mr229572985ad.37.1745350536661; Tue, 22 Apr 2025 12:35:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 116/147] target/arm/cpu: flags2 is always uint64_t Date: Tue, 22 Apr 2025 12:27:45 -0700 Message-ID: <20250422192819.302784-117-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351623772019100 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Do not rely on target dependent type, but use a fixed type instead. Since the original type is unsigned, it should be safe to extend its size without any side effect. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-21-pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 10 ++++------ target/arm/tcg/hflags.c | 4 ++-- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ab7412772b..cc975175c6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -194,7 +194,7 @@ typedef struct ARMPACKey { /* See the commentary above the TBFLAG field definitions. */ typedef struct CPUARMTBFlags { uint32_t flags; - target_ulong flags2; + uint64_t flags2; } CPUARMTBFlags; =20 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; @@ -2968,11 +2968,9 @@ uint64_t arm_sctlr(CPUARMState *env, int el); * We collect these two parts in CPUARMTBFlags where they are named * flags and flags2 respectively. * - * The flags that are shared between all execution modes, TBFLAG_ANY, - * are stored in flags. The flags that are specific to a given mode - * are stores in flags2. Since cs_base is sized on the configured - * address size, flags2 always has 64-bits for A64, and a minimum of - * 32-bits for A32 and M32. + * The flags that are shared between all execution modes, TBFLAG_ANY, are = stored + * in flags. The flags that are specific to a given mode are stored in fla= gs2. + * flags2 always has 64-bits, even though only 32-bits are used for A32 an= d M32. * * The bits for 32-bit A-profile and M-profile partially overlap: * diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 8d79b8b7ae..e51d9f7b15 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -506,8 +506,8 @@ void assert_hflags_rebuild_correctly(CPUARMState *env) =20 if (unlikely(c.flags !=3D r.flags || c.flags2 !=3D r.flags2)) { fprintf(stderr, "TCG hflags mismatch " - "(current:(0x%08x,0x" TARGET_FMT_lx ")" - " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", + "(current:(0x%08x,0x%016" PRIx64 ")" + " rebuilt:(0x%08x,0x%016" PRIx64 ")\n", c.flags, c.flags2, r.flags, r.flags2); abort(); } --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351500; cv=none; d=zohomail.com; s=zohoarc; b=nfm7GGWFFjjW8oVSt66dR6+VH/VLZZ3SC893iD0B/WcKeYS20TkBJFlv2hUCMlp9Ghh6dk1boYPGb7P/GZ9y6Jmnl3hk6jRspYWQ2HkE7T15rhkhsTvkwVEuOX7sP2VXbbVSrm2V3SdY9NshTC7WOUH5rFnUxXZU+vq1nAFef8g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351500; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=msXtfBhGOXcEDb7wOAfBlBKK4V40wttZa0c5PZCnz/Y=; b=N2U615dXTtP9gudjHjCqXyOb6yqWrAUpLn7tPz39dSLWDELLk3zuzrgKek6F96CoKSNyYYrzCh7TEdsRoQxIw1TIqLLzm3ij8rbJBcDx/iYpy8lQ0CxtsORMdWZ2c+mWmAw0GkStB2ToThJD7Jp20/64uWIDhHKn+/P3tCgyrAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351500476736.1639771283469; Tue, 22 Apr 2025 12:51:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JRE-0001Yy-Rk; Tue, 22 Apr 2025 15:37:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JPB-0005iP-FK for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:43 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JP8-000787-Lh for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:40 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-22401f4d35aso62185215ad.2 for ; Tue, 22 Apr 2025 12:35:38 -0700 (PDT) Received: from stoup.. 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Added registers are used only by aarch64 code, and the only impact is on the size of CPUARMState, and added zarray (ARMVectorReg zarray[ARM_MAX_VQ * 16]) member (+64KB) It could be eventually possible to allocate this array only for aarch64 emulation, but I'm not sure it's worth the hassle to save a few KB per vcpu. Running qemu-system takes already several hundreds of MB of (resident) memory, and qemu-user takes dozens of MB of (resident) memory anyway. As part of this, we define ARM_MAX_VQ once for aarch32 and aarch64, which will affect zregs field for aarch32. This field is used for MVE and SVE implementations. MVE implementation is clipping index value to 0 or 1 for zregs[*].d[], so we should not touch the rest of data in this case anyway. This change is safe regarding migration, because aarch64 registers still have the same size, and for aarch32, only zregs is modified. Migration code explicitly specify a size of 2 for env.vfp.zregs[0].d, VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2). So extending the storage size has no impact. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-22-pierrick.bouvier@linaro.org> --- target/arm/cpu.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cc975175c6..b1c3e46326 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -169,17 +169,12 @@ typedef struct ARMGenericTimer { * Align the data for use with TCG host vector operations. */ =20 -#ifdef TARGET_AARCH64 -# define ARM_MAX_VQ 16 -#else -# define ARM_MAX_VQ 1 -#endif +#define ARM_MAX_VQ 16 =20 typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; =20 -#ifdef TARGET_AARCH64 /* In AArch32 mode, predicate registers do not exist at all. */ typedef struct ARMPredicateReg { uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); @@ -189,7 +184,6 @@ typedef struct ARMPredicateReg { typedef struct ARMPACKey { uint64_t lo, hi; } ARMPACKey; -#endif =20 /* See the commentary above the TBFLAG field definitions. */ typedef struct CPUARMTBFlags { @@ -660,13 +654,11 @@ typedef struct CPUArchState { struct { ARMVectorReg zregs[32]; =20 -#ifdef TARGET_AARCH64 /* Store FFR as pregs[16] to make it easier to treat as any other.= */ #define FFR_PRED_NUM 16 ARMPredicateReg pregs[17]; /* Scratch space for aa64 sve predicate temporary. */ ARMPredicateReg preg_tmp; -#endif =20 /* We store these fpcsr fields separately for convenience. */ uint32_t qc[4] QEMU_ALIGNED(16); @@ -711,7 +703,6 @@ typedef struct CPUArchState { uint32_t cregs[16]; } iwmmxt; =20 -#ifdef TARGET_AARCH64 struct { ARMPACKey apia; ARMPACKey apib; @@ -743,7 +734,6 @@ typedef struct CPUArchState { * to keep the offsets into the rest of the structure smaller. */ ARMVectorReg zarray[ARM_MAX_VQ * 16]; -#endif =20 struct CPUBreakpoint *cpu_breakpoint[16]; struct CPUWatchpoint *cpu_watchpoint[16]; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352874; cv=none; d=zohomail.com; s=zohoarc; b=RCQmCQ50yBiq4wpWb1WDohauw0sll217XXeV79RbRY05wAP6O745q0YWGsHEQ5T9NDrQANvvK4jLercBZxcr/2eS23fruTFMOuwBcCz146ikXbDysQ/Nvp8QzNSY+utGb+spNvjgMFRYZdFCU35q9U+Sol+k+IA1xniB9t4KGVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352874; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hyzHc3eX2pZAMrT5P/TXvsGD8d5rYU2E84wns2dz+CQ=; b=KR49/Jyj8qYwc5meauZpPy9+zKA/DgKwmx0SZ4/CdBAe4s2XWVTXee4fybj/qQq6/Q01NvcOyt8H0D5RK2cnnT+tFsgYqpbLX70M8sZkAhvsCNPGuwUlZxJBm2lXIFiOS242Oek/terHq/UQvWSj0tEopiZw6m3DbA8OEETGXd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352874206671.8271145937069; Tue, 22 Apr 2025 13:14:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JSQ-0004DL-HT; Tue, 22 Apr 2025 15:39:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JPB-0005iO-F6 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:43 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JP9-00078H-Di for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:41 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-22c336fcdaaso62424675ad.3 for ; Tue, 22 Apr 2025 12:35:38 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-23-pierrick.bouvier@linaro.org> --- target/arm/cpu.h | 8 -------- target/arm/helper.c | 6 ++++++ 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b1c3e46326..c1a0faed3a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1222,7 +1222,6 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, */ void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); =20 -#ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); @@ -1254,13 +1253,6 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, u= int64_t *src, int nr) #endif } =20 -#else -static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } -static inline void aarch64_sve_change_el(CPUARMState *env, int o, - int n, bool a) -{ } -#endif - void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index becbbbd0d8..7fb6e88630 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6563,7 +6563,9 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ new_len =3D sve_vqm1_for_el(env, cur_el); if (new_len < old_len) { +#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); +#endif } } =20 @@ -10628,7 +10630,9 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) * Note that new_el can never be 0. If cur_el is 0, then * el0_a64 is is_a64(), else el0_a64 is ignored. */ +#ifdef TARGET_AARCH64 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); +#endif } =20 if (cur_el < new_el) { @@ -11640,7 +11644,9 @@ void aarch64_sve_change_el(CPUARMState *env, int ol= d_el, =20 /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { +#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); +#endif } } #endif --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352404; cv=none; d=zohomail.com; s=zohoarc; b=mWiGkOpGOQw5XbfoxWvjsCwp0fTFiEN/r1QrSQvVHfpcDhUj6YWWdVnq42B0IjZ3FItvP0FQMG1Z4gY2/QSeHjVS6aPsPregsl7qWVoQP/wjfgAwgEuEhHAfmOJNo9ZE1Fm7/ZOnOS8t9M0zmghWomFeU5tDgrRVqfzKL4eoA4o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352404; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=34NdhhU3f0ctFhHISwM+Va89Ek8XPnoY2t73ZYMcmeo=; b=j2Kf89zuWgkCOp/lx7m0GS/qqREDXPYq8BUEYvcfrBo2GWiVEz7MOW2JiNqzrJrCChnTEoyvtLUZg+4Z6P2/aY9KPjdJV7uJirRGaqbrCXgkzFKbwW9cymkr3gEYv81RnFRKUfistwIpR7t9WjksXVuMTGevUNqY9Y5fYogGq3o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352404210865.5720413777647; Tue, 22 Apr 2025 13:06:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JRI-0001eW-No; Tue, 22 Apr 2025 15:37:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JPD-0005kG-7k for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:45 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JPB-00078U-6B for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:35:42 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-22d95f0dda4so23679335ad.2 for ; Tue, 22 Apr 2025 12:35:39 -0700 (PDT) Received: from stoup.. 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We make sure to not include target cpu definitions (exec/cpu-defs.h) by defining header guard directly. This way, a given compilation unit can access a specific cpu definition, but not access to compile time defines associated. Previous commits took care to clean up some headers to not rely on cpu-defs.h content. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-24-pierrick.bouvier@linaro.org> --- meson.build | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 657949326b..bcb9d39a38 100644 --- a/meson.build +++ b/meson.build @@ -3682,6 +3682,7 @@ hw_arch =3D {} target_arch =3D {} target_system_arch =3D {} target_user_arch =3D {} +hw_common_arch =3D {} =20 # NOTE: the trace/ subdirectory needs the qapi_trace_events variable # that is filled in by qapi/. @@ -4079,6 +4080,34 @@ common_all =3D static_library('common', implicit_include_directories: false, dependencies: common_ss.all_dependencies()) =20 +# construct common libraries per base architecture +hw_common_arch_libs =3D {} +foreach target : target_dirs + config_target =3D config_target_mak[target] + target_base_arch =3D config_target['TARGET_BASE_ARCH'] + + # check if already generated + if target_base_arch in hw_common_arch_libs + continue + endif + + if target_base_arch in hw_common_arch + target_inc =3D [include_directories('target' / target_base_arch)] + src =3D hw_common_arch[target_base_arch] + lib =3D static_library( + 'hw_' + target_base_arch, + build_by_default: false, + sources: src.all_sources() + genh, + include_directories: common_user_inc + target_inc, + implicit_include_directories: false, + # prevent common code to access cpu compile time + # definition, but still allow access to cpu.h + c_args: ['-DCPU_DEFS_H', '-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOF= TMMU'], + dependencies: src.all_dependencies()) + hw_common_arch_libs +=3D {target_base_arch: lib} + endif +endforeach + if have_rust # We would like to use --generate-cstr, but it is only available # starting with bindgen 0.66.0. The oldest supported versions @@ -4244,8 +4273,14 @@ foreach target : target_dirs arch_deps +=3D t.dependencies() =20 target_common =3D common_ss.apply(config_target, strict: false) - objects =3D common_all.extract_objects(target_common.sources()) + objects =3D [common_all.extract_objects(target_common.sources())] arch_deps +=3D target_common.dependencies() + if target_type =3D=3D 'system' and target_base_arch in hw_common_arch_li= bs + src =3D hw_common_arch[target_base_arch].apply(config_target, strict: = false) + lib =3D hw_common_arch_libs[target_base_arch] + objects +=3D lib.extract_objects(src.sources()) + arch_deps +=3D src.dependencies() + endif =20 target_specific =3D specific_ss.apply(config_target, strict: false) arch_srcs +=3D target_specific.sources() --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351828; cv=none; d=zohomail.com; s=zohoarc; b=cVdMv6i/zMzaXlBaYOQ7pU3t2GUdnsamBWRUObv+dA51T/cupU+ePwlANxcRYRwylF/eUfb/oxe7qy6qeliR56K3iF4TENH50Y62vXhoeOCmasHhZ1qzJHf12a4DINixsRK5U6IFPrFwOs4INzSf6pwv3Kkmc1cIxFhsaSrzfmY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351828; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tMTFwuyzTM5DV5D1Qj0NNV6OmW0mRELjIvfKoj8LUWY=; b=OadCiHsMFRO9DhJ+R1vCkeb+cStQ+oVPSjRBif4VXecuAQ9Zx06IkggEu0PLdrSQqSQ2+SIDd2aZGgfvdm0ElcQM+NHMOUnuQpNV72yzfcCZCOQjiuzKPVqDufiYF3qBPvbzHRCSlB6+MqLokLJQKTwK5sjhSzxp3W9djqVcs9I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351828415967.9648134871067; Tue, 22 Apr 2025 12:57:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JSl-0005BQ-V1; Tue, 22 Apr 2025 15:39:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JS7-0003vz-Q9 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:45 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JS5-0007IO-Q2 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:43 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-2241053582dso78372485ad.1 for ; Tue, 22 Apr 2025 12:38:40 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350719; x=1745955519; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tMTFwuyzTM5DV5D1Qj0NNV6OmW0mRELjIvfKoj8LUWY=; b=EYvNhVN8fugpqoaeWNsRn1EI7hciWnaSaf7qvCE3onk9pFJBp2Bhaa/Jrm2e7sO5OP x9rliRXU1AqW0WfltgkTGJsngFASzYPrID+ncv3hCgIR+xNJc3Dt/WB/yOGMlPcyCbXL ufY6VkrF5ajSyo1w/zlnrRO/fDctgr0hf/DJ/q1iwS1zVN05pOSJrVQ/5rqC5bTr7umf pNVqsa3FhTrODh+dem9iHJgPnE7/AW5wDtC1UIJgF6oU+/C6c/qeCmi04G0p3K7SV4r7 EGlPiQgTgL+bGFWlF+nMVeTrCy21XOsoaFv6gGjdP8zVg/q+j1TrKkHQ+Zh3WAWGMSiA 0lZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350719; x=1745955519; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tMTFwuyzTM5DV5D1Qj0NNV6OmW0mRELjIvfKoj8LUWY=; b=Y2zZ8X0uAvsqBsI/Zxw4dUZ0YrIl65JB/jGXbzmreHNUZnA8aQGLYaF34eIPS0Iypz 8Z2D8AQbTbFlf5Iw9phdreaovkWUuROKQEq3j35gQfShaodohC+Jb7wdQplVyB1e/t4L sgudFNpbITDCqNBnskHIKelurQHXfDzLl/sgFiuoUhRkOtRcDv7h3WIpK3uhnHJlIhoc 95c5IXcjPlt75f2P9gl+qXhyM556vWzDX/FrBfhUXu96sOGUI+uUMzRkiupnnK3bphr+ jLsiYya+FzUI4j8g6Vy5DPXs4B6k0HFs25rSXEoxQNw/0SxcRESzzX9SZvNK3noruNcR 8k1A== X-Gm-Message-State: AOJu0YxRZF7x5ry/Cddh4W3mf0qAkvCwmCJKYwy9bpWxWZVQTV8ExHaC zXeEafBcTJ4PkYrujrnq6ftF+ehZAb2wgTA3rK2DOw3Igpx0s7UryI39uC4Aypzd/rgCwlAdm6Q h X-Gm-Gg: ASbGncv+w0daXq3Q4CDlNE5/CjOy1ywP7TFshiv5XlDwVV+2aQL4qyEhaepAzr/erSu TwFpnrOvnOg4KlR628hbTTfRMdBpBs5u3XRhuJB5LbkRDk6kEa4wxSvb3zjCuJkkUQQ81/dStfr yH09dRY76yXWYSNc4hRPCeXucjVnLi8Ai44auXPmAey6boFCy33jjLfkdAkqTzUGKzcFuolQNHI YfVWievsbb/bvW91aI42DqWCODDSNZwXNFfjMJz5lTv01MlRRS6p3DkvDVcTW6JLvJeRz3zUT2s s+VC3QrbEot22FB2c68u+6E0a0TLP371CMkCc4FQ2LhdbUIn0P+rphhgJcjgVIJ5yvgzR+9tyUE = X-Google-Smtp-Source: AGHT+IGqiEYtNYiaV4khTuda/U5/nITNMgyGzCrm2Qum37sDNZY2jHDNpUflJdgSaAMSTJXEHjQObw== X-Received: by 2002:a17:902:c40f:b0:21f:74ec:1ff0 with SMTP id d9443c01a7336-22c5360440emr247189425ad.32.1745350719556; Tue, 22 Apr 2025 12:38:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 120/147] hw/arm/boot: make compilation unit hw common Date: Tue, 22 Apr 2025 12:27:49 -0700 Message-ID: <20250422192819.302784-121-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351830154019000 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Now we eliminated poisoned identifiers from headers, this file can now be compiled once for all arm targets. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-25-pierrick.bouvier@linaro.org> --- hw/arm/boot.c | 1 + hw/arm/meson.build | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index d3811b896f..f94b940bc3 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -14,6 +14,7 @@ #include #include "hw/arm/boot.h" #include "hw/arm/linux-boot-if.h" +#include "cpu.h" #include "exec/target_page.h" #include "system/kvm.h" #include "system/tcg.h" diff --git a/hw/arm/meson.build b/hw/arm/meson.build index ac473ce7cd..9e8c96059e 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -1,5 +1,5 @@ arm_ss =3D ss.source_set() -arm_ss.add(files('boot.c')) +arm_common_ss =3D ss.source_set() arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) @@ -75,4 +75,7 @@ system_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx= 1.c')) system_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) system_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) =20 +arm_common_ss.add(fdt, files('boot.c')) + hw_arch +=3D {'arm': arm_ss} +hw_common_arch +=3D {'arm': arm_common_ss} --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351391; cv=none; d=zohomail.com; s=zohoarc; b=LztM+XtzGQwzv3HvYlNPiJEnHq34ZAyMwo42Pf6RYo7SXafhuM+K6yoYpflCNZs46lpNH1/A1SAnKc1whFVafl7meFSCYHvuw+5T5nciNxTQmoby108bE9z9yeToUXLwINQN/TFvhDvbvJP3DQnC8XMX/16qe3oPAe/jtzmIzwQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351391; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Z6H/GoAoFwszVT4TvnJT7Vzq/vNV9Nxqb0K+QM0Htps=; b=kC1upcvawuJjcykvnZfPVm/3rM58IWgrXFScROI9LfnTHNNuIfFcAEwGixe33qHGUs5VAjFucpyIjQUIfkVkPdbkMzeUlHEvMcv3LtgiKIPN9kUKYIwM3M5FJQOBWw9WQ9FgFdg5o31Fr6WjsqoqXYflUq+j+nIJpG+KB2FxHiU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351391602463.1531909987614; Tue, 22 Apr 2025 12:49:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JSG-00044p-F7; Tue, 22 Apr 2025 15:38:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JS7-0003w2-QE for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:45 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JS5-0007J1-Qq for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:43 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-22435603572so60128505ad.1 for ; Tue, 22 Apr 2025 12:38:41 -0700 (PDT) Received: from stoup.. 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charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-27-pierrick.bouvier@linaro.org> --- hw/arm/digic_boards.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 2492fafeb8..466b8b84c0 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -80,7 +80,7 @@ static void digic4_board_init(MachineState *machine, Digi= cBoard *board) static void digic_load_rom(DigicState *s, hwaddr addr, hwaddr max_size, const char *filename) { - target_long rom_size; + ssize_t rom_size; =20 if (qtest_enabled()) { /* qtest runs no code so don't attempt a ROM load which --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-28-pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/xlnx-zynqmp.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index d6022ff2d3..ec2b3a41ed 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -22,9 +22,7 @@ #include "hw/intc/arm_gic_common.h" #include "hw/misc/unimp.h" #include "hw/boards.h" -#include "system/kvm.h" #include "system/system.h" -#include "kvm_arm.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352214; cv=none; d=zohomail.com; s=zohoarc; b=JobreotTWeHpwgDC8kkNrnTPhpm+8PvYtRN7KmOH7f1wmsvFHpwS8C1HSI+TnWHInxl3S02TL+jrJpPVBDOiO9uYdQtMTqa1ps7WRGjrLXuH5FZHCwjPjVLw0mzWjOka+7n6fLftpVSVF7IoUcoih+bSYodvqd2ALYciZGXPZ7k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352214; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IzxhDXQ8yhw3qgxUo2QDT1zA0vlXRiIUxtrypSczyWI=; b=R8BhdgvzN/jeWuHRhM+5DrHaYHDYuQFqxe9RNPDsjfXE8+1bdp2HJrWKk0eduBfBulY5LsHmMy6Gvheu394T1bBInjZ3k2jo9PwvsvNTqYFYDfnvNu4M8kX6WxkoK6WzEY/c+WPwtpwjGiFgdoGDDrU/UzfnHwAy55QkwL3ud4g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352214354441.302192987803; Tue, 22 Apr 2025 13:03:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JSU-0004UB-06; Tue, 22 Apr 2025 15:39:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSD-00042t-1h for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:49 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JS6-0007Jc-V4 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:48 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-227b828de00so60307375ad.1 for ; Tue, 22 Apr 2025 12:38:42 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350721; x=1745955521; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IzxhDXQ8yhw3qgxUo2QDT1zA0vlXRiIUxtrypSczyWI=; b=FUYF+AXhJORIGnVcv7zRf6y1qlZZrf2eMN04pIsY/TmqbkwQhm6q0MLgaYd3HYCLUe GVhSOrc28TlWBFDqTjq10X4Tvb7r9Oei8wZW0R8k0lR21Hy9SiOpRnvk7iTdTzjZB2fa BRRP1pXBA1y53EmZmjiyibKp57GCPbta5T2hV1FrM9uOfRsqHLdeoGfuF01DudUXia1K F3dQlxxRsmgYXyEOVsV3Fc8gChwsK1RYDrYZWdxmZTqffAIX/8VEPUfxoE7V+xmj4r0L 4a4laMAqu09cqnaYM/OWK4sFSZo4M1qMjTegm6V5N0YLU6AHIb/eSdKixnq63jvWpBDz ev8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350721; x=1745955521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IzxhDXQ8yhw3qgxUo2QDT1zA0vlXRiIUxtrypSczyWI=; b=rzqiUPg41vR5D+7AqF9LkNJQ1llaGoVgsYkHoNm7JZIafJoF36O9klpDEGrbmdFiIG GARaScyQ9gxHlCpxW2xCn/VtmrXN5kmTgPHmbi/QtMMALHHZI+n+S7QYfVTA0xxcE3CC pqGn+UEzF334zxpograv8AgTsabxLa+0pakyxFYX16onqBg8azlpfCHf9qZe61GsXrHY dUksszGITRIvlJBo4GWOHKe+l6edcViQpdN6u2M9LOvSKcTSPpGxN0NWBn+KFFXfJLE6 97fsSYugLj+KqYIfmlwm5ySlkd1nwmndmqehrw8KX3ZTrmQqkmz8ZBeIDNYB18EiL1Yz D/pw== X-Gm-Message-State: AOJu0YxVpx4jQTnKRKex24YvOpYASEPigJrD60OzazsMbyhSoxO8y9tp M22qEwouPG1/re7D+xlbrmhh/JMcllsyymR/rPSy9yF7fzrLr4W5sMtwrz4w8gk7BNu8mlFJGt9 C X-Gm-Gg: ASbGnctUsapdpxgmK97X659d5hwbsCt6P7+ftW3KuBSMpgB6bMbJJZUBNaZQY6fXMFw VFn9BTajAXnSqX6YQSpKhQZiCzE4MNxFlP90zIIP0WmMFE3AEyJaIuTtW23EVJuAz80/NylLLkM nZwCRqmh6qwXag5eW5lWXPP81RwH4lSQC1HNQFv8GDUKbvyGiHzkjtS434Du6/zHrO6YMjiz+UK 48oNbOmFOsj7XeHPN/XteG0XhS8vaAFcuzM63fXVCkK98ugxaaxsH9yGOOc4FRgoH329Dktlcs5 gnusep9iwlO54nzTXAYE5sqXfnGW+ydBSeDnyUkGjI6nwcsObRKUQEVDUBvohzlafcwXzTqmMiQ = X-Google-Smtp-Source: AGHT+IGbtiicSLiPj/cD3gtYnscBp0+vVys6yrQTwSEKVHdD87NXX0KuKpIJ7tRabBFiM81u4PsCDQ== X-Received: by 2002:a17:902:cec7:b0:224:584:6f07 with SMTP id d9443c01a7336-22c5360772dmr221935605ad.37.1745350721373; Tue, 22 Apr 2025 12:38:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Pierrick Bouvier Subject: [PATCH 123/147] hw/arm/xlnx-versal: prepare compilation unit to be common Date: Tue, 22 Apr 2025 12:27:52 -0700 Message-ID: <20250422192819.302784-124-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352216093019000 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Remove kvm unused headers. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-29-pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/xlnx-versal.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 278545a3f7..f0b383b29e 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -17,9 +17,7 @@ #include "hw/sysbus.h" #include "net/net.h" #include "system/system.h" -#include "system/kvm.h" #include "hw/arm/boot.h" -#include "kvm_arm.h" #include "hw/misc/unimp.h" #include "hw/arm/xlnx-versal.h" #include "qemu/log.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351787; cv=none; d=zohomail.com; s=zohoarc; b=Xkzu/D/hlHf+RGfAL3FJ0Np3WOiZVTEJaC+1oLUoVeSKOlHvS1Lvi6DTIeLrseEVFDBeNgqAkUL03+5No30TwkELFfNui31uauQHonvaM85PpOu9r3Qy3JDzFFLyv93T1USsjbmfoRhvbQflFSi3bj9JpQyljPjr4Xms9rEBAFo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351787; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=k6epK1kHVGM7DWadqrW/21XmOu9df43IQ+8cLDy78ic=; b=Zk4hrJ6J7L7koi9grSgHm+coiw0PXfRmsRnhFBaLzrxF5uL6jpGMyUTnSS1n8AJ6G8et8GdO1t9s/TfD7JLUMqEpf7GV0tXgXu3B0BR27t8y18hVSeTfa9i1Kvw5wcXPTV2LM5yWgWBHSvRpF4LRLCk3WjduJgK8fgwkwabTjLs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351787377452.67467676087597; Tue, 22 Apr 2025 12:56:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JSS-0004SF-TY; Tue, 22 Apr 2025 15:39:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSA-0003yi-Bz for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:47 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JS7-0007Jl-OA for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:45 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-227914acd20so1954045ad.1 for ; Tue, 22 Apr 2025 12:38:43 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Pierrick Bouvier Signed-off-by: Richard Henderson Message-ID: <20250325045915.994760-30-pierrick.bouvier@linaro.org> --- hw/arm/meson.build | 112 ++++++++++++++++++++++----------------------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 9e8c96059e..09b1cfe5b5 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -2,43 +2,43 @@ arm_ss =3D ss.source_set() arm_common_ss =3D ss.source_set() arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) -arm_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) -arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) -arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) -arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) -arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c')) -arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) -arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) -arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-= h405.c')) -arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_bo= ards.c')) -arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c', 'npcm8xx_bo= ards.c')) -arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) +arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) +arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) +arm_common_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) +arm_common_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.= c')) +arm_common_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) +arm_common_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c')) +arm_common_ss.add(when: 'CONFIG_MUSICPAL', if_true: [pixman, files('musicp= al.c')]) +arm_common_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinopl= us2.c')) +arm_common_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex= -stm32-h405.c')) +arm_common_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npc= m7xx_boards.c')) +arm_common_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c', 'npc= m8xx_boards.c')) +arm_common_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) -arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) -arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscove= ry.c')) -arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) -arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) +arm_common_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) +arm_common_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vl= discovery.c')) +arm_common_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) +arm_common_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) =20 -arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) -arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c')) -arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c')) -arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c')) -arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c',= 'cubieboard.c')) -arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', '= orangepi.c')) -arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c',= 'bananapi_m2u.c')) +arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) +arm_common_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c')) +arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c')) +arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c')) +arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-= a10.c', 'cubieboard.c')) +arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h= 3.c', 'orangepi.c')) +arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-= r40.c', 'bananapi_m2u.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) -arm_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm28= 38.c', 'raspi4b.c')) -arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) -arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) -arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) -arm_ss.add(when: 'CONFIG_B_L475E_IOT01A', if_true: files('b-l475e-iot01a.c= ')) -arm_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_soc.c')) -arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c',= 'xlnx-zcu102.c')) -arm_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'xl= nx-versal-virt.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_= pdk.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'= )) -arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) +arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files= ('bcm2838.c', 'raspi4b.c')) +arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_= soc.c')) +arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_= soc.c')) +arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_= soc.c')) +arm_common_ss.add(when: 'CONFIG_B_L475E_IOT01A', if_true: files('b-l475e-i= ot01a.c')) +arm_common_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_= soc.c')) +arm_common_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zyn= qmp.c', 'xlnx-zcu102.c')) +arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.= c', 'xlnx-versal-virt.c')) +arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', = 'imx25_pdk.c')) +arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', = 'kzm.c')) +arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c')) arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed.c', 'aspeed_soc_common.c', @@ -47,33 +47,33 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast10x0.c', 'aspeed_eeprom.c', 'fby35.c')) -arm_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('= aspeed_ast27x0.c')) -arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) -arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) -arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) -arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c')) -arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-= sabre.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c')) -arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) -arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcim= x6ul-evk.c')) -arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) +arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: = files('aspeed_ast27x0.c')) +arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c')) +arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c')) +arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c')) +arm_common_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c')) +arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) +arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'm= cimx7d-sabre.c')) +arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'= )) +arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) +arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) +arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_ss.add(when: 'CONFIG_XEN', if_true: files( 'xen-stubs.c', 'xen-pvh.c', )) =20 -system_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) -system_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) -system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) -system_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) -system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'= )) -system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2838_peripherals.c'= )) -system_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) -system_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) -system_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) -system_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) +arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c= ')) +arm_common_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) +arm_common_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c= ')) +arm_common_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) +arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripheral= s.c')) +arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2838_peripheral= s.c')) +arm_common_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) +arm_common_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) +arm_common_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'= )) +arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) =20 arm_common_ss.add(fdt, files('boot.c')) =20 --=20 2.43.0 From nobody Thu Oct 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350723; x=1745955523; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Judoew0yyRM+ZQdcs+U7k7YNBkFAe4iaEkKni645IrU=; b=plLJg203C4IacsbSeZoFAP74DZms0SqwdQ9qbF/k6ZP1xMw27ORjkn+RM0tqbNjKrs YFw2J9NtgWYvrtQBQrBcBMDurNI4R9XIjZcN09UCdnasRZXlpBYU9++NdU7mPX8mUc28 VWc0KFab7epiZAbFyX691B65yfh/9hvTKf5xbFOgZVY2V6wzDCr+jCpMDQG4ll4pdmJG QtwWIaoavHK4HvG9aZxdV3QvvoSYWfJy8u4hooHkxbDMjq6KEees0KhrRSgKmySqSvmG S6ns2+nrE7B4Ww1eFv+XGPuduq4QyNH6Xj6SfMquMuDB3RVGbhxWO/tYOPcpEZISP4Rk eyMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350723; x=1745955523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Judoew0yyRM+ZQdcs+U7k7YNBkFAe4iaEkKni645IrU=; b=KdyDVEJj8Ql9TRVUiaulkHd2vMuaIbdcVTa1U0qGD2+c1XZVWxSSYHOSgoSEHkXz3v UXD7BDNEBTWKekaxz8ZbCQWg1BOJ9s7i+rrIwFGD4S+R0C+seJh6iyYhcpNsUOrIumva MMqCIEFa+UXsuTfAt1R3S3vp+7PushoXgobg+4AafODAntnIoxtpPFOSQZxf9kUEl7QN UqyprMAwlEpeKFaKDkiCOmT5H728lW8kylIaK06vI/Ud8ib6moj/6w02++Nx7JVYCaEr Dk17cqEucQR35pipJggal8L6MFOTVmEb7NE30Q4xGTQriSDbEnbtYT7tKrbCAKGjnMn4 1MLQ== X-Gm-Message-State: AOJu0YwFkbfFhu5/E5IuaEwbLAKjfXwdqQvzZ8bUMB7KS58Ct+h7ygWa l6G5MZnHYaMSqGzHCBbUAOWnPl/kleeR1txA58EMrGWmi0elN6xiPnPy21kdxgtqTl0kjaDXVWa q X-Gm-Gg: ASbGncsdMADDfnfB0vEYFBUma5mddgNtOTweQDAD6mqflCwaXBW+ABwAQSRJ3s4Jmog hlCOs7/nJL5VgeliBSWVuPTCUEM2m8Sm8EuM9EDcpTyKlv1Ek/RRoGG+xeZXMdxPxkAAk7gzy5v QCc3zVQ2Ruco7h2bmZIrghInllbsnQUk9tWZT3KLyA5StUmHOKP8+PqpVyuQw1Oc0sSq0kR6zIM 6VZ5uou4SDnnfnKMN8N1hwPOU2a8qfm8aMF5Gv+SkjiSoLDieBxdgjFlPNjR1ZtNNJqcB13eQS1 se0y59A9iLfV8SmV+/bhqmG0qIXAcbFGRr+HfrDbeVH12u6qddQbevRNsculh7BZBATh0a0cCcM = X-Google-Smtp-Source: AGHT+IGIEcL5Ju4FvRcR5+eAeXoYGCjLzcKRumWzc4fIs7ifNbn1v1AZVfqKacEPRMLVcZ4IDF/A3w== X-Received: by 2002:a17:902:ce01:b0:21f:7082:1137 with SMTP id d9443c01a7336-22c5357d158mr292873555ad.22.1745350722846; Tue, 22 Apr 2025 12:38:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 125/147] target/riscv: Do not expose rv128 CPU on user mode emulation Date: Tue, 22 Apr 2025 12:27:54 -0700 Message-ID: <20250422192819.302784-126-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352539781019100 From: Philippe Mathieu-Daud=C3=A9 As Richard mentioned: We should allow RV128 in user-mode at all until there's a kernel abi for it. Remove the experimental 'x-rv128' CPU on user emulation (since it is experimental, no deprecation period is required). Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 10 ++++------ target/riscv/tcg/tcg-cpu.c | 5 +++-- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 430b02d2a5..ad534cee51 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -697,7 +697,7 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj) #endif } =20 -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static void rv128_base_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -708,11 +708,9 @@ static void rv128_base_cpu_init(Object *obj) =20 /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); -#endif } -#endif /* CONFIG_TCG */ +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 static void rv64i_bare_cpu_init(Object *obj) { @@ -3255,9 +3253,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), -#endif /* CONFIG_TCG */ +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu= _init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 710449d17e..5d0429b4d0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1046,7 +1046,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(cs); - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); =20 if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name =3D riscv_cpu_get_name(cpu); @@ -1055,6 +1054,9 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) return false; } =20 +#ifndef CONFIG_USER_ONLY + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + if (mcc->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled()) { /* Missing 128-bit aligned atomics */ error_setg(errp, @@ -1063,7 +1065,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) return false; } =20 -#ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; =20 tcg_cflags_set(CPU(cs), CF_PCREL); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350723; x=1745955523; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zQn5pEpTklz98PI0kmgU6Xej9Zd0Hkqt6ZpcSg4eg/g=; b=kDhRHQWFdzlFFCzHjAAE12DUc5a5lwXo0jH7ogMkNnwGwSUwTxWPQsqKL1EO/a3bXI NixGYAAOxeDjZYNlJmjlLhFHPyuepb7cXc9zmF7WMR5gwjbP+sEgWX64e0A+6yyUtCzS N7Ol/MqG3p890KdnhGyu4r+4AXDFGMlTJi0joyEf2lms8ebuBM2FjNPiYR7hHxdXJwN9 m5gg/3+X2PLuCkBRPyC6D67DeHYcUHzjogJuvfMaICYlcD4ruCA/xX+/s832nl3ooGZX lzewnIOE4lWyUxGOkAS3TSEQELiGhmQVr8UrP/Rkvg9XYWP2QJdr60CsSp/tS7nH6d8y ZBwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350723; x=1745955523; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zQn5pEpTklz98PI0kmgU6Xej9Zd0Hkqt6ZpcSg4eg/g=; b=L/wVPNHC3/YhEMVJ1jSaxMqNLDrXQOI3X+oO9IUJyK7jsT5fbGGADojZVtr6YpKpyd vohaL85LB6OJvOLTGZOYsSxy+DgS68bAZWaw/FuyJhjtbaSY4vfKAnXweg1mTWpOII1j +j1DvTBSkcgSEWKfObdcgUxZO93XKnMBxaiw3xGd8OPywYXFnaelxJlimlJcW/3pWVDv kC1Bx54hOWDtMU1laTRxc6YqX8Br1pRSp6ifD68Dj/wmb2g3HHTwR0MM5tQ7RHm37BDe 2InVBuDQt85BGygM4dzO9e/daVf72ke5W2A1yV11jfk41h6pdm6CszIi9ggtJmcsyaqf ByPQ== X-Gm-Message-State: AOJu0YyUNYcPUy6JdktPu9YFeqlkku0fwYohDQMsE8nSlspKbEqou6em XUpfH/XBxf6I395rSu4vQRQHXaHIkvaGHDEpkGGUcwQIGAtHJPAoGMta/iSp0hbY33HMHibvjgk D X-Gm-Gg: ASbGncvARMsQYpwDJStLrHkFWkWFOKnLAbFsjM/cz5u3Z89EFA+HbCOs9xqD28EPz35 nmA2zPg+V7raKzCubaHnOjpO0ml8123MDmJBFANQQkOX0aIjtTXhbNTJUgrN/Q3ICybnUlLhJqO OxDJdr3MVTNG/KDtRPs6zWxgkugoDRH5t07Z9vGqe2Btc2ugFXOtTFqocDw63k8J7WSgHk5ycIS yE9QlIEL1efcBSfuWmwaY7Fh4zUl2YgONWmm/2R0JAZr3tnBn9oKS5yYPs4nRzZMCh2tmRsvtqE hV2SbSgRkOtHnJHrPkpICsfOH9mwoCCgk4eV2IZbkBpPrLh3KeDTqBy0Ad1IUAV0T+/cODAjw5Y = X-Google-Smtp-Source: AGHT+IF2JV24c5JD8YD5jpxofhhfvh6777+mLtCNprTRjJ/VIMctcf+V8hI20sBFui6VknZ4K6melg== X-Received: by 2002:a17:902:ce82:b0:223:6455:8752 with SMTP id d9443c01a7336-22c536420c6mr235540165ad.43.1745350723615; Tue, 22 Apr 2025 12:38:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 126/147] tcg: Include missing 'cpu.h' in translate-all.c Date: Tue, 22 Apr 2025 12:27:55 -0700 Message-ID: <20250422192819.302784-127-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351954514019100 From: Philippe Mathieu-Daud=C3=A9 tb_check_watchpoint() calls cpu_get_tb_cpu_state(), which is declared in each "cpu.h" header. It is indirectly included via "tcg/insn-start-words.h". Since we want to rework "tcg/insn-start-words.h", removing "cpu.h" in the next commit, add the missing header now, otherwise we'd get: accel/tcg/translate-all.c:598:9: error: call to undeclared function 'cpu_= get_tb_cpu_state' [-Wimplicit-function-declaration] 598 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 1 + 1 file changed, 1 insertion(+) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ed41fc5d0c..c5590eb695 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -69,6 +69,7 @@ #include "internal-target.h" #include "tcg/perf.h" #include "tcg/insn-start-words.h" +#include "cpu.h" =20 TBContext tb_ctx; =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351128; cv=none; d=zohomail.com; s=zohoarc; b=E0qkF/TyTaBimoNAOKTKCE1qR0jQk1DiHpY5OxoVgAPqNycb/0cug0pdEtH7GVhFw65d+iU95e7CVhMEygjjRqORSe0GaSn4BUoJ5CeJVZX5yfcrkFXQUjNocCMU4s6KRsGHT+wv+1l+wi01DOiFOTxinvAv2INZWxj2gr9D038= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351128; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=e0y04qvDeF5fLZ5d/2GBXABBXppk9F5Vs+m7MJCl/7A=; b=YqzneiQKfPfDY9fh19yQCe3ROLW4cS6ooitc7WxlLeKM92LgidFuIeGMsxPUAvdylQQFllr5noPM1w+TdsUe+hE9tBN0VzvrDnhAu52RifA1OR+e+2pVQ/W392IY7SCXm9YdjOv+ZBC2Y81FQ9EKRhI7KeSEDHQTsmQ10wfxoR8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174535112852132.020003135515935; Tue, 22 Apr 2025 12:45:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JSp-0005Lj-EZ; Tue, 22 Apr 2025 15:39:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSD-00042u-1e for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:49 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSA-0007L2-Fx for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:48 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-22928d629faso54300895ad.3 for ; Tue, 22 Apr 2025 12:38:45 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350724; x=1745955524; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e0y04qvDeF5fLZ5d/2GBXABBXppk9F5Vs+m7MJCl/7A=; b=D8Gxu1kyoMAsVpCwj7LaWa6K3E8KhnA8jHebpQxLrgzglv76cpPCow2P8VaxL6oARk UpvOliyK1laTsdcxmNpcGdZV6sVo0iOanGOTrF6QT/9V65yjqHXaYceNZ8HFv45/HV1J SU5KjQQ0mAkLLT9XoD7Uo4/G6qwU4WPK2NncjNzu8uE/su6aQPrKaiWKr6BYkWUDmefV 6Cnq6dHzguvzWJYm60Vz/h1G4Rk57bYkAnQ2LU9ZKv6sxzNHDp725K71hKt0KFVMLI8U rJwFsS0mHjXgISO337o9ldCMIRu3cP8205padsTjV1UeaAHJrmJBxxA0qs/JbQZKgg/S XJjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350724; x=1745955524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e0y04qvDeF5fLZ5d/2GBXABBXppk9F5Vs+m7MJCl/7A=; b=FOlw9a2qXoOf3pJZ6LlzsiqcqF3pyx9OJ/ifCnsjx+YLaisRAT1304eIYt8jVE1Lo4 Oq1q+L9H2vQaC4ommyMZ/uBcLzZX6w4YiAxN+hhAs/lByE9TzFXhT7xaPfst7NsGUsa9 SF3Sw5mCENdvrMPqA4QuYp/A68pzDixDG2+qAIdw+s4H2+xnqrpsi9vhDBgcoBqXgTuo fFzIfz8mBvfLZBG8uoLifIl36rU6O7JtHhQQBQfslYPeHN4SDmH+Rkmj8aVmHWhD621R JreMoNR4Qy9vJnE/2rw5Ar8KRxh2rODNCE9O2rTmUynmJya+jOC/Mqr13Zqn2gCgeUMU hYMg== X-Gm-Message-State: AOJu0YyJaz8+XUF+KEnQlg++QCS/fA1wGoBNXiYA9uVaTllJgsM46+10 1rltefxS5IEQpF4DUIYX6fB7GYiSXRy3lrJNha0JfisjoQAt0+E4VyG/sw6K4R/+kK+6wmIIb/2 a X-Gm-Gg: ASbGncsjo4bTIgubkBJdxHSoeEza1TsT6tuj2Efgr9RyjM5wg7Hi1bGOfPcDI6t6vaF Qw8jsvsPe30X1Mmi9v1k0VQjY9Ms46+6g+zXo7pLiss38Ip018wEXnOxAN+/E4M5qK/vrrvPzmJ 0XSXgF1C4JqaNv/L5nO7OrOHOhHRAS3mh0FZ8oOLzSc9ittej3qlP6XjSmUUDatWdSB7W6Gwzyz ClfRoeDr7WnExR9py6lvoLhsdSdLFoID6GTc6qU0hkvIefUzFqxE+/D5QZYlZXvpVLe++R4e3Ks n9JUxHN3UR3L0h8OUslIBpmh2NrUvxk4TzIizYw3NagR+1bNeO9xcgoG+Zmj8HBl4FaDLzBNTz7 CrdaCxUF13A== X-Google-Smtp-Source: AGHT+IFS1qhulYWmTrvgurfAdx5R0xg+gOOvZDyyKgT0SJbk5RNhTtFYQGor5Cl7bD+XIxXL0b1OAg== X-Received: by 2002:a17:903:287:b0:223:33cb:335f with SMTP id d9443c01a7336-22c5337a07fmr210958245ad.3.1745350724277; Tue, 22 Apr 2025 12:38:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 127/147] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h' Date: Tue, 22 Apr 2025 12:27:56 -0700 Message-ID: <20250422192819.302784-128-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351129628019000 From: Philippe Mathieu-Daud=C3=A9 To avoid including the huge "cpu.h" for a simple definition, move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/insn-start-words.h | 2 +- target/arm/cpu-param.h | 7 +++++++ target/arm/cpu.h | 6 ------ target/hppa/cpu-param.h | 2 ++ target/hppa/cpu.h | 2 -- target/i386/cpu-param.h | 2 ++ target/i386/cpu.h | 2 -- target/m68k/cpu-param.h | 2 ++ target/m68k/cpu.h | 2 -- target/microblaze/cpu-param.h | 2 ++ target/microblaze/cpu.h | 2 -- target/mips/cpu-param.h | 2 ++ target/mips/cpu.h | 2 -- target/openrisc/cpu-param.h | 2 ++ target/openrisc/cpu.h | 2 -- target/riscv/cpu-param.h | 8 ++++++++ target/riscv/cpu.h | 6 ------ target/s390x/cpu-param.h | 2 ++ target/s390x/cpu.h | 2 -- target/sh4/cpu-param.h | 2 ++ target/sh4/cpu.h | 2 -- target/sparc/cpu-param.h | 2 ++ target/sparc/cpu.h | 1 - 23 files changed, 34 insertions(+), 30 deletions(-) diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h index 50c18bd326..c439c09f2f 100644 --- a/include/tcg/insn-start-words.h +++ b/include/tcg/insn-start-words.h @@ -6,7 +6,7 @@ =20 #ifndef TARGET_INSN_START_WORDS =20 -#include "cpu.h" +#include "cpu-param.h" =20 #ifndef TARGET_INSN_START_EXTRA_WORDS # define TARGET_INSN_START_WORDS 1 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index a7ae42d17d..2cee4be693 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -37,6 +37,13 @@ # define TARGET_PAGE_BITS_LEGACY 10 #endif /* !CONFIG_USER_ONLY */ =20 +/* + * ARM-specific extra insn start words: + * 1: Conditional execution bits + * 2: Partial exception syndrome for data aborts + */ +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1a0faed3a..3705b34285 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -98,12 +98,6 @@ #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif =20 -/* ARM-specific extra insn start words: - * 1: Conditional execution bits - * 2: Partial exception syndrome for data aborts - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - /* The 2nd extra word holding syndrome info for data aborts does not use * the upper 6 bits nor the lower 13 bits. We mask and shift it down to * help the sleb128 encoder do a better job. diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 7ed6b5741e..68ed84e84a 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -19,6 +19,8 @@ =20 #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* PA-RISC 1.x processors have a strong memory model. */ /* * ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index da5f8adcd5..acc9937240 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -48,8 +48,6 @@ #define PRIV_KERNEL 0 #define PRIV_USER 3 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - /* No need to flush MMU_ABS*_IDX */ #define HPPA_MMU_FLUSH_MASK \ (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \ diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index b0e884c5d7..0c8efce861 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -22,6 +22,8 @@ #endif #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + /* The x86 has a strong memory model with some store-after-load re-orderin= g */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 35c16302bd..16d76df34b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1610,8 +1610,6 @@ typedef struct { #define MAX_FIXED_COUNTERS 3 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #define NB_OPMASK_REGS 8 =20 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 7afbf6d302..256a2b5f8b 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -17,4 +17,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + #endif diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 0b70e8c6ab..39d0b9d6d7 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -78,8 +78,6 @@ #define M68K_MAX_TTR 2 #define TTR(type, index) ttr[((type & ACCESS_CODE) =3D=3D ACCESS_CODE) * 2= + index] =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - typedef CPU_LDoubleU FPReg; =20 typedef struct CPUArchState { diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index c866ec6c14..5d55e0e3c4 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -27,6 +27,8 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + /* MicroBlaze is always in-order. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 2bfa396c96..d511f22a55 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -233,8 +233,6 @@ typedef struct CPUArchState CPUMBState; #define STREAM_CONTROL (1 << 3) #define STREAM_NONBLOCK (1 << 4) =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - /* use-non-secure property masks */ #define USE_NON_SECURE_M_AXI_DP_MASK 0x1 #define USE_NON_SECURE_M_AXI_IP_MASK 0x2 diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 8fcb1b4f5f..99ca8d1684 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -20,6 +20,8 @@ #endif #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 2 + #define TCG_GUEST_DEFAULT_MO (0) =20 #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 20f31370bc..d16f9a7220 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -100,8 +100,6 @@ struct CPUMIPSFPUContext { #define FP_UNIMPLEMENTED 32 }; =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { int32_t CP0_MVPControl; diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 37627f2c39..7ea0ecb55a 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -12,6 +12,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + #define TCG_GUEST_DEFAULT_MO (0) =20 #endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 19ee85ff5a..569819bfb0 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -40,8 +40,6 @@ struct OpenRISCCPUClass { ResettablePhases parent_phases; }; =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - enum { MMU_NOMMU_IDX =3D 0, MMU_SUPERVISOR_IDX =3D 1, diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index fba30e966a..ff4ba81965 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -16,6 +16,14 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ + +/* + * RISC-V-specific extra insn start words: + * 1: Original instruction opcode + * 2: more information about instruction + */ +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* * The current MMU Modes are: * - U mode 0b000 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 867e539b53..167909c89b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -45,12 +45,6 @@ typedef struct CPUArchState CPURISCVState; # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif =20 -/* - * RISC-V-specific extra insn start words: - * 1: Original instruction opcode - * 2: more information about instruction - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 /* * b0: Whether a instruction always raise a store AMO or not. */ diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index 5c331ec424..a8a4377f4f 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -12,6 +12,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 =20 +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 940eda8dd1..90f64ee20c 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -37,8 +37,6 @@ =20 #define TARGET_HAS_PRECISE_SMC =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #define MMU_USER_IDX 0 =20 #define S390_MAX_CPUS 248 diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index 2b6e11dd0a..f328715ee8 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -16,4 +16,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 7752a0c2e1..906f99ddf0 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -127,8 +127,6 @@ typedef struct tlb_t { #define UTLB_SIZE 64 #define ITLB_SIZE 4 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - enum sh_features { SH_FEATURE_SH4A =3D 1, SH_FEATURE_BCR3_AND_BCR4 =3D 2, diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 6952ee2b82..62d47b804b 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -21,6 +21,8 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + /* * From Oracle SPARC Architecture 2015: * diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 734dfdb1d3..83ac818933 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -223,7 +223,6 @@ typedef struct trap_state { uint32_t tt; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/tcg/insn-start-words.h | 4 ---- include/tcg/tcg-op.h | 2 +- target/alpha/cpu-param.h | 2 ++ target/avr/cpu-param.h | 2 ++ target/hexagon/cpu-param.h | 2 ++ target/loongarch/cpu-param.h | 2 ++ target/ppc/cpu-param.h | 2 ++ target/rx/cpu-param.h | 2 ++ target/tricore/cpu-param.h | 2 ++ target/xtensa/cpu-param.h | 2 ++ 10 files changed, 17 insertions(+), 5 deletions(-) diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h index c439c09f2f..d416d19bcf 100644 --- a/include/tcg/insn-start-words.h +++ b/include/tcg/insn-start-words.h @@ -8,10 +8,6 @@ =20 #include "cpu-param.h" =20 -#ifndef TARGET_INSN_START_EXTRA_WORDS -# define TARGET_INSN_START_WORDS 1 -#else # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) -#endif =20 #endif /* TARGET_INSN_START_WORDS */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index bc46b5570c..cded92a447 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -23,7 +23,7 @@ # error #endif =20 -#ifndef TARGET_INSN_START_EXTRA_WORDS +#if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 static inline void tcg_gen_insn_start(target_ulong pc) { TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BIT= S); diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index 63989e71c0..dd44feb179 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -24,6 +24,8 @@ # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f5248ce9e7..9d37848d97 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -25,6 +25,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO 0 =20 #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 45ee7b4640..635d509e74 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -23,4 +23,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 52437946e5..dbe414bb35 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -13,6 +13,8 @@ =20 #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO (0) =20 #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 553ad2f4c6..d0651d2ac8 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -37,6 +37,8 @@ # define TARGET_PAGE_BITS 12 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO 0 =20 #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index ef1970a09e..84934f3bca 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -24,4 +24,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 790242ef3d..eb33a67c41 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -12,4 +12,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 5e4848ad05..e7cb747aaa 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -16,6 +16,8 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 22 Apr 2025 12:38:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 129/147] exec: Restrict 'cpu-ldst-common.h' to accel/tcg/ Date: Tue, 22 Apr 2025 12:27:58 -0700 Message-ID: <20250422192819.302784-130-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351343175019100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/{exec =3D> accel/tcg}/cpu-ldst-common.h | 6 +++--- include/exec/cpu_ldst.h | 2 +- accel/tcg/translator.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) rename include/{exec =3D> accel/tcg}/cpu-ldst-common.h (97%) diff --git a/include/exec/cpu-ldst-common.h b/include/accel/tcg/cpu-ldst-co= mmon.h similarity index 97% rename from include/exec/cpu-ldst-common.h rename to include/accel/tcg/cpu-ldst-common.h index c46a6ade5d..8bf17c2fab 100644 --- a/include/exec/cpu-ldst-common.h +++ b/include/accel/tcg/cpu-ldst-common.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ =20 -#ifndef CPU_LDST_COMMON_H -#define CPU_LDST_COMMON_H +#ifndef ACCEL_TCG_CPU_LDST_COMMON_H +#define ACCEL_TCG_CPU_LDST_COMMON_H =20 #ifndef CONFIG_TCG #error Can only include this header with TCG @@ -119,4 +119,4 @@ uint32_t cpu_ldl_code_mmu(CPUArchState *env, vaddr addr, uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra); =20 -#endif /* CPU_LDST_COMMON_H */ +#endif /* ACCEL_TCG_CPU_LDST_COMMON_H */ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 63847f6e61..74761ba5f3 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -67,7 +67,7 @@ #endif =20 #include "exec/cpu-common.h" -#include "exec/cpu-ldst-common.h" +#include "accel/tcg/cpu-ldst-common.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/abi_ptr.h" =20 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index c53bbdef99..034f2f359e 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -11,7 +11,7 @@ #include "qemu/bswap.h" #include "qemu/log.h" #include "qemu/error-report.h" -#include "exec/cpu-ldst-common.h" +#include "accel/tcg/cpu-ldst-common.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/target_page.h" #include "exec/translator.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 22 Apr 2025 12:38:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 130/147] exec: Restrict 'cpu_ldst.h' to accel/tcg/ Date: Tue, 22 Apr 2025 12:27:59 -0700 Message-ID: <20250422192819.302784-131-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351441733019100 From: Philippe Mathieu-Daud=C3=A9 Mechanical change using: $ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \ $(git grep -l exec/cpu_ldst.h) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- bsd-user/qemu.h | 2 +- include/{exec/cpu_ldst.h =3D> accel/tcg/cpu-ldst.h} | 6 +++--- include/exec/exec-all.h | 2 +- linux-user/qemu.h | 2 +- target/arm/tcg/sve_ldst_internal.h | 2 +- accel/tcg/cputlb.c | 2 +- accel/tcg/user-exec.c | 2 +- target/alpha/mem_helper.c | 2 +- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/mve_helper.c | 2 +- target/arm/tcg/op_helper.c | 2 +- target/arm/tcg/pauth_helper.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/avr/helper.c | 2 +- target/hexagon/op_helper.c | 2 +- target/hexagon/translate.c | 2 +- target/hppa/op_helper.c | 2 +- target/i386/tcg/access.c | 2 +- target/i386/tcg/fpu_helper.c | 2 +- target/i386/tcg/mem_helper.c | 2 +- target/i386/tcg/mpx_helper.c | 2 +- target/i386/tcg/seg_helper.c | 2 +- target/i386/tcg/system/excp_helper.c | 2 +- target/i386/tcg/system/misc_helper.c | 2 +- target/i386/tcg/system/seg_helper.c | 2 +- target/i386/tcg/system/svm_helper.c | 2 +- target/i386/tcg/user/seg_helper.c | 2 +- target/loongarch/cpu.c | 2 +- target/loongarch/tcg/csr_helper.c | 2 +- target/loongarch/tcg/fpu_helper.c | 2 +- target/loongarch/tcg/iocsr_helper.c | 2 +- target/loongarch/tcg/op_helper.c | 2 +- target/loongarch/tcg/tlb_helper.c | 2 +- target/m68k/fpu_helper.c | 2 +- target/m68k/op_helper.c | 2 +- target/microblaze/cpu.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/tcg/ldst_helper.c | 2 +- target/mips/tcg/msa_helper.c | 2 +- target/mips/tcg/system/tlb_helper.c | 2 +- target/ppc/mem_helper.c | 2 +- target/ppc/mmu_helper.c | 2 +- target/ppc/tcg-excp_helper.c | 2 +- target/riscv/op_helper.c | 2 +- target/riscv/vector_helper.c | 2 +- target/riscv/zce_helper.c | 2 +- target/rx/helper.c | 2 +- target/rx/op_helper.c | 2 +- target/s390x/tcg/crypto_helper.c | 2 +- target/s390x/tcg/int_helper.c | 2 +- target/s390x/tcg/mem_helper.c | 2 +- target/s390x/tcg/misc_helper.c | 2 +- target/s390x/tcg/vec_helper.c | 2 +- target/sh4/op_helper.c | 2 +- target/sparc/int32_helper.c | 2 +- target/sparc/ldst_helper.c | 2 +- target/tricore/op_helper.c | 2 +- target/tricore/translate.c | 2 +- 61 files changed, 63 insertions(+), 63 deletions(-) rename include/{exec/cpu_ldst.h =3D> accel/tcg/cpu-ldst.h} (99%) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index c1c508281a..244670dd24 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -22,7 +22,7 @@ #include "qemu/int128.h" #include "cpu.h" #include "qemu/units.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" =20 #include "user/abitypes.h" diff --git a/include/exec/cpu_ldst.h b/include/accel/tcg/cpu-ldst.h similarity index 99% rename from include/exec/cpu_ldst.h rename to include/accel/tcg/cpu-ldst.h index 74761ba5f3..f97a730703 100644 --- a/include/exec/cpu_ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -59,8 +59,8 @@ * The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the * MemOp including alignment requirements. The alignment will be enforced. */ -#ifndef CPU_LDST_H -#define CPU_LDST_H +#ifndef ACCEL_TCG_CPU_LDST_H +#define ACCEL_TCG_CPU_LDST_H =20 #ifndef CONFIG_TCG #error Can only include this header with TCG @@ -560,4 +560,4 @@ static inline void clear_helper_retaddr(void) #define clear_helper_retaddr() do { } while (0) #endif =20 -#endif /* CPU_LDST_H */ +#endif /* ACCEL_TCG_CPU_LDST_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f52a680f42..70608a11b6 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -21,7 +21,7 @@ #define EXEC_ALL_H =20 #if defined(CONFIG_USER_ONLY) -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #endif #include "exec/mmu-access-type.h" #include "exec/translation-block.h" diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 948de8431a..0b19fa43e6 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -2,7 +2,7 @@ #define QEMU_H =20 #include "cpu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 #include "user/abitypes.h" #include "user/page-protection.h" diff --git a/target/arm/tcg/sve_ldst_internal.h b/target/arm/tcg/sve_ldst_i= nternal.h index 4f159ec4ad..f2243daf37 100644 --- a/target/arm/tcg/sve_ldst_internal.h +++ b/target/arm/tcg/sve_ldst_internal.h @@ -20,7 +20,7 @@ #ifndef TARGET_ARM_SVE_LDST_INTERNAL_H #define TARGET_ARM_SVE_LDST_INTERNAL_H =20 -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 /* * Load one element into @vd + @reg_off from @host. diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0de46903dd..2cafd38d2a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -23,7 +23,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "system/memory.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/cputlb.h" #include "exec/tb-flush.h" #include "system/ram_addr.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7f57d8f1af..1b878ead7a 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -26,7 +26,7 @@ #include "tcg/tcg.h" #include "qemu/bitops.h" #include "qemu/rcu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "user/cpu_loop.h" #include "qemu/main-loop.h" #include "user/page-protection.h" diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 872955f5e7..a4d5adb40c 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t = retaddr) { diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 507dbc1a44..08d8f63ffe 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -30,7 +30,7 @@ #include "qemu/crc32c.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "qemu/int128.h" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index f7354f3c6e..37dc98dc35 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -18,7 +18,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #ifdef CONFIG_TCG -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "semihosting/common-semi.h" #endif #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 888c670754..7dc5fb776b 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -29,7 +29,7 @@ #else #include "system/ram_addr.h" #endif -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 274003e2e5..f9f67d1f88 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -22,7 +22,7 @@ #include "internals.h" #include "vec_internal.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "tcg/tcg.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 71ba406782..38d49cbb9d 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -24,7 +24,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "cpregs.h" =20 #define SIGNBIT (uint32_t)0x80000000 diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index c4b143024f..59bf27541d 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -22,7 +22,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index dcc48e43db..96b84c37a2 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -22,7 +22,7 @@ #include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" #include "fpu/softfloat.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index 32cbf17919..afa591470f 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -27,7 +27,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" =20 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 6da8db8ea5..3f3d86db2b 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -18,7 +18,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "cpu.h" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index fe7858703c..dd26801e64 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -23,7 +23,7 @@ #include "exec/helper-gen.h" #include "exec/helper-proto.h" #include "exec/translation-block.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "internal.h" #include "attribs.h" diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index beb8f88799..2398ce2c64 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "qemu/timer.h" #include "trace.h" #ifdef CONFIG_USER_ONLY diff --git a/target/i386/tcg/access.c b/target/i386/tcg/access.c index 5a4721dcee..0fdd587edd 100644 --- a/target/i386/tcg/access.c +++ b/target/i386/tcg/access.c @@ -3,7 +3,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "exec/target_page.h" #include "access.h" diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index c1184ca219..1cbadb1453 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "tcg-cpu.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 3ef84e90d9..84a0815217 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" #include "tcg/tcg.h" diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index b942665adc..a0f816dfae 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "exec/target_page.h" #include "helper-tcg.h" diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 9dfbc4208c..3af902e0ec 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -23,7 +23,7 @@ #include "qemu/log.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "helper-tcg.h" #include "seg_helper.h" diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index a563c9b35e..93614aa3e5 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/= misc_helper.c index 67896c8c87..9c3f5cc99b 100644 --- a/target/i386/tcg/system/misc_helper.c +++ b/target/i386/tcg/system/misc_helper.c @@ -21,7 +21,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "system/address-spaces.h" #include "system/memory.h" #include "exec/cputlb.h" diff --git a/target/i386/tcg/system/seg_helper.c b/target/i386/tcg/system/s= eg_helper.c index b07cc9f9b1..d4ea890c12 100644 --- a/target/i386/tcg/system/seg_helper.c +++ b/target/i386/tcg/system/seg_helper.c @@ -23,7 +23,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/helper-tcg.h" #include "../seg_helper.h" =20 diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/s= vm_helper.c index f9982b72d1..b27049b9ed 100644 --- a/target/i386/tcg/system/svm_helper.c +++ b/target/i386/tcg/system/svm_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/helper-tcg.h" =20 /* Secure Virtual Machine helpers */ diff --git a/target/i386/tcg/user/seg_helper.c b/target/i386/tcg/user/seg_h= elper.c index c45f2ac2ba..5692dd5195 100644 --- a/target/i386/tcg/user/seg_helper.c +++ b/target/i386/tcg/user/seg_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/helper-tcg.h" #include "tcg/seg_helper.h" =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index cb96b17911..4cc8e02f70 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -29,7 +29,7 @@ #include #endif #ifdef CONFIG_TCG -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/tcg.h" #endif =20 diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 6a7a65c860..2942d7feb8 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -13,7 +13,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "hw/irq.h" #include "cpu-csr.h" =20 diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_h= elper.c index a83acf64b0..fc3fd0561e 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -9,7 +9,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" #include "internals.h" =20 diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/ioc= sr_helper.c index b6916f53d2..e62170de3c 100644 --- a/target/loongarch/tcg/iocsr_helper.c +++ b/target/loongarch/tcg/iocsr_helper.c @@ -10,7 +10,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 #define GET_MEMTXATTRS(cas) \ ((MemTxAttrs){.requester_id =3D env_cpu(cas)->cpu_index}) diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_hel= per.c index b17208e5b9..94e3b28016 100644 --- a/target/loongarch/tcg/op_helper.c +++ b/target/loongarch/tcg/op_helper.c @@ -11,7 +11,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "internals.h" #include "qemu/crc32c.h" #include /* for crc32 */ diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 0d6c9844a6..9a76a2a205 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -16,7 +16,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "cpu-csr.h" =20 diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index eb1cb8c687..ac4a0d85be 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "softfloat.h" =20 /* diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 15bad5dd46..242aecccbb 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "semihosting/semihost.h" =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 88baeb6807..d10ae0702a 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -28,7 +28,7 @@ #include "qemu/module.h" #include "hw/qdev-properties.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/gdbstub.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f6378030b7..4624ce5b67 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -24,7 +24,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" =20 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4bb867c969..7dcad6cf0d 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index f92a923d7a..2fb879fcbc 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -24,7 +24,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/memop.h" #include "internal.h" =20 diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 969dd34b3e..14de4a71ff 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -22,7 +22,7 @@ #include "internal.h" #include "tcg/tcg.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "exec/memop.h" #include "exec/target_page.h" diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index d239fa9353..e477ef812a 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -25,7 +25,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" =20 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 0967624afe..d7e8d678f4 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,7 +24,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "helper_regs.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "internal.h" #include "qemu/atomic128.h" =20 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index c90ceb7d60..2138666122 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -37,7 +37,7 @@ #include "mmu-radix64.h" #include "mmu-booke.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 /* #define FLUSH_ALL_TLBS */ =20 diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index c422648cfd..2b15e5f2f0 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -20,7 +20,7 @@ #include "qemu/main-loop.h" #include "qemu/log.h" #include "target/ppc/cpu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "system/runstate.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f3d26b6b95..5b0db2c45a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -23,7 +23,7 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "trace.h" diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7de6cbae5c..b8ae704457 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c index b433bda16d..50d65f386c 100644 --- a/target/riscv/zce_helper.c +++ b/target/riscv/zce_helper.c @@ -20,7 +20,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index) { diff --git a/target/rx/helper.c b/target/rx/helper.c index e8aabf40ff..0640ab322b 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -20,7 +20,7 @@ #include "qemu/bitops.h" #include "cpu.h" #include "exec/log.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "hw/irq.h" =20 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index b3ed822dd1..a2f1f3824d 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" =20 diff --git a/target/s390x/tcg/crypto_helper.c b/target/s390x/tcg/crypto_hel= per.c index 93aabd236f..642c1b18c4 100644 --- a/target/s390x/tcg/crypto_helper.c +++ b/target/s390x/tcg/crypto_helper.c @@ -18,7 +18,7 @@ #include "tcg_s390x.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 static uint64_t R(uint64_t x, int c) { diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 2af970f2c8..253c036415 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -25,7 +25,7 @@ #include "exec/exec-all.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 /* #define DEBUG_HELPER */ #ifdef DEBUG_HELPER diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index d5eece4384..0cdfd380ce 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -28,7 +28,7 @@ #include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/page-protection.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index e02f443850..d5088493ea 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -28,7 +28,7 @@ #include "qemu/timer.h" #include "exec/exec-all.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/target_page.h" #include "qapi/error.h" #include "tcg_s390x.h" diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c index dafc4c3582..781ccc565b 100644 --- a/target/s390x/tcg/vec_helper.c +++ b/target/s390x/tcg/vec_helper.c @@ -16,7 +16,7 @@ #include "tcg/tcg.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" =20 void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3, diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 99394b714c..e7fcad3c1b 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -20,7 +20,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" =20 #ifndef CONFIG_USER_ONLY diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index f026606102..39db4ffa70 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -21,7 +21,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "trace.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "system/runstate.h" =20 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 3fa5e78816..4c5dba19d1 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -27,7 +27,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "system/memory.h" #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index a0d5a0da1d..ae559b6922 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -19,7 +19,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include /* for crc32 */ =20 =20 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 5c7ed395ca..7cd26d8eab 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "qemu/qemu-print.h" =20 #include "exec/helper-proto.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352523; cv=none; d=zohomail.com; s=zohoarc; b=Gp5dLsYqmAW5Kv7iRqV/R+J/B3/jKAQcGZpNJ75XznwFCX5p6U7CxceL7Ks2ech889SKkBvggci80JwiCydeD8y+ZthGdnqBL/yeIz/t7/CQKFs0DAQoIISutne7XVPEqtREl/LW+KGRRVqouvOLsGYkDCwB60xo9bw2gFJSIEk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352523; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 3 --- accel/tcg/cpu-exec.c | 1 + target/arm/tcg/sve_helper.c | 1 + 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 70608a11b6..944b579d91 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -20,9 +20,6 @@ #ifndef EXEC_ALL_H #define EXEC_ALL_H =20 -#if defined(CONFIG_USER_ONLY) -#include "accel/tcg/cpu-ldst.h" -#endif #include "exec/mmu-access-type.h" #include "exec/translation-block.h" =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5ced3879ac..b00f046b29 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,6 +22,7 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/cpu.h" +#include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" #include "trace.h" #include "disas/disas.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 9b0d40c9e1..87b6b4b3e6 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -30,6 +30,7 @@ #include "tcg/tcg.h" #include "vec_internal.h" #include "sve_ldst_internal.h" +#include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352494; cv=none; d=zohomail.com; s=zohoarc; b=WPHa/fCTjnk6j+N8gscS3kDS+VGxd+wRXXba5sTaKHRrjLXf9lhowY1j3BWiEIB4vHa/Wp4IR8T0yhMhatUiqfBjLKXH833imDBgpGebN+p8aIEtx0FPc0Y3aeu3riW8ftEHP1tS97VFbXoQ5peS2dJYE4aQAZSM0IOcZH8Mizc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352494; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Q2Qeo3QXQKKP4XnDRGevpdG6ZhTAI9iOzSVzVjKvTY4=; b=CZkLwjT10O6VcdEXYs6tKB/4ouoCKwzm3j9L6gybLzP9HC4fZudQRfgkjT/bieiaRldg1T4qK5kXUD9yL8AIwO8cWBap/hi1iaWlR+OtMlcmJplxwFSphSxrv5ro2t8Bmz7tEYHo05ekf9LEJc3+tSXkbUD5+U10cIyV9cQPISY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352494410939.904223565853; Tue, 22 Apr 2025 13:08:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JSh-000520-0M; Tue, 22 Apr 2025 15:39:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSF-00045h-Dx for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:51 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSD-0007Lk-7e for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:51 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-227914acd20so1954565ad.1 for ; Tue, 22 Apr 2025 12:38:48 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350728; x=1745955528; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q2Qeo3QXQKKP4XnDRGevpdG6ZhTAI9iOzSVzVjKvTY4=; b=B+b4TYzskieNgoxz2hYMI08GjhauWR+fMH3cRdx41CxRfVw09BAaUpynj9R0fa95JH +e2GJWh9Jt8DA7ZH6vIQdbKZmEHiOXbAXaQPTmo1wCzNn7t4feRmjs1AD4lsSKF2dvQ0 Va4F+UFSwsFjyf0usOp1buC/hd2qA9RaPLUGll/ULJ/qRpWUqLU0UHqJPyhDiJ3KoKVu SEbRibQAp2Krovn8y7t4AJEWyZapwqliw4reIdyXo7mvD8jMTnNnIepxGFKI+TNWHDS6 Bav293FCl/27YkE21+JgqwDVxpL6T0TOfog0Jg0YRIUHuXgiRZT/5NVVn/N+eiD2dp1Q +E0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350728; x=1745955528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q2Qeo3QXQKKP4XnDRGevpdG6ZhTAI9iOzSVzVjKvTY4=; b=M7LH3gTcH7HbE8tpDnfFFMWeCvTKSQZ+MAmZeSnnbvKEwRwentqJhWqGya+O6uxQ5Y M3HWycobKNKbRVvLS0q3J9T4inOdEQTG1J4bgYyE+ayqJS7qfFyjA7TzVKvdQ2YmODBc Tg5KVJ3KfnXN6alF0YMcxhG2pycEx3tn9o0embW3F+Jeecy85urvfXLIgJQHRJqvCxVw phLd4pGpERPBaTendtRio/wW475cw4k/v+MKIXFXg9HOiYBLOg68isVJbxXAIIg5Bnk0 A+JGx1Ji2aYcZ5s5oiNOhsOtvrMfxsDa4uSYBkWJDlGVRk14Zbc1qc1nRIAmVS5WoGOl fuhw== X-Gm-Message-State: AOJu0YzfPs08tNVCKZc/YzdCYn+q3DAv+smHliDyLlo15HFSOU0rlxzB mlqns5ACs61y4rsStKa2nMJHikoCDz0NO5jS34NN7aHDGT8W4DzDL60yA/8aExsjcRUJZehEgsb A X-Gm-Gg: ASbGncvVPQT40A9/jimWmjxzi4hNLAqx7IBVz7khoZ50Zkcg+6l0aaL/EqLuY/cvg0E 4rFf6RKzw+rCIrGk+0jdYPRuTatZ/RzsUuhARoVrEwyqB2dfKpP2mcxrOnX1mxhlRlO69ZulBX6 eQvufRfvROUz7lXyaEgOorqcwJkC+x3sAHhUsDn7vEc+O7Gl4fvL9mF/yGmOjYJyJXwIJAe1BPu oBEcIzt6YmmD8QN5BUZVlhgxZbknLEC44k6N9PQmpkpEqeINxW8ZVlCzAI/LtbMb9zfhpNPHbFX 0cKDT+B7Qf8aDxRm81zjqiheTM4fK4/7C/bgsUYXdocBpgXjm0zICj8HGEeZtrehzLPJjEK1JAE = X-Google-Smtp-Source: AGHT+IESJa7MesmduoVh/F36xBloNm2lMZFs8puxoNSx4WYmM6G3t98CKNmJ6/dr7T9sFx7xu9wibA== X-Received: by 2002:a17:903:2352:b0:224:3610:bef4 with SMTP id d9443c01a7336-22da337b263mr2908145ad.25.1745350727770; Tue, 22 Apr 2025 12:38:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH 132/147] tcg: Always define TCG_GUEST_DEFAULT_MO Date: Tue, 22 Apr 2025 12:28:01 -0700 Message-ID: <20250422192819.302784-133-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352495166019000 From: Philippe Mathieu-Daud=C3=A9 We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled frontends, otherwise we use a default value of TCG_MO_ALL. In order to simplify, require the definition for all targets, defining it for hexagon, m68k, rx, sh4 and tricore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/hexagon/cpu-param.h | 3 +++ target/m68k/cpu-param.h | 3 +++ target/rx/cpu-param.h | 3 +++ target/sh4/cpu-param.h | 3 +++ target/tricore/cpu-param.h | 3 +++ accel/tcg/translate-all.c | 4 ---- 6 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e74..7cc63a01d4 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,4 +25,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 256a2b5f8b..10a8d74bfa 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -19,4 +19,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 84934f3bca..fe39a77ca3 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -26,4 +26,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index f328715ee8..acdf239749 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -18,4 +18,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index eb33a67c41..45fde756b6 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -14,4 +14,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c5590eb695..7467255f6e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -353,11 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; -#ifdef TCG_GUEST_DEFAULT_MO tcg_ctx->guest_mo =3D TCG_GUEST_DEFAULT_MO; -#else - tcg_ctx->guest_mo =3D TCG_MO_ALL; -#endif =20 restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745350917; cv=none; d=zohomail.com; s=zohoarc; b=EGkHQPEGrsmKIhlHypxuTM8FASYTHn+pkX62QOBpTErlfXUxvfRiNM7WVc2CvIofLxXbrSx3KnB8aFZA5EJFO7CH+uE0hoMM38oFoKZ2Nf9LZMUTBcEPpyovkrBxgOrAV87Pd104LEos+czNP0CAlwzOhBH0LES1X2jyP/8KVro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745350917; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350728; x=1745955528; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sQncdcCBTAzD3tdjUYfUMSnmVN4uvUMzzqpT196vY4c=; b=dRCmGBwll1XObaBKqySKvhYxm/iKdqmRXz8pI7ra612AkbVbTY896TmN5XlEvrNiqO zd1wuGZhkYHe47Qb7IlUS8+1SxLB5vzxVcVkkEVYwhl+VWlktUim0GX+fUK1ZngAes6X KC07WMhr+O6EY3+nHm1GJIafH3N5W19WXPrBDi8+PYgp20d0eedviRsVvHohhhvHBudI Q61FRCtBAX3ewsJ1RmUf9VaDaZ4tJ5l9d646rznhd16v8M+0bogyGW46PgzaNsrrEbzI BMl3o89BT2FA3afTci6AlfOgYnhIEs0ENdk2W4Tk6Z03roSNXx2NYVXKvIbyTWS7qeTe F/bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350728; x=1745955528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sQncdcCBTAzD3tdjUYfUMSnmVN4uvUMzzqpT196vY4c=; b=MEZlmg8pjrTvbyM2Om7P5MWVS8Xst66GVz5WiXwn4kOroTV4Go4f6OOaPYLiUF2M9w Z9fhuRVPBOP86QJd/M/eaitmzQRVT7Cj6H6xczYzxtIIbicHoJc7qXllQadnilpSzukc b9VMEUdPVJPAumdpkJXJ3ZBogXrDzsRYRjzwIaVATjmrtF37B1XHiyF3A2SQCES1t07G mH11R0D8ARiuKIpezXoBuCBse7An1MyrIsC+e675GA90jz8BBlO4TZ5jc9uP6inSgj89 bbHE07xqCBhylhTa+P5S1an8pUAwCk/ZXfAFKqxUU7MmqMRCHnCIb3pubswqjSu54xOo +bBg== X-Gm-Message-State: AOJu0Yx9TCp84vOsJWcYPtqFRx12w+ZmxXxaxjK2+B6FxhqGwGLRaEbp 8qJlTafx7VqlLEVhtwKrfQzs2ovpTn8vD2gQggtJmT0RlICmS1UipqD3ChLOsJlOAOCytPWeksP p X-Gm-Gg: ASbGncvTEmllVhPoWSsYaAowIW7lokMyh1HFbmE5phZWs/S6OS8KQqrGwenlRwZNCZL aeWbbNp59ChUArzUOdCGS3k0WUjQAsDoMQD0ojErrJpq0rXJb1adPf1UBz6B4xzIJSz3+2MHdmc v1emVT2w2bysQA15q7OuRhCOYSWP4K0ZqswtUjx7qu3Hzw/lcEE/XyTzwWSPdCy8t0DvsfNknMg orWqR5NDPrva1CiOuyWvdg9f+sQzBgA5SfF/M6g+nFug+DCCy+dx54EiYkpGujdau/XWRSAYoXN PbUr6Zt+hMnFZiw1usHISTCBpAurc2xXLK+Hp6yt24oye6hOxZB+F9havrMHWHGYG5sJJjEqfps = X-Google-Smtp-Source: AGHT+IEhNtJynkbCfBhrqh5s1DgEZssBHHajXaM+XiGoInegDVsDyioR37bXfhKn3mHQEM/7Em71Sw== X-Received: by 2002:a17:903:2306:b0:223:517a:d2a3 with SMTP id d9443c01a7336-22c535a5567mr258099045ad.17.1745350728582; Tue, 22 Apr 2025 12:38:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH 133/147] tcg: Simplify tcg_req_mo() macro Date: Tue, 22 Apr 2025 12:28:02 -0700 Message-ID: <20250422192819.302784-134-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350918705019000 From: Philippe Mathieu-Daud=C3=A9 Now that TCG_GUEST_DEFAULT_MO is always defined, simplify the tcg_req_mo() macro. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- accel/tcg/internal-target.h | 9 +-------- accel/tcg/tcg-all.c | 3 --- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 05abaeb8e0..1a46a7c87d 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -52,17 +52,10 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); * memory ordering vs the host memory ordering. A non-zero * result indicates that some barrier is required. * - * If TCG_GUEST_DEFAULT_MO is not defined, assume that the - * guest requires strict ordering. - * * This is a macro so that it's constant even without optimization. */ -#ifdef TCG_GUEST_DEFAULT_MO -# define tcg_req_mo(type) \ +#define tcg_req_mo(type) \ ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) -#else -# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO) -#endif =20 /** * cpu_req_mo: diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 7a5b810b88..a5a1fd6a11 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -77,9 +77,6 @@ static bool default_mttcg_enabled(void) return false; } #ifdef TARGET_SUPPORTS_MTTCG -# ifndef TCG_GUEST_DEFAULT_MO -# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO" -# endif return true; #else return false; --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351462; cv=none; d=zohomail.com; s=zohoarc; b=ZKW5CYjqY2InEnRpaLsq5X+JCCh5x9FN8pb4R3B5WOMoQXAIYkLL3N0ett/FZpyZ49/7Rb6l/pLtMh0l8bAcOYKl2oEbrmlSfQG9irJVPjgvxWS3TefndwXW/Ib4V3SKTXEbLqEPPrV8GQhM8z4sy9gznpl6zCb7OGuZIDAT80c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351462; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=daDsqIY3JqZY3gWJRoer5Pq3HW0D1tA51SVXkh4oP34=; b=Z0qoaWwJKVwU3hrQNlxTPnYyzRXYBB42kIY7Hv7D5BtOaO/jc402v9FXZNRU2O3nd+zI/L0Kn12CpFJ0ORUVcpEjH2LwuLwpWE6s3Amuay4OOAGtwvNjL8/TtymCGjSCQcf3ux2xMrW8Z+xq6msquZ+QgPNbjYE9CLil+DnPWe0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351462838374.46682820458614; Tue, 22 Apr 2025 12:51:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JTB-0006di-Bu; Tue, 22 Apr 2025 15:39:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSI-0004BY-8s for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:54 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSF-0007MF-6d for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:53 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-22c3407a87aso84292335ad.3 for ; Tue, 22 Apr 2025 12:38:50 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350729; x=1745955529; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=daDsqIY3JqZY3gWJRoer5Pq3HW0D1tA51SVXkh4oP34=; b=cziVlss2CKx7YMt4mkwLUysInhrcSfLMVDTTfQkp/DLkJDUNVd2szhxdvBuZIs0Qiq fXUtEEmxfzH25eixF57LO10DjsJdXy8uTaoiIBqGlr3OmdWJK64Ue6lHLd9jQ3RZyaYY vCohyYqTOfN+nLADKMSXywrpXTzpDwnC0S0+nErB+AuVKiGrPoSGCEey0srxb0LhaDQJ WiBFWUGFjXSorpaj8HXYivGPnu+F/N8iY+KFr6s7PhljFOPOP2kLR068uvxGR8VVzd8U yed1M6srXY2e4d/qHqb7adpVd8JYVv/DjtppifjBL1ERGhxUxk1xt4haYiZPil1+18p2 0L5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350729; x=1745955529; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=daDsqIY3JqZY3gWJRoer5Pq3HW0D1tA51SVXkh4oP34=; b=b/ltPW2wOOqKfBAKsheKj5UXIEHhuolQXKEtj3hgthxF672bh0SPz0kNhe0qE90tda l48NFRYOFzCTWixsh7QRm7Hm7hlQwsXmX20UpH26yG3JFvTDyDJ6REWN09f7DEhF0jFU E4CanRNTJrO9ao6FYPUN0KP9cy1LFX0jwW2cu0Nr0d688iTqhK5wWpfUQxnrMYeURHVR sVV/Ix94vbykoPM9in87tawz8L2PU/13Xrq5Wm8/kx3uPv17nVoCxtH1RCtWNu2kCgZj AZdQaU25z31qGrGaRAAqnEykzRvGjk4ZEg09+VC6T2B+yoKxZlyvEBmLB/znQacvXs2Y /5tA== X-Gm-Message-State: AOJu0YydxhD5EehY6BJ1+sEKuTO6qZUp6qysO8mGvTyzKBtV9VZvilDb I7QdyBro+hq1UgoeM14h5imvnndtI5eVmzRPp4J9HzJyVeAYsfRK4W/6DYa5GIOuu6oNzUch3Qa y X-Gm-Gg: ASbGnctxw/Ojty/51ex+tTZ0Y5sL/lTNsBI6o07sDg2dfX9REbMt29MSGV+OyNVcbyo V5IJN7GHbXZjdB0C8DTcTnXQyzNJm8wecmjNSfxSnBG6VMhZz84tqiThVmKZpLNO3JQjd1FEQwT wqavNMA3ndXuz1H0ASfWrP34HvYqTNDy1xrAyEul4EpseIwgoJwd9R/QmsDMWQI76s1GqV6r7Ov X4VycgyGkxgUVFuVK70+5YaQ5tAshHwbRom8mGuC+up9d4qFISYooH0DjboL8CD9/hhlyCXMvsk vgmI/d2NU61D4G3BjsLaqhheZ2vv76D/Mu/nnCNylTYjSnoxvxTKsD1JuG50lg8R7jA5GijgVSk = X-Google-Smtp-Source: AGHT+IFBmz53arONzZlfENM+1tYf2MgRBrsdQiDq10vBD6ULHE/Fq8q9ns9GQDrceh1OqAm/VMCUhA== X-Received: by 2002:a17:902:d4c9:b0:223:f7ec:f834 with SMTP id d9443c01a7336-22c535b094amr235274625ad.31.1745350729453; Tue, 22 Apr 2025 12:38:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH 134/147] tcg: Define guest_default_memory_order in TCGCPUOps Date: Tue, 22 Apr 2025 12:28:03 -0700 Message-ID: <20250422192819.302784-135-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351465693019100 From: Philippe Mathieu-Daud=C3=A9 Add the TCGCPUOps::guest_default_memory_order field and have each target initialize it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 8 ++++++++ target/alpha/cpu.c | 2 ++ target/arm/cpu.c | 2 ++ target/arm/tcg/cpu-v7m.c | 2 ++ target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 2 ++ target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 2 ++ target/m68k/cpu.c | 2 ++ target/microblaze/cpu.c | 2 ++ target/mips/cpu.c | 2 ++ target/openrisc/cpu.c | 2 ++ target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 2 ++ target/rx/cpu.c | 2 ++ target/s390x/cpu.c | 2 ++ target/sh4/cpu.c | 2 ++ target/sparc/cpu.c | 2 ++ target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 2 ++ 21 files changed, 43 insertions(+) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 106a0688da..a4932fc5d7 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -16,8 +16,16 @@ #include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" +#include "tcg/tcg-mo.h" =20 struct TCGCPUOps { + + /** + * @guest_default_memory_order: default barrier that is required + * for the guest memory ordering. + */ + TCGBar guest_default_memory_order; + /** * @initialize: Initialize TCG state * diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 99d839a279..6f931117a2 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,6 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps alpha_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, .synchronize_from_tb =3D alpha_cpu_synchronize_from_tb, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c9e043bc9b..3f20e258fd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { =20 #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 1a913faa50..4553fe9de0 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,6 +232,8 @@ static void cortex_m55_initfn(Object *obj) } =20 static const TCGCPUOps arm_v7m_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index feb73e722b..67918684fa 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,6 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps avr_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ad1f303fbc..b12e0dccd0 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -325,6 +325,7 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hexagon_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 51bff0c5d6..ac4560febe 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,6 +253,8 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hppa_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 35b17f2b18..3e1b315340 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps x86_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 4cc8e02f70..ee74509a66 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,6 +864,8 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps loongarch_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 4409d8941c..bfde9b8594 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,6 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps m68k_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, .restore_state_to_opc =3D m68k_restore_state_to_opc, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d10ae0702a..e46863574c 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,6 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps mb_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index cb0d6dde0e..67a8550cc1 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -551,6 +551,8 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) } =20 static const TCGCPUOps mips_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index dc55594a7d..e62c698a40 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,6 +243,8 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps openrisc_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, .synchronize_from_tb =3D openrisc_cpu_synchronize_from_tb, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index fd8c42069e..1cf18e0dae 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7479,6 +7479,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps ppc_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, .restore_state_to_opc =3D ppc_restore_state_to_opc, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5d0429b4d0..ded2d68ad7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,6 +140,8 @@ static void riscv_restore_state_to_opc(CPUState *cs, } =20 static const TCGCPUOps riscv_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index e14d9cbef9..d7eac551fd 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,6 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps rx_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d15b1943e0..f232d82fa3 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,8 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } =20 static const TCGCPUOps s390_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, .restore_state_to_opc =3D s390x_restore_state_to_opc, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index df093988cb..29f4be7ba9 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,6 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps superh_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index af3cec43e7..ef04efcb18 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,6 +1001,8 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps sparc_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 833a93d37a..3bf399335a 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,6 +172,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps tricore_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 51f9ee9e89..2347106495 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,6 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps xtensa_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, .debug_excp_handler =3D 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7467255f6e..c007b9a190 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -353,7 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; - tcg_ctx->guest_mo =3D TCG_GUEST_DEFAULT_MO; + tcg_ctx->guest_mo =3D cpu->cc->tcg_ops->guest_default_memory_order; =20 restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352544; cv=none; d=zohomail.com; s=zohoarc; b=DYwzn7hM93WwZKKZ5Z6w8k/6i5i/gV4Jh/UPWhrSdE4KtdZ17OQ0DhMM0TJQUx0uAddNa4GmPPB/Ceywl+Ku0kHShIgT1vgWqLaBzqG4zdCv5w6+mHTNCv9BW8kaaz9WM/rh4QbhjwwpM+c/J2zx+NWqv3R90WdHxGy/eIvr5yo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352544; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9MNvSRDi98aye64ClUWawrfGEwwTpHlnQYD/vV4dHwA=; b=VcNIJoUXeu1D7iuYzRpTwILNvsyFHgEhTXW1mHQl1y6GeflL5WP66bK7qB9M1OJYX3PXspLgymRugeF1BgXoT7g+aeO1wkhbsLHJI8NzKAy6D2pBM042L+GKhPGmwk7VNpVuJRx4diEMjSYVFv6k0grHxo3L0PA6dhrnRDeBBSM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745352544962410.9447864440277; Tue, 22 Apr 2025 13:09:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JSm-0005E6-SA; Tue, 22 Apr 2025 15:39:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSK-0004Fd-Mj for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:00 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSH-0007Mc-0d for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:55 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-227b828de00so60308705ad.1 for ; Tue, 22 Apr 2025 12:38:52 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350731; x=1745955531; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9MNvSRDi98aye64ClUWawrfGEwwTpHlnQYD/vV4dHwA=; b=UL0E99AOTBIQSbyS9uumOeHz53xKqqVCCn7fjTVcvG5Rb0fK8yBqZNFvD839x1exWE 7Qa2ZAC7cXJ1RoNmYU1dGT/p+B7RB5MVzje/+JuEshpvO0UkcJutQycDTEl5Vha8BCn6 nMid/Z8DQfWdDjosHffVFWdyZkx2jTKk+EARrbgoST9K8jC9FQ+186mQh0z2HCTvdpFQ nBwFErcsE54BZVJ4wZQ4M0y+jRpw+JHxs57bHuUNWCFCux2mX6uxLz+m5KYnFR0u1swn N7V7l4Sd4acdWftn7v6khOn2SLoI12rx0iYs1TXRMBrceCP5hac+oDmi4a4jD8khKLwT UM+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350731; x=1745955531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9MNvSRDi98aye64ClUWawrfGEwwTpHlnQYD/vV4dHwA=; b=SMt+EZSEI9CBFq4CD70mgw2v2QViibLQsf99sdxQElokLwF50dcG5DqBETUSXIAstd 8kd0WKg+zwatN77xmBMhoUa9ZyUlaA9wAv7F4U+I3yzBxWqy/+OYJD5WG/O2s+kJGdTi 6xvbMxnzNrprhKPunI5tao3Lxs9cMFpgt7iy6SacwDGK60lABGZLgECHfc0Yv8mFQUZJ 39sIwzKoDq2DORdLwL1ttfWl6H74kpOFGxV/0fyOxpic0Gnm9ofYxL1ItcvQeib/UlVG 1CaCju59FXMqrngg9CAhLIP9tJXuUM4rPk7TM14vPbLbzxvCT/6bP7j8oWIpm86UuJVC PZ0w== X-Gm-Message-State: AOJu0Yw2VFIeRZoTcOyYj3PoaEy2/B0L6W2EGweMw5QssrZhOTgFvSA+ 1mkV10vcZ5uCrrf6W3u1EB96QE/VkHBMDxJJzSYZ3sh9Ux4dPbebaoSTGQXCBxMjfgx0i2RRSgk N X-Gm-Gg: ASbGncv56tGpkFfFbIJ7GDd80h8Kswwusx/N+3H9Hx3sSpO+TMaUKfjcgCbV4MFszIS VzNU6WYnzdmI48ideB1R81H9qcmbMdBpJV2zo+H5pdUArAbeU3M65GloWn/Uz5vdQRuiR4Zfjlj G0hohzquz71pqG2JvPUOdV+pezq80qgNZz6I0h8qXX30kgBNM9Uvh2usXkxsagaShNEWtkaU7TV gnfWAvMJKvgX3FTpJQgnuAdoSidcyPEz7FzhkYA02f8VLMNx9rKbpEaKeve6QB0MmhK6QpPCN0L 41VagJAhO4uMMAYjWJUqw4ddFYpFENriNRziZuTLbmEhSvDn6rVlZV+L30N50d68fH55/KJ2cL0 = X-Google-Smtp-Source: AGHT+IErJu7SGnmpD7GLFGIqIRzbRLeft68oogKohVNfZWMtMikpMhxPEU90TrSOJcCr07TGE4x0Hw== X-Received: by 2002:a17:902:e54b:b0:22c:33e4:fa5a with SMTP id d9443c01a7336-22c5356841cmr222772075ad.9.1745350730839; Tue, 22 Apr 2025 12:38:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 136/147] tcg: Propagate CPUState argument to cpu_req_mo() Date: Tue, 22 Apr 2025 12:28:05 -0700 Message-ID: <20250422192819.302784-137-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352546062019100 From: Philippe Mathieu-Daud=C3=A9 In preparation of having tcg_req_mo() access CPUState in the next commit, pass it to cpu_req_mo(), its single caller. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/internal-target.h | 3 ++- accel/tcg/cputlb.c | 20 ++++++++++---------- accel/tcg/user-exec.c | 20 ++++++++++---------- 3 files changed, 22 insertions(+), 21 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 1a46a7c87d..23aac39b57 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -59,12 +59,13 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); =20 /** * cpu_req_mo: + * @cpu: CPUState * @type: TCGBar * * If tcg_req_mo indicates a barrier for @type is required * for the guest memory model, issue a host memory barrier. */ -#define cpu_req_mo(type) \ +#define cpu_req_mo(cpu, type) \ do { \ if (tcg_req_mo(type)) { \ smp_mb(); \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2cafd38d2a..35b1ff03a5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2324,7 +2324,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); tcg_debug_assert(!crosspage); =20 @@ -2339,7 +2339,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2363,7 +2363,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint32_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2384,7 +2384,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint64_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2407,7 +2407,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, Int128 ret; int first; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { @@ -2735,7 +2735,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); tcg_debug_assert(!crosspage); =20 @@ -2749,7 +2749,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, bool crosspage; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2771,7 +2771,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2792,7 +2792,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2815,7 +2815,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, uint64_t a, b; int first; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1b878ead7a..3f4d682446 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1061,7 +1061,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, void *haddr; uint8_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, access_type); ret =3D ldub_p(haddr); clear_helper_retaddr(); @@ -1075,7 +1075,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_2(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1093,7 +1093,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint32_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_4(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1111,7 +1111,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint64_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_8(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1130,7 +1130,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr, MemOp mop =3D get_memop(oi); =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_LOAD); ret =3D load_atom_16(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1146,7 +1146,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, { void *haddr; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, MMU_DATA_STORE); stb_p(haddr, val); clear_helper_retaddr(); @@ -1158,7 +1158,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1174,7 +1174,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1190,7 +1190,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1206,7 +1206,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, void *haddr; MemOpIdx mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350731; x=1745955531; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NFR9lsWoMXNYRBlDfEvBXzbnQL4knAWePayfKJdKcZo=; b=P1WNj+bwGmp8ugxK1jKvHw0yQRI1PsMmNOIHzLfSrHQxPrVKLFMJHnJ9xlW8NR9xBo 9HFi8WQFDbB3g/NpbEkNknbRUWOzQ0T7rbLl+cSrfGwjR9eQ3Q22ykqKa8ockFtDAsdF yqvLpsq+XvRw8gjjYh34OYSsyUkWhKzmk4LQp5ZHEUVj3pEcvkD4yeu1WSc4Z19hXZAt SurUNqa+/3L5NmHmjpUFlrAPKaFiXUd19Z9d4N5jZdMjWkJCzqOfIF70zY3KWnkeiwRE DAGzXtW8bMBYY8e00NONB9oNxtchtcoaNeZ/dv8lsh6tKnkEAJTfK09pV6XmQFxZbGhY WSIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350731; x=1745955531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NFR9lsWoMXNYRBlDfEvBXzbnQL4knAWePayfKJdKcZo=; b=lCscyYEnk9aw4lWncIttcLOiQEjjr1urAUFBZM/KcV1dVV8PPIxUvL8/Q4tMCTlSj7 nAk5SVw8+6u3Scl87bCrION5mE3LFGifN/no/EOzdjl/uuvJ5nJA1P0ekU8zb+a5W/zX PbkRCFVbGs/+xM/MtxiupVPFTnHLom8zoynXqo+E7TMoZMWp3xUQyzoB82tZ7ZsqJWOR KL1e6zY2VoFl9rBFsuk6tMoaLjLeqSZUebkf20OvoRGeo6eiEpjqMhDVuQbQHjnO2Cfn F+djx4OurtRqnMwe7KkQxq6nd3DK2X5sodJ4o9L4SvWUXnSh8wAndAMToCAiWpk+WuD7 FE5Q== X-Gm-Message-State: AOJu0Yzx7n1LifGggWP2lv3L5l1Ypr3LkXtXjitd15RmgAoJvZGfaPjF 6anZ50rGLVlMoAN1rM5rPf/gLSwFxjqB6AwEgfvHkoZndkVN86HAvVL9Ef5fZ0z8bzxD2Cdf7Zo b X-Gm-Gg: ASbGnctSYx7yBktnszcOR0OZEF0ByFr3A1RIL5x39TDYLxWvZDwKTYTtYOFyHOQ0tkj PWzyOtbNj7JNRAb1N5HRMQ6MwcTQyl+yKaO+rvAXWkoQ/4jwDOyvLPwKv1Sjyjl/hFdGo9AYrj+ HLjner1zjMN7+RHaZ9cIfTwMMR2gNKl+Qb5cRN7roMC8huhL0xeRb9uDnGFIDGU7SxbJYyWY7rN BbD1ExPWA4F21gpn+DmBq1ydX09MehwV02MKfagmgQ09A9XlaAuh6gqaznRaE9xtr1rO8hH0UCw VfHIE/P+Lf4DBtr7Kn6/+Fx9goZDjxrsKm2hb+60r6hAKJjVc37CoyoHsri633ZDzoknUCJdWDA = X-Google-Smtp-Source: AGHT+IGKhPtN38jryYnImHi6oAruAJqqx6NzT3JhvY/HSUk2qIyahtf81egAcj939wy31z44SHFrzw== X-Received: by 2002:a17:902:e544:b0:216:2bd7:1c2f with SMTP id d9443c01a7336-22c5359c356mr202602155ad.18.1745350731528; Tue, 22 Apr 2025 12:38:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 137/147] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order Date: Tue, 22 Apr 2025 12:28:06 -0700 Message-ID: <20250422192819.302784-138-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351272998019100 From: Philippe Mathieu-Daud=C3=A9 In order to use TCG with multiple targets, replace the compile time use of TCG_GUEST_DEFAULT_MO by a runtime access to TCGCPUOps::guest_default_memory_order via CPUState. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/internal-target.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 23aac39b57..f5a3fd7e40 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -46,16 +46,15 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); =20 /** * tcg_req_mo: + * @guest_mo: Guest default memory order * @type: TCGBar * * Filter @type to the barrier that is required for the guest * memory ordering vs the host memory ordering. A non-zero * result indicates that some barrier is required. - * - * This is a macro so that it's constant even without optimization. */ -#define tcg_req_mo(type) \ - ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) =20 /** * cpu_req_mo: @@ -67,7 +66,7 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t= retaddr); */ #define cpu_req_mo(cpu, type) \ do { \ - if (tcg_req_mo(type)) { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)= ) { \ smp_mb(); \ } \ } while (0) --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351017; cv=none; d=zohomail.com; s=zohoarc; b=XexxgwOawlv8SQ5fLN0+vPhlN8T5kC8gEShCwdF6cSKhL+AQEWxoq9pibs1bAk9Yed9Kp43p87C0tTwWtHt7AkSGGoK6R46CKl2USzNwQkBh9p42lQ3wMzxbK+4T62jmrtQ+NduU3I/X+yi1CNXU6aTVFKWaOLfieqdyoJ7dA5w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351017; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YYHQtuGiuymmjGUHHCn+9yiZGa5qUf/qG4Dwvjes2M8=; b=aLivp+IjJQDeVcKyFmLbaT6TueyWh07It5fN/PBjhoT9X09r1WwKSZujT6TV9LA+FJCDai0St/TBI2pqB9x4i77oO9WhU0JEmLHunkjzj/xpGqtNp8IMLOwqan2JiA4vL2WF+NmWez2qSLzA+TPKZdtd4c+DhlfnNQs+V+ugJTY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTP id 1745351017477125.36820240693316; Tue, 22 Apr 2025 12:43:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JSw-0005dp-EO; Tue, 22 Apr 2025 15:39:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSN-0004Ke-KF for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:02 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSI-0007Mz-8r for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:58 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-225df540edcso2926905ad.0 for ; Tue, 22 Apr 2025 12:38:53 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350732; x=1745955532; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YYHQtuGiuymmjGUHHCn+9yiZGa5qUf/qG4Dwvjes2M8=; b=mWmWGYmtTKYJrPuHG4TDrt21tsiCcaVUk6yYAB9lmSlt0lWB9rtAhj7UyxwfpDufQQ /DWeHEUGS5T4U2sgEX5jDnBEBYgMyMV3jKTP6SWQ5jMpVHYp/OzE/J8CFRQUUp6jZSUZ 4eOzio1uXRt+nKeuFvCyW+iy1k4jBQHAIqqJvrTPXq4FVM2eqmLVGR6h0AEnH9J2ji4r O/OUWM/1UqNZIENFp4Y+xDBainvNcztEn/IenhhSCcE2AoZwf1XVE2Um/bbNKNSq0qx9 oUc1751UghCSWeMQxf2Y4sEt7lStqiOvKm1N8FWLBkoOJhurps8+OI4qiQQon9262UnP 8+tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350732; x=1745955532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YYHQtuGiuymmjGUHHCn+9yiZGa5qUf/qG4Dwvjes2M8=; b=MR5Yk4AqcEEVQBnbsPW05J+nuNK2GIbiZAt8dacRBjQKdnHa19d4DJKRkUFl0qK/WM M5nf/Xfzu63P6vvgxZY8iYQjnTJvvk1nCtYQrWhnUM/PGQ7q0m02bwmzbOfWOOnhxJq7 h5bL7axs5mBu9cF+hgp2VDr+17GHymxjbnzys6xt9FwmD42KbvpjXlPMVk+hYy55Pynj GsHifVIS9J8lLKmaghEibwTUsErHlPwjMdm/60UrnYc34Nfl/jdZIPeb68cuNX/loKIX Sb05p+OkFgImBNYaMNyLEMgfF/41U/HNIBUGUuhmaLbFYr1abR9+J64wZ2fdsmaRfSL6 vAgA== X-Gm-Message-State: AOJu0YxxNOlvLsdiscAGmxuBp4OBA0/E1C9uSo9mIAXrqlp6SaoxQZ9v YqtBVJnFoLHyYURvgfLW6uDNYUjRzfIQ4Ft7XPw4XTrTWSS/Gtq+Pup3WUnLdRYVylSaMV49Iu5 y X-Gm-Gg: ASbGncsHsoZZXp3LNMDVvtswMVGOrj5ur7fJ3DTP/0TcKQF55pPRG4YiIXoyKBkJKGh 2dP7Kg1I5NljLWd9cReyxjbc/z/1Yu5PN7/4UhtwFfxgADCuBso5l6X0RcuBeE4j8rpRCH42uLW Ti0vjtuRoh89+gMxifN0sGMAlBYY8eqIxSyff0+dIQ3mn/gXuWhyxFtcAXeuWKXnUsbS2JNIDFu ibU36pA5JgJsaAEgxFHaT2mYyNvP1f9CYhCLaI8zCn+QqYfmJey2bL+J73KAvVF//cZBCS6nE+w dfrpC/aKyqmMfcgzN3OvX1VicnRIqwzNN2/yoATOV/DFbOmMLgCCgS3v3BImA3LiD6Ew0a1n3H4 = X-Google-Smtp-Source: AGHT+IGcQLtbxyx2uOMoqKIoGGIuTmfPcp67/Mr5G0QviRRI/ceiPa2EG9v4wGc5Qh9TOhGbbJT1pg== X-Received: by 2002:a17:902:ce8c:b0:221:8568:c00f with SMTP id d9443c01a7336-22da303cf77mr3954985ad.0.1745350732238; Tue, 22 Apr 2025 12:38:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH 138/147] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally Date: Tue, 22 Apr 2025 12:28:07 -0700 Message-ID: <20250422192819.302784-139-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351018676019100 From: Philippe Mathieu-Daud=C3=A9 By directly using TCGCPUOps::guest_default_memory_order, we don't need the TCG_GUEST_DEFAULT_MO definition anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/alpha/cpu-param.h | 3 --- target/arm/cpu-param.h | 3 --- target/avr/cpu-param.h | 2 -- target/hexagon/cpu-param.h | 3 --- target/hppa/cpu-param.h | 8 -------- target/i386/cpu-param.h | 3 --- target/loongarch/cpu-param.h | 2 -- target/m68k/cpu-param.h | 3 --- target/microblaze/cpu-param.h | 3 --- target/mips/cpu-param.h | 2 -- target/openrisc/cpu-param.h | 2 -- target/ppc/cpu-param.h | 2 -- target/riscv/cpu-param.h | 2 -- target/rx/cpu-param.h | 3 --- target/s390x/cpu-param.h | 6 ------ target/sh4/cpu-param.h | 3 --- target/sparc/cpu-param.h | 23 ----------------------- target/tricore/cpu-param.h | 3 --- target/xtensa/cpu-param.h | 3 --- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 3 ++- target/arm/tcg/cpu-v7m.c | 3 ++- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 3 ++- target/hppa/cpu.c | 8 +++++++- target/i386/tcg/tcg-cpu.c | 5 ++++- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 3 ++- target/s390x/cpu.c | 6 +++++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 23 ++++++++++++++++++++++- target/tricore/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- docs/devel/multi-thread-tcg.rst | 4 ++-- 40 files changed, 66 insertions(+), 101 deletions(-) diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index dd44feb179..a799f42db3 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -26,7 +26,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* Alpha processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 2cee4be693..5c5bc8a009 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -44,7 +44,4 @@ */ #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -/* ARM processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 9d37848d97..f74bfc2580 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -27,6 +27,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 7cc63a01d4..635d509e74 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,7 +25,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 68ed84e84a..9bf7ac76d0 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -21,12 +21,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -/* PA-RISC 1.x processors have a strong memory model. */ -/* - * ??? While we do not yet implement PA-RISC 2.0, those processors have - * a weak memory model, but with TLB bits that force ordering on a per-page - * basis. It's probably easier to fall back to a strong memory model. - */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 0c8efce861..ebb844bcc8 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,7 +24,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* The x86 has a strong memory model with some store-after-load re-orderin= g */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index dbe414bb35..58cc45a377 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -15,6 +15,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 10a8d74bfa..256a2b5f8b 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -19,7 +19,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 5d55e0e3c4..e0a3794513 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -29,7 +29,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* MicroBlaze is always in-order. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 99ca8d1684..58f450827f 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -22,6 +22,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 7ea0ecb55a..b4f57bbe69 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -14,6 +14,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index d0651d2ac8..e4ed9080ee 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -39,6 +39,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index ff4ba81965..cfdc67c258 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -34,6 +34,4 @@ * - M mode HLV/HLVX/HSV 0b111 */ =20 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index fe39a77ca3..84934f3bca 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -26,7 +26,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index a8a4377f4f..abfae3bedf 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -14,10 +14,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -/* - * The z/Architecture has a strong memory model with some - * store-after-load re-ordering. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index acdf239749..f328715ee8 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -18,7 +18,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 62d47b804b..45eea9d6ba 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -23,27 +23,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* - * From Oracle SPARC Architecture 2015: - * - * Compatibility notes: The PSO memory model described in SPARC V8 and - * SPARC V9 compatibility architecture specifications was never implemen= ted - * in a SPARC V9 implementation and is not included in the Oracle SPARC - * Architecture specification. - * - * The RMO memory model described in the SPARC V9 specification was - * implemented in some non-Sun SPARC V9 implementations, but is not - * directly supported in Oracle SPARC Architecture 2015 implementations. - * - * Therefore always use TSO in QEMU. - * - * D.5 Specification of Partial Store Order (PSO) - * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. - * - * D.6 Specification of Total Store Order (TSO) - * ... PSO with the additional requirement that all [stores] are followed - * by an implied MEMBAR #StoreStore. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) - #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 45fde756b6..eb33a67c41 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -14,7 +14,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index e7cb747aaa..7a0c22c900 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -18,7 +18,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 6f931117a2..eeaf3a81c1 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,7 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps alpha_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* Alpha processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3f20e258fd..3e9760b551 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,7 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { =20 #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* ARM processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 4553fe9de0..89d4e4b4a2 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,7 +232,8 @@ static void cortex_m55_initfn(Object *obj) } =20 static const TCGCPUOps arm_v7m_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* ARM processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 67918684fa..8f79cf4c08 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,7 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps avr_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b12e0dccd0..3d14e5cc6a 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -325,7 +325,8 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hexagon_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ac4560febe..dfbd933056 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,7 +253,13 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hppa_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* PA-RISC 1.x processors have a strong memory model. */ + /* + * ??? While we do not yet implement PA-RISC 2.0, those processors have + * a weak memory model, but with TLB bits that force ordering on a per= -page + * basis. It's probably easier to fall back to a strong memory model. + */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3e1b315340..d941df0956 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,7 +125,10 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps x86_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * The x86 has a strong memory model with some store-after-load re-ord= ering + */ + .guest_default_memory_order =3D TCG_MO_ALL & ~TCG_MO_ST_LD, .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ee74509a66..f5b8ef29ab 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,7 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps loongarch_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index bfde9b8594..b2d8c8f1de 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,7 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps m68k_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index e46863574c..4efba0dddb 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,7 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps mb_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MicroBlaze is always in-order. */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 67a8550cc1..2ae7ba4407 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -551,7 +551,7 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) } =20 static const TCGCPUOps mips_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e62c698a40..87fe779042 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,7 +243,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps openrisc_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 1cf18e0dae..9ba775971a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7479,7 +7479,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps ppc_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, .restore_state_to_opc =3D ppc_restore_state_to_opc, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ded2d68ad7..50e81b2e52 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,7 +140,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } =20 static const TCGCPUOps riscv_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index d7eac551fd..f073fe8fc9 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,7 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps rx_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index f232d82fa3..1e101b5afe 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,7 +345,11 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *p= c, } =20 static const TCGCPUOps s390_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * The z/Architecture has a strong memory model with some + * store-after-load re-ordering. + */ + .guest_default_memory_order =3D TCG_MO_ALL & ~TCG_MO_ST_LD, =20 .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 29f4be7ba9..7a05301c6f 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,7 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps superh_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ef04efcb18..56d9417ae3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,7 +1001,28 @@ static const struct SysemuCPUOps sparc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps sparc_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * From Oracle SPARC Architecture 2015: + * + * Compatibility notes: The PSO memory model described in SPARC V8 a= nd + * SPARC V9 compatibility architecture specifications was never + * implemented in a SPARC V9 implementation and is not included in t= he + * Oracle SPARC Architecture specification. + * + * The RMO memory model described in the SPARC V9 specification was + * implemented in some non-Sun SPARC V9 implementations, but is not + * directly supported in Oracle SPARC Architecture 2015 implementati= ons. + * + * Therefore always use TSO in QEMU. + * + * D.5 Specification of Partial Store Order (PSO) + * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadSt= ore. + * + * D.6 Specification of Total Store Order (TSO) + * ... PSO with the additional requirement that all [stores] are fol= lowed + * by an implied MEMBAR #StoreStore. + */ + .guest_default_memory_order =3D TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_S= T_ST, =20 .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 3bf399335a..c68954b409 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,7 +172,8 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps tricore_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 2347106495..2cbf4e3010 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,7 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps xtensa_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* Xtensa processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.= rst index b0f473961d..14a2a9dc7b 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -28,8 +28,8 @@ vCPU Scheduling We introduce a new running mode where each vCPU will run on its own user-space thread. This is enabled by default for all FE/BE combinations where the host memory model is able to accommodate the -guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the -guest has had the required work done to support this safely +guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is z= ero) +and the guest has had the required work done to support this safely (TARGET_SUPPORTS_MTTCG). =20 System emulation will fall back to the original round robin approach --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351952; cv=none; d=zohomail.com; s=zohoarc; b=jZzANJ/KUrL2QYrfYEx7ToB/6zkwC0X14v2PVhl1zfGv+lcWczETqcoKnjnZIrb+neSGJo37Fm0RPjkXMCsvEntyoXTJsZfxxJwG8LcGK5woGxu/d3LgSn+C+POSiHWMHI+TlHNrbfIIa3vdgINEMdhD48Nm5b6MdL+S2ksdqvk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351952; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7VXEDUlPkpIMjb0Jt+mGuDdJy2bXxmmNFXU1sXIXZA4=; b=fw5oTmZ0X0BWb7qHVzckxXkQqz0TmTFwDdukuCjBFGWW/ConVR/R9sxBoFsX9ryOtqv57Nbu9jrn469/3fDvFUUc0H8upCGjN1Xp1CvbHVEdlaucXAe57EQ9JbTJfDCJ311KzCGmeL4nySEOvCssDH5Z2p2tno8XgnGTYQ84ZyE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351952253116.3507506186462; Tue, 22 Apr 2025 12:59:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JT2-00065r-K0; Tue, 22 Apr 2025 15:39:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSM-0004ID-6R for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:02 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSI-0007N3-Pa for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:56 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-224191d92e4so55809375ad.3 for ; Tue, 22 Apr 2025 12:38:53 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350733; x=1745955533; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7VXEDUlPkpIMjb0Jt+mGuDdJy2bXxmmNFXU1sXIXZA4=; b=eN45/jjB0RY2W+mI+d7ds/ol9TQLgN4oyclBRCK8TTaY/5xf+uQQP3dnfRoMsUO69l QpQCMfmkHaoKAVOlrutUa2cEd1cB/dOZcsApZYEpN6bG22nI7RgaB0WVzqupii9xyUah y09K6sCNfs6R/MY+jdPAuXT+0EnODgq2s5nxfeJ+uqrONOM05zHygwOWiDyZlkxpFWut yMOmlVBHvHcCakQ96WKsIWNEbYAWFvod230k+AICpPNZvxq4ru+0UQN3pz0wgK/nm/3H fBAbRNKhWSPbG6QD5kieSCYb4G/SGLnH5nielTHe8n9SNdV4yuSH1LaAJvXuO8ykSpYU ZYoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350733; x=1745955533; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7VXEDUlPkpIMjb0Jt+mGuDdJy2bXxmmNFXU1sXIXZA4=; b=wjU3z065KZg6vfH5QR4yYZlDndudYPPXCq/fBVtFAyrdTloPttCOHCsSnBv/CblLi1 18EpJKph2TAEYeLXOZa2lRw6VUWn0SHB7wEK4sdFxbePNujeW3xtjDjsObOvUuukUdbb a84jI36bdwSQ4c0jjiYBH+/TxEelLrodolrv8CnSNhguBNkqzpLHHrHEmAaze2xaUafc LzLsr1iYNBYEQXdjiVs2NT8fvLxyh78oNWhdLrQzI1Zj/hOryRecuLcMhtEaG28MHFy8 tKwmsjJrIoUVR1qzT1fF50LBaDwyeF+f6vCexwQEt8gRiIGQNvfqRlrESY0Eco6hRDEM XMqA== X-Gm-Message-State: AOJu0YyX1pFBEcXkOAkGdWgKdWtWLig4b1S/K2kxBu0imZIJGvM0ekpA hGRwsh5mqXvtWBpNg/CPvfmFL8TXhLXux2ZB4cyKPsNZT3gh8DNeFmwTGNJjN2qtQ7u8TVtPGAT U X-Gm-Gg: ASbGncscbt2N9rv+J07D2f/5mYGmnAn+HMUlnW+eMaDOD78Vmg8z818e4/uAbblqj/z 0YaBcLxhoprNAJpNWxiBRWEu0gjP0x4Y65a3rG5w+HidvkbNntvduGeqcp1qaQ6rqiGsdBp/Ynt TG2BmDpSnZ8s3M30tZg3j0u/WU1m7jKsvwsv2ePm2GT59cl+Fmq1KrHxFCIRrALHeAggvhn1YMP JWPZV3+lUTlchR0AyiQgH5qvX5/fwnaLOoabCjCaHJ7bEczzdDmDdBdNdhtA1sCY2EyQGjqLswp t5w/S7kMH/unTuqNu5tF5Z+79WtE9+sJljV6EmL34iCMYvJ/80Dfp2N7SwTcHaAIytdBd1ly+qq CehV0QOnD7Q== X-Google-Smtp-Source: AGHT+IFQ8rq2FwLQqzpSBXBSMOu4zyjLi+dXKlCkxTAZubN39f245Dgu51poAQwbov95rW8CYg9Y/Q== X-Received: by 2002:a17:903:46cb:b0:225:ac99:ae08 with SMTP id d9443c01a7336-22c5337a025mr262341995ad.5.1745350732868; Tue, 22 Apr 2025 12:38:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 139/147] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Date: Tue, 22 Apr 2025 12:28:08 -0700 Message-ID: <20250422192819.302784-140-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351954578019100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/backend-ldst.h | 41 +++++++++++++++++++++++++++++++++++++ accel/tcg/internal-target.h | 28 ------------------------- accel/tcg/cputlb.c | 1 + accel/tcg/user-exec.c | 1 + 4 files changed, 43 insertions(+), 28 deletions(-) create mode 100644 accel/tcg/backend-ldst.h diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h new file mode 100644 index 0000000000..9c3a407a5a --- /dev/null +++ b/accel/tcg/backend-ldst.h @@ -0,0 +1,41 @@ +/* + * Internal memory barrier helpers for QEMU (target agnostic) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_BACKEND_LDST_H +#define ACCEL_TCG_BACKEND_LDST_H + +#include "tcg-target-mo.h" + +/** + * tcg_req_mo: + * @guest_mo: Guest default memory order + * @type: TCGBar + * + * Filter @type to the barrier that is required for the guest + * memory ordering vs the host memory ordering. A non-zero + * result indicates that some barrier is required. + */ +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) + +/** + * cpu_req_mo: + * @cpu: CPUState + * @type: TCGBar + * + * If tcg_req_mo indicates a barrier for @type is required + * for the guest memory model, issue a host memory barrier. + */ +#define cpu_req_mo(cpu, type) \ + do { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)= ) { \ + smp_mb(); \ + } \ + } while (0) + +#endif diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index f5a3fd7e40..9a9cef3140 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -13,7 +13,6 @@ #include "exec/exec-all.h" #include "exec/translation-block.h" #include "tb-internal.h" -#include "tcg-target-mo.h" #include "exec/mmap-lock.h" =20 /* @@ -44,31 +43,4 @@ void page_table_config_init(void); G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); #endif /* CONFIG_USER_ONLY */ =20 -/** - * tcg_req_mo: - * @guest_mo: Guest default memory order - * @type: TCGBar - * - * Filter @type to the barrier that is required for the guest - * memory ordering vs the host memory ordering. A non-zero - * result indicates that some barrier is required. - */ -#define tcg_req_mo(guest_mo, type) \ - ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) - -/** - * cpu_req_mo: - * @cpu: CPUState - * @type: TCGBar - * - * If tcg_req_mo indicates a barrier for @type is required - * for the guest memory model, issue a host memory barrier. - */ -#define cpu_req_mo(cpu, type) \ - do { \ - if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)= ) { \ - smp_mb(); \ - } \ - } while (0) - #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 35b1ff03a5..d9fb68d719 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -48,6 +48,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" =20 =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f4d682446..5eef8e7f18 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -37,6 +37,7 @@ #include "qemu/int128.h" #include "trace.h" #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" #include "internal-common.h" #include "internal-target.h" #include "tb-internal.h" --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351392; cv=none; d=zohomail.com; s=zohoarc; b=WanHl/7oJPtP7r4nqMB/xVBBkLwT5ptuqNIHr208bU/4I6wg5Wg/fqiTipAyp0TTcjOEADED9MoJ1TjP/N3z5zZIvMIElODM/4XmesE9lF8PtgYkIKdQh1afVx8WTYEZon0qY7vXljavs6vsjBIekFVV8DmdHr9XqaNN2ckqkAM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351392; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7dzx5TGrM0CiSq77kWcMK2agZzO7Wx5pZTOsmWaPtYI=; b=b01GQ9hMCgKytMjwo15LhBPt1jYPKyp1V48Fms8TAPcTppfaB/seFAIOPOXKZdXxBeg0UXIfTg35BmioSh7sa51DQtoh9TbexbghkSBaHBjnapgrgQ/u6A42odKrzt3FmK6BfrzAsGlZlnWIiFKpFwXh3olSPWzXBoQEAadpx/o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351392347906.0708657757414; Tue, 22 Apr 2025 12:49:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JTG-0006vi-Mu; Tue, 22 Apr 2025 15:39:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSN-0004JI-31 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:02 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSJ-0007NH-9t for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:57 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-22409077c06so78139085ad.1 for ; Tue, 22 Apr 2025 12:38:54 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350734; x=1745955534; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7dzx5TGrM0CiSq77kWcMK2agZzO7Wx5pZTOsmWaPtYI=; b=PkOaG5mRrJEDvn1sNZAllGG38vIxaNCNb4PwmtFP3ylKtkXCmiP1g4waz8zx+NLJ8u IR7g/xg1YwAMvIUy8Bv58TqUCMSqiITQpmNmw4ZE/LxcfjbTFK+PbrTvG9151IORE5RC xXfatadu6JTbfjggSBh7dT3hDery+JbSrOWbl6NblUj4jt6wYa0E55ZjS8p2m5OFtFd4 KS206Rp0g7N44Dq9gA6X8o3Jg4YPXQx7c4sC8pT1I8m48iMTathwbkUlNzC2za4WPLzl M4MvwvWpj5iBIebeLMS1gwtiFeF/1nboYn8ZAtdM6fpVdiYPO+cgd7nD2uekl1zUn7d+ jcuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350734; x=1745955534; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7dzx5TGrM0CiSq77kWcMK2agZzO7Wx5pZTOsmWaPtYI=; b=mn5CJWV4OrKH8xyvme5I8SEOsP1OPxgfBm/DiSHh3mICELOi6v4EtoUd3RNyXHNtd1 /dfrWOy0bnyHI176qL2Aezs7px9Z+2BQTnrpi+xkRdv+hk+Jh9p6WIwwC+GZxN3eQWaX BO1kwPc3+I3FnEjWujRQDgS6CgCvLUDrrYVjXZ5xL3fijPzbs2+4bwEYkENMu0iQHz0O +zL8St55jzLmFDyRU62VI20j5q/45+TFzA3WzT1svXTmbOqMbCkTXDi9S987Qx2HSQ6s GCnUq/lKu/Ow4KF+9WLZWK9sjU+bP+B0+72AbCGw/gyUBx/ph5hEkqfhOUSYJ1vJzuOg 7v9g== X-Gm-Message-State: AOJu0YxdpTa78WxAjHTNIUASU0fwXEorSM//H9YkRRi4saSNYRaXOmS4 WLFTFoAVlGKhjdC6Z0iLt1A/SCCxjf+GyqePpwP8xuo68S6sBllpA2MEoX1rRp8Y0tQ448FG6nk V X-Gm-Gg: ASbGncs+DmdRUXjnXZSDe5HaLVOzgF5TDJIfTeLqN5coE6Kcauxqj0hJ17gb+FqaOFq U8oRZMLLUq+eMCxfslzrE9sJ0BmczNjnfAweRn7rJo30n17XKyv35nBFYy8ynRNM14Y2QKkEi/z Y3ic6LrF7YFJKU3Afj9zBhjoJfWodx+q/Lp+1IRSO7L0Ou8v/AE+Q6V9GxbWmocWa6HlEi0Z2mF 5TchPI52nhhFN2wgu5rIzN+8eZX5u/wVj1nPffaFu317+FWPiam5GJNbgiLCL94ZMAsAMzhVVqU wYIAHuL7R08MYRLyaKwTiV4cVMFbWltoeRX0tZSQTR6anaUy+qOD93S31EUn8m2Rqdte+d0tb64 = X-Google-Smtp-Source: AGHT+IHkcj9qzsjO/OFW8PJAQ6o4JOtrPJjPd1i0doqVjQYmsjWlaGK7s9n5V7UgBHslHs1N6WF15Q== X-Received: by 2002:a17:903:32d1:b0:224:fa0:36da with SMTP id d9443c01a7336-22c5358321dmr212298325ad.18.1745350733525; Tue, 22 Apr 2025 12:38:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 140/147] tcg: Pass max_threads not max_cpus to tcg_init Date: Tue, 22 Apr 2025 12:28:09 -0700 Message-ID: <20250422192819.302784-141-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351393659019100 Content-Type: text/plain; charset="utf-8" In effect, hoist the check for mttcg from tcg_n_regions() to tcg_init_machine(). Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/tcg/startup.h | 6 +++--- tcg/tcg-internal.h | 2 +- accel/tcg/tcg-all.c | 14 ++++++++------ tcg/region.c | 27 ++++++++++++--------------- tcg/tcg.c | 14 +++++++------- 5 files changed, 31 insertions(+), 32 deletions(-) diff --git a/include/tcg/startup.h b/include/tcg/startup.h index f71305765c..95f574af2b 100644 --- a/include/tcg/startup.h +++ b/include/tcg/startup.h @@ -29,12 +29,12 @@ * tcg_init: Initialize the TCG runtime * @tb_size: translation buffer size * @splitwx: use separate rw and rx mappings - * @max_cpus: number of vcpus in system mode + * @max_threads: number of vcpu threads in system mode * * Allocate and initialize TCG resources, especially the JIT buffer. - * In user-only mode, @max_cpus is unused. + * In user-only mode, @max_threads is unused. */ -void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); +void tcg_init(size_t tb_size, int splitwx, unsigned max_threads); =20 /** * tcg_register_thread: Register this thread with the TCG runtime diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index a648ee7a0e..ff85fb23fa 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -34,7 +34,7 @@ extern TCGContext **tcg_ctxs; extern unsigned int tcg_cur_ctxs; extern unsigned int tcg_max_ctxs; =20 -void tcg_region_init(size_t tb_size, int splitwx, unsigned max_cpus); +void tcg_region_init(size_t tb_size, int splitwx, unsigned max_threads); bool tcg_region_alloc(TCGContext *s); void tcg_region_initial_alloc(TCGContext *s); void tcg_region_prologue_set(TCGContext *s); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index a5a1fd6a11..3efc7350eb 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -103,18 +103,20 @@ bool one_insn_per_tb; static int tcg_init_machine(MachineState *ms) { TCGState *s =3D TCG_STATE(current_accel()); -#ifdef CONFIG_USER_ONLY - unsigned max_cpus =3D 1; -#else - unsigned max_cpus =3D ms->smp.max_cpus; -#endif + unsigned max_threads =3D 1; =20 tcg_allowed =3D true; mttcg_enabled =3D s->mttcg_enabled; =20 page_init(); tb_htable_init(); - tcg_init(s->tb_size * MiB, s->splitwx_enabled, max_cpus); + +#ifndef CONFIG_USER_ONLY + if (mttcg_enabled) { + max_threads =3D ms->smp.max_cpus; + } +#endif + tcg_init(s->tb_size * MiB, s->splitwx_enabled, max_threads); =20 #if defined(CONFIG_SOFTMMU) /* diff --git a/tcg/region.c b/tcg/region.c index 478ec051c4..7ea0b37a84 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -422,7 +422,7 @@ void tcg_region_reset_all(void) tcg_region_tree_reset_all(); } =20 -static size_t tcg_n_regions(size_t tb_size, unsigned max_cpus) +static size_t tcg_n_regions(size_t tb_size, unsigned max_threads) { #ifdef CONFIG_USER_ONLY return 1; @@ -431,24 +431,25 @@ static size_t tcg_n_regions(size_t tb_size, unsigned = max_cpus) =20 /* * It is likely that some vCPUs will translate more code than others, - * so we first try to set more regions than max_cpus, with those regio= ns + * so we first try to set more regions than threads, with those regions * being of reasonable size. If that's not possible we make do by even= ly * dividing the code_gen_buffer among the vCPUs. + * + * Use a single region if all we have is one vCPU thread. */ - /* Use a single region if all we have is one vCPU thread */ - if (max_cpus =3D=3D 1 || !qemu_tcg_mttcg_enabled()) { + if (max_threads =3D=3D 1) { return 1; } =20 /* - * Try to have more regions than max_cpus, with each region being >=3D= 2 MB. + * Try to have more regions than threads, with each region being >=3D = 2 MB. * If we can't, then just allocate one region per vCPU thread. */ n_regions =3D tb_size / (2 * MiB); - if (n_regions <=3D max_cpus) { - return max_cpus; + if (n_regions <=3D max_threads) { + return max_threads; } - return MIN(n_regions, max_cpus * 8); + return MIN(n_regions, max_threads * 8); #endif } =20 @@ -731,11 +732,7 @@ static int alloc_code_gen_buffer(size_t size, int spli= twx, Error **errp) * and then assigning regions to TCG threads so that the threads can trans= late * code in parallel without synchronization. * - * In system-mode the number of TCG threads is bounded by max_cpus, so we = use at - * least max_cpus regions in MTTCG. In !MTTCG we use a single region. - * Note that the TCG options from the command-line (i.e. -accel accel=3Dtc= g,[...]) - * must have been parsed before calling this function, since it calls - * qemu_tcg_mttcg_enabled(). + * In system-mode the number of TCG threads is bounded by max_threads, * * In user-mode we use a single region. Having multiple regions in user-m= ode * is not supported, because the number of vCPU threads (recall that each = thread @@ -749,7 +746,7 @@ static int alloc_code_gen_buffer(size_t size, int split= wx, Error **errp) * in practice. Multi-threaded guests share most if not all of their trans= lated * code, which makes parallel code generation less appealing than in syste= m-mode */ -void tcg_region_init(size_t tb_size, int splitwx, unsigned max_cpus) +void tcg_region_init(size_t tb_size, int splitwx, unsigned max_threads) { const size_t page_size =3D qemu_real_host_page_size(); size_t region_size; @@ -787,7 +784,7 @@ void tcg_region_init(size_t tb_size, int splitwx, unsig= ned max_cpus) * As a result of this we might end up with a few extra pages at the e= nd of * the buffer; we will assign those to the last region. */ - region.n =3D tcg_n_regions(tb_size, max_cpus); + region.n =3D tcg_n_regions(tb_size, max_threads); region_size =3D tb_size / region.n; region_size =3D QEMU_ALIGN_DOWN(region_size, page_size); =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index dfd48b8264..ec7f6743d7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1499,7 +1499,7 @@ static void process_constraint_sets(void); static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, TCGReg reg, const char *name); =20 -static void tcg_context_init(unsigned max_cpus) +static void tcg_context_init(unsigned max_threads) { TCGContext *s =3D &tcg_init_ctx; int n, i; @@ -1538,15 +1538,15 @@ static void tcg_context_init(unsigned max_cpus) * In user-mode we simply share the init context among threads, since = we * use a single region. See the documentation tcg_region_init() for the * reasoning behind this. - * In system-mode we will have at most max_cpus TCG threads. + * In system-mode we will have at most max_threads TCG threads. */ #ifdef CONFIG_USER_ONLY tcg_ctxs =3D &tcg_ctx; tcg_cur_ctxs =3D 1; tcg_max_ctxs =3D 1; #else - tcg_max_ctxs =3D max_cpus; - tcg_ctxs =3D g_new0(TCGContext *, max_cpus); + tcg_max_ctxs =3D max_threads; + tcg_ctxs =3D g_new0(TCGContext *, max_threads); #endif =20 tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); @@ -1554,10 +1554,10 @@ static void tcg_context_init(unsigned max_cpus) tcg_env =3D temp_tcgv_ptr(ts); } =20 -void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus) +void tcg_init(size_t tb_size, int splitwx, unsigned max_threads) { - tcg_context_init(max_cpus); - tcg_region_init(tb_size, splitwx, max_cpus); + tcg_context_init(max_threads); + tcg_region_init(tb_size, splitwx, max_threads); } =20 /* --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352662; cv=none; d=zohomail.com; s=zohoarc; b=PD5huDzIecO3GQvybXzpiHyYUYeruXc/5t45PiRACZ4fQ7dc/XI7HMmM5BT7+M00waDqKM19+Y9viO+PkduT7HfIbqADeWimxcUNuR9RuQKnFjmtBccue1q72V9AxSrAJFInbqB3aR0s0kya23TgfV8AfGD3AoS4B8T8NEd52nU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352662; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Lgi2ZSVQ13wT2MCsVR2Sol/xGooWiIWNyPhzHZZ9Q0k=; b=S9hD7Ob9LT+GUd1kDqOhG2kh7uyPLIROSCg6AVyk58mekWeCXP3BNFCysSpSTykAJ4UICv+E+MOMoXFkz1F4pG1PegJIrDfcVQ4T75PJbc4Pi596mCYrKnKwFMGIP3H74mQY/zRFeIp49Id9f+lZtCNRvOvdEhnrRN/anfkgAAQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17453526621491000.1534847558196; Tue, 22 Apr 2025 13:11:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JT9-0006Vh-GZ; Tue, 22 Apr 2025 15:39:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSN-0004Kd-I3 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:02 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSK-0007NM-2e for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:58 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-2254e0b4b79so85309145ad.2 for ; Tue, 22 Apr 2025 12:38:55 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350734; x=1745955534; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lgi2ZSVQ13wT2MCsVR2Sol/xGooWiIWNyPhzHZZ9Q0k=; b=V9NV6X2gO9YPyy1sIz1UgClUCoovnkHdJjQ4Cb+t+z7MsFQssdm/EWdzO40/2fLerP Mhz6o+YtybiPJnjFiActyGNxE1lS59L40UWWBnbZFe1gGg/uIIevAAk7eQrTjgKKNjJQ lgU/0LJhhdLN69Z7WYcXk4qtBe/JqO7hEza6a4zF9+thCGU6+dqDkOv8DH9gTsdDSjOL btcXURLRE5l/4l6+1/ggcsiebKhUzeo/DTdqyRHbuycEz4+GsHvjKHmjEzK04p8MaGRK 1w70ItkOLdq30sr2lPgsk9ByqyjFIzvnpaa7gX8wU8/wNWHrrKBm35dnHTXX6ivKGwLQ VO2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350734; x=1745955534; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lgi2ZSVQ13wT2MCsVR2Sol/xGooWiIWNyPhzHZZ9Q0k=; b=P7INJ0d17osGAbogwP1C7fqkUkSWpAxKb3YLcmapoiBFZUigLN+TQzWby6MZmNl8BQ aL+NUrjTkpDlVx88iyrYv4JffdhHG5qCcWykMuQ0Uv+8JqwN8MzMlUHh94ibDooMAyRb vmHA9/axGifx9Ldso5ECdaKRQGHdc8/ZAhek3LUuVF37/j4YuRD4ymqV1UMUu6BEW9Ae Vp+2fVoPS3aWrvOwjp0kJ9xQJmhBCbXACw0FAnFKVWhBJXWP88TFYczzzeK/AsoXtHHM AnyD9rcbrPqRNFIayP0o9c+4RULTAxCdhe+Wy3qBafwjhWfmETs3i5Pu5Yh3KIFbvipT DvLg== X-Gm-Message-State: AOJu0YwVdHFaf6CG+7df0qMow4K1o/3rE8edSLd/ZRINPJwfCtU0uoHM avVst8UsDsORqwMEIlE9CSe7sR+2Vbhr6cYjLhS7MGYg8Pzzq/HN8L6eFxVC4JiC6g5qbdBe+e4 8 X-Gm-Gg: ASbGncuIK/LBQz6Ee/SpuIxg+HZrzzH8MwIHa8BdzyPNkT09PA84WmM7JRksy+912X/ KVRdou4ofmXh1fWNEksTvmjNS1mY+0K6/jVhhGrlCD+F4DWtovPnKhFaXlawmLkvthfdQ1Xizcg ya2JCQgEg0LT9jPj38SovZ3nqyF8lNno0hKRxYUXbhF/JrsONdZ0kZzsfiP4RRf9MuEijMeZB9N dmTtgpfhMU/eERt2cTt15YreBqBF7kY+mVttCuRJZfdLJtNytRuMhktbevzXfTtHCzwZSXdNNYy UPaWmJbiImNg6I4rant9gVLmVIa1S8ki32bDewOsIHWdAmhRVzJ9gMtKfVJD0cz8UAe2020EfM8 = X-Google-Smtp-Source: AGHT+IGr+gExjmgnV7yjdS5opKkbSYL+ooMSYnyKBhvKwkj+sNHat9/zjcOC6/XzXYh52nRO0x8s6g== X-Received: by 2002:a17:902:e808:b0:223:8256:533d with SMTP id d9443c01a7336-22c536207d3mr243061725ad.46.1745350734114; Tue, 22 Apr 2025 12:38:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH 141/147] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Date: Tue, 22 Apr 2025 12:28:10 -0700 Message-ID: <20250422192819.302784-142-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745352664036019100 From: Philippe Mathieu-Daud=C3=A9 qemu_tcg_mttcg_enabled() is specific to 1/ TCG and 2/ system emulation. Move the prototype declaration to "system/tcg.h", reducing 'mttcg_enabled' variable scope. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-ID: <20250403220420.78937-17-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 9 --------- include/system/tcg.h | 8 ++++++++ accel/tcg/tcg-all.c | 17 ++++++++++++++--- target/riscv/tcg/tcg-cpu.c | 1 + 4 files changed, 23 insertions(+), 12 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 10b6b25b34..c8d6abff19 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,15 +594,6 @@ extern CPUTailQ cpus_queue; =20 extern __thread CPUState *current_cpu; =20 -/** - * qemu_tcg_mttcg_enabled: - * Check whether we are running MultiThread TCG or not. - * - * Returns: %true if we are in MTTCG mode %false otherwise. - */ -extern bool mttcg_enabled; -#define qemu_tcg_mttcg_enabled() (mttcg_enabled) - /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/include/system/tcg.h b/include/system/tcg.h index 73229648c6..7622dcea30 100644 --- a/include/system/tcg.h +++ b/include/system/tcg.h @@ -17,4 +17,12 @@ extern bool tcg_allowed; #define tcg_enabled() 0 #endif =20 +/** + * qemu_tcg_mttcg_enabled: + * Check whether we are running MultiThread TCG or not. + * + * Returns: %true if we are in MTTCG mode %false otherwise. + */ +bool qemu_tcg_mttcg_enabled(void); + #endif diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 3efc7350eb..bb759cec07 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -38,6 +38,7 @@ #include "hw/qdev-core.h" #else #include "hw/boards.h" +#include "system/tcg.h" #endif #include "internal-common.h" #include "cpu-param.h" @@ -58,6 +59,17 @@ typedef struct TCGState TCGState; DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, TYPE_TCG_ACCEL) =20 +#ifndef CONFIG_USER_ONLY + +static bool mttcg_enabled; + +bool qemu_tcg_mttcg_enabled(void) +{ + return mttcg_enabled; +} + +#endif /* !CONFIG_USER_ONLY */ + /* * We default to false if we know other options have been enabled * which are currently incompatible with MTTCG. Otherwise when each @@ -97,7 +109,6 @@ static void tcg_accel_instance_init(Object *obj) #endif } =20 -bool mttcg_enabled; bool one_insn_per_tb; =20 static int tcg_init_machine(MachineState *ms) @@ -106,14 +117,14 @@ static int tcg_init_machine(MachineState *ms) unsigned max_threads =3D 1; =20 tcg_allowed =3D true; - mttcg_enabled =3D s->mttcg_enabled; =20 page_init(); tb_htable_init(); =20 #ifndef CONFIG_USER_ONLY - if (mttcg_enabled) { + if (s->mttcg_enabled) { max_threads =3D ms->smp.max_cpus; + mttcg_enabled =3D true; } #endif tcg_init(s->tb_size * MiB, s->splitwx_enabled, max_threads); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 50e81b2e52..88f7cdb887 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" +#include "system/tcg.h" #endif =20 /* Hash that stores user set extensions */ --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351786; cv=none; d=zohomail.com; s=zohoarc; b=HSBgEV7pqCVVx6dac6JG/x1R8Od9sbZ8xoLnt47pB82BRTnDrAeVKttzCbv/Q7Oe5R6zWfWayegjpgYKym/nyXsQQAfA/QsdT11z+8Oy45kR1jfzQZw+dmAoLYz1ow22xxsDQWdmlcnjzxVAbagGfToxaA4maoYuARDkHkWVkzo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351786; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=q6jXpda4WDLp9/Pv3j909jBuMMAiayizqN/RLechrcE=; b=TkTVGNdKUX2FkVCz3MUFr8Q391odoRbxM/CSEwl1bf4ZxFkP5v/uHJglJjMJNgTLSdwWJnd43dQIAYB3xb5nSE+VdzRUI9MovdI2P3piWQbNP4j77cvpQ+AOJ973iXMZEpa5VdPNVU25odo0sbrtBN27P5oebLvg7KAJJvHPMWE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351786815823.8977580313116; Tue, 22 Apr 2025 12:56:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JT2-00065w-Ly; Tue, 22 Apr 2025 15:39:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSN-0004KY-H6 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:02 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSK-0007NS-No for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:58 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-b041afe0ee1so5107538a12.1 for ; Tue, 22 Apr 2025 12:38:55 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350734; x=1745955534; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=q6jXpda4WDLp9/Pv3j909jBuMMAiayizqN/RLechrcE=; b=JoH4W2zkHwKuAB9+2dJRzuBkxhT7eFdDpWVQ51p5B/JcPkik2Ezkf72q8T01K7GjTY FwBIQCd7AWD+K94JwSkWNWp91h088GXvllk9g1ZItOPpS/KwTPvO7iCOfa5cS2yrvcBl h8DpqTGJoB+XLKBArRdoZOkdthoAqgDkgvQ2oUuJSQC4Q6bm9gOuqAzd6w+qx/nb5QEW fV4UWLo1bx7l22lN5dBns7UDIrCxYecZgU5Adugh3OpnMlCAdhNczuosSlch9PuMC86t jrhOJSC9ni9taNGg3d8nwcG0EX6+2tAYtMlL3bUyXagsD5CURPRoeDXj5mQfxLYXRjdq UNKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350734; x=1745955534; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q6jXpda4WDLp9/Pv3j909jBuMMAiayizqN/RLechrcE=; b=gsuPJHCEUwXn7RfAy9uMhBwL54DfVcpyK1C9gis3TSCtvAYGY/p/yXAjGa8vmwF5YN De6rWQ4cRqdU1nWXGQz5hLXg3rv41AEEZOWYfvSwkj50htMW1eMnx5ssbu/fAll9h01P qZ6p3FkpXzZS5GRKqPgL6SsWRUUahpRT5ux6k7dnVgCJYEIOSUO5bD1YnA4rYko/erUS TET3M8K3iHnD0k7SPdFJTvz8aHCOqcgR5QRkRLAiB0NQ6SHNSnLLmYH2tBOVcfN22xXj l+xGPInBhpJHLJt4CbFQ51j81YgJszc6ZZSWu+xyQNmb5GKkd5N+9jIUOd+ic87QqfdW qLSQ== X-Gm-Message-State: AOJu0Yx1dgQFxd27ZKi5jJd1byaO+HXkkZ09//ViTFD4pUem5iwGz4uW E5lBsvP8cltu6k+cfvC0bVQWw7OpcL/PjazPe2S3i8QT24cNQyuFuwqEORAdwrY0XlflsEBhWWF p X-Gm-Gg: ASbGncuP9JpZUP1MnM83MTSx5v2YRyiEthelgZMVT5GKowLQCeWDdLd5lo03ptta6L9 xvkimeYOqG3G2T9n+cT8pvRyCbr6rrxGxu5roSawizBPNz34AlaJTYdkNs9y15xYInizXDgNusr y55rnWNPu7qIIwh9wMgBICtUjrQr3B2Yh2drL5yg1NfrEKExNepD4/oPPmGM06EtFWtnSdk5CrC kUX4LHruwB42rP9LqghZdbXGnowkdJ6iejWfm+52HrcqvUArrYaN7KdR1822UD9r8kd9XJzVWQF GHVHke0B0RbfVkCLRcw+G1XbhMJc+oZc4YnhlaaD/rSOP4A/eDXOQFOWvaH2XJvwTai+heQ0ShM = X-Google-Smtp-Source: AGHT+IFGkMQFRrmhCW6aPvFYG2MIaT8vo5xkK/oq7gizweh1nOHgsEEaE1iN7Tyas0nrUI22lGIDQQ== X-Received: by 2002:a17:902:e84f:b0:220:cd9a:a167 with SMTP id d9443c01a7336-22c5357a689mr272151435ad.4.1745350734699; Tue, 22 Apr 2025 12:38:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 142/147] accel/tcg: Remove mttcg_enabled Date: Tue, 22 Apr 2025 12:28:11 -0700 Message-ID: <20250422192819.302784-143-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351788060019000 Content-Type: text/plain; charset="utf-8" In qemu_tcg_mttcg_enabled, read the value from TCGState and eliminate the separate global variable. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-all.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index bb759cec07..b754f92905 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -60,14 +60,11 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, TYPE_TCG_ACCEL) =20 #ifndef CONFIG_USER_ONLY - -static bool mttcg_enabled; - bool qemu_tcg_mttcg_enabled(void) { - return mttcg_enabled; + TCGState *s =3D TCG_STATE(current_accel()); + return s->mttcg_enabled; } - #endif /* !CONFIG_USER_ONLY */ =20 /* @@ -124,7 +121,6 @@ static int tcg_init_machine(MachineState *ms) #ifndef CONFIG_USER_ONLY if (s->mttcg_enabled) { max_threads =3D ms->smp.max_cpus; - mttcg_enabled =3D true; } #endif tcg_init(s->tb_size * MiB, s->splitwx_enabled, max_threads); --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351950; cv=none; d=zohomail.com; s=zohoarc; b=JCOGgrQgJ+5s0+k7T4jYUtVaJaGaVx6QSja67RYFiymvA6w7prAYkcsx4H825XeVPBr8dAXhG231qYCMVsLrvmgbQ8rWksOcA4Tq9E3xhGJzKPAnG9RHDocGmRFlXhoUHo6x3c0xdHeVrsf1d9Y0Tp/UZ8sEg5b86CIjuS8g8Vk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351950; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mQbPDTOsf1VGzqz8fPGND6jRUNUvO1vNZUX54zef5RU=; b=ACl9/NZdpkn44B7pQg3WiBeH+QF5fcj/np8v5jV4ZkRm6sNBswLbQ4wFyDiNX0Bs8FST2cR0HaM99g9GNfkcQ86Hd/5SqqQqYWOy0u7EEgZnmG0VqWNqT8eZv7xxsHJjHunCwA64ylagqBdsrkdqw+nB/bMte1jPsiRcgVX43dw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351950872248.21746437043748; Tue, 22 Apr 2025 12:59:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JTH-0006xc-Hg; Tue, 22 Apr 2025 15:39:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSO-0004Kq-Hp for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:02 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSL-0007Na-9A for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:38:59 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-223fd89d036so69496175ad.1 for ; Tue, 22 Apr 2025 12:38:56 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350735; x=1745955535; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mQbPDTOsf1VGzqz8fPGND6jRUNUvO1vNZUX54zef5RU=; b=IoV8JGA0xFDvLDkIcvKcEBujqUkk3Pldn5lLpPcGeUwNyL44H9McsU6cVdnosz9W7o Sjsi3yCfQaKZXgnALslNVtbbWopyHPb/8Kv15zKfT0nuCucuE0OlQHmAI1aSpfGtUckN 6gqhg2WbkWutYHIJkXDy/8ZrzcksYDQAZBdoHRhTvikEr3M2R4xyK/EYJMyXf7YtVtwS T8LvXdv1OKUB8YV8kiPMAn8ZGXaKAZ5id4W2nj/Gz5/vSTfhgW/KzF6dg7htDZ0JuiEY pouV+68Ou/zJiciqkjeS3IEimdWwtZ4yPwbmEqH3RXFoY4CUkSkZYpif1Lm+nAeJe2rw OUQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350735; x=1745955535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mQbPDTOsf1VGzqz8fPGND6jRUNUvO1vNZUX54zef5RU=; b=QqUGEovveGvQzIGiqGA1DZTXUlxcMvmrcy03cfpsu8XjkzI9bAUgpQxc9OWMLkxy4V K18kVhxb6ewAdEbcKjdwVl7yJ804YtxLMOTQ+HjV27IaJ2TNRDZQ6+9T1x6ShIvbYoan Zg3u+4BkgyjjFmkcMHeYE3leR51R59SQs5u+iGnx3RPlbpobSAxA1hSfCaEkZWUUpNHD cXRk/dWXhLwl76CnDkqkCwZSvZDI9XEqE/N0YrkxtfJdZ9ifOHhDa10ih/4R4Z2iiepd VXra7qa8xEVk7BkkHjmV/OhvL2jKCBEiDBCc2Y9XbNnzzRJ/mt9WR5wWyVgWNlJYSTJ3 fL1w== X-Gm-Message-State: AOJu0YwoxZjdWWfpLoTeFCqJyhDYmzeiF/1JBv224Yj3Mv8FuTA5HI5v ZtTs1eTcBbAzkQdjO/ErS9uGr4jPuXK7WLSAbAuD0knqK8Gg3CliGTtcxy4aljPzg+8gVwuOypQ 1 X-Gm-Gg: ASbGnctfmPt8nN59RWJHGX494n+wu7ZzW2rbfiDt2A3D0aZPSh/IrwDFj/WMR0jNWm2 EnULWKq5vVP6bGL4E+z/ZndGIgbHWM2FLYJOrU9LFjPeXMFA8ODYRzm43lN+C74rW952nJ9vXzS QSXmMcdJgUMgpVBuHYbIGRQEU5e+7Ute3pRWI09Hwcl1Dyn1ikYnS1VXUkPVDMzToUHi6DzUS6i y8Dsvcj5ovEM1ShCG62YyU6H/dAg0tkxms62iey6sUfCHCQdC/zNOrytMO1Oosx+Xa7TP5OW940 mExAOEMKA98ULXTAAVTx+2oPO8ZbAhPrW/rvhfgt4dIYOYZRGIHM1hRQSiMFP6b+wV2HvNFbRRs AMrgGbc4NYw== X-Google-Smtp-Source: AGHT+IFf2Y7o6LVSkeTFe4oZhXkRnK+BtKsY6d5x9iVjhxXhHJxFK9LrFKX9ox8ulCNPY1joYt7bPw== X-Received: by 2002:a17:903:19ed:b0:224:1c95:451e with SMTP id d9443c01a7336-22c53607dffmr241060035ad.33.1745350735396; Tue, 22 Apr 2025 12:38:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 143/147] tcg: Convert TCGState::mttcg_enabled to TriState Date: Tue, 22 Apr 2025 12:28:12 -0700 Message-ID: <20250422192819.302784-144-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351952714019000 From: Philippe Mathieu-Daud=C3=A9 Use the OnOffAuto type as 3-state. Since the TCGState instance is zero-initialized, the mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO). In tcg_init_machine(), if mttcg_enabled is still AUTO, set a default value (effectively inlining the default_mttcg_enabled() method content). In the tcg_get_thread() getter, consider AUTO / OFF states as "single", otherwise ON is "multi". Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/tcg-all.c | 74 ++++++++++++++++++++++----------------------- 1 file changed, 36 insertions(+), 38 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index b754f92905..fa77a4c5a2 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -32,6 +32,7 @@ #include "qemu/error-report.h" #include "qemu/accel.h" #include "qemu/atomic.h" +#include "qapi/qapi-types-common.h" #include "qapi/qapi-builtin-visit.h" #include "qemu/units.h" #if defined(CONFIG_USER_ONLY) @@ -47,7 +48,7 @@ struct TCGState { AccelState parent_obj; =20 - bool mttcg_enabled; + OnOffAuto mttcg_enabled; bool one_insn_per_tb; int splitwx_enabled; unsigned long tb_size; @@ -63,41 +64,14 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, bool qemu_tcg_mttcg_enabled(void) { TCGState *s =3D TCG_STATE(current_accel()); - return s->mttcg_enabled; + return s->mttcg_enabled =3D=3D ON_OFF_AUTO_ON; } #endif /* !CONFIG_USER_ONLY */ =20 -/* - * We default to false if we know other options have been enabled - * which are currently incompatible with MTTCG. Otherwise when each - * guest (target) has been updated to support: - * - atomic instructions - * - memory ordering primitives (barriers) - * they can set the appropriate CONFIG flags in ${target}-softmmu.mak - * - * Once a guest architecture has been converted to the new primitives - * there is one remaining limitation to check: - * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) - */ - -static bool default_mttcg_enabled(void) -{ - if (icount_enabled()) { - return false; - } -#ifdef TARGET_SUPPORTS_MTTCG - return true; -#else - return false; -#endif -} - static void tcg_accel_instance_init(Object *obj) { TCGState *s =3D TCG_STATE(obj); =20 - s->mttcg_enabled =3D default_mttcg_enabled(); - /* If debugging enabled, default "auto on", otherwise off. */ #if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) s->splitwx_enabled =3D -1; @@ -113,16 +87,40 @@ static int tcg_init_machine(MachineState *ms) TCGState *s =3D TCG_STATE(current_accel()); unsigned max_threads =3D 1; =20 +#ifndef CONFIG_USER_ONLY +# ifdef TARGET_SUPPORTS_MTTCG + bool mttcg_supported =3D true; +# else + bool mttcg_supported =3D false; +# endif + if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_AUTO) { + /* + * We default to false if we know other options have been enabled + * which are currently incompatible with MTTCG. Otherwise when each + * guest (target) has been updated to support: + * - atomic instructions + * - memory ordering primitives (barriers) + * they can set the appropriate CONFIG flags in ${target}-softmmu.= mak + * + * Once a guest architecture has been converted to the new primiti= ves + * there is one remaining limitation to check: + * - The guest can't be oversized (e.g. 64 bit guest on 32 bit h= ost) + */ + if (mttcg_supported && !icount_enabled()) { + s->mttcg_enabled =3D ON_OFF_AUTO_ON; + } else { + s->mttcg_enabled =3D ON_OFF_AUTO_OFF; + } + } + if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_ON) { + max_threads =3D ms->smp.max_cpus; + } +#endif + tcg_allowed =3D true; =20 page_init(); tb_htable_init(); - -#ifndef CONFIG_USER_ONLY - if (s->mttcg_enabled) { - max_threads =3D ms->smp.max_cpus; - } -#endif tcg_init(s->tb_size * MiB, s->splitwx_enabled, max_threads); =20 #if defined(CONFIG_SOFTMMU) @@ -144,7 +142,7 @@ static char *tcg_get_thread(Object *obj, Error **errp) { TCGState *s =3D TCG_STATE(obj); =20 - return g_strdup(s->mttcg_enabled ? "multi" : "single"); + return g_strdup(s->mttcg_enabled =3D=3D ON_OFF_AUTO_ON ? "multi" : "si= ngle"); } =20 static void tcg_set_thread(Object *obj, const char *value, Error **errp) @@ -159,10 +157,10 @@ static void tcg_set_thread(Object *obj, const char *v= alue, Error **errp) warn_report("Guest not yet converted to MTTCG - " "you may get unexpected results"); #endif - s->mttcg_enabled =3D true; + s->mttcg_enabled =3D ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") =3D=3D 0) { - s->mttcg_enabled =3D false; + s->mttcg_enabled =3D ON_OFF_AUTO_OFF; } else { error_setg(errp, "Invalid 'thread' setting %s", value); } --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745352037; cv=none; d=zohomail.com; s=zohoarc; b=LJ7myg/Brrpzcf98yG9bGNmYCvLZPurlsTd/tPjDPcctow9SLchjrLPXblEhNItkB9hTV3kVRB2KWpDLeKxPWOVLfIlrejTJKTuof5eAnfBlyD33bt6oAUK8i5WIdxJdU+f2X3N8gjERaT5D26WwvcYj/1kzfz6RK90KHq82maw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745352037; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=TEwojCbipjqc0WV/gEzN3cyq9jAbkGKw7ev6nih1Z3Y=; b=PYR9JBYy/cnuvSVMP1s6Nm0NQ7wm8XEfrrW8AntOJnCjsySBC5ua46YSBDaPNUTgHVNYmKdkmc0hrjhLuRUpLocVVOdnnEyiEHQt994a7gK4U3nY4kJfqEcUrp03qh6iHMxZRDnX6uKFQBuUBrYmXA5Avo+FJd1GwM1ZFs8Im30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174535203780111.631569195735437; Tue, 22 Apr 2025 13:00:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JTI-000735-8E; Tue, 22 Apr 2025 15:39:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSO-0004Kp-Hh for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:02 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSM-0007Nm-3b for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:00 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-227a8cdd241so63321705ad.3 for ; Tue, 22 Apr 2025 12:38:57 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- accel/tcg/tcg-all.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index fa77a4c5a2..ecdd48847c 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -93,7 +93,8 @@ static int tcg_init_machine(MachineState *ms) # else bool mttcg_supported =3D false; # endif - if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_AUTO) { + switch (s->mttcg_enabled) { + case ON_OFF_AUTO_AUTO: /* * We default to false if we know other options have been enabled * which are currently incompatible with MTTCG. Otherwise when each @@ -108,12 +109,22 @@ static int tcg_init_machine(MachineState *ms) */ if (mttcg_supported && !icount_enabled()) { s->mttcg_enabled =3D ON_OFF_AUTO_ON; + max_threads =3D ms->smp.max_cpus; } else { s->mttcg_enabled =3D ON_OFF_AUTO_OFF; } - } - if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_ON) { + break; + case ON_OFF_AUTO_ON: + if (!mttcg_supported) { + warn_report("Guest not yet converted to MTTCG - " + "you may get unexpected results"); + } max_threads =3D ms->smp.max_cpus; + break; + case ON_OFF_AUTO_OFF: + break; + default: + g_assert_not_reached(); } #endif =20 @@ -153,10 +164,6 @@ static void tcg_set_thread(Object *obj, const char *va= lue, Error **errp) if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { -#ifndef TARGET_SUPPORTS_MTTCG - warn_report("Guest not yet converted to MTTCG - " - "you may get unexpected results"); -#endif s->mttcg_enabled =3D ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") =3D=3D 0) { --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351452; cv=none; d=zohomail.com; s=zohoarc; b=UmbX/h4ykd5LNU2loauQ/oah4+MBsTEYlfRTChebbocg3m1H9hHC2p3Q5y1+vVFv77AkGzlNtu3VXs8bCanaOKvUEVUgW2bHWeU1/NCoRKQYuTnChtXeCKweutLk8SEqeuQFxQHN9Pt6PYVrxUe0INb2m7cn8+dHTI7nvFoeO4s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351452; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kCb0nI+2CCy6xbgQ0QUcGLa1ZUmAGxVEjmnQDdUz4pI=; b=hm7Z11YLFTUR68QuEUmd4CkOsECwDAsInc/CKSnNkvDQfHjOUW2j4W7J8InN41WwBZz79xZxziPcIXilvjqrSHfyTgx+qnIIxs552dudPD+DZDxLxplZjp/pgmTKBcr/binN05oYwCx7fJcWT3WTti9Kt3BmR4d+LN7w5yiwk94= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351452428284.3272423487605; Tue, 22 Apr 2025 12:50:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JT1-00061p-Vr; Tue, 22 Apr 2025 15:39:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSP-0004Ks-31 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:02 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSM-0007Np-Mc for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:00 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-22d95f0dda4so23725265ad.2 for ; Tue, 22 Apr 2025 12:38:57 -0700 (PDT) Received: from stoup.. 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No need for the AccelCPUClass::cpu_class_init() handler anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20250405161320.76854-2-philmd@linaro.org> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/riscv/tcg/tcg-cpu.h | 2 ++ target/riscv/cpu.c | 3 +++ target/riscv/tcg/tcg-cpu.c | 16 +--------------- 3 files changed, 6 insertions(+), 15 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h index ce94253fe4..a23716a5ac 100644 --- a/target/riscv/tcg/tcg-cpu.h +++ b/target/riscv/tcg/tcg-cpu.h @@ -26,6 +26,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Err= or **errp); void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp); bool riscv_cpu_tcg_compatible(RISCVCPU *cpu); =20 +extern const TCGCPUOps riscv_tcg_ops; + struct DisasContext; struct RISCVCPUConfig; typedef struct RISCVDecoder { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ad534cee51..2b830b3317 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3054,6 +3054,9 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, void *data) cc->get_arch_id =3D riscv_get_arch_id; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; +#ifdef CONFIG_TCG + cc->tcg_ops =3D &riscv_tcg_ops; +#endif /* CONFIG_TCG */ =20 device_class_set_props(dc, riscv_cpu_properties); } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 88f7cdb887..44fdf6c4cf 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,7 +140,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->excp_uw2 =3D data[2]; } =20 -static const TCGCPUOps riscv_tcg_ops =3D { +const TCGCPUOps riscv_tcg_ops =3D { .guest_default_memory_order =3D 0, =20 .initialize =3D riscv_translate_init, @@ -1527,24 +1527,10 @@ static void riscv_tcg_cpu_instance_init(CPUState *c= s) } } =20 -static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) -{ - /* - * All cpus use the same set of operations. - */ - cc->tcg_ops =3D &riscv_tcg_ops; -} - -static void riscv_tcg_cpu_class_init(CPUClass *cc) -{ - cc->init_accel_cpu =3D riscv_tcg_cpu_init_ops; -} - static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 - acc->cpu_class_init =3D riscv_tcg_cpu_class_init; acc->cpu_instance_init =3D riscv_tcg_cpu_instance_init; acc->cpu_target_realize =3D riscv_tcg_cpu_realize; } --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1745351277; cv=none; d=zohomail.com; s=zohoarc; b=jEoDT6s4NFrOTHbIvS5AFzLxBVWTQEMSbWiLoxDBkJ8w6WaqST5tixfmxsB3WnUW/rCCb4qPCwjX496rF0ID9zJgvuKGGTpddKN14iAUNyCJ31956ECGNalB/PJOaSitFRgZupUUeucnK/drUZQ+vW0Z/DGSBG3Hlq4CgaonOqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745351277; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TW4N3ReYmKveN3DtkTRFhUmPoxz9JDSNytNFvFcor3s=; b=Vdl0KYXfA2X6zpIsGfMjXxS5uC0rYWlnedUA4qcpE7ukLRQgcCwEPVEHxlkF1RBsyR40Y8xJjcF9822Qcgi3yF0rRnj1NUVvanHRbpLWOQWaYB5gkSYO0vKG0CTZ3lUmdNoVBjW7tq9NYsNrxNNiC3GvoXlrthFg1pHVhMOlJyM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745351277215819.240945287603; Tue, 22 Apr 2025 12:47:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7JT7-0006N7-LB; Tue, 22 Apr 2025 15:39:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7JSQ-0004MB-1n for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:02 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7JSN-0007Nw-73 for qemu-devel@nongnu.org; Tue, 22 Apr 2025 15:39:01 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-22c33677183so65874685ad.2 for ; Tue, 22 Apr 2025 12:38:58 -0700 (PDT) Received: from stoup.. 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350737; x=1745955537; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TW4N3ReYmKveN3DtkTRFhUmPoxz9JDSNytNFvFcor3s=; b=ltj6Rp4PuGgS1vYQe7Q1ica0xDvbxsNvFGUjeYwi59ukvKceSaNefi59UHP9agYH/V /qdy4jsHi+hdaXyVDIEweBsGbMuOmdxoqe7yXHlJWPc7912360tV8Q2lD3L/eo3wOUIC XI2wQp+XIHoUx63FdLdBbPH85q0MoFRkuqB+IeeZj9TUTTIJXDIo+Shu5tGvz8sZYAzS MlnDEYaQJWTI7fKfJltXZuvwwaEPZ3RtC6Yw13y6tSHktUdx+Zz0C4VbcKngcwuoh3uh 6mC1sj6WO/S9qlY9zt/QfoFkxp4Rk8Za5yzjfyc/KRTwkmqIus3vG0rhWSZQGdOFeEIz TRoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350737; x=1745955537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TW4N3ReYmKveN3DtkTRFhUmPoxz9JDSNytNFvFcor3s=; b=FrsZprrkcfdMjF+WajURaKV4EWEYg6qrBv9JWubq0tTQOyXLiLQzRfFUwLEH2UEsDJ 41Pw7+R6wb4KEHKksdSKzUA8pV8o+2LdDgr6Oi64BKDInYfI0kYhfrRZuSQAHS9UdC4E DVvpUsYwbiIJqRuVSJRuwcPW7QMHq9sqppWPILAiQUlGdZ6rr0q4MrqCRCwCIxm+kCK9 A15k1VzKJYDIub1C7sACy5UIgnvSJnpLmK6pIU5acNo3Gkkf6i2Feu2NaYUZNC3eISqj TzjASLIve2q6exxbjYZyk8Y/185KV88rcYGWSyGVLyKP/tMODULGBltfdyah3hcB+rTo Dsjw== X-Gm-Message-State: AOJu0YyvSpZ93aev7F7oTWnWepNVMHBLH4Q90bKDynbWxN0bEdIaGytY RhrFSHpV6NjSACtTyrMF1iROGRDLVpf4fIuTKWdM3MBgf7hQ/EdX+IUQsh9r8mtnrP8IEhwjev6 X X-Gm-Gg: ASbGncuhSS3Elk4nwExYYOkqzgV2Qpila3acvB/61+BEOCvYCSKabNXrMBJXCIYbycI RAGx088/vCfagEk7nLSdwl8pbGSya04uWK8GpLxxu6RZa06tK+XFks7+YluQeii193W/LKJ0Ifv Nj4e1Cr+WyXiKcEVC2wrUWy5GlC89z100LgWr/iY66GBV7vB+JiMmFSm3ssTBxWRp6C/5NSYCoA +nSsZ5btVmhBkdfxFYjdCcir9ZoxPQUkOr86BGQyM31VueXaI9gF0DtoSt7YqCkk0pOhRh9rFjm i0mbVinVvXoxZloA0e0nzZyqQLITH1wlSM9Dqtf2VMR13D1WDDt6eAsVHfI14LoEgUhIYBGnbXb 1kwOC51xgTw== X-Google-Smtp-Source: AGHT+IFBP8BXSno0ocNf5zHGzoEvSQ8K01g8QYaLPu6p5KMfevvtuWHn+qmG3jzCGBcThPldjCz1jg== X-Received: by 2002:a17:903:11c5:b0:221:85:f384 with SMTP id d9443c01a7336-22c5359c36cmr229258785ad.16.1745350737383; Tue, 22 Apr 2025 12:38:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 146/147] target/i386: Remove AccelCPUClass::cpu_class_init need Date: Tue, 22 Apr 2025 12:28:15 -0700 Message-ID: <20250422192819.302784-147-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745351278265019000 From: Philippe Mathieu-Daud=C3=A9 Expose x86_tcg_ops symbol, then directly set it as CPUClass::tcg_ops in TYPE_X86_CPU's class_init(), using CONFIG_TCG #ifdef'ry. No need for the AccelCPUClass::cpu_class_init() handler anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20250405161320.76854-3-philmd@linaro.org> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/i386/tcg/tcg-cpu.h | 4 ++++ target/i386/cpu.c | 4 ++++ target/i386/tcg/tcg-cpu.c | 14 +------------- 3 files changed, 9 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h index 7580f8afb4..85bcd61678 100644 --- a/target/i386/tcg/tcg-cpu.h +++ b/target/i386/tcg/tcg-cpu.h @@ -19,6 +19,8 @@ #ifndef TCG_CPU_H #define TCG_CPU_H =20 +#include "cpu.h" + #define XSAVE_FCW_FSW_OFFSET 0x000 #define XSAVE_FTW_FOP_OFFSET 0x004 #define XSAVE_CWD_RIP_OFFSET 0x008 @@ -76,6 +78,8 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state)= !=3D XSAVE_ZMM_HI256_OFF QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) !=3D XSAVE_HI16_Z= MM_OFFSET); QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=3D XSAVE_PKRU_OFFSE= T); =20 +extern const TCGCPUOps x86_tcg_ops; + bool tcg_cpu_realizefn(CPUState *cs, Error **errp); =20 int x86_mmu_index_pl(CPUX86State *env, unsigned pl); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d930ebd262..31487f4b28 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -43,6 +43,7 @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "tcg/tcg-cpu.h" =20 #include "disas/capstone.h" #include "cpu-internal.h" @@ -8903,6 +8904,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ +#ifdef CONFIG_TCG + cc->tcg_ops =3D &x86_tcg_ops; +#endif /* CONFIG_TCG */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; #ifdef TARGET_X86_64 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d941df0956..e13d0f6f86 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -124,7 +124,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) =20 #include "accel/tcg/cpu-ops.h" =20 -static const TCGCPUOps x86_tcg_ops =3D { +const TCGCPUOps x86_tcg_ops =3D { /* * The x86 has a strong memory model with some store-after-load re-ord= ering */ @@ -152,17 +152,6 @@ static const TCGCPUOps x86_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 -static void x86_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) -{ - /* for x86, all cpus use the same set of operations */ - cc->tcg_ops =3D &x86_tcg_ops; -} - -static void x86_tcg_cpu_class_init(CPUClass *cc) -{ - cc->init_accel_cpu =3D x86_tcg_cpu_init_ops; -} - static void x86_tcg_cpu_xsave_init(void) { #define XO(bit, field) \ @@ -211,7 +200,6 @@ static void x86_tcg_cpu_accel_class_init(ObjectClass *o= c, void *data) acc->cpu_target_realize =3D tcg_cpu_realizefn; #endif /* CONFIG_USER_ONLY */ =20 - acc->cpu_class_init =3D x86_tcg_cpu_class_init; acc->cpu_instance_init =3D x86_tcg_cpu_instance_init; } static const TypeInfo x86_tcg_cpu_accel_type_info =3D { --=20 2.43.0 From nobody Thu Oct 16 02:04:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22c50eb484dsm88951765ad.148.2025.04.22.12.38.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 12:38:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745350738; x=1745955538; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C0qngBJCPNXNfsiuFxmeWRFoswe6YlL4dUU/ayinRo4=; b=vpXvgSy1X8vtZuYHSX1bRfSXnrb8Se4cxnsFCO9NlyE4IsMS7QRHMiadqaojydnlDJ UqWI10PEQSRBPc19pASwIwsXAo66EVfnJA+hw4yN9+lgr4cq46nCBEVZPDDL/F3RrtGQ 65LxHSjuS9ROFBr1zxVLWLa98sIPmsmp2Yo74OubCPRIYMgaJWl1VFYPhv5PuqLEOQaE MVKMJiC3cfo3Aj0ACTXNVAwWd8alyeBOdMib3tRFCPgTxtRc+IV9lJRI7lGeHGIc4C4V RSuTXacNmW88Gv8fpf0neEgvYnvPvc9oBBVDTJAqIyo5iZ7YwFk09mWv51E6dQvZH7wX 6gQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745350738; x=1745955538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C0qngBJCPNXNfsiuFxmeWRFoswe6YlL4dUU/ayinRo4=; b=CnSlJx70wwNk62yH8YqBzZn2CIuDtX/WxZaPYeDzt8YF49Pn4uI3HQPukUinmZtZS2 LVhDLwSbxa2RFly/ajUc4RZWWVXRQilKWkUgWooZILn0ewEMdcH0IckvZsoFMzLCP/WF AGCkJliWH8hGuRiynA35SkFPvuTzibWCqKNXnMfKChojdhlL4RJO3z7DPO2Bbpqsz1vv 8AZtA4u8q8wEyxOR6gyQ5f4b23BSu52I6d58XWuEZKtHy6i9Vd4oWVvCzDJfXe+U/XSz xNXewcWY5A27UheI8yuVuAdsLLKp8ozH9LgGlj6Kd90gsrVO2ePrdN2Lp1Hisow7kUj/ CCdg== X-Gm-Message-State: AOJu0YxsYPvo4BWsibo3aT9oj0zIZjCPuNQb+YYurqziVUolfaCAh21S GtwcF4jkwXbto1n0np2QXk7ocXem9tUtUjzyBd1gmzKnsMpKy3xrytGZwkwbyMnFgCIJ/nerIjt 4 X-Gm-Gg: ASbGncsO5rkR5RJu/4G6mLjn3Qcwl6Bctsfg//sUOoTWqAUS6t6ET4b2D5cp2Owp9m4 4IwxHkrkEGgjCfr8hTp6jUtATA6E+e6PGV8Q9UWWMCKzuDruqYaeVHTL0Y/6/XDNrPEKfBUJvYv mzPebHQwX0GqcwCgDJ1A1t+zII6phGMI4la/5Drrpz1mSO487iId7yQFPiUfdYZmfuU43sP0dZO isBDT3SUsoM6g6cvZDGkx3FDD5TU2RaetkJffoBQHMpHGH6CYlEbIfcqj5fA+qNH/mRlTk1hqyo Bo8gBQPdh3Hu7tlc1KEDUeNK5bQbfoU79VcSk5iw7BWHUTAJ6AwUwisBLkyB/ZPcTZ8SaGKCxpY = X-Google-Smtp-Source: AGHT+IGpKojlTq2pRjT/xLFHmJyxUJaIpxysR7g8bz30JFVab0E8XwoUUs7/Zr9LsXW/dQWWRlNHZg== X-Received: by 2002:a17:902:d502:b0:224:a74:28d2 with SMTP id d9443c01a7336-22c535bfcffmr217189975ad.26.1745350738066; Tue, 22 Apr 2025 12:38:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH 147/147] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Date: Tue, 22 Apr 2025 12:28:16 -0700 Message-ID: <20250422192819.302784-148-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250422192819.302784-1-richard.henderson@linaro.org> References: <20250422192819.302784-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1745350817534019000 From: Philippe Mathieu-Daud=C3=A9 Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition, have each target set the 'mttcg_supported' field in the TCGCPUOps structure. Since so far we only emulate one target architecture at a time, tcg_init_machine() gets whether MTTCG is supported via the current CPU class (CPU_RESOLVING_TYPE). Since TARGET_SUPPORTS_MTTCG isn't available anymore, instead of emiting a warning when the 'thread' property is set in tcg_set_thread(), emit it in tcg_init_machine() where it is consumed. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-ID: <20250405161320.76854-17-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/accel/tcg/cpu-ops.h | 8 ++++++++ include/exec/poison.h | 1 - accel/tcg/tcg-all.c | 11 +++++------ target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + configs/targets/aarch64-softmmu.mak | 1 - configs/targets/alpha-softmmu.mak | 1 - configs/targets/arm-softmmu.mak | 1 - configs/targets/hppa-softmmu.mak | 1 - configs/targets/i386-softmmu.mak | 1 - configs/targets/loongarch64-softmmu.mak | 1 - configs/targets/microblaze-softmmu.mak | 1 - configs/targets/microblazeel-softmmu.mak | 1 - configs/targets/mips-softmmu.mak | 1 - configs/targets/mipsel-softmmu.mak | 1 - configs/targets/or1k-softmmu.mak | 1 - configs/targets/ppc64-softmmu.mak | 1 - configs/targets/riscv32-softmmu.mak | 1 - configs/targets/riscv64-softmmu.mak | 1 - configs/targets/s390x-softmmu.mak | 1 - configs/targets/sparc-softmmu.mak | 1 - configs/targets/sparc64-softmmu.mak | 1 - configs/targets/x86_64-softmmu.mak | 1 - configs/targets/xtensa-softmmu.mak | 1 - configs/targets/xtensaeb-softmmu.mak | 1 - docs/devel/multi-thread-tcg.rst | 2 +- 44 files changed, 34 insertions(+), 28 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index a4932fc5d7..0e4352513d 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,6 +19,14 @@ #include "tcg/tcg-mo.h" =20 struct TCGCPUOps { + /** + * mttcg_supported: multi-threaded TCG is supported + * + * Target (TCG frontend) supports: + * - atomic instructions + * - memory ordering primitives (barriers) + */ + bool mttcg_supported; =20 /** * @guest_default_memory_order: default barrier that is required diff --git a/include/exec/poison.h b/include/exec/poison.h index a09e0c1263..bc422719d8 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,7 +35,6 @@ =20 #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME -#pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN #pragma GCC poison TCG_GUEST_DEFAULT_MO #pragma GCC poison TARGET_HAS_PRECISE_SMC diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index ecdd48847c..b0d4e3e136 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -41,8 +41,9 @@ #include "hw/boards.h" #include "system/tcg.h" #endif +#include "accel/tcg/cpu-ops.h" #include "internal-common.h" -#include "cpu-param.h" +#include "cpu.h" =20 =20 struct TCGState { @@ -88,11 +89,9 @@ static int tcg_init_machine(MachineState *ms) unsigned max_threads =3D 1; =20 #ifndef CONFIG_USER_ONLY -# ifdef TARGET_SUPPORTS_MTTCG - bool mttcg_supported =3D true; -# else - bool mttcg_supported =3D false; -# endif + CPUClass *cc =3D CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE)); + bool mttcg_supported =3D cc->tcg_ops->mttcg_supported; + switch (s->mttcg_enabled) { case ON_OFF_AUTO_AUTO: /* diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index eeaf3a81c1..35fb145d27 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -237,6 +237,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { static const TCGCPUOps alpha_tcg_ops =3D { /* Alpha processors have a weak memory model */ .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3e9760b551..377791c84d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,7 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { =20 #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops =3D { + .mttcg_supported =3D true, /* ARM processors have a weak memory model */ .guest_default_memory_order =3D 0, =20 diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 89d4e4b4a2..f71560aa43 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -234,6 +234,7 @@ static void cortex_m55_initfn(Object *obj) static const TCGCPUOps arm_v7m_tcg_ops =3D { /* ARM processors have a weak memory model */ .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8f79cf4c08..84f3b839c9 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -225,6 +225,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { =20 static const TCGCPUOps avr_tcg_ops =3D { .guest_default_memory_order =3D 0, + .mttcg_supported =3D false, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3d14e5cc6a..3c5191282e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -327,6 +327,7 @@ static void hexagon_cpu_init(Object *obj) static const TCGCPUOps hexagon_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index dfbd933056..10e18c945e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -260,6 +260,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { * basis. It's probably easier to fall back to a strong memory model. */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D true, =20 .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e13d0f6f86..621502c984 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 const TCGCPUOps x86_tcg_ops =3D { + .mttcg_supported =3D true, /* * The x86 has a strong memory model with some store-after-load re-ord= ering */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index f5b8ef29ab..fe9462b3b7 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -865,6 +865,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) =20 static const TCGCPUOps loongarch_tcg_ops =3D { .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b2d8c8f1de..99adc5eb91 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -591,6 +591,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { static const TCGCPUOps m68k_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, =20 .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4efba0dddb..edfb05758b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -429,6 +429,7 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { static const TCGCPUOps mb_tcg_ops =3D { /* MicroBlaze is always in-order. */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D true, =20 .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 2ae7ba4407..473cecdebc 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -551,6 +551,7 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) } =20 static const TCGCPUOps mips_tcg_ops =3D { + .mttcg_supported =3D TARGET_LONG_BITS =3D=3D 32, .guest_default_memory_order =3D 0, =20 .initialize =3D mips_tcg_init, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 87fe779042..6601e0c066 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -244,6 +244,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { =20 static const TCGCPUOps openrisc_tcg_ops =3D { .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 9ba775971a..fde7d71fc6 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7479,6 +7479,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps ppc_tcg_ops =3D { + .mttcg_supported =3D TARGET_LONG_BITS =3D=3D 64, .guest_default_memory_order =3D 0, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 44fdf6c4cf..426145c3b9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -141,6 +141,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } =20 const TCGCPUOps riscv_tcg_ops =3D { + .mttcg_supported =3D true, .guest_default_memory_order =3D 0, =20 .initialize =3D riscv_translate_init, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index f073fe8fc9..0a7a2b55b5 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -206,6 +206,7 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { static const TCGCPUOps rx_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, =20 .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 1e101b5afe..41cccc1e69 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } =20 static const TCGCPUOps s390_tcg_ops =3D { + .mttcg_supported =3D true, /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 7a05301c6f..861fdd47f7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -264,6 +264,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { static const TCGCPUOps superh_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, =20 .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 56d9417ae3..f7d231c6f8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1023,6 +1023,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { * by an implied MEMBAR #StoreStore. */ .guest_default_memory_order =3D TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_S= T_ST, + .mttcg_supported =3D true, =20 .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index c68954b409..a4f93e7d91 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -174,6 +174,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { static const TCGCPUOps tricore_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 2cbf4e3010..971e67ad97 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -234,6 +234,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { static const TCGCPUOps xtensa_tcg_ops =3D { /* Xtensa processors have a weak memory model */ .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-= softmmu.mak index 82cb72cb83..5dfeb35af9 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sy= sregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-prof= ile-mve.xml gdb-xml/aarch64-pauth.xml # needed by boot.c diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-soft= mmu.mak index 89f3517aca..5275076e50 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dalpha -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.= mak index afc64f5927..6a5a8eda94 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Darm -TARGET_SUPPORTS_MTTCG=3Dy TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml gdb-xml/arm-m-profile-mve.xml # needed by boot.c TARGET_NEED_FDT=3Dy diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmm= u.mak index 63ca74ed5e..ea331107a0 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dhppa TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmm= u.mak index 5dd8921756..e9d89e8ab4 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Di386 -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy TARGET_XML_FILES=3D gdb-xml/i386-32bit.xml diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loon= garch64-softmmu.mak index 351341132f..fc44c54233 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=3Dloongarch64 TARGET_BASE_ARCH=3Dloongarch TARGET_KVM_HAVE_GUEST_DEBUG=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_XML_FILES=3D gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.= xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-l= asx.xml # all boards require libfdt TARGET_NEED_FDT=3Dy diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/micro= blaze-softmmu.mak index 99a33ed44a..23457d0ae6 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Dmicroblaze TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3Dgdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-pr= otect.xml diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/mic= roblazeel-softmmu.mak index 52cdeae1a2..c82c509623 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dmicroblaze -TARGET_SUPPORTS_MTTCG=3Dy # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3Dgdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-pr= otect.xml diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmm= u.mak index b62a088249..c9588066b8 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dmips TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-so= ftmmu.mak index 620ec68178..90e09bdc3e 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dmips -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmm= u.mak index adfddb1a8a..0e47d9878b 100644 --- a/configs/targets/or1k-softmmu.mak +++ b/configs/targets/or1k-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dopenrisc -TARGET_SUPPORTS_MTTCG=3Dy TARGET_BIG_ENDIAN=3Dy # needed by boot.c and all boards TARGET_NEED_FDT=3Dy diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-soft= mmu.mak index 7cee0e97f4..74572864b3 100644 --- a/configs/targets/ppc64-softmmu.mak +++ b/configs/targets/ppc64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=3Dppc64 TARGET_BASE_ARCH=3Dppc TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml= /power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml # all boards require libfdt diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-= softmmu.mak index c828066ce6..db55275b86 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Driscv32 TARGET_BASE_ARCH=3Driscv -TARGET_SUPPORTS_MTTCG=3Dy TARGET_XML_FILES=3D gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=3Dy diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-= softmmu.mak index 09f613d24a..2bdd4a62cd 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv= -32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-soft= mmu.mak index 5242ebe7c2..76dd5de658 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Ds390x TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/= s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml = gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=3D64 diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-soft= mmu.mak index 78c2e25bd1..57801faf1f 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-= softmmu.mak index f7bab97a00..2504e31ae3 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dsparc64 TARGET_BASE_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index 1ceefde131..5619b2bc68 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy TARGET_XML_FILES=3D gdb-xml/i386-64bit.xml diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-so= ftmmu.mak index 65845df4ff..2a9797338a 100644 --- a/configs/targets/xtensa-softmmu.mak +++ b/configs/targets/xtensa-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dxtensa -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/xtensaeb-softmmu.mak b/configs/targets/xtensae= b-softmmu.mak index f1f789d697..5204729af8 100644 --- a/configs/targets/xtensaeb-softmmu.mak +++ b/configs/targets/xtensaeb-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dxtensa TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.= rst index 14a2a9dc7b..da9a1530c9 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -30,7 +30,7 @@ user-space thread. This is enabled by default for all FE/= BE combinations where the host memory model is able to accommodate the guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is z= ero) and the guest has had the required work done to support this safely -(TARGET_SUPPORTS_MTTCG). +(TCGCPUOps::mttcg_supported). =20 System emulation will fall back to the original round robin approach if: --=20 2.43.0