From nobody Sat Nov 15 23:39:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1745228881; cv=none; d=zohomail.com; s=zohoarc; b=h+dLDZV4ciVGoSmxBJ8W0qTtYmPf4Qs1/zuSZHDTvWxGkEuk+mM7P+sc+enXEvcgi0UCDvoV0qNHQy+llKW2q984YqhOp+7p9rsr1xJK3bUQ6oP37pm92XiStIKx6zyJfvUT1aMtejm/Qocy359xtDpHqKnClK9tGVt4tp+yo8A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745228881; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6qApAmRS/EJm6ky3TEJfeDc9SHlRYeSh29BCQyDFBc4=; b=SqK1wc/2wFblOzpBMnJnTPeS6FpKoUh+wTfiigS/5FB3tR+PYKLJmEscKzeojHc5AwwiVqj/yFgjMfPVK7zj1Q/SScdpHy3o9fkcqQY2yGLd7ZhUCtrjbHGHL17tqnL6yNOd7BRkUVJlMNEasSUujejFfePlH5f8POw7zvlOtF8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745228881002419.4161785030054; Mon, 21 Apr 2025 02:48:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u6nkL-0005Wn-BD; Mon, 21 Apr 2025 05:47:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u6nkH-0005W8-Qu for qemu-devel@nongnu.org; Mon, 21 Apr 2025 05:47:21 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u6nkF-0000Dj-I6 for qemu-devel@nongnu.org; Mon, 21 Apr 2025 05:47:21 -0400 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-301918a4e1bso3315394a91.1 for ; Mon, 21 Apr 2025 02:47:18 -0700 (PDT) Received: from jchang-1875.internal.sifive.com ([147.161.192.170]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087dee330bsm6162137a91.3.2025.04.21.02.47.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 21 Apr 2025 02:47:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1745228837; x=1745833637; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6qApAmRS/EJm6ky3TEJfeDc9SHlRYeSh29BCQyDFBc4=; b=WxkZhfj9A+h49flTWo+OcWTaA9ieQ2iMCMq8ZBlbfrdixmwmRnzycS9eGkCceKLDyp Eavor7sa8b5w2zf6Eaeu+Gz/57hpZ3aw+ZK6JJW72eYdmC26w5/IHxaDcCG02Wo8fJyH dpAcqNyJmGPfMeASnJhYjxh9A+qAl7ZnpSDOGZnFAyXqjBAmw1tmx8W+thuYgYZwq+Mm uDXeT2ARCYl4ZcwGH94zt0Nmc8imG8UmS88ZT7erZL73/HQ98UXc4NVawPKvOFoaIpiy ds66zRoSD4GYnhEEzVYTLgen5StjOov/WW1XcrFc/vmmrp9/0Sa39QlKvJi2OG0SPW/m +qeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745228837; x=1745833637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6qApAmRS/EJm6ky3TEJfeDc9SHlRYeSh29BCQyDFBc4=; b=fCIomHScJlFSBzRNJWH1sIHxOoB5ZIL3FH2aqYjecluhYKylq7OClc1cH4JHEUqKBG U9dhCNOHXqK8Dvd+cdGTGRRi3P7MOZynXJL4BRXZg1XDpnS9/tR2Zv+zkGQ48YJCSS3K ZnWIkHX4L+bXWVCv5efn6EezcOHU5tMlTWXJ8GJZIXGT00mtG+veP6mpwpxzjiyQCfYn CYZHoy/2Ng7fE9IAH8+GdvrpfeBm/sfiU+D9Ob4HEbPgcd5iLQoBMtBECUPxzyJGT/Pz iJKuKbINzRAnX01T44x/Lt/AB3kt6s7+0PJ1EAdi9PdZfKPEYuMiDFhkOzeRWcHMZgtQ WhFw== X-Gm-Message-State: AOJu0Yx22wzEKBeRsPAVg8A3Jgt1gQnV+jE6q2ZcVUX1RUapgBZBRAZB 2Qp7e5glQXrsHvDJEnNJY3wnz/ZYGzIkK2B0FtnEK3BKmFSIntSQEpsmsk5ZF5G3/wQQU6A45y/ 27bB4bjVR8h7SoGM/UzQEk9n5wOUkiGk9HOXjZnLLvH8di66XmzMoORavK79KD4jv5xGt26T9k+ SeADqH2HQUhkHGSef/GtzUkGPXi/xdbYhwaSyO3CQcAw== X-Gm-Gg: ASbGncta+XBdsf3kCEXa8064pM7v6x3UaQlxIEx5e+kyFJ41WPaOGQC2V8ColQeTkah OS/5egc15MBl6yZuRppDCQQsWV0zfi+GliwNhzjPmFw9PsLM37jKZIoFX4uvs1pChiTjCf1MrQS vMU/MCocIBqwq3q82Ntrlo2OvmReiupxw+yDKY4uU4dOK+1v0dcNFswYTYcPMzpYEOIly71xgC5 Ux37GnDWfy6zy9gbAsD8Z3iy2galRYlsAbChHvnAlmGST7uUasyYmjnhM7/Nj0dxkmzBptSY9mM Df+paG7+31qPJGLqna4o76Odt2uv5AUgAuA3t17i9Rq/A5GyGjOIYo0ztA2DZN96EK1WXrApks1 x70KH X-Google-Smtp-Source: AGHT+IG+TtVdk0hqOBBnbrueti6rFORSlcR9NRwTss/Cm1nO8/rBloOrXmiXUnozbC8MpmmfoGzTlg== X-Received: by 2002:a17:90b:1f8c:b0:2ff:5ed8:83d0 with SMTP id 98e67ed59e1d1-3087bb631d7mr17943281a91.16.1745228837178; Mon, 21 Apr 2025 02:47:17 -0700 (PDT) From: Jay Chang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jay Chang , Frank Chang Subject: [PATCH 1/2] target/riscv: Extend PMP region up to 64 Date: Mon, 21 Apr 2025 17:46:55 +0800 Message-ID: <20250421094656.48997-2-jay.chang@sifive.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250421094656.48997-1-jay.chang@sifive.com> References: <20250421094656.48997-1-jay.chang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=jay.chang@sifive.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1745228883334019100 According to the RISC-V Privileged Specification (version >1.12), RV32 supports 16 CSRs (pmpcfg0=E2=80=93pmpcfg15) to configure 64 PMP regions (pmpaddr0=E2=80=93pmpaddr63). Reviewed-by: Frank Chang Signed-off-by: Jay Chang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_bits.h | 60 +++++++++++++++++++ target/riscv/csr.c | 124 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 182 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a30317c617..e6b3e28386 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -372,6 +372,18 @@ #define CSR_PMPCFG1 0x3a1 #define CSR_PMPCFG2 0x3a2 #define CSR_PMPCFG3 0x3a3 +#define CSR_PMPCFG4 0x3a4 +#define CSR_PMPCFG5 0x3a5 +#define CSR_PMPCFG6 0x3a6 +#define CSR_PMPCFG7 0x3a7 +#define CSR_PMPCFG8 0x3a8 +#define CSR_PMPCFG9 0x3a9 +#define CSR_PMPCFG10 0x3aa +#define CSR_PMPCFG11 0x3ab +#define CSR_PMPCFG12 0x3ac +#define CSR_PMPCFG13 0x3ad +#define CSR_PMPCFG14 0x3ae +#define CSR_PMPCFG15 0x3af #define CSR_PMPADDR0 0x3b0 #define CSR_PMPADDR1 0x3b1 #define CSR_PMPADDR2 0x3b2 @@ -388,6 +400,54 @@ #define CSR_PMPADDR13 0x3bd #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf +#define CSR_PMPADDR16 0x3c0 +#define CSR_PMPADDR17 0x3c1 +#define CSR_PMPADDR18 0x3c2 +#define CSR_PMPADDR19 0x3c3 +#define CSR_PMPADDR20 0x3c4 +#define CSR_PMPADDR21 0x3c5 +#define CSR_PMPADDR22 0x3c6 +#define CSR_PMPADDR23 0x3c7 +#define CSR_PMPADDR24 0x3c8 +#define CSR_PMPADDR25 0x3c9 +#define CSR_PMPADDR26 0x3ca +#define CSR_PMPADDR27 0x3cb +#define CSR_PMPADDR28 0x3cc +#define CSR_PMPADDR29 0x3cd +#define CSR_PMPADDR30 0x3ce +#define CSR_PMPADDR31 0x3cf +#define CSR_PMPADDR32 0x3d0 +#define CSR_PMPADDR33 0x3d1 +#define CSR_PMPADDR34 0x3d2 +#define CSR_PMPADDR35 0x3d3 +#define CSR_PMPADDR36 0x3d4 +#define CSR_PMPADDR37 0x3d5 +#define CSR_PMPADDR38 0x3d6 +#define CSR_PMPADDR39 0x3d7 +#define CSR_PMPADDR40 0x3d8 +#define CSR_PMPADDR41 0x3d9 +#define CSR_PMPADDR42 0x3da +#define CSR_PMPADDR43 0x3db +#define CSR_PMPADDR44 0x3dc +#define CSR_PMPADDR45 0x3dd +#define CSR_PMPADDR46 0x3de +#define CSR_PMPADDR47 0x3df +#define CSR_PMPADDR48 0x3e0 +#define CSR_PMPADDR49 0x3e1 +#define CSR_PMPADDR50 0x3e2 +#define CSR_PMPADDR51 0x3e3 +#define CSR_PMPADDR52 0x3e4 +#define CSR_PMPADDR53 0x3e5 +#define CSR_PMPADDR54 0x3e6 +#define CSR_PMPADDR55 0x3e7 +#define CSR_PMPADDR56 0x3e8 +#define CSR_PMPADDR57 0x3e9 +#define CSR_PMPADDR58 0x3ea +#define CSR_PMPADDR59 0x3eb +#define CSR_PMPADDR60 0x3ec +#define CSR_PMPADDR61 0x3ed +#define CSR_PMPADDR62 0x3ee +#define CSR_PMPADDR63 0x3ef =20 /* RNMI */ #define CSR_MNSCRATCH 0x740 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7948188356..f8f61ffff5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -6088,6 +6088,30 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] =3D { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG3] =3D { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, + [CSR_PMPCFG4] =3D { "pmpcfg4", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG5] =3D { "pmpcfg5", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG6] =3D { "pmpcfg6", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG7] =3D { "pmpcfg7", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG8] =3D { "pmpcfg8", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG9] =3D { "pmpcfg9", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG10] =3D { "pmpcfg10", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG11] =3D { "pmpcfg11", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG12] =3D { "pmpcfg12", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG13] =3D { "pmpcfg13", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG14] =3D { "pmpcfg14", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPCFG15] =3D { "pmpcfg15", pmp, read_pmpcfg, write_pmpcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, [CSR_PMPADDR0] =3D { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR1] =3D { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR2] =3D { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, @@ -6102,8 +6126,104 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPADDR11] =3D { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR12] =3D { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR13] =3D { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, - [CSR_PMPADDR14] =3D { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, - [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR14] =3D { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR16] =3D { "pmpaddr16", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR17] =3D { "pmpaddr17", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR18] =3D { "pmpaddr18", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR19] =3D { "pmpaddr19", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR20] =3D { "pmpaddr20", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR21] =3D { "pmpaddr21", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR22] =3D { "pmpaddr22", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR23] =3D { "pmpaddr23", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR24] =3D { "pmpaddr24", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR25] =3D { "pmpaddr25", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR26] =3D { "pmpaddr26", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR27] =3D { "pmpaddr27", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR28] =3D { "pmpaddr28", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR29] =3D { "pmpaddr29", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR30] =3D { "pmpaddr30", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR31] =3D { "pmpaddr31", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR32] =3D { "pmpaddr32", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR33] =3D { "pmpaddr33", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR34] =3D { "pmpaddr34", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR35] =3D { "pmpaddr35", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR36] =3D { "pmpaddr36", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR37] =3D { "pmpaddr37", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR38] =3D { "pmpaddr38", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR39] =3D { "pmpaddr39", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR40] =3D { "pmpaddr40", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR41] =3D { "pmpaddr41", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR42] =3D { "pmpaddr42", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR43] =3D { "pmpaddr43", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR44] =3D { "pmpaddr44", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR45] =3D { "pmpaddr45", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR46] =3D { "pmpaddr46", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR47] =3D { "pmpaddr47", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR48] =3D { "pmpaddr48", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR49] =3D { "pmpaddr49", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR50] =3D { "pmpaddr50", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR51] =3D { "pmpaddr51", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR52] =3D { "pmpaddr52", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR53] =3D { "pmpaddr53", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR54] =3D { "pmpaddr54", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR55] =3D { "pmpaddr55", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR56] =3D { "pmpaddr56", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR57] =3D { "pmpaddr57", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR58] =3D { "pmpaddr58", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR59] =3D { "pmpaddr59", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR60] =3D { "pmpaddr60", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR61] =3D { "pmpaddr61", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR62] =3D { "pmpaddr62", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_PMPADDR63] =3D { "pmpaddr63", pmp, read_pmpaddr, write_pmpaddr, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 /* Debug CSRs */ [CSR_TSELECT] =3D { "tselect", debug, read_tselect, write_tselect= }, --=20 2.48.1 From nobody Sat Nov 15 23:39:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1745228895; cv=none; d=zohomail.com; s=zohoarc; b=L1L7MtAdZbvls7cAQvfB0mpLgadHwvSmMc+IQ5SNiC8XgZeHvlklkKuCiPsPpSmkcZI7WWsBgk0HB8i41NrnEMFiTT0XHxAd1B0VblVs8XBpZrpDdX5V22iJkTStMXS8/PZgE9m9QYlJWcNpIhto9+bHqLWLkQ8FqNXuoZ4KXR8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745228895; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rXJeNfsAZ6hA+l8T57FZAI2ZxHCiBOWiIM/wn2t3kAA=; b=Iw5zCqw1+NNj7stHigeAUMfVJbh2cQB6Z1dQxJZceh+YHfDleIDJEZ1u4dVWI89kscHs91YSB+fy5JtLJNtaEQNj4tdYnhleQdLjY1ktzAt/FjJVlVBuRt4VTEEO032ZuiWfdJt2WXyRyk4Q/GizL2+lzKmrmCn8KuR+L7E/EDQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1745228895246729.7967617594034; Mon, 21 Apr 2025 02:48:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u6nkQ-0005ZZ-7d; Mon, 21 Apr 2025 05:47:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u6nkM-0005Xa-Oc for qemu-devel@nongnu.org; Mon, 21 Apr 2025 05:47:26 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u6nkK-0000E5-H0 for qemu-devel@nongnu.org; Mon, 21 Apr 2025 05:47:26 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-227914acd20so37662765ad.1 for ; Mon, 21 Apr 2025 02:47:24 -0700 (PDT) Received: from jchang-1875.internal.sifive.com ([147.161.192.170]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3087dee330bsm6162137a91.3.2025.04.21.02.47.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 21 Apr 2025 02:47:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1745228843; x=1745833643; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rXJeNfsAZ6hA+l8T57FZAI2ZxHCiBOWiIM/wn2t3kAA=; b=mm/oWycGBGQHVNzyR0ZsKlKU0rW+sg7AFSC2tM/qTN1OJxGtz76gc7sai2ZxFWze/2 BaoloWyqG4X9rIHfAzG3J6lOMOJhIcstRTnQ6d6np4SWn1T9iFNigwu1F6A/6/5bM83C HcuEJ8irj2Lgns968KHJEIi4XUHze1KmePJIU5Ii44K1TxAhkfPeS6lnn9bOEAv6L0ie ES3zFozZE52K7gLj9CyJjeu1IhbBOb5i7KESXErXdiuSXlh8zlrMGDPeFAkFcOleedcw umi3n1lmtfa9wRzanNRodH17oGVsEcyi+EQWrrL+IrJ1XO2AGX/GQoBHwoWgi5vwUGW7 MicQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745228843; x=1745833643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rXJeNfsAZ6hA+l8T57FZAI2ZxHCiBOWiIM/wn2t3kAA=; b=g/wNFz42faM/C7C+9Rj9ZVqFNgnQC58oVjlSOwN/5p9PaUyEERQVcRgxJkrJJBv9Wl LrmowdToaSJ9pe8AOIjBzGnrgGzNzQJxJ/jnBZQ4bwHnKr/Rywbk+2QKZrQj9s7aBsUb I3Guti9u5NQYGw8avbpBo8XzOSfJhLkPpnP28jdgaRo1hpY1l9BA0oW07Gvq9VyYwDX8 6vzYy2VLQ8fjz9mmV+YDns9bCZ2Gjjv05mv0Xfah4BTUJCluTXPVqvvX9tz9XCjaCyDv 4jc7WzxGHFP4MFxk6NKT+WNirrw65/qDXj9THY78/lIOfiEEcm3bIOIm9JzBiXeMdcq8 5/WQ== X-Gm-Message-State: AOJu0YzNCjDIfwugewt526zEAHhgo8i1H04m7s+bKb4nlGZdOkkKKJk8 OG74rKNjzkLkqbzM7HeQYfcokKHvTNteqiFQnF+8leawD1dLDVdZXIGrB8LLz/+GMVMqnYLdl4P 5SxCyiUwQUWeYkOMqt93eJukHfNBXIkRGOlcArbSSxKUl9o103AFx7TTRtDSxQPIaDTlG1/CNou RtQDYbdfWDJY0bv1h5CYPDJ4oKwujS8rq3B8LJXPEqgw== X-Gm-Gg: ASbGnctOSqsof+dGY81YLfKLaWLfxfwqIvFtudHkfe+ouL6hFlGGleZKInmEQzsKVEo sESFot/UeOiS51Q4yYb+7hAykQMsQWDamlHtRj71Tn3yIU4FlmJXxc0KDZgVp8nS8dpZjmU+hYL Aby3Mw0Lhl9nit4UVyYbGmt477D8cUZyaF/kKtRdgDEHnCVzYbPPxiS7YVBBYgjuy7OzZ+BzxhS 5GwwWPV/d/fa3XCH7tO4VSggGZCv4f82bZNK8gPi/JEWZi/nA5EgQwfbo4VCx5+6pZO3I2Oek5o nnAe0LzO52qsBstaKoMKY5QO/nti74IPKBm6bL02GfxHqMImhjIHrzd5vIIW4jLJUX9Bm9RAnnJ tmwhv X-Google-Smtp-Source: AGHT+IGLWvXZMMiyRYjEwu431APQjspeFV5LDg3sfHt+6v30zxhgrxML0/jiKEUv449J8VeHPrLPNQ== X-Received: by 2002:a17:902:cf05:b0:21f:98fc:8414 with SMTP id d9443c01a7336-22c50d8c10fmr168123895ad.26.1745228842464; Mon, 21 Apr 2025 02:47:22 -0700 (PDT) From: Jay Chang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jay Chang , Frank Chang Subject: [PATCH 2/2] target/riscv: Make PMP region count configurable Date: Mon, 21 Apr 2025 17:46:56 +0800 Message-ID: <20250421094656.48997-3-jay.chang@sifive.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250421094656.48997-1-jay.chang@sifive.com> References: <20250421094656.48997-1-jay.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=jay.chang@sifive.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1745228896601019000 Content-Type: text/plain; charset="utf-8" Previously, the number of PMP regions was hardcoded to 16 in QEMU. This patch replaces the fixed value with a new `pmp_regions` field, allowing platforms to configure the number of PMP regions. If no specific value is provided, the default number of PMP regions remains 16 to preserve the existing behavior. A new CPU parameter num-pmp-regions has been introduced to the QEMU command line. For example: -cpu rv64, g=3Dtrue, c=3Dtrue, pmp=3Dtrue, num-pmp-regions=3D8 Reviewed-by: Frank Chang Signed-off-by: Jay Chang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 2 +- target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 5 ++++- target/riscv/machine.c | 3 ++- target/riscv/pmp.c | 28 ++++++++++++++++--------- 6 files changed, 73 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 09ded6829a..528d77b820 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -512,6 +512,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) cpu->cfg.ext_zicsr =3D true; cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; + cpu->cfg.pmp_regions =3D 8; } =20 static void rv64_sifive_e_cpu_init(Object *obj) @@ -529,6 +530,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_zicsr =3D true; cpu->cfg.pmp =3D true; + cpu->cfg.pmp_regions =3D 8; } =20 static void rv64_thead_c906_cpu_init(Object *obj) @@ -761,6 +763,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) cpu->cfg.ext_zicsr =3D true; cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; + cpu->cfg.pmp_regions =3D 8; } =20 static void rv32_sifive_e_cpu_init(Object *obj) @@ -778,6 +781,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) cpu->cfg.ext_zifencei =3D true; cpu->cfg.ext_zicsr =3D true; cpu->cfg.pmp =3D true; + cpu->cfg.pmp_regions =3D 8; } =20 static void rv32_ibex_cpu_init(Object *obj) @@ -1478,6 +1482,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.cbom_blocksize =3D 64; cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; + cpu->cfg.pmp_regions =3D 16; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 @@ -1935,6 +1940,46 @@ static const PropertyInfo prop_pmp =3D { .set =3D prop_pmp_set, }; =20 +static void prop_num_pmp_regions_set(Object *obj, Visitor *v, const char *= name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + visit_type_uint16(v, name, &value, errp); + + if (cpu->cfg.pmp_regions !=3D value && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + return; + } + + if (cpu->env.priv_ver < PRIV_VERSION_1_12_0 && value > 16) { + error_setg(errp, "Number of PMP regions exceeds maximum available"= ); + return; + } else if (value > 64) { + error_setg(errp, "Number of PMP regions exceeds maximum available"= ); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.pmp_regions =3D value; +} + +static void prop_num_pmp_regions_get(Object *obj, Visitor *v, const char *= name, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.pmp_regions; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_num_pmp_regions =3D { + .type =3D "uint16", + .description =3D "num-pmp-regions", + .get =3D prop_num_pmp_regions_get, + .set =3D prop_num_pmp_regions_set, +}; + static int priv_spec_from_str(const char *priv_spec_str) { int priv_version =3D -1; @@ -2934,6 +2979,7 @@ static const Property riscv_cpu_properties[] =3D { =20 {.name =3D "mmu", .info =3D &prop_mmu}, {.name =3D "pmp", .info =3D &prop_pmp}, + {.name =3D "num-pmp-regions", .info =3D &prop_num_pmp_regions}, =20 {.name =3D "priv_spec", .info =3D &prop_priv_spec}, {.name =3D "vext_spec", .info =3D &prop_vext_spec}, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51e49e03de..50d58c15f2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -162,7 +162,7 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied= _rules[]; =20 #define MMU_USER_IDX 3 =20 -#define MAX_RISCV_PMPS (16) +#define MAX_RISCV_PMPS (64) =20 #if !defined(CONFIG_USER_ONLY) #include "pmp.h" diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 8a843482cc..8c805b45f6 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -189,6 +189,7 @@ struct RISCVCPUConfig { uint16_t cbom_blocksize; uint16_t cbop_blocksize; uint16_t cboz_blocksize; + uint16_t pmp_regions; bool mmu; bool pmp; bool debug; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f8f61ffff5..65f91be9c0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -736,7 +736,10 @@ static RISCVException dbltrp_hmode(CPURISCVState *env,= int csrno) static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->pmp) { - if (csrno <=3D CSR_PMPCFG3) { + uint16_t MAX_PMPCFG =3D (env->priv_ver >=3D PRIV_VERSION_1_12_0) ? ++ CSR_PMPCFG15 : CSR_PMPCFG3; + + if (csrno <=3D MAX_PMPCFG) { uint32_t reg_index =3D csrno - CSR_PMPCFG0; =20 /* TODO: RV128 restriction check */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 889e2b6570..c3e4e78802 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -36,8 +36,9 @@ static int pmp_post_load(void *opaque, int version_id) RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; int i; + uint16_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { pmp_update_rule_addr(env, i); } pmp_update_rule_nums(env); diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index c685f7f2c5..3439295d41 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -121,7 +121,9 @@ uint32_t pmp_get_num_rules(CPURISCVState *env) */ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index) { - if (pmp_index < MAX_RISCV_PMPS) { + uint16_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; + + if (pmp_index < pmp_regions) { return env->pmp_state.pmp[pmp_index].cfg_reg; } =20 @@ -135,7 +137,9 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, = uint32_t pmp_index) */ static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t = val) { - if (pmp_index < MAX_RISCV_PMPS) { + uint16_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; + + if (pmp_index < pmp_regions) { if (env->pmp_state.pmp[pmp_index].cfg_reg =3D=3D val) { /* no change */ return false; @@ -235,9 +239,10 @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t= pmp_index) void pmp_update_rule_nums(CPURISCVState *env) { int i; + uint16_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 env->pmp_state.num_rules =3D 0; - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { const uint8_t a_field =3D pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); if (PMP_AMATCH_OFF !=3D a_field) { @@ -331,6 +336,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, int pmp_size =3D 0; hwaddr s =3D 0; hwaddr e =3D 0; + uint16_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 /* Short cut if no rules */ if (0 =3D=3D pmp_get_num_rules(env)) { @@ -355,7 +361,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr, * 1.10 draft priv spec states there is an implicit order * from low to high */ - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { s =3D pmp_is_in_range(env, i, addr); e =3D pmp_is_in_range(env, i, addr + pmp_size - 1); =20 @@ -526,8 +532,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add= r_index, { trace_pmpaddr_csr_write(env->mhartid, addr_index, val); bool is_next_cfg_tor =3D false; + uint16_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 - if (addr_index < MAX_RISCV_PMPS) { + if (addr_index < pmp_regions) { if (env->pmp_state.pmp[addr_index].addr_reg =3D=3D val) { /* no change */ return; @@ -537,7 +544,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add= r_index, * In TOR mode, need to check the lock bit of the next pmp * (if there is a next). */ - if (addr_index + 1 < MAX_RISCV_PMPS) { + if (addr_index + 1 < pmp_regions) { uint8_t pmp_cfg =3D env->pmp_state.pmp[addr_index + 1].cfg_reg; is_next_cfg_tor =3D PMP_AMATCH_TOR =3D=3D pmp_get_a_field(pmp_= cfg); =20 @@ -572,8 +579,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add= r_index, target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) { target_ulong val =3D 0; + uint16_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 - if (addr_index < MAX_RISCV_PMPS) { + if (addr_index < pmp_regions) { val =3D env->pmp_state.pmp[addr_index].addr_reg; trace_pmpaddr_csr_read(env->mhartid, addr_index, val); } else { @@ -591,6 +599,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong= val) { int i; uint64_t mask =3D MSECCFG_MMWP | MSECCFG_MML; + uint16_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; /* Update PMM field only if the value is valid according to Zjpm v1.0 = */ if (riscv_cpu_cfg(env)->ext_smmpm && riscv_cpu_mxl(env) =3D=3D MXL_RV64 && @@ -602,7 +611,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong= val) =20 /* RLB cannot be enabled if it's already 0 and if any regions are lock= ed */ if (!MSECCFG_RLB_ISSET(env)) { - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { if (pmp_is_locked(env, i)) { val &=3D ~MSECCFG_RLB; break; @@ -658,6 +667,7 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, hwadd= r addr) hwaddr tlb_sa =3D addr & ~(TARGET_PAGE_SIZE - 1); hwaddr tlb_ea =3D tlb_sa + TARGET_PAGE_SIZE - 1; int i; + uint16_t pmp_regions =3D riscv_cpu_cfg(env)->pmp_regions; =20 /* * If PMP is not supported or there are no PMP rules, the TLB page wil= l not @@ -668,7 +678,7 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, hwadd= r addr) return TARGET_PAGE_SIZE; } =20 - for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + for (i =3D 0; i < pmp_regions; i++) { if (pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg) =3D=3D PMP_AMAT= CH_OFF) { continue; } --=20 2.48.1