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Tue, 15 Apr 2025 16:07:48 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id C4C44140114; Tue, 15 Apr 2025 16:11:59 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 15 Apr 2025 10:11:52 +0200 To: , CC: , , , , , , , , , , , , , Subject: [PATCH 1/5] hw/arm/smmuv3: Introduce SMMUv3 device Date: Tue, 15 Apr 2025 09:11:00 +0100 Message-ID: <20250415081104.71708-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250415081104.71708-1-shameerali.kolothum.thodi@huawei.com> References: <20250415081104.71708-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1744704789636019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Initial support to have a user-creatable SMMUv3 device associated with a PCIe root complex, -device arm-smmuv3-dev,bus=3Dpcie.x Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3.c | 54 +++++++++++++++++++++++++++++++++++++++++ include/hw/arm/smmuv3.h | 16 ++++++++++++ 2 files changed, 70 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 1a96287ba9..e3b8e13ca3 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -24,6 +24,7 @@ #include "hw/qdev-properties.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "cpu.h" #include "trace.h" #include "qemu/log.h" @@ -1873,6 +1874,38 @@ static void smmu_reset_exit(Object *obj, ResetType t= ype) smmuv3_init_regs(s); } =20 +static int smmuv3_dev_pcie_bus(Object *obj, void *opaque) +{ + DeviceState *d =3D opaque; + PCIBus *bus; + + if (!object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { + return 0; + } + + bus =3D PCI_HOST_BRIDGE(obj)->bus; + if (d->parent_bus && !strcmp(bus->qbus.name, d->parent_bus->name)) { + object_property_set_link(OBJECT(d), "primary-bus", OBJECT(bus), + &error_abort); + return 1; + } + return 0; +} + +static void smmuv3_dev_realize(DeviceState *d, Error **errp) +{ + SMMUv3DevState *s_nested =3D ARM_SMMUV3_DEV(d); + SMMUv3DevClass *c =3D ARM_SMMUV3_DEV_GET_CLASS(s_nested); + Error *local_err =3D NULL; + + object_child_foreach_recursive(object_get_root(), smmuv3_dev_pcie_bus,= d); + c->parent_realize(d, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } +} + static void smmu_realize(DeviceState *d, Error **errp) { SMMUState *sys =3D ARM_SMMU(d); @@ -1983,6 +2016,18 @@ static void smmuv3_instance_init(Object *obj) /* Nothing much to do here as of now */ } =20 +static void smmuv3_dev_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + SMMUv3DevClass *c =3D ARM_SMMUV3_DEV_CLASS(klass); + + dc->vmsd =3D &vmstate_smmuv3; + device_class_set_parent_realize(dc, smmuv3_dev_realize, + &c->parent_realize); + dc->hotpluggable =3D false; + dc->bus_type =3D TYPE_PCIE_BUS; +} + static void smmuv3_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -2038,6 +2083,14 @@ static void smmuv3_iommu_memory_region_class_init(Ob= jectClass *klass, imrc->notify_flag_changed =3D smmuv3_notify_flag_changed; } =20 +static const TypeInfo smmuv3_dev_type_info =3D { + .name =3D TYPE_ARM_SMMUV3_DEV, + .parent =3D TYPE_ARM_SMMUV3, + .instance_size =3D sizeof(SMMUv3DevState), + .class_size =3D sizeof(SMMUv3DevClass), + .class_init =3D smmuv3_dev_class_init, +}; + static const TypeInfo smmuv3_type_info =3D { .name =3D TYPE_ARM_SMMUV3, .parent =3D TYPE_ARM_SMMU, @@ -2056,6 +2109,7 @@ static const TypeInfo smmuv3_iommu_memory_region_info= =3D { static void smmuv3_register_types(void) { type_register_static(&smmuv3_type_info); + type_register_static(&smmuv3_dev_type_info); type_register_static(&smmuv3_iommu_memory_region_info); } =20 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d183a62766..7d3846ac40 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -87,4 +87,20 @@ OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) #define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P) #define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P) =20 +struct SMMUv3DevState { + SMMUv3State smmuv3_state; +}; + +struct SMMUv3DevClass { + /*< private >*/ + SMMUv3Class smmuv3_class; + /*< public >*/ + + DeviceRealize parent_realize; +}; + +/* User creatable smmuv3 device */ +#define TYPE_ARM_SMMUV3_DEV "arm-smmuv3-dev" +OBJECT_DECLARE_TYPE(SMMUv3DevState, SMMUv3DevClass, ARM_SMMUV3_DEV) + #endif --=20 2.34.1 From nobody Mon Feb 9 22:00:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 15 Apr 2025 16:12:09 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 15 Apr 2025 10:12:01 +0200 To: , CC: , , , , , , , , , , , , , Subject: [PATCH 2/5] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Date: Tue, 15 Apr 2025 09:11:01 +0100 Message-ID: <20250415081104.71708-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250415081104.71708-1-shameerali.kolothum.thodi@huawei.com> References: <20250415081104.71708-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1744704883132019100 With the soon to be introduced=C2=A0user-creatable=C2=A0SMMUv3 devices for virt, it is possible=C2=A0to have multiple SMMUv3 devices associated with different PCIe root complexes. Update IORT nodes accordingly. Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 119 +++++++++++++++++++++++++++++++++++---- include/hw/arm/virt.h | 1 + 2 files changed, 108 insertions(+), 12 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3ac8f8e178..d1e083ee31 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -43,6 +43,7 @@ #include "hw/acpi/generic_event_device.h" #include "hw/acpi/tpm.h" #include "hw/acpi/hmat.h" +#include "hw/arm/smmuv3.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -266,6 +267,60 @@ static int iort_idmap_compare(gconstpointer a, gconstp= ointer b) return idmap_a->input_base - idmap_b->input_base; } =20 +struct SMMUv3Device { + int irq; + hwaddr base; + AcpiIortIdMapping smmu_idmap; +}; +typedef struct SMMUv3Device SMMUv3Device; + +static int smmuv3_dev_idmap_compare(gconstpointer a, gconstpointer b) +{ + SMMUv3Device *sdev_a =3D (SMMUv3Device *)a; + SMMUv3Device *sdev_b =3D (SMMUv3Device *)b; + + return sdev_a->smmu_idmap.input_base - sdev_b->smmu_idmap.input_base; +} + +static int get_smmuv3_device(Object *obj, void *opaque) +{ + GArray *sdev_blob =3D opaque; + int min_bus, max_bus; + VirtMachineState *vms; + PlatformBusDevice *pbus; + SysBusDevice *sbdev; + SMMUv3Device sdev; + hwaddr base; + int irq; + PCIBus *bus; + + if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3_DEV)) { + return 0; + } + + bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); + if (!bus || pci_bus_bypass_iommu(bus)) { + return 0; + } + + vms =3D VIRT_MACHINE(qdev_get_machine()); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + + base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + + pci_bus_range(bus, &min_bus, &max_bus); + sdev.smmu_idmap.input_base =3D min_bus << 8; + sdev.smmu_idmap.id_count =3D (max_bus - min_bus + 1) << 8; + sdev.base =3D base; + sdev.irq =3D irq + ARM_SPI_BASE; + g_array_append_val(sdev_blob, sdev); + return 0; +} + /* * Input Output Remapping Table (IORT) * Conforms to "IO Remapping Table System Software on ARM Platforms", @@ -275,25 +330,42 @@ static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { int i, nb_nodes, rc_mapping_count; - size_t node_size, smmu_offset =3D 0; + size_t node_size, *smmu_offset =3D NULL; AcpiIortIdMapping *idmap; + int num_smmus =3D 0; uint32_t id =3D 0; GArray *smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); GArray *its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMappi= ng)); + GArray *smmuv3_devices =3D g_array_new(false, true, sizeof(SMMUv3Devic= e)); =20 AcpiTable table =3D { .sig =3D "IORT", .rev =3D 3, .oem_id =3D vms->oe= m_id, .oem_table_id =3D vms->oem_table_id }; /* Table 2 The IORT */ acpi_table_begin(&table, table_data); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - AcpiIortIdMapping next_range =3D {0}; - + nb_nodes =3D 2; /* RC, ITS */ + if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3_DEV) { + object_child_foreach_recursive(object_get_root(), + get_smmuv3_device, smmuv3_devices); + /* Sort the smmuv3-devices by smmu idmap input_base */ + g_array_sort(smmuv3_devices, smmuv3_dev_idmap_compare); + /* Fill smmu idmap from sorted smmuv3 devices array */ + for (i =3D 0; i < smmuv3_devices->len; i++) { + SMMUv3Device *s =3D &g_array_index(smmuv3_devices, SMMUv3Devic= e, i); + g_array_append_val(smmu_idmaps, s->smmu_idmap); + } + num_smmus =3D smmuv3_devices->len; + } else if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { object_child_foreach_recursive(object_get_root(), iort_host_bridges, smmu_idmaps); =20 /* Sort the smmu idmap by input_base */ g_array_sort(smmu_idmaps, iort_idmap_compare); + num_smmus =3D 1; + } + + if (num_smmus) { + AcpiIortIdMapping next_range =3D {0}; =20 /* * Split the whole RIDs by mapping from RC to SMMU, @@ -316,10 +388,10 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) g_array_append_val(its_idmaps, next_range); } =20 - nb_nodes =3D 3; /* RC, ITS, SMMUv3 */ + smmu_offset =3D g_new0(size_t, num_smmus); + nb_nodes +=3D num_smmus; rc_mapping_count =3D smmu_idmaps->len + its_idmaps->len; } else { - nb_nodes =3D 2; /* RC, ITS */ rc_mapping_count =3D 1; } /* Number of IORT Nodes */ @@ -341,10 +413,20 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) /* GIC ITS Identifier Array */ build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4); =20 - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + for (i =3D 0; i < num_smmus; i++) { + hwaddr base; + int irq; + + if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3_DEV) { + SMMUv3Device *s =3D &g_array_index(smmuv3_devices, SMMUv3Devic= e, i); + base =3D s->base; + irq =3D s->irq; + } else { + base =3D vms->memmap[VIRT_SMMU].base; + irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + } =20 - smmu_offset =3D table_data->len - table.table_offset; + smmu_offset[i] =3D table_data->len - table.table_offset; /* Table 9 SMMUv3 Format */ build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type = */ node_size =3D SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE; @@ -355,7 +437,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) /* Reference to ID Array */ build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4); /* Base address */ - build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base,= 8); + build_append_int_noprefix(table_data, base, 8); /* Flags */ build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ @@ -404,15 +486,26 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) build_append_int_noprefix(table_data, 0, 3); /* Reserved */ =20 /* Output Reference */ - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { + if (num_smmus) { AcpiIortIdMapping *range; =20 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */ for (i =3D 0; i < smmu_idmaps->len; i++) { + size_t offset; + if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3_DEV) { + offset =3D smmu_offset[i]; + } else { + /* + * For legacy VIRT_IOMMU_SMMUV3 case, one machine wide + * smmuv3 may have multiple smmu_idmaps. + */ + offset =3D smmu_offset[0]; + } + range =3D &g_array_index(smmu_idmaps, AcpiIortIdMapping, i); /* output IORT node is the smmuv3 node */ build_iort_id_mapping(table_data, range->input_base, - range->id_count, smmu_offset); + range->id_count, offset); } =20 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */ @@ -430,6 +523,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) acpi_table_end(linker, &table); g_array_free(smmu_idmaps, true); g_array_free(its_idmaps, true); + g_free(smmu_offset); + g_array_free(smmuv3_devices, true); } =20 /* diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index c8e94e6aed..12395c7594 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -92,6 +92,7 @@ enum { typedef enum VirtIOMMUType { VIRT_IOMMU_NONE, VIRT_IOMMU_SMMUV3, + VIRT_IOMMU_SMMUV3_DEV, VIRT_IOMMU_VIRTIO, } VirtIOMMUType; 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Tue, 15 Apr 2025 16:08:21 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id A848A140114; Tue, 15 Apr 2025 16:12:18 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 15 Apr 2025 10:12:11 +0200 To: , CC: , , , , , , , , , , , , , Subject: [PATCH 3/5] hw/arm/virt: Factor out common SMMUV3 dt bindings code Date: Tue, 15 Apr 2025 09:11:02 +0100 Message-ID: <20250415081104.71708-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250415081104.71708-1-shameerali.kolothum.thodi@huawei.com> References: <20250415081104.71708-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1744704909976019000 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No functional changes intended. This will be useful when we add support for user-creatable smmuv3 device. Signed-off-by: Shameer Kolothum --- hw/arm/virt.c | 55 +++++++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a96452f17a..729f192558 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1417,19 +1417,42 @@ static void create_pcie_irq_map(const MachineState = *ms, 0x7 /* PCI irq */); } =20 +static void create_smmuv3_dt_bindings(const VirtMachineState *vms, hwaddr = base, + int irq) +{ + char *node; + const char compat[] =3D "arm,smmu-v3"; + const char irq_names[] =3D "eventq\0priq\0cmdq-sync\0gerror"; + MachineState *ms =3D MACHINE(vms); + + node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); + qemu_fdt_add_subnode(ms->fdt, node); + qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, 0x20000= ); + + qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, + GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + + qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, + sizeof(irq_names)); + + qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); + qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); + g_free(node); +} + static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); - char *node; - const char compat[] =3D "arm,smmu-v3"; int irq =3D vms->irqmap[VIRT_SMMU]; int i; hwaddr base =3D vms->memmap[VIRT_SMMU].base; - hwaddr size =3D vms->memmap[VIRT_SMMU].size; - const char irq_names[] =3D "eventq\0priq\0cmdq-sync\0gerror"; DeviceState *dev; - MachineState *ms =3D MACHINE(vms); =20 if (vms->iommu !=3D VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { return; @@ -1448,27 +1471,7 @@ static void create_smmu(const VirtMachineState *vms, sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, qdev_get_gpio_in(vms->gic, irq + i)); } - - node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); - qemu_fdt_add_subnode(ms->fdt, node); - qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); - - qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, - GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); - - qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, - sizeof(irq_names)); - - qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); - - qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); - - qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); - g_free(node); + create_smmuv3_dt_bindings(vms, base, irq); } =20 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) --=20 2.34.1 From nobody Mon Feb 9 22:00:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 15 Apr 2025 16:08:30 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id AF0D01402C3; Tue, 15 Apr 2025 16:12:27 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 15 Apr 2025 10:12:20 +0200 To: , CC: , , , , , , , , , , , , , Subject: [PATCH 4/5] hw/arm/virt: Add support for smmuv3 device Date: Tue, 15 Apr 2025 09:11:03 +0100 Message-ID: <20250415081104.71708-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250415081104.71708-1-shameerali.kolothum.thodi@huawei.com> References: <20250415081104.71708-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1744705201638019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow cold-plug of smmuv3 device to virt If the machine wide smmuv3 or a virtio-iommu is not specified. Also restrict the usage if virt <=3D 9.2. This will prevent accidently creating a SMMUv3 device on machines prior to 9.2 and cause failure on migrating to machines with same version but has a legacy smmuv3 device. Signed-off-by: Shameer Kolothum --- ToDo: probably need to change virt <=3D 9.2 to 10.0 considering the=20 Qemu cycle we are at now. --- hw/arm/virt.c | 54 +++++++++++++++++++++++++++++++++++++++++++ hw/core/sysbus-fdt.c | 3 +++ include/hw/arm/virt.h | 1 + 3 files changed, 58 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 729f192558..8d0ae79f4d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -56,6 +56,7 @@ #include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" #include "hw/virtio/virtio-pci.h" #include "hw/core/sysbus-fdt.h" @@ -1445,6 +1446,31 @@ static void create_smmuv3_dt_bindings(const VirtMach= ineState *vms, hwaddr base, g_free(node); } =20 +static void create_smmuv3_dev_dtb(VirtMachineState *vms, + DeviceState *dev) +{ + PlatformBusDevice *pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + SysBusDevice *sbdev =3D SYS_BUS_DEVICE(dev); + int irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + hwaddr base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + MachineState *ms =3D MACHINE(vms); + PCIBus *bus; + + bus =3D PCI_BUS(object_property_get_link(OBJECT(dev), "primary-bus", + &error_abort)); + if (strcmp("pcie.0", bus->qbus.name)) { + warn_report("SMMUv3 device only supported with pcie.0 for DT"); + return; + } + base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + + vms->iommu_phandle =3D qemu_fdt_alloc_phandle(ms->fdt); + create_smmuv3_dt_bindings(vms, base, irq); + qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", + 0x0, vms->iommu_phandle, 0x0, 0x10000); +} + static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { @@ -2944,6 +2970,18 @@ static void virt_machine_device_pre_plug_cb(HotplugH= andler *hotplug_dev, qlist_append_str(reserved_regions, resv_prop_str); qdev_prop_set_array(dev, "reserved-regions", reserved_regions); g_free(resv_prop_str); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3_DEV)) { + VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); + + if (vmc->no_smmuv3_device) { + error_setg(errp, "virt machine does not support arm-smmuv3-dev= ice"); + } else if ((vms->iommu =3D=3D VIRT_IOMMU_VIRTIO) || + (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3)) { + error_setg(errp, "virt machine already has %s set." + "Doesn't support multiple incompatible iommus", + (vms->iommu =3D=3D VIRT_IOMMU_VIRTIO) ? + "virtio-iommu" : "iommu=3Dsmmuv3"); + } } } =20 @@ -2967,6 +3005,19 @@ static void virt_machine_device_plug_cb(HotplugHandl= er *hotplug_dev, virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); } =20 + if (object_dynamic_cast(OBJECT(dev), TYPE_ARM_SMMUV3_DEV)) { + VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); + + create_smmuv3_dev_dtb(vms, dev); + if (vms->iommu !=3D VIRT_IOMMU_SMMUV3_DEV) { + vms->iommu =3D VIRT_IOMMU_SMMUV3_DEV; + } + if (!vmc->no_nested_smmu) { + object_property_set_str(OBJECT(dev), "stage", "nested", + &error_fatal); + } + } + if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { PCIDevice *pdev =3D PCI_DEVICE(dev); =20 @@ -3169,6 +3220,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ARM_SMMUV3_DEV); #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); #endif @@ -3418,8 +3470,10 @@ DEFINE_VIRT_MACHINE_AS_LATEST(10, 0) =20 static void virt_machine_9_2_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); virt_machine_10_0_options(mc); compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len); + vmc->no_smmuv3_device =3D true; } DEFINE_VIRT_MACHINE(9, 2) =20 diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c index e85066b905..ec90ed2c14 100644 --- a/hw/core/sysbus-fdt.c +++ b/hw/core/sysbus-fdt.c @@ -31,6 +31,7 @@ #include "qemu/error-report.h" #include "system/device_tree.h" #include "system/tpm.h" +#include "hw/arm/smmuv3.h" #include "hw/platform-bus.h" #include "hw/vfio/vfio-platform.h" #include "hw/vfio/vfio-calxeda-xgmac.h" @@ -512,6 +513,8 @@ static const BindingEntry bindings[] =3D { #ifdef CONFIG_LINUX TYPE_BINDING(TYPE_VFIO_CALXEDA_XGMAC, add_calxeda_midway_xgmac_fdt_nod= e), TYPE_BINDING(TYPE_VFIO_AMD_XGBE, add_amd_xgbe_fdt_node), + /* No generic DT support for smmuv3 dev. Support added for arm virt on= ly */ + TYPE_BINDING(TYPE_ARM_SMMUV3_DEV, no_fdt_node), VFIO_PLATFORM_BINDING("amd,xgbe-seattle-v1a", add_amd_xgbe_fdt_node), #endif #ifdef CONFIG_TPM diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 12395c7594..9f98345c92 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -136,6 +136,7 @@ struct VirtMachineClass { bool no_tcg_lpa2; bool no_ns_el2_virt_timer_irq; bool no_nested_smmu; + bool no_smmuv3_device; }; =20 struct VirtMachineState { --=20 2.34.1 From nobody Mon Feb 9 22:00:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1744705141; cv=none; d=zohomail.com; s=zohoarc; b=Lzkc+wxSs3abZnAhZZ7mfNF2sNLtsbhD2sm5dihFn4yMnYC0iFXeW8warZ6FdtQaWOO0iT5Oo9PmvmfFpqVVWgTbVG8w0haCujqIUZxuR6jraAwpE6Gw7DKA6yXpgmegcO4hjgNDmkwb6pFSpwGjUooGo1bktYFnYY3L601SaYk= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1744705143231019100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e3b8e13ca3..572119e472 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2026,6 +2026,7 @@ static void smmuv3_dev_class_init(ObjectClass *klass,= void *data) &c->parent_realize); dc->hotpluggable =3D false; dc->bus_type =3D TYPE_PCIE_BUS; + dc->user_creatable =3D true; } =20 static void smmuv3_class_init(ObjectClass *klass, void *data) --=20 2.34.1