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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1744648781; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ST/Epdwc6K7kU2DxufZKND7JF8yJCWJgqDVNPy8cEvo=; b=WDgSr+x5Z2BAjSmlMXLf5lHhpXCk1+9X1GjvhjQWT5mmlIXsJr8HcsEqrn1NcAvJzc3QuF FjsiC6TvOqxlk3lUzQOHb8i6E+D+KcHMpoI4uubHc2zC9FQxQpbxz4ltvu+Bx6/WEQdMPi ue7buYvx7NWoY8CUVW9Frm9V7hGvvDI= X-MC-Unique: amOgVnpCMKCnzCTnfgOphQ-1 X-Mimecast-MFC-AGG-ID: amOgVnpCMKCnzCTnfgOphQ_1744648771 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v3 01/10] arm/cpu: Add infra to handle generated ID register definitions Date: Mon, 14 Apr 2025 18:38:40 +0200 Message-ID: <20250414163849.321857-2-cohuck@redhat.com> In-Reply-To: <20250414163849.321857-1-cohuck@redhat.com> References: <20250414163849.321857-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Eric Auger The known ID regs are described in a new initialization function dubbed initialize_cpu_sysreg_properties(). That code will be automatically generated from linux arch/arm64/tools/sysreg. For the time being let's just describe a single id reg, CTR_EL0. In this description we only care about non RES/RAZ fields, ie. named fields. The registers are populated in an array indexed by ARMIDRegisterIdx and their fields are added in a sorted list. [CH: adapted to reworked register storage] Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-custom.h | 60 ++++++++++++++++++++++++++++++ target/arm/cpu-sysreg-properties.c | 41 ++++++++++++++++++++ target/arm/cpu64.c | 2 + target/arm/meson.build | 1 + 4 files changed, 104 insertions(+) create mode 100644 target/arm/cpu-custom.h create mode 100644 target/arm/cpu-sysreg-properties.c diff --git a/target/arm/cpu-custom.h b/target/arm/cpu-custom.h new file mode 100644 index 000000000000..615347376e56 --- /dev/null +++ b/target/arm/cpu-custom.h @@ -0,0 +1,60 @@ +/* + * handle ID registers and their fields + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ARM_CPU_CUSTOM_H +#define ARM_CPU_CUSTOM_H + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "cpu-sysregs.h" + +typedef struct ARM64SysRegField { + const char *name; /* name of the field, for instance CTR_EL0_IDC */ + int index; + int lower; + int upper; +} ARM64SysRegField; + +typedef struct ARM64SysReg { + const char *name; /* name of the sysreg, for instance CTR_EL0 */ + ARMSysRegs sysreg; + int index; + GList *fields; /* list of named fields, excluding RES* */ +} ARM64SysReg; + +void initialize_cpu_sysreg_properties(void); + +/* + * List of exposed ID regs (automatically populated from linux + * arch/arm64/tools/sysreg) + */ +extern ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +/* Allocate a new field and insert it at the head of the @reg list */ +static inline GList *arm64_sysreg_add_field(ARM64SysReg *reg, const char *= name, + uint8_t min, uint8_t max) { + + ARM64SysRegField *field =3D g_new0(ARM64SysRegField, 1); + + field->name =3D name; + field->lower =3D min; + field->upper =3D max; + field->index =3D reg->index; + + reg->fields =3D g_list_append(reg->fields, field); + return reg->fields; +} + +static inline ARM64SysReg *arm64_sysreg_get(ARMIDRegisterIdx index) +{ + ARM64SysReg *reg =3D &arm64_id_regs[index]; + + reg->index =3D index; + reg->sysreg =3D id_register_sysreg[index]; + return reg; +} + +#endif diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-pro= perties.c new file mode 100644 index 000000000000..8b7ef5badfb9 --- /dev/null +++ b/target/arm/cpu-sysreg-properties.c @@ -0,0 +1,41 @@ +/* + * QEMU ARM CPU SYSREG PROPERTIES + * to be generated from linux sysreg + * + * Copyright (c) Red Hat, Inc. 2024 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "cpu-custom.h" + +ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +void initialize_cpu_sysreg_properties(void) +{ + memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_IDX); + /* CTR_EL0 */ + ARM64SysReg *CTR_EL0 =3D arm64_sysreg_get(CTR_EL0_IDX); + CTR_EL0->name =3D "CTR_EL0"; + arm64_sysreg_add_field(CTR_EL0, "TminLine", 32, 37); + arm64_sysreg_add_field(CTR_EL0, "DIC", 29, 29); + arm64_sysreg_add_field(CTR_EL0, "IDC", 28, 28); + arm64_sysreg_add_field(CTR_EL0, "CWG", 24, 27); + arm64_sysreg_add_field(CTR_EL0, "ERG", 20, 23); + arm64_sysreg_add_field(CTR_EL0, "DminLine", 16, 19); + arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15); + arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3); +} + diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9769401a8585..839442745ea4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -35,6 +35,7 @@ #include "internals.h" #include "cpu-features.h" #include "cpregs.h" +#include "cpu-custom.h" =20 /* convert between _IDX and SYS_ */ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ @@ -891,6 +892,7 @@ static void aarch64_cpu_register_types(void) { size_t i; =20 + initialize_cpu_sysreg_properties(); type_register_static(&aarch64_cpu_type_info); =20 for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { diff --git a/target/arm/meson.build b/target/arm/meson.build index 3065081d241d..1c97c1ef7580 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -14,6 +14,7 @@ arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstu= b.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', 'gdbstub64.c', + 'cpu-sysreg-properties.c', )) =20 arm_system_ss =3D ss.source_set() --=20 2.49.0