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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1744648781; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ST/Epdwc6K7kU2DxufZKND7JF8yJCWJgqDVNPy8cEvo=; b=WDgSr+x5Z2BAjSmlMXLf5lHhpXCk1+9X1GjvhjQWT5mmlIXsJr8HcsEqrn1NcAvJzc3QuF FjsiC6TvOqxlk3lUzQOHb8i6E+D+KcHMpoI4uubHc2zC9FQxQpbxz4ltvu+Bx6/WEQdMPi ue7buYvx7NWoY8CUVW9Frm9V7hGvvDI= X-MC-Unique: amOgVnpCMKCnzCTnfgOphQ-1 X-Mimecast-MFC-AGG-ID: amOgVnpCMKCnzCTnfgOphQ_1744648771 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v3 01/10] arm/cpu: Add infra to handle generated ID register definitions Date: Mon, 14 Apr 2025 18:38:40 +0200 Message-ID: <20250414163849.321857-2-cohuck@redhat.com> In-Reply-To: <20250414163849.321857-1-cohuck@redhat.com> References: <20250414163849.321857-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Eric Auger The known ID regs are described in a new initialization function dubbed initialize_cpu_sysreg_properties(). That code will be automatically generated from linux arch/arm64/tools/sysreg. For the time being let's just describe a single id reg, CTR_EL0. In this description we only care about non RES/RAZ fields, ie. named fields. The registers are populated in an array indexed by ARMIDRegisterIdx and their fields are added in a sorted list. [CH: adapted to reworked register storage] Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-custom.h | 60 ++++++++++++++++++++++++++++++ target/arm/cpu-sysreg-properties.c | 41 ++++++++++++++++++++ target/arm/cpu64.c | 2 + target/arm/meson.build | 1 + 4 files changed, 104 insertions(+) create mode 100644 target/arm/cpu-custom.h create mode 100644 target/arm/cpu-sysreg-properties.c diff --git a/target/arm/cpu-custom.h b/target/arm/cpu-custom.h new file mode 100644 index 000000000000..615347376e56 --- /dev/null +++ b/target/arm/cpu-custom.h @@ -0,0 +1,60 @@ +/* + * handle ID registers and their fields + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ARM_CPU_CUSTOM_H +#define ARM_CPU_CUSTOM_H + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "cpu-sysregs.h" + +typedef struct ARM64SysRegField { + const char *name; /* name of the field, for instance CTR_EL0_IDC */ + int index; + int lower; + int upper; +} ARM64SysRegField; + +typedef struct ARM64SysReg { + const char *name; /* name of the sysreg, for instance CTR_EL0 */ + ARMSysRegs sysreg; + int index; + GList *fields; /* list of named fields, excluding RES* */ +} ARM64SysReg; + +void initialize_cpu_sysreg_properties(void); + +/* + * List of exposed ID regs (automatically populated from linux + * arch/arm64/tools/sysreg) + */ +extern ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +/* Allocate a new field and insert it at the head of the @reg list */ +static inline GList *arm64_sysreg_add_field(ARM64SysReg *reg, const char *= name, + uint8_t min, uint8_t max) { + + ARM64SysRegField *field =3D g_new0(ARM64SysRegField, 1); + + field->name =3D name; + field->lower =3D min; + field->upper =3D max; + field->index =3D reg->index; + + reg->fields =3D g_list_append(reg->fields, field); + return reg->fields; +} + +static inline ARM64SysReg *arm64_sysreg_get(ARMIDRegisterIdx index) +{ + ARM64SysReg *reg =3D &arm64_id_regs[index]; + + reg->index =3D index; + reg->sysreg =3D id_register_sysreg[index]; + return reg; +} + +#endif diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-pro= perties.c new file mode 100644 index 000000000000..8b7ef5badfb9 --- /dev/null +++ b/target/arm/cpu-sysreg-properties.c @@ -0,0 +1,41 @@ +/* + * QEMU ARM CPU SYSREG PROPERTIES + * to be generated from linux sysreg + * + * Copyright (c) Red Hat, Inc. 2024 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "cpu-custom.h" + +ARM64SysReg arm64_id_regs[NUM_ID_IDX]; + +void initialize_cpu_sysreg_properties(void) +{ + memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_IDX); + /* CTR_EL0 */ + ARM64SysReg *CTR_EL0 =3D arm64_sysreg_get(CTR_EL0_IDX); + CTR_EL0->name =3D "CTR_EL0"; + arm64_sysreg_add_field(CTR_EL0, "TminLine", 32, 37); + arm64_sysreg_add_field(CTR_EL0, "DIC", 29, 29); + arm64_sysreg_add_field(CTR_EL0, "IDC", 28, 28); + arm64_sysreg_add_field(CTR_EL0, "CWG", 24, 27); + arm64_sysreg_add_field(CTR_EL0, "ERG", 20, 23); + arm64_sysreg_add_field(CTR_EL0, "DminLine", 16, 19); + arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15); + arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3); +} + diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9769401a8585..839442745ea4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -35,6 +35,7 @@ #include "internals.h" #include "cpu-features.h" #include "cpregs.h" +#include "cpu-custom.h" =20 /* convert between _IDX and SYS_ */ #define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ @@ -891,6 +892,7 @@ static void aarch64_cpu_register_types(void) { size_t i; =20 + initialize_cpu_sysreg_properties(); type_register_static(&aarch64_cpu_type_info); =20 for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { diff --git a/target/arm/meson.build b/target/arm/meson.build index 3065081d241d..1c97c1ef7580 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -14,6 +14,7 @@ arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstu= b.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', 'gdbstub64.c', + 'cpu-sysreg-properties.c', )) =20 arm_system_ss =3D ss.source_set() --=20 2.49.0 From nobody Fri Dec 19 04:27:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1744648914; cv=none; d=zohomail.com; s=zohoarc; b=jqkkuWVfeP/Tje9oJkBwV6qbBVGlOxkwG3MCsSK2XuX4DKErP42uZnGuBi9guTVYFgIE2oEo+vJzks+0F+r6+ClG5x2IszOpuyRl4PqvQuL4meIOaOZyRkgQk9nozy4DJDiJ/ka6IhF1+KEmQb5yv93YFIYPGuB1FH2NdEkBUe4= ARC-Message-Signature: i=1; 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charset="utf-8" From: Eric Auger Introduce a script that automates the generation of system register properties definitions from a given linux source tree arch/arm64/tools/sysreg. Invocation of ./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE in scripts directory additionally generates target/arm/cpu-sysreg-properties.c containing definitions for feature ID registers. update-aarch64-sysreg-code.sh additionally calls gen-cpu-sysreg-properties.awk which is inherited from kernel arch/arm64/tools/gen-sysreg.awk. All credits to Mark Rutland the original author of this script. [CH: split off from original patch adding both sysreg definitions and properties] Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- scripts/gen-cpu-sysreg-properties.awk | 325 ++++++++++++++++++++++++++ scripts/update-aarch64-sysreg-code.sh | 5 +- 2 files changed, 329 insertions(+), 1 deletion(-) create mode 100755 scripts/gen-cpu-sysreg-properties.awk diff --git a/scripts/gen-cpu-sysreg-properties.awk b/scripts/gen-cpu-sysreg= -properties.awk new file mode 100755 index 000000000000..76c37938b168 --- /dev/null +++ b/scripts/gen-cpu-sysreg-properties.awk @@ -0,0 +1,325 @@ +#!/bin/awk -f +# SPDX-License-Identifier: GPL-2.0 +# gen-cpu-sysreg-properties.awk: arm64 sysreg header generator +# +# Usage: awk -f gen-cpu-sysreg-properties.awk $LINUX_PATH/arch/arm64/tools= /sysreg + +function block_current() { + return __current_block[__current_block_depth]; +} + +# Log an error and terminate +function fatal(msg) { + print "Error at " NR ": " msg > "/dev/stderr" + + printf "Current block nesting:" + + for (i =3D 0; i <=3D __current_block_depth; i++) { + printf " " __current_block[i] + } + printf "\n" + + exit 1 +} + +# Enter a new block, setting the active block to @block +function block_push(block) { + __current_block[++__current_block_depth] =3D block +} + +# Exit a block, setting the active block to the parent block +function block_pop() { + if (__current_block_depth =3D=3D 0) + fatal("error: block_pop() in root block") + + __current_block_depth--; +} + +# Sanity check the number of records for a field makes sense. If not, prod= uce +# an error and terminate. +function expect_fields(nf) { + if (NF !=3D nf) + fatal(NF " fields found where " nf " expected") +} + +# Print a CPP macro definition, padded with spaces so that the macro bodies +# line up in a column +function define(name, val) { + printf "%-56s%s\n", "#define " name, val +} + +# Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field +function define_field(reg, field, msb, lsb, idreg) { + if (idreg) + print " arm64_sysreg_add_field("reg", \""field"\", "lsb", "= msb");" +} + +# Print a field _SIGNED definition for a field +function define_field_sign(reg, field, sign, idreg) { + if (idreg) + print " arm64_sysreg_add_field("reg", \""field"\", "lsb", "= msb");" +} + +# Parse a "[:]" string into the global variables @msb and @lsb +function parse_bitdef(reg, field, bitdef, _bits) +{ + if (bitdef ~ /^[0-9]+$/) { + msb =3D bitdef + lsb =3D bitdef + } else if (split(bitdef, _bits, ":") =3D=3D 2) { + msb =3D _bits[1] + lsb =3D _bits[2] + } else { + fatal("invalid bit-range definition '" bitdef "'") + } + + + if (msb !=3D next_bit) + fatal(reg "." field " starts at " msb " not " next_bit) + if (63 < msb || msb < 0) + fatal(reg "." field " invalid high bit in '" bitdef "'") + if (63 < lsb || lsb < 0) + fatal(reg "." field " invalid low bit in '" bitdef "'") + if (msb < lsb) + fatal(reg "." field " invalid bit-range '" bitdef "'") + if (low > high) + fatal(reg "." field " has invalid range " high "-" low) + + next_bit =3D lsb - 1 +} + +BEGIN { + print "#include \"cpu-custom.h\"" + print "" + print "ARM64SysReg arm64_id_regs[NUM_ID_IDX];" + print "" + print "void initialize_cpu_sysreg_properties(void)" + print "{" + print " memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_I= DX);" + print "" + + __current_block_depth =3D 0 + __current_block[__current_block_depth] =3D "Root" +} + +END { + if (__current_block_depth !=3D 0) + fatal("Missing terminator for " block_current() " block") + + print "}" +} + +# skip blank lines and comment lines +/^$/ { next } +/^[\t ]*#/ { next } + +/^SysregFields/ && block_current() =3D=3D "Root" { + block_push("SysregFields") + + expect_fields(2) + + reg =3D $2 + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + + next_bit =3D 63 + + next +} + +/^EndSysregFields/ && block_current() =3D=3D "SysregFields" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + reg =3D null + res0 =3D null + res1 =3D null + unkn =3D null + + block_pop() + next +} + +/^Sysreg/ && block_current() =3D=3D "Root" { + block_push("Sysreg") + + expect_fields(7) + + reg =3D $2 + op0 =3D $3 + op1 =3D $4 + crn =3D $5 + crm =3D $6 + op2 =3D $7 + + res0 =3D "UL(0)" + res1 =3D "UL(0)" + unkn =3D "UL(0)" + + if (op0 =3D=3D 3 && (op1>=3D0 && op1<=3D3) && crn=3D=3D0 && (crm>=3D0 && = crm<=3D7) && (op2>=3D0 && op2<=3D7)) { + idreg =3D 1 + } else { + idreg =3D 0 + } + + if (idreg =3D=3D 1) { + print " /* "reg" */" + print " ARM64SysReg *"reg" =3D arm64_sysreg_get("reg"_IDX);" + print " "reg"->name =3D \""reg"\";" + } + + next_bit =3D 63 + + next +} + +/^EndSysreg/ && block_current() =3D=3D "Sysreg" { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + reg =3D null + op0 =3D null + op1 =3D null + crn =3D null + crm =3D null + op2 =3D null + res0 =3D null + res1 =3D null + unkn =3D null + + if (idreg=3D=3D1) + print "" + block_pop() + next +} + +# Currently this is effectivey a comment, in future we may want to emit +# defines for the fields. +(/^Fields/ || /^Mapping/) && block_current() =3D=3D "Sysreg" { + expect_fields(2) + + if (next_bit !=3D 63) + fatal("Some fields already defined for " reg) + + print "/* For " reg " fields see " $2 " */" + print "" + + next_bit =3D 0 + res0 =3D null + res1 =3D null + unkn =3D null + + next +} + + +/^Res0/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + expect_fields(2) + parse_bitdef(reg, "RES0", $2) + field =3D "RES0_" msb "_" lsb + + res0 =3D res0 " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + +/^Res1/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + expect_fields(2) + parse_bitdef(reg, "RES1", $2) + field =3D "RES1_" msb "_" lsb + + res1 =3D res1 " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + +/^Unkn/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + expect_fields(2) + parse_bitdef(reg, "UNKN", $2) + field =3D "UNKN_" msb "_" lsb + + unkn =3D unkn " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + +/^Field/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sy= sregFields") { + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + + define_field(reg, field, msb, lsb, idreg) + + next +} + +/^Raz/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sysr= egFields") { + expect_fields(2) + parse_bitdef(reg, field, $2) + + next +} + +/^SignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb, idreg) + define_field_sign(reg, field, "true", idreg) + + next +} + +/^UnsignedEnum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D= =3D "SysregFields") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb, idreg) + #define_field_sign(reg, field, "false", idreg) + + next +} + +/^Enum/ && (block_current() =3D=3D "Sysreg" || block_current() =3D=3D "Sys= regFields") { + block_push("Enum") + + expect_fields(3) + field =3D $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb, idreg) + + next +} + +/^EndEnum/ && block_current() =3D=3D "Enum" { + + field =3D null + msb =3D null + lsb =3D null + + block_pop() + next +} + +/0b[01]+/ && block_current() =3D=3D "Enum" { + expect_fields(2) + val =3D $1 + name =3D $2 + + next +} + +# Any lines not handled by previous rules are unexpected +{ + fatal("unhandled statement") +} diff --git a/scripts/update-aarch64-sysreg-code.sh b/scripts/update-aarch64= -sysreg-code.sh index 721f41a9a516..a11637091815 100755 --- a/scripts/update-aarch64-sysreg-code.sh +++ b/scripts/update-aarch64-sysreg-code.sh @@ -1,6 +1,6 @@ #!/bin/sh -e # -# Update target/arm/cpu-sysregs.h +# Update target/arm/cpu-sysreg-properties.c and target/arm/cpu-sysregs.h # from a linux source tree (arch/arm64/tools/sysreg) # # Copyright Red Hat, Inc. 2024 @@ -23,3 +23,6 @@ fi =20 awk -f gen-cpu-sysregs-header.awk \ $linux/arch/arm64/tools/sysreg > ../target/arm/cpu-sysregs.h.inc + +awk -f gen-cpu-sysreg-properties.awk \ + $linux/arch/arm64/tools/sysreg > ../target/arm/cpu-sysreg-propertie= s.c --=20 2.49.0 From nobody Fri Dec 19 04:27:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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Signed-off-by: Cornelia Huck --- target/arm/cpu-sysreg-properties.c | 716 ++++++++++++++++++++++++++++- 1 file changed, 694 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-pro= perties.c index 8b7ef5badfb9..05eb40487313 100644 --- a/target/arm/cpu-sysreg-properties.c +++ b/target/arm/cpu-sysreg-properties.c @@ -1,24 +1,3 @@ -/* - * QEMU ARM CPU SYSREG PROPERTIES - * to be generated from linux sysreg - * - * Copyright (c) Red Hat, Inc. 2024 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see - * - */ - #include "cpu-custom.h" =20 ARM64SysReg arm64_id_regs[NUM_ID_IDX]; @@ -26,6 +5,627 @@ ARM64SysReg arm64_id_regs[NUM_ID_IDX]; void initialize_cpu_sysreg_properties(void) { memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_IDX); + + /* ID_PFR0_EL1 */ + ARM64SysReg *ID_PFR0_EL1 =3D arm64_sysreg_get(ID_PFR0_EL1_IDX); + ID_PFR0_EL1->name =3D "ID_PFR0_EL1"; + arm64_sysreg_add_field(ID_PFR0_EL1, "RAS", 28, 31); + arm64_sysreg_add_field(ID_PFR0_EL1, "DIT", 24, 27); + arm64_sysreg_add_field(ID_PFR0_EL1, "AMU", 20, 23); + arm64_sysreg_add_field(ID_PFR0_EL1, "CSV2", 16, 19); + arm64_sysreg_add_field(ID_PFR0_EL1, "State3", 12, 15); + arm64_sysreg_add_field(ID_PFR0_EL1, "State2", 8, 11); + arm64_sysreg_add_field(ID_PFR0_EL1, "State1", 4, 7); + arm64_sysreg_add_field(ID_PFR0_EL1, "State0", 0, 3); + + /* ID_PFR1_EL1 */ + ARM64SysReg *ID_PFR1_EL1 =3D arm64_sysreg_get(ID_PFR1_EL1_IDX); + ID_PFR1_EL1->name =3D "ID_PFR1_EL1"; + arm64_sysreg_add_field(ID_PFR1_EL1, "GIC", 28, 31); + arm64_sysreg_add_field(ID_PFR1_EL1, "Virt_frac", 24, 27); + arm64_sysreg_add_field(ID_PFR1_EL1, "Sec_frac", 20, 23); + arm64_sysreg_add_field(ID_PFR1_EL1, "GenTimer", 16, 19); + arm64_sysreg_add_field(ID_PFR1_EL1, "Virtualization", 12, 15); + arm64_sysreg_add_field(ID_PFR1_EL1, "MProgMod", 8, 11); + arm64_sysreg_add_field(ID_PFR1_EL1, "Security", 4, 7); + arm64_sysreg_add_field(ID_PFR1_EL1, "ProgMod", 0, 3); + + /* ID_DFR0_EL1 */ + ARM64SysReg *ID_DFR0_EL1 =3D arm64_sysreg_get(ID_DFR0_EL1_IDX); + ID_DFR0_EL1->name =3D "ID_DFR0_EL1"; + arm64_sysreg_add_field(ID_DFR0_EL1, "TraceFilt", 28, 31); + arm64_sysreg_add_field(ID_DFR0_EL1, "PerfMon", 24, 27); + arm64_sysreg_add_field(ID_DFR0_EL1, "MProfDbg", 20, 23); + arm64_sysreg_add_field(ID_DFR0_EL1, "MMapTrc", 16, 19); + arm64_sysreg_add_field(ID_DFR0_EL1, "CopTrc", 12, 15); + arm64_sysreg_add_field(ID_DFR0_EL1, "MMapDbg", 8, 11); + arm64_sysreg_add_field(ID_DFR0_EL1, "CopSDbg", 4, 7); + arm64_sysreg_add_field(ID_DFR0_EL1, "CopDbg", 0, 3); + + /* ID_AFR0_EL1 */ + ARM64SysReg *ID_AFR0_EL1 =3D arm64_sysreg_get(ID_AFR0_EL1_IDX); + ID_AFR0_EL1->name =3D "ID_AFR0_EL1"; + arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF3", 12, 15); + arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF2", 8, 11); + arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF1", 4, 7); + arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF0", 0, 3); + + /* ID_MMFR0_EL1 */ + ARM64SysReg *ID_MMFR0_EL1 =3D arm64_sysreg_get(ID_MMFR0_EL1_IDX); + ID_MMFR0_EL1->name =3D "ID_MMFR0_EL1"; + arm64_sysreg_add_field(ID_MMFR0_EL1, "InnerShr", 28, 31); + arm64_sysreg_add_field(ID_MMFR0_EL1, "FCSE", 24, 27); + arm64_sysreg_add_field(ID_MMFR0_EL1, "AuxReg", 20, 23); + arm64_sysreg_add_field(ID_MMFR0_EL1, "TCM", 16, 19); + arm64_sysreg_add_field(ID_MMFR0_EL1, "ShareLvl", 12, 15); + arm64_sysreg_add_field(ID_MMFR0_EL1, "OuterShr", 8, 11); + arm64_sysreg_add_field(ID_MMFR0_EL1, "PMSA", 4, 7); + arm64_sysreg_add_field(ID_MMFR0_EL1, "VMSA", 0, 3); + + /* ID_MMFR1_EL1 */ + ARM64SysReg *ID_MMFR1_EL1 =3D arm64_sysreg_get(ID_MMFR1_EL1_IDX); + ID_MMFR1_EL1->name =3D "ID_MMFR1_EL1"; + arm64_sysreg_add_field(ID_MMFR1_EL1, "BPred", 28, 31); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1TstCln", 24, 27); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1Uni", 20, 23); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1Hvd", 16, 19); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1UniSW", 12, 15); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1HvdSW", 8, 11); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1UniVA", 4, 7); + arm64_sysreg_add_field(ID_MMFR1_EL1, "L1HvdVA", 0, 3); + + /* ID_MMFR2_EL1 */ + ARM64SysReg *ID_MMFR2_EL1 =3D arm64_sysreg_get(ID_MMFR2_EL1_IDX); + ID_MMFR2_EL1->name =3D "ID_MMFR2_EL1"; + arm64_sysreg_add_field(ID_MMFR2_EL1, "HWAccFlg", 28, 31); + arm64_sysreg_add_field(ID_MMFR2_EL1, "WFIStall", 24, 27); + arm64_sysreg_add_field(ID_MMFR2_EL1, "MemBarr", 20, 23); + arm64_sysreg_add_field(ID_MMFR2_EL1, "UniTLB", 16, 19); + arm64_sysreg_add_field(ID_MMFR2_EL1, "HvdTLB", 12, 15); + arm64_sysreg_add_field(ID_MMFR2_EL1, "L1HvdRng", 8, 11); + arm64_sysreg_add_field(ID_MMFR2_EL1, "L1HvdBG", 4, 7); + arm64_sysreg_add_field(ID_MMFR2_EL1, "L1HvdFG", 0, 3); + + /* ID_MMFR3_EL1 */ + ARM64SysReg *ID_MMFR3_EL1 =3D arm64_sysreg_get(ID_MMFR3_EL1_IDX); + ID_MMFR3_EL1->name =3D "ID_MMFR3_EL1"; + arm64_sysreg_add_field(ID_MMFR3_EL1, "Supersec", 28, 31); + arm64_sysreg_add_field(ID_MMFR3_EL1, "CMemSz", 24, 27); + arm64_sysreg_add_field(ID_MMFR3_EL1, "CohWalk", 20, 23); + arm64_sysreg_add_field(ID_MMFR3_EL1, "PAN", 16, 19); + arm64_sysreg_add_field(ID_MMFR3_EL1, "MaintBcst", 12, 15); + arm64_sysreg_add_field(ID_MMFR3_EL1, "BPMaint", 8, 11); + arm64_sysreg_add_field(ID_MMFR3_EL1, "CMaintSW", 4, 7); + arm64_sysreg_add_field(ID_MMFR3_EL1, "CMaintVA", 0, 3); + + /* ID_ISAR0_EL1 */ + ARM64SysReg *ID_ISAR0_EL1 =3D arm64_sysreg_get(ID_ISAR0_EL1_IDX); + ID_ISAR0_EL1->name =3D "ID_ISAR0_EL1"; + arm64_sysreg_add_field(ID_ISAR0_EL1, "Divide", 24, 27); + arm64_sysreg_add_field(ID_ISAR0_EL1, "Debug", 20, 23); + arm64_sysreg_add_field(ID_ISAR0_EL1, "Coproc", 16, 19); + arm64_sysreg_add_field(ID_ISAR0_EL1, "CmpBranch", 12, 15); + arm64_sysreg_add_field(ID_ISAR0_EL1, "BitField", 8, 11); + arm64_sysreg_add_field(ID_ISAR0_EL1, "BitCount", 4, 7); + arm64_sysreg_add_field(ID_ISAR0_EL1, "Swap", 0, 3); + + /* ID_ISAR1_EL1 */ + ARM64SysReg *ID_ISAR1_EL1 =3D arm64_sysreg_get(ID_ISAR1_EL1_IDX); + ID_ISAR1_EL1->name =3D "ID_ISAR1_EL1"; + arm64_sysreg_add_field(ID_ISAR1_EL1, "Jazelle", 28, 31); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Interwork", 24, 27); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Immediate", 20, 23); + arm64_sysreg_add_field(ID_ISAR1_EL1, "IfThen", 16, 19); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Extend", 12, 15); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Except_AR", 8, 11); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Except", 4, 7); + arm64_sysreg_add_field(ID_ISAR1_EL1, "Endian", 0, 3); + + /* ID_ISAR2_EL1 */ + ARM64SysReg *ID_ISAR2_EL1 =3D arm64_sysreg_get(ID_ISAR2_EL1_IDX); + ID_ISAR2_EL1->name =3D "ID_ISAR2_EL1"; + arm64_sysreg_add_field(ID_ISAR2_EL1, "Reversal", 28, 31); + arm64_sysreg_add_field(ID_ISAR2_EL1, "PSR_AR", 24, 27); + arm64_sysreg_add_field(ID_ISAR2_EL1, "MultU", 20, 23); + arm64_sysreg_add_field(ID_ISAR2_EL1, "MultS", 16, 19); + arm64_sysreg_add_field(ID_ISAR2_EL1, "Mult", 12, 15); + arm64_sysreg_add_field(ID_ISAR2_EL1, "MultiAccessInt", 8, 11); + arm64_sysreg_add_field(ID_ISAR2_EL1, "MemHint", 4, 7); + arm64_sysreg_add_field(ID_ISAR2_EL1, "LoadStore", 0, 3); + + /* ID_ISAR3_EL1 */ + ARM64SysReg *ID_ISAR3_EL1 =3D arm64_sysreg_get(ID_ISAR3_EL1_IDX); + ID_ISAR3_EL1->name =3D "ID_ISAR3_EL1"; + arm64_sysreg_add_field(ID_ISAR3_EL1, "T32EE", 28, 31); + arm64_sysreg_add_field(ID_ISAR3_EL1, "TrueNOP", 24, 27); + arm64_sysreg_add_field(ID_ISAR3_EL1, "T32Copy", 20, 23); + arm64_sysreg_add_field(ID_ISAR3_EL1, "TabBranch", 16, 19); + arm64_sysreg_add_field(ID_ISAR3_EL1, "SynchPrim", 12, 15); + arm64_sysreg_add_field(ID_ISAR3_EL1, "SVC", 8, 11); + arm64_sysreg_add_field(ID_ISAR3_EL1, "SIMD", 4, 7); + arm64_sysreg_add_field(ID_ISAR3_EL1, "Saturate", 0, 3); + + /* ID_ISAR4_EL1 */ + ARM64SysReg *ID_ISAR4_EL1 =3D arm64_sysreg_get(ID_ISAR4_EL1_IDX); + ID_ISAR4_EL1->name =3D "ID_ISAR4_EL1"; + arm64_sysreg_add_field(ID_ISAR4_EL1, "SWP_frac", 28, 31); + arm64_sysreg_add_field(ID_ISAR4_EL1, "PSR_M", 24, 27); + arm64_sysreg_add_field(ID_ISAR4_EL1, "SynchPrim_frac", 20, 23); + arm64_sysreg_add_field(ID_ISAR4_EL1, "Barrier", 16, 19); + arm64_sysreg_add_field(ID_ISAR4_EL1, "SMC", 12, 15); + arm64_sysreg_add_field(ID_ISAR4_EL1, "Writeback", 8, 11); + arm64_sysreg_add_field(ID_ISAR4_EL1, "WithShifts", 4, 7); + arm64_sysreg_add_field(ID_ISAR4_EL1, "Unpriv", 0, 3); + + /* ID_ISAR5_EL1 */ + ARM64SysReg *ID_ISAR5_EL1 =3D arm64_sysreg_get(ID_ISAR5_EL1_IDX); + ID_ISAR5_EL1->name =3D "ID_ISAR5_EL1"; + arm64_sysreg_add_field(ID_ISAR5_EL1, "VCMA", 28, 31); + arm64_sysreg_add_field(ID_ISAR5_EL1, "RDM", 24, 27); + arm64_sysreg_add_field(ID_ISAR5_EL1, "CRC32", 16, 19); + arm64_sysreg_add_field(ID_ISAR5_EL1, "SHA2", 12, 15); + arm64_sysreg_add_field(ID_ISAR5_EL1, "SHA1", 8, 11); + arm64_sysreg_add_field(ID_ISAR5_EL1, "AES", 4, 7); + arm64_sysreg_add_field(ID_ISAR5_EL1, "SEVL", 0, 3); + + /* ID_ISAR6_EL1 */ + ARM64SysReg *ID_ISAR6_EL1 =3D arm64_sysreg_get(ID_ISAR6_EL1_IDX); + ID_ISAR6_EL1->name =3D "ID_ISAR6_EL1"; + arm64_sysreg_add_field(ID_ISAR6_EL1, "I8MM", 24, 27); + arm64_sysreg_add_field(ID_ISAR6_EL1, "BF16", 20, 23); + arm64_sysreg_add_field(ID_ISAR6_EL1, "SPECRES", 16, 19); + arm64_sysreg_add_field(ID_ISAR6_EL1, "SB", 12, 15); + arm64_sysreg_add_field(ID_ISAR6_EL1, "FHM", 8, 11); + arm64_sysreg_add_field(ID_ISAR6_EL1, "DP", 4, 7); + arm64_sysreg_add_field(ID_ISAR6_EL1, "JSCVT", 0, 3); + + /* ID_MMFR4_EL1 */ + ARM64SysReg *ID_MMFR4_EL1 =3D arm64_sysreg_get(ID_MMFR4_EL1_IDX); + ID_MMFR4_EL1->name =3D "ID_MMFR4_EL1"; + arm64_sysreg_add_field(ID_MMFR4_EL1, "EVT", 28, 31); + arm64_sysreg_add_field(ID_MMFR4_EL1, "CCIDX", 24, 27); + arm64_sysreg_add_field(ID_MMFR4_EL1, "LSM", 20, 23); + arm64_sysreg_add_field(ID_MMFR4_EL1, "HPDS", 16, 19); + arm64_sysreg_add_field(ID_MMFR4_EL1, "CnP", 12, 15); + arm64_sysreg_add_field(ID_MMFR4_EL1, "XNX", 8, 11); + arm64_sysreg_add_field(ID_MMFR4_EL1, "AC2", 4, 7); + arm64_sysreg_add_field(ID_MMFR4_EL1, "SpecSEI", 0, 3); + + /* MVFR0_EL1 */ + ARM64SysReg *MVFR0_EL1 =3D arm64_sysreg_get(MVFR0_EL1_IDX); + MVFR0_EL1->name =3D "MVFR0_EL1"; + arm64_sysreg_add_field(MVFR0_EL1, "FPRound", 28, 31); + arm64_sysreg_add_field(MVFR0_EL1, "FPShVec", 24, 27); + arm64_sysreg_add_field(MVFR0_EL1, "FPSqrt", 20, 23); + arm64_sysreg_add_field(MVFR0_EL1, "FPDivide", 16, 19); + arm64_sysreg_add_field(MVFR0_EL1, "FPTrap", 12, 15); + arm64_sysreg_add_field(MVFR0_EL1, "FPDP", 8, 11); + arm64_sysreg_add_field(MVFR0_EL1, "FPSP", 4, 7); + arm64_sysreg_add_field(MVFR0_EL1, "SIMDReg", 0, 3); + + /* MVFR1_EL1 */ + ARM64SysReg *MVFR1_EL1 =3D arm64_sysreg_get(MVFR1_EL1_IDX); + MVFR1_EL1->name =3D "MVFR1_EL1"; + arm64_sysreg_add_field(MVFR1_EL1, "SIMDFMAC", 28, 31); + arm64_sysreg_add_field(MVFR1_EL1, "FPHP", 24, 27); + arm64_sysreg_add_field(MVFR1_EL1, "SIMDHP", 20, 23); + arm64_sysreg_add_field(MVFR1_EL1, "SIMDSP", 16, 19); + arm64_sysreg_add_field(MVFR1_EL1, "SIMDInt", 12, 15); + arm64_sysreg_add_field(MVFR1_EL1, "SIMDLS", 8, 11); + arm64_sysreg_add_field(MVFR1_EL1, "FPDNaN", 4, 7); + arm64_sysreg_add_field(MVFR1_EL1, "FPFtZ", 0, 3); + + /* MVFR2_EL1 */ + ARM64SysReg *MVFR2_EL1 =3D arm64_sysreg_get(MVFR2_EL1_IDX); + MVFR2_EL1->name =3D "MVFR2_EL1"; + arm64_sysreg_add_field(MVFR2_EL1, "FPMisc", 4, 7); + arm64_sysreg_add_field(MVFR2_EL1, "SIMDMisc", 0, 3); + + /* ID_PFR2_EL1 */ + ARM64SysReg *ID_PFR2_EL1 =3D arm64_sysreg_get(ID_PFR2_EL1_IDX); + ID_PFR2_EL1->name =3D "ID_PFR2_EL1"; + arm64_sysreg_add_field(ID_PFR2_EL1, "RAS_frac", 8, 11); + arm64_sysreg_add_field(ID_PFR2_EL1, "SSBS", 4, 7); + arm64_sysreg_add_field(ID_PFR2_EL1, "CSV3", 0, 3); + + /* ID_DFR1_EL1 */ + ARM64SysReg *ID_DFR1_EL1 =3D arm64_sysreg_get(ID_DFR1_EL1_IDX); + ID_DFR1_EL1->name =3D "ID_DFR1_EL1"; + arm64_sysreg_add_field(ID_DFR1_EL1, "HPMN0", 4, 7); + arm64_sysreg_add_field(ID_DFR1_EL1, "MTPMU", 0, 3); + + /* ID_MMFR5_EL1 */ + ARM64SysReg *ID_MMFR5_EL1 =3D arm64_sysreg_get(ID_MMFR5_EL1_IDX); + ID_MMFR5_EL1->name =3D "ID_MMFR5_EL1"; + arm64_sysreg_add_field(ID_MMFR5_EL1, "nTLBPA", 4, 7); + arm64_sysreg_add_field(ID_MMFR5_EL1, "ETS", 0, 3); + + /* ID_AA64PFR0_EL1 */ + ARM64SysReg *ID_AA64PFR0_EL1 =3D arm64_sysreg_get(ID_AA64PFR0_EL1_IDX); + ID_AA64PFR0_EL1->name =3D "ID_AA64PFR0_EL1"; + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "CSV3", 60, 63); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "CSV2", 56, 59); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "RME", 52, 55); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "DIT", 48, 51); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "AMU", 44, 47); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "MPAM", 40, 43); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "SEL2", 36, 39); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "SVE", 32, 35); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "RAS", 28, 31); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "GIC", 24, 27); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "AdvSIMD", 20, 23); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "AdvSIMD", 20, 23); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "FP", 16, 19); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "FP", 16, 19); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL3", 12, 15); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL2", 8, 11); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL1", 4, 7); + arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL0", 0, 3); + + /* ID_AA64PFR1_EL1 */ + ARM64SysReg *ID_AA64PFR1_EL1 =3D arm64_sysreg_get(ID_AA64PFR1_EL1_IDX); + ID_AA64PFR1_EL1->name =3D "ID_AA64PFR1_EL1"; + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "PFAR", 60, 63); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "DF2", 56, 59); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MTEX", 52, 55); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "THE", 48, 51); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "GCS", 44, 47); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MTE_frac", 40, 43); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "NMI", 36, 39); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "CSV2_frac", 32, 35); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "RNDR_trap", 28, 31); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "SME", 24, 27); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MPAM_frac", 16, 19); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "RAS_frac", 12, 15); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MTE", 8, 11); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "SSBS", 4, 7); + arm64_sysreg_add_field(ID_AA64PFR1_EL1, "BT", 0, 3); + + /* ID_AA64PFR2_EL1 */ + ARM64SysReg *ID_AA64PFR2_EL1 =3D arm64_sysreg_get(ID_AA64PFR2_EL1_IDX); + ID_AA64PFR2_EL1->name =3D "ID_AA64PFR2_EL1"; + arm64_sysreg_add_field(ID_AA64PFR2_EL1, "FPMR", 32, 35); + arm64_sysreg_add_field(ID_AA64PFR2_EL1, "UINJ", 16, 19); + arm64_sysreg_add_field(ID_AA64PFR2_EL1, "MTEFAR", 8, 11); + arm64_sysreg_add_field(ID_AA64PFR2_EL1, "MTESTOREONLY", 4, 7); + arm64_sysreg_add_field(ID_AA64PFR2_EL1, "MTEPERM", 0, 3); + + /* ID_AA64ZFR0_EL1 */ + ARM64SysReg *ID_AA64ZFR0_EL1 =3D arm64_sysreg_get(ID_AA64ZFR0_EL1_IDX); + ID_AA64ZFR0_EL1->name =3D "ID_AA64ZFR0_EL1"; + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "F64MM", 56, 59); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "F32MM", 52, 55); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "F16MM", 48, 51); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "I8MM", 44, 47); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "SM4", 40, 43); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "SHA3", 32, 35); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "B16B16", 24, 27); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "BF16", 20, 23); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "BitPerm", 16, 19); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "EltPerm", 12, 15); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "AES", 4, 7); + arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "SVEver", 0, 3); + + /* ID_AA64SMFR0_EL1 */ + ARM64SysReg *ID_AA64SMFR0_EL1 =3D arm64_sysreg_get(ID_AA64SMFR0_EL1_ID= X); + ID_AA64SMFR0_EL1->name =3D "ID_AA64SMFR0_EL1"; + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "FA64", 63, 63); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "LUTv2", 60, 60); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SMEver", 56, 59); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "I16I64", 52, 55); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F64F64", 48, 48); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "I16I32", 44, 47); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "B16B16", 43, 43); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F16F16", 42, 42); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F8F16", 41, 41); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F8F32", 40, 40); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "I8I32", 36, 39); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F16F32", 35, 35); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "B16F32", 34, 34); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "BI32I32", 33, 33); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F32F32", 32, 32); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SF8FMA", 30, 30); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SF8DP4", 29, 29); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SF8DP2", 28, 28); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SBitPerm", 25, 25); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "AES", 24, 24); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SFEXPA", 23, 23); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "STMOP", 16, 16); + arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SMOP4", 0, 0); + + /* ID_AA64FPFR0_EL1 */ + ARM64SysReg *ID_AA64FPFR0_EL1 =3D arm64_sysreg_get(ID_AA64FPFR0_EL1_ID= X); + ID_AA64FPFR0_EL1->name =3D "ID_AA64FPFR0_EL1"; + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8CVT", 31, 31); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8FMA", 30, 30); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8DP4", 29, 29); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8DP2", 28, 28); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8MM8", 27, 27); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8MM4", 26, 26); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8E4M3", 1, 1); + arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8E5M2", 0, 0); + + /* ID_AA64DFR0_EL1 */ + ARM64SysReg *ID_AA64DFR0_EL1 =3D arm64_sysreg_get(ID_AA64DFR0_EL1_IDX); + ID_AA64DFR0_EL1->name =3D "ID_AA64DFR0_EL1"; + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "HPMN0", 60, 63); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "ExtTrcBuff", 56, 59); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "BRBE", 52, 55); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "MTPMU", 48, 51); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "MTPMU", 48, 51); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "TraceBuffer", 44, 47); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "TraceFilt", 40, 43); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "DoubleLock", 36, 39); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "PMSVer", 32, 35); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "CTX_CMPs", 28, 31); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "SEBEP", 24, 27); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "WRPs", 20, 23); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "PMSS", 16, 19); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "BRPs", 12, 15); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "PMUVer", 8, 11); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "TraceVer", 4, 7); + arm64_sysreg_add_field(ID_AA64DFR0_EL1, "DebugVer", 0, 3); + + /* ID_AA64DFR1_EL1 */ + ARM64SysReg *ID_AA64DFR1_EL1 =3D arm64_sysreg_get(ID_AA64DFR1_EL1_IDX); + ID_AA64DFR1_EL1->name =3D "ID_AA64DFR1_EL1"; + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "ABL_CMPs", 56, 63); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "DPFZS", 52, 55); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "EBEP", 48, 51); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "ITE", 44, 47); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "ABLE", 40, 43); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "PMICNTR", 36, 39); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "SPMU", 32, 35); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "CTX_CMPs", 24, 31); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "WRPs", 16, 23); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "BRPs", 8, 15); + arm64_sysreg_add_field(ID_AA64DFR1_EL1, "SYSPMUID", 0, 7); + + /* ID_AA64DFR2_EL1 */ + ARM64SysReg *ID_AA64DFR2_EL1 =3D arm64_sysreg_get(ID_AA64DFR2_EL1_IDX); + ID_AA64DFR2_EL1->name =3D "ID_AA64DFR2_EL1"; + arm64_sysreg_add_field(ID_AA64DFR2_EL1, "TRBE_EXC", 24, 27); + arm64_sysreg_add_field(ID_AA64DFR2_EL1, "SPE_nVM", 20, 23); + arm64_sysreg_add_field(ID_AA64DFR2_EL1, "SPE_EXC", 16, 19); + arm64_sysreg_add_field(ID_AA64DFR2_EL1, "BWE", 4, 7); + arm64_sysreg_add_field(ID_AA64DFR2_EL1, "STEP", 0, 3); + + /* ID_AA64AFR0_EL1 */ + ARM64SysReg *ID_AA64AFR0_EL1 =3D arm64_sysreg_get(ID_AA64AFR0_EL1_IDX); + ID_AA64AFR0_EL1->name =3D "ID_AA64AFR0_EL1"; + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF7", 28, 31); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF6", 24, 27); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF5", 20, 23); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF4", 16, 19); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF3", 12, 15); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF2", 8, 11); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF1", 4, 7); + arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF0", 0, 3); + + /* ID_AA64AFR1_EL1 */ + ARM64SysReg *ID_AA64AFR1_EL1 =3D arm64_sysreg_get(ID_AA64AFR1_EL1_IDX); + ID_AA64AFR1_EL1->name =3D "ID_AA64AFR1_EL1"; + + /* ID_AA64ISAR0_EL1 */ + ARM64SysReg *ID_AA64ISAR0_EL1 =3D arm64_sysreg_get(ID_AA64ISAR0_EL1_ID= X); + ID_AA64ISAR0_EL1->name =3D "ID_AA64ISAR0_EL1"; + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "RNDR", 60, 63); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "TLB", 56, 59); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "TS", 52, 55); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "FHM", 48, 51); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "DP", 44, 47); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SM4", 40, 43); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SM3", 36, 39); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SHA3", 32, 35); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "RDM", 28, 31); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "TME", 24, 27); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "ATOMIC", 20, 23); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "CRC32", 16, 19); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SHA2", 12, 15); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SHA1", 8, 11); + arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "AES", 4, 7); + + /* ID_AA64ISAR1_EL1 */ + ARM64SysReg *ID_AA64ISAR1_EL1 =3D arm64_sysreg_get(ID_AA64ISAR1_EL1_ID= X); + ID_AA64ISAR1_EL1->name =3D "ID_AA64ISAR1_EL1"; + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "LS64", 60, 63); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "XS", 56, 59); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "I8MM", 52, 55); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "DGH", 48, 51); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "BF16", 44, 47); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "SPECRES", 40, 43); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "SB", 36, 39); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "FRINTTS", 32, 35); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "GPI", 28, 31); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "GPA", 24, 27); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "LRCPC", 20, 23); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "FCMA", 16, 19); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "JSCVT", 12, 15); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "API", 8, 11); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "APA", 4, 7); + arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "DPB", 0, 3); + + /* ID_AA64ISAR2_EL1 */ + ARM64SysReg *ID_AA64ISAR2_EL1 =3D arm64_sysreg_get(ID_AA64ISAR2_EL1_ID= X); + ID_AA64ISAR2_EL1->name =3D "ID_AA64ISAR2_EL1"; + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "ATS1A", 60, 63); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "LUT", 56, 59); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "CSSC", 52, 55); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "RPRFM", 48, 51); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "PCDPHINT", 44, 47); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "PRFMSLC", 40, 43); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "SYSINSTR_128", 36, 39); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "SYSREG_128", 32, 35); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "CLRBHB", 28, 31); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "PAC_frac", 24, 27); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "BC", 20, 23); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "MOPS", 16, 19); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "APA3", 12, 15); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "GPA3", 8, 11); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "RPRES", 4, 7); + arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "WFxT", 0, 3); + + /* ID_AA64ISAR3_EL1 */ + ARM64SysReg *ID_AA64ISAR3_EL1 =3D arm64_sysreg_get(ID_AA64ISAR3_EL1_ID= X); + ID_AA64ISAR3_EL1->name =3D "ID_AA64ISAR3_EL1"; + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "FPRCVT", 28, 31); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "LSUI", 24, 27); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "OCCMO", 20, 23); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "LSFE", 16, 19); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "PACM", 12, 15); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "TLBIW", 8, 11); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "FAMINMAX", 4, 7); + arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "CPA", 0, 3); + + /* ID_AA64MMFR0_EL1 */ + ARM64SysReg *ID_AA64MMFR0_EL1 =3D arm64_sysreg_get(ID_AA64MMFR0_EL1_ID= X); + ID_AA64MMFR0_EL1->name =3D "ID_AA64MMFR0_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "ECV", 60, 63); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "FGT", 56, 59); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "EXS", 44, 47); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN4_2", 40, 43); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN64_2", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN16_2", 32, 35); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN4", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN4", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN64", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN64", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN16", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "BIGENDEL0", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "SNSMEM", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "BIGEND", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "ASIDBITS", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "PARANGE", 0, 3); + + /* ID_AA64MMFR1_EL1 */ + ARM64SysReg *ID_AA64MMFR1_EL1 =3D arm64_sysreg_get(ID_AA64MMFR1_EL1_ID= X); + ID_AA64MMFR1_EL1->name =3D "ID_AA64MMFR1_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "ECBHB", 60, 63); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "CMOW", 56, 59); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "TIDCP1", 52, 55); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "nTLBPA", 48, 51); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "AFP", 44, 47); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "HCX", 40, 43); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "ETS", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "TWED", 32, 35); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "XNX", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "SpecSEI", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "PAN", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "LO", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "HPDS", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "VH", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "VMIDBits", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "HAFDBS", 0, 3); + + /* ID_AA64MMFR2_EL1 */ + ARM64SysReg *ID_AA64MMFR2_EL1 =3D arm64_sysreg_get(ID_AA64MMFR2_EL1_ID= X); + ID_AA64MMFR2_EL1->name =3D "ID_AA64MMFR2_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "E0PD", 60, 63); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "EVT", 56, 59); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "BBM", 52, 55); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "TTL", 48, 51); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "FWB", 40, 43); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "IDS", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "AT", 32, 35); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "ST", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "NV", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "CCIDX", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "VARange", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "IESB", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "LSM", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "UAO", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "CnP", 0, 3); + + /* ID_AA64MMFR3_EL1 */ + ARM64SysReg *ID_AA64MMFR3_EL1 =3D arm64_sysreg_get(ID_AA64MMFR3_EL1_ID= X); + ID_AA64MMFR3_EL1->name =3D "ID_AA64MMFR3_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "Spec_FPACC", 60, 63); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "ADERR", 56, 59); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "SDERR", 52, 55); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "ANERR", 44, 47); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "SNERR", 40, 43); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "D128_2", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "D128", 32, 35); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "MEC", 28, 31); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "AIE", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S2POE", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S1POE", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S2PIE", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S1PIE", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "SCTLRX", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "TCRX", 0, 3); + + /* ID_AA64MMFR4_EL1 */ + ARM64SysReg *ID_AA64MMFR4_EL1 =3D arm64_sysreg_get(ID_AA64MMFR4_EL1_ID= X); + ID_AA64MMFR4_EL1->name =3D "ID_AA64MMFR4_EL1"; + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "E3DSE", 36, 39); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "E2H0", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "E2H0", 24, 27); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "NV_frac", 20, 23); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "FGWTE3", 16, 19); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "HACDBS", 12, 15); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "ASID2", 8, 11); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "EIESB", 4, 7); + arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "EIESB", 4, 7); + +/* For ZCR_EL1 fields see ZCR_ELx */ + +/* For SMCR_EL1 fields see SMCR_ELx */ + +/* For GCSCR_EL1 fields see GCSCR_ELx */ + +/* For GCSPR_EL1 fields see GCSPR_ELx */ + +/* For CONTEXTIDR_EL1 fields see CONTEXTIDR_ELx */ + + /* CCSIDR_EL1 */ + ARM64SysReg *CCSIDR_EL1 =3D arm64_sysreg_get(CCSIDR_EL1_IDX); + CCSIDR_EL1->name =3D "CCSIDR_EL1"; + arm64_sysreg_add_field(CCSIDR_EL1, "NumSets", 13, 27); + arm64_sysreg_add_field(CCSIDR_EL1, "Associativity", 3, 12); + arm64_sysreg_add_field(CCSIDR_EL1, "LineSize", 0, 2); + + /* CLIDR_EL1 */ + ARM64SysReg *CLIDR_EL1 =3D arm64_sysreg_get(CLIDR_EL1_IDX); + CLIDR_EL1->name =3D "CLIDR_EL1"; + arm64_sysreg_add_field(CLIDR_EL1, "Ttypen", 33, 46); + arm64_sysreg_add_field(CLIDR_EL1, "ICB", 30, 32); + arm64_sysreg_add_field(CLIDR_EL1, "LoUU", 27, 29); + arm64_sysreg_add_field(CLIDR_EL1, "LoC", 24, 26); + arm64_sysreg_add_field(CLIDR_EL1, "LoUIS", 21, 23); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype7", 18, 20); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype6", 15, 17); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype5", 12, 14); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype4", 9, 11); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype3", 6, 8); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype2", 3, 5); + arm64_sysreg_add_field(CLIDR_EL1, "Ctype1", 0, 2); + + /* CCSIDR2_EL1 */ + ARM64SysReg *CCSIDR2_EL1 =3D arm64_sysreg_get(CCSIDR2_EL1_IDX); + CCSIDR2_EL1->name =3D "CCSIDR2_EL1"; + arm64_sysreg_add_field(CCSIDR2_EL1, "NumSets", 0, 23); + + /* GMID_EL1 */ + ARM64SysReg *GMID_EL1 =3D arm64_sysreg_get(GMID_EL1_IDX); + GMID_EL1->name =3D "GMID_EL1"; + arm64_sysreg_add_field(GMID_EL1, "BS", 0, 3); + + /* SMIDR_EL1 */ + ARM64SysReg *SMIDR_EL1 =3D arm64_sysreg_get(SMIDR_EL1_IDX); + SMIDR_EL1->name =3D "SMIDR_EL1"; + arm64_sysreg_add_field(SMIDR_EL1, "IMPLEMENTER", 24, 31); + arm64_sysreg_add_field(SMIDR_EL1, "REVISION", 16, 23); + arm64_sysreg_add_field(SMIDR_EL1, "SMPS", 15, 15); + arm64_sysreg_add_field(SMIDR_EL1, "AFFINITY", 0, 11); + + /* CSSELR_EL1 */ + ARM64SysReg *CSSELR_EL1 =3D arm64_sysreg_get(CSSELR_EL1_IDX); + CSSELR_EL1->name =3D "CSSELR_EL1"; + arm64_sysreg_add_field(CSSELR_EL1, "TnD", 4, 4); + arm64_sysreg_add_field(CSSELR_EL1, "Level", 1, 3); + arm64_sysreg_add_field(CSSELR_EL1, "InD", 0, 0); + /* CTR_EL0 */ ARM64SysReg *CTR_EL0 =3D arm64_sysreg_get(CTR_EL0_IDX); CTR_EL0->name =3D "CTR_EL0"; @@ -37,5 +637,77 @@ void initialize_cpu_sysreg_properties(void) arm64_sysreg_add_field(CTR_EL0, "DminLine", 16, 19); arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15); arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3); -} =20 + /* DCZID_EL0 */ + ARM64SysReg *DCZID_EL0 =3D arm64_sysreg_get(DCZID_EL0_IDX); + DCZID_EL0->name =3D "DCZID_EL0"; + arm64_sysreg_add_field(DCZID_EL0, "DZP", 4, 4); + arm64_sysreg_add_field(DCZID_EL0, "BS", 0, 3); + +/* For GCSPR_EL0 fields see GCSPR_ELx */ + +/* For HFGRTR_EL2 fields see HFGxTR_EL2 */ + +/* For HFGWTR_EL2 fields see HFGxTR_EL2 */ + +/* For ZCR_EL2 fields see ZCR_ELx */ + +/* For SMCR_EL2 fields see SMCR_ELx */ + +/* For GCSCR_EL2 fields see GCSCR_ELx */ + +/* For GCSPR_EL2 fields see GCSPR_ELx */ + +/* For CONTEXTIDR_EL2 fields see CONTEXTIDR_ELx */ + +/* For CPACR_EL12 fields see CPACR_EL1 */ + +/* For ZCR_EL12 fields see ZCR_EL1 */ + +/* For TRFCR_EL12 fields see TRFCR_EL1 */ + +/* For SMCR_EL12 fields see SMCR_EL1 */ + +/* For GCSCR_EL12 fields see GCSCR_EL1 */ + +/* For GCSPR_EL12 fields see GCSPR_EL1 */ + +/* For MPAM1_EL12 fields see MPAM1_ELx */ + +/* For CONTEXTIDR_EL12 fields see CONTEXTIDR_EL1 */ + +/* For TTBR0_EL1 fields see TTBRx_EL1 */ + +/* For TTBR1_EL1 fields see TTBRx_EL1 */ + +/* For TCR2_EL12 fields see TCR2_EL1 */ + +/* For MAIR2_EL1 fields see MAIR2_ELx */ + +/* For MAIR2_EL2 fields see MAIR2_ELx */ + +/* For PIRE0_EL1 fields see PIRx_ELx */ + +/* For PIRE0_EL12 fields see PIRE0_EL1 */ + +/* For PIRE0_EL2 fields see PIRx_ELx */ + +/* For PIR_EL1 fields see PIRx_ELx */ + +/* For PIR_EL12 fields see PIR_EL1 */ + +/* For PIR_EL2 fields see PIRx_ELx */ + +/* For POR_EL0 fields see PIRx_ELx */ + +/* For POR_EL1 fields see PIRx_ELx */ + +/* For POR_EL2 fields see PIRx_ELx */ + +/* For POR_EL12 fields see POR_EL1 */ + +/* For S2POR_EL1 fields see PIRx_ELx */ + +/* For S2PIR_EL2 fields see PIRx_ELx */ + +} --=20 2.49.0 From nobody Fri Dec 19 04:27:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1744648825; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/c7JiX/L4oLi4jXQpUEkVkuVVt5PROWavD7NxMww6sE=; b=TSReFfFJ3y1Ycn0P1cs2YWYcBkE0F7mz9rNYPkdzF5I7kxMcmjaMAiSuY/nh52daCNwqCW 1Ut4tkqOKzNbRQgbJGwdvAZ1tL+oCeMfL3XCBFlUFcBBudRnFD8fKs23VbHwIvMY4c6QI0 6sJ5ZgV/1mqKwNUy02u/CJpZjg/B8NA= X-MC-Unique: rgJqEI60MIi-19Hhx40NIA-1 X-Mimecast-MFC-AGG-ID: rgJqEI60MIi-19Hhx40NIA_1744648819 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v3 04/10] kvm: kvm_get_writable_id_regs Date: Mon, 14 Apr 2025 18:38:43 +0200 Message-ID: <20250414163849.321857-5-cohuck@redhat.com> In-Reply-To: <20250414163849.321857-1-cohuck@redhat.com> References: <20250414163849.321857-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add an helper to retrieve the writable id reg bitmask. The status of the query is stored in the CPU struct so that an an error, if any, can be reported on vcpu realize(). Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu.h | 26 ++++++++++++++++++++++++++ target/arm/kvm.c | 32 ++++++++++++++++++++++++++++++++ target/arm/kvm_arm.h | 7 +++++++ 3 files changed, 65 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d27134f4a025..bbee7ff2414a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -856,6 +856,26 @@ typedef struct { uint32_t map, init, supported; } ARMVQMap; =20 +typedef enum ARMIdRegsState { + WRITABLE_ID_REGS_UNKNOWN, + WRITABLE_ID_REGS_NOT_DISCOVERABLE, + WRITABLE_ID_REGS_FAILED, + WRITABLE_ID_REGS_AVAIL, +} ARMIdRegsState; + +/* + * The following structures are for the purpose of mapping the output of + * KVM_ARM_GET_REG_WRITABLE_MASKS that also may cover id registers we do + * not support in QEMU + * ID registers in op0=3D=3D3, op1=3D=3D{0,1,3}, crn=3D0, crm=3D=3D{0-7}, = op2=3D=3D{0-7}, + * as used by the KVM_ARM_GET_REG_WRITABLE_MASKS ioctl call. + */ +#define NR_ID_REGS (3 * 8 * 8) + +typedef struct IdRegMap { + uint64_t regs[NR_ID_REGS]; +} IdRegMap; + /* REG is ID_XXX */ #define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \ ({ \ @@ -1044,6 +1064,12 @@ struct ArchCPU { */ bool host_cpu_probe_failed; =20 + /* + * state of writable id regs query used to report an error, if any, + * on KVM custom vcpu model realize + */ + ARMIdRegsState writable_id_regs; + /* QOM property to indicate we should use the back-compat CNTFRQ defau= lt */ bool backcompat_cntfrq; =20 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8491f42a18d2..6e3cd06e9bc5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -50,6 +50,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = =3D { static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; static bool cap_has_inject_ext_dabt; +static int cap_writable_id_regs; =20 /** * ARMHostCPUFeatures: information about the host CPU (identified @@ -488,6 +489,37 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) env->features =3D arm_host_cpu_features.features; } =20 +int kvm_arm_get_writable_id_regs(ARMCPU *cpu, IdRegMap *idregmap) +{ + struct reg_mask_range range =3D { + .range =3D 0, /* up to now only a single range is supported */ + .addr =3D (uint64_t)idregmap, + }; + int ret; + + if (!kvm_enabled()) { + cpu->writable_id_regs =3D WRITABLE_ID_REGS_NOT_DISCOVERABLE; + return -ENOSYS; + } + + cap_writable_id_regs =3D + kvm_check_extension(kvm_state, KVM_CAP_ARM_SUPPORTED_REG_MASK_RANG= ES); + + if (!cap_writable_id_regs || + !(cap_writable_id_regs & (1 << KVM_ARM_FEATURE_ID_RANGE))) { + cpu->writable_id_regs =3D WRITABLE_ID_REGS_NOT_DISCOVERABLE; + return -ENOSYS; + } + + ret =3D kvm_vm_ioctl(kvm_state, KVM_ARM_GET_REG_WRITABLE_MASKS, &range= ); + if (ret) { + cpu->writable_id_regs =3D WRITABLE_ID_REGS_FAILED; + return ret; + } + cpu->writable_id_regs =3D WRITABLE_ID_REGS_AVAIL; + return ret; +} + static bool kvm_no_adjvtime_get(Object *obj, Error **errp) { return !ARM_CPU(obj)->kvm_adjvtime; diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 05c3de8cd46e..8d1f20ca8d89 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -221,6 +221,8 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int = level); =20 void kvm_arm_enable_mte(Object *cpuobj, Error **errp); =20 +int kvm_arm_get_writable_id_regs(ARMCPU *cpu, IdRegMap *idregmap); + #else =20 /* @@ -247,6 +249,11 @@ static inline bool kvm_arm_mte_supported(void) return false; } =20 +static inline int kvm_arm_get_writable_id_regs(ARMCPU *cpu, IdRegMap *idre= gmap) +{ + return -ENOSYS; +} + /* * These functions should never actually be called without KVM support. */ --=20 2.49.0 From nobody Fri Dec 19 04:27:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1744648910; cv=none; d=zohomail.com; s=zohoarc; b=Oy4yVqZrIcgRiIlBGN6DX1SxP+HZ6Kc2qT0aO+6AwKUM7T8jPzoZvnRfHx4QjYg9/6A05J+r4IEb44Ac6ckm5D6j7rkKlElxfPO/ewuC4QDBIaB5+EPvgg+KoO8NxxWWUf4MUt/VfujoOannZ0IwN56FLdRSqSQLn/TZZvJptyY= ARC-Message-Signature: i=1; a=rsa-sha256; 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Mon, 14 Apr 2025 16:40:35 +0000 (UTC) Received: from gondolin.redhat.com (unknown [10.67.24.14]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id A9EA8180B487; Mon, 14 Apr 2025 16:40:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1744648842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=g9wxNH81JIH2IEDZg20aj6k00TZH42Y7fo7oUdlKPTI=; b=SCjIbEL3Yev18H9LUVr2tkWzuNTJslVA/DUxQKnJhtCYaYnAhu/vhpc4gLFRKrejhgx6Kr KYq8/mpERfqZeWRsYMaXzp9YUk3QlMH9MZXWK58oUiQU1oHOQD3i6fQN4r7KvFka9a0Sro VSWUFVz1TZm6mo907RYGIwoXiB7FkkI= X-MC-Unique: AgPxKZf3N3er18B2CtWUSw-1 X-Mimecast-MFC-AGG-ID: AgPxKZf3N3er18B2CtWUSw_1744648836 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v3 05/10] arm/cpu: accessors for writable id registers Date: Mon, 14 Apr 2025 18:38:44 +0200 Message-ID: <20250414163849.321857-6-cohuck@redhat.com> In-Reply-To: <20250414163849.321857-1-cohuck@redhat.com> References: <20250414163849.321857-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Also add conversion between the different indices. Signed-off-by: Cornelia Huck --- target/arm/cpu.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bbee7ff2414a..775a8aebc5d3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -876,6 +876,13 @@ typedef struct IdRegMap { uint64_t regs[NR_ID_REGS]; } IdRegMap; =20 +#define ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ + ({ \ + __u64 __op1 =3D (op1) & 3; \ + __op1 -=3D (__op1 =3D=3D 3); = \ + (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ + }) + /* REG is ID_XXX */ #define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \ ({ \ @@ -923,6 +930,17 @@ typedef struct IdRegMap { i_->idregs[REG ## _EL1_IDX]; \ }) =20 +#define GET_IDREG_WRITABLE(MAP, REG) \ + ({ \ + const IdRegMap *m_ =3D (MAP); \ + int index =3D ARM_FEATURE_ID_RANGE_IDX((sysreg >> 14) & 0x0000c000, \ + (sysreg >> 11) & 0x00003800, \ + (sysreg >> 7) & 0x00000780, \ + (sysreg >> 3) & 0x00000078, \ + sysreg & 0x00000007); \ + m_->regs[index]; \ + }) + /** * ARMCPU: * @env: #CPUARMState --=20 2.49.0 From nobody Fri Dec 19 04:27:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1744648858; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/cm0715fZCJ1Z/wDTOFk0hsjOspQTrfFjfUTkh4U41I=; b=UYHlLrM/m19lp2x6tzIm9HXmulP1O2gTyseG2FmsOXOS0o4yTcK/DzPW6fbKiAoRWkUXgD pLPTgf7SdVPjWCTuS8ZFagrXWoU/GDJvkuXxyOcl6wJFfVnNnNNPUSKyqDHAGB9GEw4rts gXcoPeeEEAEH8kStU2JGNx2OX3fJK6U= X-MC-Unique: rydyobF0My2CeO6h_6QyHg-1 X-Mimecast-MFC-AGG-ID: rydyobF0My2CeO6h_6QyHg_1744648853 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v3 06/10] arm/kvm: Allow reading all the writable ID registers Date: Mon, 14 Apr 2025 18:38:45 +0200 Message-ID: <20250414163849.321857-7-cohuck@redhat.com> In-Reply-To: <20250414163849.321857-1-cohuck@redhat.com> References: <20250414163849.321857-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Eric Auger At the moment kvm_arm_get_host_cpu_features() reads a subset of the ID regs. As we want to introduce properties for all writable ID reg fields, we want more genericity and read more default host register values. Introduce a new get_host_cpu_idregs() helper and add a new exhaustive boolean parameter to kvm_arm_get_host_cpu_features() and kvm_arm_set_cpu_features_from_host() to select the right behavior. The host cpu model will keep the legacy behavior unless the writable id register interface is available. A writable_map IdRegMap is introduced in the CPU object. A subsequent patch will populate it. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-sysregs.h | 2 ++ target/arm/cpu.h | 3 ++ target/arm/cpu64.c | 2 +- target/arm/kvm.c | 78 ++++++++++++++++++++++++++++++++++++++-- target/arm/kvm_arm.h | 9 +++-- target/arm/trace-events | 1 + 6 files changed, 89 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h index e89a1105904c..367fab51f19e 100644 --- a/target/arm/cpu-sysregs.h +++ b/target/arm/cpu-sysregs.h @@ -41,6 +41,8 @@ int get_sysreg_idx(ARMSysRegs sysreg); =20 #ifdef CONFIG_KVM uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg); +int kvm_idx_to_idregs_idx(int kidx); +int idregs_idx_to_kvm_idx(ARMIDRegisterIdx idx); #endif =20 #endif /* ARM_CPU_SYSREGS_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 775a8aebc5d3..8717c5e7695b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1088,6 +1088,9 @@ struct ArchCPU { */ ARMIdRegsState writable_id_regs; =20 + /* ID reg writable bitmask (KVM only) */ + IdRegMap *writable_map; + /* QOM property to indicate we should use the back-compat CNTFRQ defau= lt */ bool backcompat_cntfrq; =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 839442745ea4..60a709502697 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -757,7 +757,7 @@ static void aarch64_host_initfn(Object *obj) { #if defined(CONFIG_KVM) ARMCPU *cpu =3D ARM_CPU(obj); - kvm_arm_set_cpu_features_from_host(cpu); + kvm_arm_set_cpu_features_from_host(cpu, false); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); aarch64_add_pauth_properties(obj); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6e3cd06e9bc5..b07d5f16db50 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -41,6 +41,7 @@ #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" #include "migration/blocker.h" +#include "cpu-custom.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_INFO(DEVICE_CTRL), @@ -270,7 +271,73 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures= *ahcf, ARMIDRegisterIdx i return ret; } =20 -static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +int kvm_idx_to_idregs_idx(int kidx) +{ + int op1, crm, op2; + ARMSysRegs sysreg; + + op1 =3D kidx / 64; + if (op1 =3D=3D 2) { + op1 =3D 3; + } + crm =3D (kidx % 64) / 8; + op2 =3D kidx % 8; + sysreg =3D ENCODE_ID_REG(3, op1, 0, crm, op2); + return get_sysreg_idx(sysreg); +} + +int idregs_idx_to_kvm_idx(ARMIDRegisterIdx idx) +{ + ARMSysRegs sysreg =3D id_register_sysreg[idx]; + + return KVM_ARM_FEATURE_ID_RANGE_IDX((sysreg & CP_REG_ARM64_SYSREG_OP0_= MASK) >> CP_REG_ARM64_SYSREG_OP0_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP1_= MASK) >> CP_REG_ARM64_SYSREG_OP1_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRN_= MASK) >> CP_REG_ARM64_SYSREG_CRN_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRM_= MASK) >> CP_REG_ARM64_SYSREG_CRM_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP2_= MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT); +} + + +/* + * get_host_cpu_idregs: Read all the writable ID reg host values + * + * Need to be called once the writable mask has been populated + * Note we may want to read all the known id regs but some of them are not + * writable and return an error, hence the choice of reading only those wh= ich + * are writable. Those are also readable! + */ +static int get_host_cpu_idregs(ARMCPU *cpu, int fd, ARMHostCPUFeatures *ah= cf) +{ + int err =3D 0; + int i; + + for (i =3D 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc =3D &arm64_id_regs[i]; + ARMSysRegs sysreg =3D sysregdesc->sysreg; + uint64_t writable_mask =3D cpu->writable_map->regs[idregs_idx_to_k= vm_idx(i)]; + uint64_t *reg; + int ret; + + if (!writable_mask) { + continue; + } + + reg =3D &ahcf->isar.idregs[i]; + ret =3D read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg)); + trace_get_host_cpu_idregs(sysregdesc->name, *reg); + if (ret) { + error_report("%s error reading value of host %s register (%m)", + __func__, sysregdesc->name); + + err =3D ret; + } + } + return err; +} + +static bool +kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf, + bool exhaustive) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -398,6 +465,11 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) err |=3D get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_MMFR5_EL1_IDX); =20 + /* Make sure writable ID reg values are read */ + if (exhaustive) { + err |=3D get_host_cpu_idregs(cpu, fd, ahcf); + } + /* * DBGDIDR is a bit complicated because the kernel doesn't * provide an accessor for it in 64-bit mode, which is what this @@ -467,13 +539,13 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) return true; } =20 -void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu, bool exhaustive) { CPUARMState *env =3D &cpu->env; =20 if (!arm_host_cpu_features.dtb_compatible) { if (!kvm_enabled() || - !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) { + !kvm_arm_get_host_cpu_features(cpu, &arm_host_cpu_features, ex= haustive)) { /* We can't report this error yet, so flag that we need to * in arm_cpu_realizefn(). */ diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 8d1f20ca8d89..90ba4f7d8987 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -141,8 +141,12 @@ uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu); * * Set up the ARMCPU struct fields up to match the information probed * from the host CPU. + * + * @cpu: cpu object + * @exhaustive: if true, all the feature ID regs are queried instead of + * a subset */ -void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu, bool exhaustive); =20 /** * kvm_arm_add_vcpu_properties: @@ -257,7 +261,8 @@ static inline int kvm_arm_get_writable_id_regs(ARMCPU *= cpu, IdRegMap *idregmap) /* * These functions should never actually be called without KVM support. */ -static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) +static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu, + bool exhaustive) { g_assert_not_reached(); } diff --git a/target/arm/trace-events b/target/arm/trace-events index 4438dce7becc..17e52c0705f2 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,3 +13,4 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" =20 # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 +get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 --=20 2.49.0 From nobody Fri Dec 19 04:27:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1744648874; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8EyLEZ3HI7CqZABdZVcXz92ZT3jwespQsaTUlJJTXjs=; b=h0iKVKi6f+3J5tpIpV2lVjzavDkjhGZypk5WmMy2+3Jn5bAkGzn2jwvLoHOi8uZzmP3w4x O6LB5v3fYoAAuBfCvENSlWBFAtKHG0gZy8cWfw7ZnqWcHgHGDmGH4jOAF0lbaYokgLnPdr ZoazfSANWA2xZAW/rRaJLcBDkS8AMTE= X-MC-Unique: N-mCmTkQNBSx3dUD_6wKJg-1 X-Mimecast-MFC-AGG-ID: N-mCmTkQNBSx3dUD_6wKJg_1744648869 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v3 07/10] arm/kvm: write back modified ID regs to KVM Date: Mon, 14 Apr 2025 18:38:46 +0200 Message-ID: <20250414163849.321857-8-cohuck@redhat.com> In-Reply-To: <20250414163849.321857-1-cohuck@redhat.com> References: <20250414163849.321857-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1744648914700019100 Content-Type: text/plain; charset="utf-8" From: Eric Auger We want to give a chance to override the value of host ID regs. In a previous patch we made sure all their values could be fetched through kvm_get_one_reg() calls before their modification. After their potential modification we need to make sure we write back the values through kvm_set_one_reg() calls. Make sure the cpreg_list is modified with updated values and transfer those values back to kvm. Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/kvm.c | 44 ++++++++++++++++++++++++++++++++++++++++- target/arm/trace-events | 1 + 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b07d5f16db50..9e4cca1705c8 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1083,6 +1083,39 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu) } } =20 +static void kvm_arm_writable_idregs_to_cpreg_list(ARMCPU *cpu) +{ + if (!cpu->writable_map) { + return; + } + for (int i =3D 0; i < NR_ID_REGS; i++) { + uint64_t writable_mask =3D cpu->writable_map->regs[i]; + uint64_t *cpreg; + + if (writable_mask) { + uint64_t previous, new; + int idx =3D kvm_idx_to_idregs_idx(i); + ARM64SysReg *sysregdesc; + uint32_t sysreg; + + if (idx =3D=3D -1) { + /* sysreg writable, but we don't know it */ + continue; + } + sysregdesc =3D &arm64_id_regs[idx]; + sysreg =3D sysregdesc->sysreg; + cpreg =3D kvm_arm_get_cpreg_ptr(cpu, idregs_sysreg_to_kvm_reg(= sysreg)); + previous =3D *cpreg; + new =3D cpu->isar.idregs[idx]; + if (previous !=3D new) { + *cpreg =3D new; + trace_kvm_arm_writable_idregs_to_cpreg_list(sysregdesc->na= me, + previous, new); + } + } + } +} + void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; @@ -2050,7 +2083,16 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 - return kvm_arm_init_cpreg_list(cpu); + ret =3D kvm_arm_init_cpreg_list(cpu); + if (ret) { + return ret; + } + /* overwrite writable ID regs with their updated property values */ + kvm_arm_writable_idregs_to_cpreg_list(cpu); + + write_list_to_kvmstate(cpu, 3); + + return 0; } =20 int kvm_arch_destroy_vcpu(CPUState *cs) diff --git a/target/arm/trace-events b/target/arm/trace-events index 17e52c0705f2..955149ee1ac4 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -14,3 +14,4 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 +kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 --=20 2.49.0 From nobody Fri Dec 19 04:27:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1744648890; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HL09en4O4QOpGwm35ea50Di8JN6ZUxSvnOPz3AJzN7k=; b=WDzyGHTx/ibzGEDp4dKoGOMZkumcYZtX0HiDzf9bWYMYyCOUtcKllAiGDLYb6DGtaCIufs 10DOaynLaQMw9UsOr8WKJbxA0TWMq5ZTr/KT/TPFl/+4hMcY5Djg0Ha93+J0FdEawqdstA gH+hQbtyZL6IwYQIVq9MBuNYgi50cg4= X-MC-Unique: i3vWu4ptOUuEuCtaNKY4xQ-1 X-Mimecast-MFC-AGG-ID: i3vWu4ptOUuEuCtaNKY4xQ_1744648885 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com Cc: agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH v3 08/10] arm/cpu: more customization for the kvm host cpu model Date: Mon, 14 Apr 2025 18:38:47 +0200 Message-ID: <20250414163849.321857-9-cohuck@redhat.com> In-Reply-To: <20250414163849.321857-1-cohuck@redhat.com> References: <20250414163849.321857-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1744648925904019000 Content-Type: text/plain; charset="utf-8" From: Eric Auger If the interface for writable ID registers is available, expose uint64 SYSREG properties for writable ID reg fields exposed by the host kernel. Properties are named SYSREG__ with REG and FIELD being those used in linux arch/arm64/tools/sysreg. This done by matching the writable fields retrieved from the host kernel against the generated description of sysregs. An example of invocation is: -cpu host,SYSREG_ID_AA64ISAR0_EL1_DP=3D0x0 which sets DP field of ID_AA64ISAR0_EL1 to 0. [CH: add properties to the host model instead of introducing a new "custom" model] Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- Interaction with the existing cpu properties is still a bit unclear -- at the moment, the different configurations can overwrite each other. --- target/arm/cpu.c | 12 ++++ target/arm/cpu64.c | 22 ++++++- target/arm/kvm.c | 135 ++++++++++++++++++++++++++++++++++++++++ target/arm/kvm_arm.h | 10 +++ target/arm/trace-events | 4 ++ 5 files changed, 182 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a3de5ee2b19c..c03f38ad5cfe 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1991,6 +1991,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) return; } =20 + /* + * If we failed to retrieve the set of writable ID registers for the "= host" + * CPU model, report it here. No error if the interface for discovering + * writable ID registers is not available. + * In case we did get the set of writable ID registers, set the featur= es to + * the configured values here and perform some sanity checks. + */ + if (cpu->writable_id_regs =3D=3D WRITABLE_ID_REGS_FAILED) { + error_setg(errp, "Failed to discover writable id registers"); + return; + } + if (!cpu->gt_cntfrq_hz) { /* * 0 means "the board didn't set a value, use the default". (We al= so diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 60a709502697..c595dbb532c1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -757,11 +757,31 @@ static void aarch64_host_initfn(Object *obj) { #if defined(CONFIG_KVM) ARMCPU *cpu =3D ARM_CPU(obj); - kvm_arm_set_cpu_features_from_host(cpu, false); + bool expose_id_regs =3D true; + int ret; + + cpu->writable_map =3D g_malloc(sizeof(IdRegMap)); + + /* discover via KVM_ARM_GET_REG_WRITABLE_MASKS */ + ret =3D kvm_arm_get_writable_id_regs(cpu, cpu->writable_map); + if (ret =3D=3D -ENOSYS) { + /* legacy: continue without writable id regs */ + expose_id_regs =3D false; + } else if (ret) { + /* function will have marked an error */ + return; + } + + kvm_arm_set_cpu_features_from_host(cpu, expose_id_regs); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); aarch64_add_pauth_properties(obj); } + if (expose_id_regs) { + /* generate SYSREG properties according to writable masks */ + kvm_arm_expose_idreg_properties(cpu, arm64_id_regs); + } + #elif defined(CONFIG_HVF) ARMCPU *cpu =3D ARM_CPU(obj); hvf_arm_set_cpu_features_from_host(cpu); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9e4cca1705c8..63e27906cc42 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -335,6 +335,141 @@ static int get_host_cpu_idregs(ARMCPU *cpu, int fd, A= RMHostCPUFeatures *ahcf) return err; } =20 +static ARM64SysRegField *get_field(int i, ARM64SysReg *reg) +{ + GList *l; + + for (l =3D reg->fields; l; l =3D l->next) { + ARM64SysRegField *field =3D (ARM64SysRegField *)l->data; + + if (i >=3D field->lower && i <=3D field->upper) { + return field; + } + } + return NULL; +} + +static void set_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t *idregs =3D cpu->isar.idregs; + uint64_t old, value, mask; + int lower =3D field->lower; + int upper =3D field->upper; + int length =3D upper - lower + 1; + int index =3D field->index; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (length < 64 && value > ((1 << length) - 1)) { + error_setg(errp, + "idreg %s set value (0x%lx) exceeds length of field (%d= )!", + name, value, length); + return; + } + + mask =3D MAKE_64BIT_MASK(lower, length); + value =3D value << lower; + old =3D idregs[index]; + idregs[index] =3D old & ~mask; + idregs[index] |=3D value; + trace_set_sysreg_prop(name, old, mask, value, idregs[index]); +} + +static void get_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field =3D (ARM64SysRegField *)opaque; + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t *idregs =3D cpu->isar.idregs; + uint64_t value, mask; + int lower =3D field->lower; + int upper =3D field->upper; + int length =3D upper - lower + 1; + int index =3D field->index; + + mask =3D MAKE_64BIT_MASK(lower, length); + value =3D (idregs[index] & mask) >> lower; + visit_type_uint64(v, name, &value, errp); + trace_get_sysreg_prop(name, value); +} + +/* + * decode_idreg_writemap: Generate props for writable fields + * + * @obj: CPU object + * @index: index of the sysreg + * @map: writable map for the sysreg + * @reg: description of the sysreg + */ +static int +decode_idreg_writemap(Object *obj, int index, uint64_t map, ARM64SysReg *r= eg) +{ + int i =3D ctz64(map); + int nb_sysreg_props =3D 0; + + while (map) { + + ARM64SysRegField *field =3D get_field(i, reg); + int lower, upper; + uint64_t mask; + char *prop_name; + + if (!field) { + /* the field cannot be matched to any know id named field */ + warn_report("%s bit %d of %s is writable but cannot be matched= ", + __func__, i, reg->name); + warn_report("%s is cpu-sysreg-properties.c up to date?", __fun= c__); + map =3D map & ~BIT_ULL(i); + i =3D ctz64(map); + continue; + } + lower =3D field->lower; + upper =3D field->upper; + prop_name =3D g_strdup_printf("SYSREG_%s_%s", reg->name, field->na= me); + trace_decode_idreg_writemap(field->name, lower, upper, prop_name); + object_property_add(obj, prop_name, "uint64", + get_sysreg_prop, set_sysreg_prop, NULL, field); + nb_sysreg_props++; + + mask =3D MAKE_64BIT_MASK(lower, upper - lower + 1); + map =3D map & ~mask; + i =3D ctz64(map); + } + trace_nb_sysreg_props(reg->name, nb_sysreg_props); + return 0; +} + +/* analyze the writable mask and generate properties for writable fields */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs) +{ + int i, idx; + IdRegMap *map =3D cpu->writable_map; + Object *obj =3D OBJECT(cpu); + + for (i =3D 0; i < NR_ID_REGS; i++) { + uint64_t mask =3D map->regs[i]; + + if (mask) { + /* reg @i has some writable fields, decode them */ + idx =3D kvm_idx_to_idregs_idx(i); + if (idx < 0) { + /* no matching reg? */ + warn_report("%s: reg %d writable, but not in list of idreg= s?", + __func__, i); + } else { + decode_idreg_writemap(obj, i, mask, ®s[idx]); + } + } + } +} + static bool kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf, bool exhaustive) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 90ba4f7d8987..ba5de45f868c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -157,6 +157,16 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu, b= ool exhaustive); */ void kvm_arm_add_vcpu_properties(ARMCPU *cpu); =20 +typedef struct ARM64SysReg ARM64SysReg; +/** + * kvm_arm_expose_idreg_properties: + * @cpu: The CPU object to generate the properties for + * @reg: registers from the host + * + * analyze the writable mask and generate properties for writable fields + */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs); + /** * kvm_arm_steal_time_finalize: * @cpu: ARMCPU for which to finalize kvm-steal-time diff --git a/target/arm/trace-events b/target/arm/trace-events index 955149ee1ac4..8d2a234d5272 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -15,3 +15,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host v= alue for %s is 0x%"PRIx64 kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous,= uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 +decode_idreg_writemap(const char* name, int lower, int upper, char *prop_n= ame) "%s [%d:%d] is writable (prop %s)" +get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 +set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t fi= eld_value, uint64_t new) "%s old reg value=3D0x%"PRIx64" mask=3D0x%"PRIx64"= new field value=3D0x%"PRIx64" new reg value=3D0x%"PRIx64 +nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" --=20 2.49.0 From nobody Fri Dec 19 04:27:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Implement the capability to query available ID register values by adding SYSREG_* options and values to the cpu model expansion for the host model, if available. Excerpt: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} {"return": {"model": {"name": "host", "props": {"SYSREG_ID_AA64PFR0_EL1_EL3": 1224979098931106066, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, ../.. So this allows the upper stack to detect available writable ID regs and the "host passthrough model" values. [CH: moved SYSREG_* values to host model] Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- TODO: Add the moment there is no way to test changing a given ID reg field value. ie: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host", "prop"= :{"SYSREG_ID_AA64ISAR0_EL1_DP":0x13}} --- target/arm/arm-qmp-cmds.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index 883c0a0e8cce..5f48c7d835e1 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -21,6 +21,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "hw/boards.h" #include "kvm_arm.h" #include "qapi/error.h" @@ -209,6 +210,24 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, } } =20 + /* If writable ID regs are supported, add them as well */ + if (ARM_CPU(obj)->writable_id_regs =3D=3D WRITABLE_ID_REGS_AVAIL) { + ObjectProperty *prop; + ObjectPropertyIterator iter; + + object_property_iter_init(&iter, obj); + + while ((prop =3D object_property_iter_next(&iter))) { + QObject *value; + + if (!g_str_has_prefix(prop->name, "SYSREG_")) { + continue; + } + value =3D object_property_get_qobject(obj, prop->name, &error_= abort); + qdict_put_obj(qdict_out, prop->name, value); + } + } + if (!qdict_size(qdict_out)) { qobject_unref(qdict_out); } else { --=20 2.49.0 From nobody Fri Dec 19 04:27:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1744648991; cv=none; d=zohomail.com; s=zohoarc; b=SJMi7YQbhIkkkmTU/JjJx4of1ufu+Sls6rAMAqvrpv8tq7HWbz4/GpQdjEyz4RsNpKFWVWfLcWMw31TrFsVJaK52k7FKkjsPDCRZKVO3EafmR+4sCkqbcA3MIR4fhunjOpvRGy95g4UbXkcHfRegD+8osQcnOTnopp9QkCNsVYs= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1744648993115019100 Content-Type: text/plain; charset="utf-8" Add some documentation for how individual ID registers can be configured with the host cpu model. [CH: adapt to removal of the 'custom' model, added some more explanations about using the ID register props] Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- docs/system/arm/cpu-features.rst | 104 ++++++++++++++++++++++++++++--- 1 file changed, 96 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 37d5dfd15b34..22faefd76edd 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -2,7 +2,10 @@ Arm CPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 CPU features are optional features that a CPU of supporting type may -choose to implement or not. In QEMU, optional CPU features have +choose to implement or not. QEMU provides two different mechanisms +to configure those features: + +1. For most CPU models, optional CPU features may have corresponding boolean CPU proprieties that, when enabled, indicate that the feature is implemented, and, conversely, when disabled, indicate that it is not implemented. An example of an Arm CPU feature @@ -29,6 +32,16 @@ supports the feature. While ``aarch64`` currently only = works with KVM, it could work with TCG. CPU features that are specific to KVM are prefixed with "kvm-" and are described in "KVM VCPU Features". =20 +2. Additionally, the ``host`` CPU model on KVM allows to configure optional +CPU features via the corresponding ID registers. The host kernel allows +to write a subset of ID register fields. The host model exposes +properties for each writable ID register field. Those options are named +SYSREG__. IDREG and FIELD names are those used in the +ARM ARM Reference Manual. They can also be found in the Linux +arch/arm64/tool/sysreg file which is used to automatically generate the +description for those registers and fields. This currently only has been +implemented for KVM. + CPU Feature Probing =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -124,13 +137,20 @@ A note about CPU models and KVM =20 Named CPU models generally do not work with KVM. There are a few cases that do work, e.g. using the named CPU model ``cortex-a57`` with KVM on a -seattle host, but mostly if KVM is enabled the ``host`` CPU type must be -used. This means the guest is provided all the same CPU features as the -host CPU type has. And, for this reason, the ``host`` CPU type should -enable all CPU features that the host has by default. Indeed it's even -a bit strange to allow disabling CPU features that the host has when using -the ``host`` CPU type, but in the absence of CPU models it's the best we c= an -do if we want to launch guests without all the host's CPU features enabled. +seattle host, but mostly if KVM is enabled, the ``host`` CPU model must be +used. + +Using the ``host`` type means the guest is provided all the same CPU +features as the host CPU type has. And, for this reason, the ``host`` +CPU type should enable all CPU features that the host has by default. + +In case some features need to be hidden to the guest, and the host kernel +supports it, the ``host`` model can be instructed to disable individual +ID register values. This is especially useful for migration purposes. +However, this interface will not allow configuring an arbitrary set of +features; the ID registers must describe a subset of the host's features, +and all differences to the host's configuration must actually be supported +by the kernel to be deconfigured. =20 Enabling KVM also affects the ``query-cpu-model-expansion`` QMP command. = The affect is not only limited to specific features, as pointed out in example @@ -167,6 +187,13 @@ disabling many SVE vector lengths would be quite verbo= se, the ``sve`` CPU properties have special semantics (see "SVE CPU Property Parsing Semantics"). =20 +Additionally, if supported by KVM on the host kernel, the ``host`` CPU mod= el +may be configured via individual ID register field properties, for example= :: + + $ qemu-system-aarch64 -M virt -cpu host,SYSREG_ID_AA64ISAR0_EL1_DP=3D0x0 + +This forces ID_AA64ISAR0_EL1 DP field to 0. + KVM VCPU Features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 @@ -466,3 +493,64 @@ Legal values for ``S`` are 30, 34, 36, and 39; the def= ault is 30. =20 As with ``x-rme``, the ``x-l0gptsz`` property may be renamed or removed in some future QEMU release. + +Configuring CPU features via ID register fields +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Note that this is currently only supported under KVM, and with the +``host`` CPU model. + +Querying available ID register fields +------------------------------------- + +QEMU will create properties for all ID register fields that are +reported as being writable by the kernel, and that are known to the +QEMU instance. Therefore, the same QEMU binary may expose different +properties when run under a different kernel. + +To find out all available writable ID register fields, use the +``query-cpu-model-expansion`` QMP command:: + + (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} + {"return": { + "model": {"name": "host", "props": { + "SYSREG_ID_AA64PFR0_EL1_EL3": 1, "SYSREG_ID_AA64ISAR2_EL1_CLRBHB": 0, + "SYSREG_CTR_EL0_L1Ip": 3, "SYSREG_CTR_EL0_DminLine": 4, + "SYSREG_ID_AA64MMFR0_EL1_BIGEND": 1, "SYSREG_ID_AA64MMFR1_EL1_ECBHB": 0, + "SYSREG_ID_AA64MMFR2_EL1_CnP": 1, "SYSREG_ID_DFR0_EL1_PerfMon": 4, + "SYSREG_ID_AA64PFR0_EL1_DIT": 0, "SYSREG_ID_AA64MMFR1_EL1_HAFDBS": 2, + "SYSREG_ID_AA64ISAR0_EL1_FHM": 0, "SYSREG_ID_AA64ISAR2_EL1_CSSC": 0, + "SYSREG_ID_AA64ISAR0_EL1_DP": 1, (...) + }}}} + +If a certain field in an ID register does not show up in this list, it +is not writable with the specific host kernel. + +A note on compatibility +----------------------- + +A common use case for providing a defined set of ID register values is +to be able to present a fixed set of features to a guest, often referred +to as "stable guest ABI". This may take the form of ironing out differences +between two similar CPUs with the intention of being able to migrate +between machines with those CPUs, or providing the same CPU across Linux +kernel updates on the host. + +Over the course of time, the Linux kernel is changing the set of ID regist= er +fields that are writable by userspace. Newly introduced writable ID +registers should be initialized to 0 to ensure compatibility. However, ID +registers that have already been introduced that undergo a change as to +which fields are writable may introduce incompatibities that need to be +addressed on a case-by-case basis for the systems that you wish to migrate +inbetween. + +A note on Arm CPU features (FEAT_xxx) +------------------------------------- + +Configuring CPUs is done on a feature level on other architectures, and th= is +would imply configuring FEAT_xxx values on Arm. However, differences betwe= en +CPUs may not map to FEAT_xxx, but to differences in other registers in the +ID register range; for example, differences in the cache architecture expo= sed +via ``CTR_EL0``. We therefore cannot rely on configuration via FEAT_xxx. A +feature-based interface more similar to other architectures may be impleme= nted +on top of the ID register interface in the future. --=20 2.49.0