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Tsirkin" , Marcel Apfelbaum , Fabiano Rosas , Laurent Vivier , Phil Dennis-Jordan , Bernhard Beschow Subject: [PATCH v3 7/8] hw/usb/hcd-xhci-pci: Make PCI device more configurable Date: Fri, 11 Apr 2025 17:58:49 +1000 Message-ID: <20250411075851.206995-8-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250411075851.206995-1-npiggin@gmail.com> References: <20250411075851.206995-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1744358463702019100 Content-Type: text/plain; charset="utf-8" To prepare to support another USB PCI Host Controller, make some PCI configuration dynamic. Signed-off-by: Nicholas Piggin --- hw/usb/hcd-xhci-pci.h | 9 ++++ hw/usb/hcd-xhci-pci.c | 118 +++++++++++++++++++++++++++++++++--------- 2 files changed, 103 insertions(+), 24 deletions(-) diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h index 5b61ae84555..09aabae6e01 100644 --- a/hw/usb/hcd-xhci-pci.h +++ b/hw/usb/hcd-xhci-pci.h @@ -41,6 +41,15 @@ typedef struct XHCIPciState { OnOffAuto msi; OnOffAuto msix; bool conditional_intr_mapping; + uint8_t cache_line_size; + uint8_t pm_cap_off; + uint8_t pcie_cap_off; + uint8_t msi_cap_off; + uint8_t msix_cap_off; + int msix_bar_nr; + uint64_t msix_bar_size; + uint32_t msix_table_off; + uint32_t msix_pba_off; } XHCIPciState; =20 #endif diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c index d908eb787d3..eb918ce3d6e 100644 --- a/hw/usb/hcd-xhci-pci.c +++ b/hw/usb/hcd-xhci-pci.c @@ -32,9 +32,6 @@ #include "trace.h" #include "qapi/error.h" =20 -#define OFF_MSIX_TABLE 0x3000 -#define OFF_MSIX_PBA 0x3800 - static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable) { XHCIPciState *s =3D container_of(xhci, XHCIPciState, xhci); @@ -120,6 +117,31 @@ static int xhci_pci_vmstate_post_load(void *opaque, in= t version_id) return 0; } =20 +static int xhci_pci_add_pm_capability(PCIDevice *pci_dev, uint8_t offset, + Error **errp) +{ + int err; + + err =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, + PCI_PM_SIZEOF, errp); + if (err < 0) { + return err; + } + + pci_set_word(pci_dev->config + offset + PCI_PM_PMC, + PCI_PM_CAP_VER_1_2 | + PCI_PM_CAP_D1 | PCI_PM_CAP_D2 | + PCI_PM_CAP_PME_D0 | PCI_PM_CAP_PME_D1 | + PCI_PM_CAP_PME_D2 | PCI_PM_CAP_PME_D3hot); + pci_set_word(pci_dev->wmask + offset + PCI_PM_PMC, 0); + pci_set_word(pci_dev->config + offset + PCI_PM_CTRL, + PCI_PM_CTRL_NO_SOFT_RESET); + pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL, + PCI_PM_CTRL_STATE_MASK); + + return 0; +} + static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp) { int ret; @@ -128,7 +150,7 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev,= Error **errp) =20 dev->config[PCI_CLASS_PROG] =3D 0x30; /* xHCI */ dev->config[PCI_INTERRUPT_PIN] =3D 0x01; /* interrupt pin 1 */ - dev->config[PCI_CACHE_LINE_SIZE] =3D 0x10; + dev->config[PCI_CACHE_LINE_SIZE] =3D s->cache_line_size; dev->config[0x60] =3D 0x30; /* release number */ =20 object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL); @@ -144,40 +166,78 @@ static void usb_xhci_pci_realize(struct PCIDevice *de= v, Error **errp) s->xhci.nec_quirks =3D true; } =20 - if (s->msi !=3D ON_OFF_AUTO_OFF) { - ret =3D msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err); - /* - * Any error other than -ENOTSUP(board's MSI support is broken) - * is a programming error - */ - assert(!ret || ret =3D=3D -ENOTSUP); - if (ret && s->msi =3D=3D ON_OFF_AUTO_ON) { - /* Can't satisfy user's explicit msi=3Don request, fail */ - error_append_hint(&err, "You have to use msi=3Dauto (default) = or " - "msi=3Doff with this machine type.\n"); + if (s->pm_cap_off) { + if (xhci_pci_add_pm_capability(dev, s->pm_cap_off, &err)) { error_propagate(errp, err); return; } - assert(!err || s->msi =3D=3D ON_OFF_AUTO_AUTO); - /* With msi=3Dauto, we fall back to MSI off silently */ - error_free(err); } + + if (s->msi !=3D ON_OFF_AUTO_OFF) { + ret =3D msi_init(dev, s->msi_cap_off, s->xhci.numintrs, + true, false, &err); + if (ret) { + if (ret !=3D -ENOTSUP) { + /* Programming error */ + error_propagate(errp, err); + return; + } + if (s->msi =3D=3D ON_OFF_AUTO_ON) { + /* Can't satisfy user's explicit msi=3Don request, fail */ + error_append_hint(&err, "You have to use msi=3Dauto (defau= lt) " + "or msi=3Doff with this machine type.\n"= ); + error_propagate(errp, err); + return; + } + error_free(err); + err =3D NULL; /* With msi=3Dauto, we fall back to MSI off sile= ntly */ + } + } + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &s->xhci.mem); =20 if (pci_bus_is_express(pci_get_bus(dev))) { - ret =3D pcie_endpoint_cap_init(dev, 0xa0); + ret =3D pcie_endpoint_cap_init(dev, s->pcie_cap_off); assert(ret > 0); } =20 if (s->msix !=3D ON_OFF_AUTO_OFF) { - /* TODO check for errors, and should fail when msix=3Don */ - msix_init(dev, s->xhci.numintrs, - &s->xhci.mem, 0, OFF_MSIX_TABLE, - &s->xhci.mem, 0, OFF_MSIX_PBA, - 0x90, NULL); + MemoryRegion *msix_bar =3D &s->xhci.mem; + + if (s->msix_bar_nr !=3D 0) { + memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), + "xhci-msix", s->msix_bar_size); + msix_bar =3D &dev->msix_exclusive_bar; + pci_register_bar(dev, s->msix_bar_nr, + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, + msix_bar); + } + + ret =3D msix_init(dev, s->xhci.numintrs, + msix_bar, s->msix_bar_nr, s->msix_table_off, + msix_bar, s->msix_bar_nr, s->msix_pba_off, + s->msix_cap_off, &err); + if (ret) { + if (ret !=3D -ENOTSUP) { + /* Programming error */ + error_propagate(errp, err); + return; + } + if (s->msix =3D=3D ON_OFF_AUTO_ON) { + /* Can't satisfy user's explicit msix=3Don request, fail */ + error_append_hint(&err, "You have to use msix=3Dauto (defa= ult) " + "or msix=3Doff with this machine type.\n= "); + error_propagate(errp, err); + return; + } + error_free(err); + err =3D NULL; /* With msix=3Dauto, we fall back to MSI-X off s= ilently */ + /* Should we unregister BAR and memory region here? */ + } } s->xhci.as =3D pci_get_address_space(dev); } @@ -214,6 +274,16 @@ static void xhci_instance_init(Object *obj) PCI_DEVICE(obj)->cap_present |=3D QEMU_PCI_CAP_EXPRESS; object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI); qdev_alias_all_properties(DEVICE(&s->xhci), obj); + + s->cache_line_size =3D 0x10; + s->pm_cap_off =3D 0; + s->pcie_cap_off =3D 0xa0; + s->msi_cap_off =3D 0x70; + s->msix_cap_off =3D 0x90; + s->msix_bar_nr =3D 0; + s->msix_bar_size =3D 0; + s->msix_table_off =3D 0x3000; + s->msix_pba_off =3D 0x3800; } =20 static const Property xhci_pci_properties[] =3D { --=20 2.47.1