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Tsirkin" , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org Subject: [PATCH v4 6/7] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0 Date: Fri, 11 Apr 2025 14:41:28 +1000 Message-ID: <20250411044130.201724-7-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250411044130.201724-1-npiggin@gmail.com> References: <20250411044130.201724-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=npiggin@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1744346595443019100 Content-Type: text/plain; charset="utf-8" Devices where the MSI-X addresses are shared with other MMIO on BAR0 can not use msi_enable because it unmaps and remaps BAR0, which interferes with device MMIO mappings. xhci-nec is one such device we would like to test with msix. Use the BAR iomap tracking structure introduced in the previous change to have qpci_misx_enable() use existing iomaps if msix bars are already mapped. Cc: Michael S. Tsirkin Cc: Marcel Apfelbaum Reviewed-by: Akihiko Odaki Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin --- tests/qtest/libqos/pci.h | 1 + tests/qtest/libqos/pci.c | 40 ++++++++++++++++++++++++++++++++++------ 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index 5c7ebad4270..d334d9c0837 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -75,6 +75,7 @@ struct QPCIDevice bool bars_mapped[QPCI_NUM_REGIONS]; QPCIBar bars[QPCI_NUM_REGIONS]; bool msix_enabled; + bool msix_table_bar_iomap, msix_pba_bar_iomap; QPCIBar msix_table_bar, msix_pba_bar; uint64_t msix_table_off, msix_pba_off; }; diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index 02d88acd500..72adf81ddd6 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -288,15 +288,21 @@ void qpci_msix_enable(QPCIDevice *dev) =20 table =3D qpci_config_readl(dev, addr + PCI_MSIX_TABLE); bir_table =3D table & PCI_MSIX_FLAGS_BIRMASK; - dev->msix_table_bar =3D qpci_iomap(dev, bir_table, NULL); + if (dev->bars_mapped[bir_table]) { + dev->msix_table_bar =3D dev->bars[bir_table]; + } else { + dev->msix_table_bar_iomap =3D true; + dev->msix_table_bar =3D qpci_iomap(dev, bir_table, NULL); + } dev->msix_table_off =3D table & ~PCI_MSIX_FLAGS_BIRMASK; =20 table =3D qpci_config_readl(dev, addr + PCI_MSIX_PBA); bir_pba =3D table & PCI_MSIX_FLAGS_BIRMASK; - if (bir_pba !=3D bir_table) { - dev->msix_pba_bar =3D qpci_iomap(dev, bir_pba, NULL); + if (dev->bars_mapped[bir_pba]) { + dev->msix_pba_bar =3D dev->bars[bir_pba]; } else { - dev->msix_pba_bar =3D dev->msix_table_bar; + dev->msix_pba_bar_iomap =3D true; + dev->msix_pba_bar =3D qpci_iomap(dev, bir_pba, NULL); } dev->msix_pba_off =3D table & ~PCI_MSIX_FLAGS_BIRMASK; =20 @@ -307,6 +313,7 @@ void qpci_msix_disable(QPCIDevice *dev) { uint8_t addr; uint16_t val; + uint32_t table; =20 g_assert(dev->msix_enabled); addr =3D qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0); @@ -315,10 +322,31 @@ void qpci_msix_disable(QPCIDevice *dev) qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val & ~PCI_MSIX_FLAGS_ENAB= LE); =20 - if (dev->msix_pba_bar.addr !=3D dev->msix_table_bar.addr) { + if (dev->msix_pba_bar_iomap) { + dev->msix_pba_bar_iomap =3D false; qpci_iounmap(dev, dev->msix_pba_bar); + } else { + /* + * If we had reused an existing iomap, ensure it is still mapped + * otherwise it would be a bug if it were unmapped before msix is + * disabled. A refcounting iomap implementation could avoid this + * issue entirely, but let's wait until that's needed. + */ + uint8_t bir_pba; + table =3D qpci_config_readl(dev, addr + PCI_MSIX_PBA); + bir_pba =3D table & PCI_MSIX_FLAGS_BIRMASK; + g_assert(dev->bars_mapped[bir_pba]); + } + + if (dev->msix_table_bar_iomap) { + dev->msix_table_bar_iomap =3D false; + qpci_iounmap(dev, dev->msix_table_bar); + } else { + uint8_t bir_table; + table =3D qpci_config_readl(dev, addr + PCI_MSIX_TABLE); + bir_table =3D table & PCI_MSIX_FLAGS_BIRMASK; + g_assert(dev->bars_mapped[bir_table]); } - qpci_iounmap(dev, dev->msix_table_bar); =20 dev->msix_enabled =3D 0; dev->msix_table_off =3D 0; --=20 2.47.1