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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1744209849; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=URX2J495sHMdJNFBMyHM0OA0s/WzayWSv+12R4q7WI8=; b=QYK71qs6oZy9FK6ygwpr3bnnF1hGixK3ujJwhH8WpMDfnXcOevsUzpQokwr6+LVuhpso1T DKxHsM981cn6BMXGQgpsZSxfyuON2q22ehy1bv9SiI8+Q5jVMCQJHLZhw+AEZ9rFwy/k4x 74lR0eIQftbbDX5UMUJfPXTM5G8Il7A= X-MC-Unique: TrjIPT4pPT2p5G386QmZFg-1 X-Mimecast-MFC-AGG-ID: TrjIPT4pPT2p5G386QmZFg_1744209844 From: Cornelia Huck To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de Cc: shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com, Cornelia Huck Subject: [PATCH for-10.1 v5 07/13] arm/cpu: Store aa64smfr0 into the idregs array Date: Wed, 9 Apr 2025 16:42:58 +0200 Message-ID: <20250409144304.912325-8-cohuck@redhat.com> In-Reply-To: <20250409144304.912325-1-cohuck@redhat.com> References: <20250409144304.912325-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.505, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1744209900473019000 Content-Type: text/plain; charset="utf-8" From: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Sebastian Ott Signed-off-by: Eric Auger Signed-off-by: Cornelia Huck --- target/arm/cpu-features.h | 6 +++--- target/arm/cpu.h | 1 - target/arm/cpu64.c | 7 ++----- target/arm/helper.c | 2 +- target/arm/kvm.c | 3 +-- target/arm/tcg/cpu64.c | 4 ++-- 6 files changed, 9 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 7f6331ca437d..1ac1f3e95984 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -978,17 +978,17 @@ static inline bool isar_feature_aa64_sve_f64mm(const = ARMISARegisters *id) =20 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F64F64); } =20 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) =3D=3D 0xf; + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, I16I64) =3D=3D 0xf; } =20 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); + return FIELD_EX64_IDREG(id, ID_AA64SMFR0, FA64); } =20 /* diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 37bb337b3c71..a3a3b8031eed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1097,7 +1097,6 @@ struct ArchCPU { uint32_t dbgdidr; uint32_t dbgdevid; uint32_t dbgdevid1; - uint64_t id_aa64smfr0; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; } isar; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4ba53f75ed96..c8ab8761282a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -328,7 +328,7 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) =20 if (vq_map =3D=3D 0) { if (!cpu_isar_feature(aa64_sme, cpu)) { - cpu->isar.id_aa64smfr0 =3D 0; + SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); return; } =20 @@ -381,11 +381,8 @@ static bool cpu_arm_get_sme_fa64(Object *obj, Error **= errp) static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; =20 - t =3D cpu->isar.id_aa64smfr0; - t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, value); - cpu->isar.id_aa64smfr0 =3D t; + FIELD_DP64_IDREG(&cpu->isar, ID_AA64SMFR0, FA64, value); } =20 #ifdef CONFIG_USER_ONLY diff --git a/target/arm/helper.c b/target/arm/helper.c index 8efe508306e5..275e590876bf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7946,7 +7946,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64smfr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64SMFR0)}, { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e999d98dcf7f..a73ff0a603bc 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -353,8 +353,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) err =3D 0; } else { err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, - ARM64_SYS_REG(3, 0, 0, 4, 5)); + err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX); err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 41077b3dcd08..cadc1258fc40 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1268,7 +1268,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */ SET_IDREG(isar, ID_AA64DFR0, t); =20 - t =3D cpu->isar.id_aa64smfr0; + t =3D GET_IDREG(isar, ID_AA64SMFR0); t =3D FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */ t =3D FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */ @@ -1276,7 +1276,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */ t =3D FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */ - cpu->isar.id_aa64smfr0 =3D t; + SET_IDREG(isar, ID_AA64SMFR0, t); =20 /* Replicate the same data to the 32-bit id registers. */ aa32_max_features(cpu); --=20 2.48.1