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Tue, 08 Apr 2025 19:51:58 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jim Shu Subject: [PATCH v2 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed Date: Wed, 9 Apr 2025 10:51:31 +0800 Message-Id: <20250409025131.3670-5-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250409025131.3670-1-jim.shu@sifive.com> References: <20250409025131.3670-1-jim.shu@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1744167181571019100 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR. Signed-off-by: Jim Shu Acked-by: Alistair Francis --- target/riscv/csr.c | 44 ++++++++++++++++++++++++++++++++++++ target/riscv/time_helper.c | 46 ++++++++++++++++++++++++++++++++++++++ target/riscv/time_helper.h | 1 + 3 files changed, 91 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e86808fd98..548daf6a7a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3161,6 +3161,7 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE | MENVCFG_CDE; + bool stce_changed =3D false; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | @@ -3186,10 +3187,19 @@ static RISCVException write_menvcfg(CPURISCVState *= env, int csrno, if ((val & MENVCFG_DTE) =3D=3D 0) { env->mstatus &=3D ~MSTATUS_SDT; } + + if (cfg->ext_sstc && + ((env->menvcfg & MENVCFG_STCE) !=3D (val & MENVCFG_STCE))) { + stce_changed =3D true; + } } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); write_henvcfg(env, CSR_HENVCFG, env->henvcfg); =20 + if (stce_changed) { + riscv_timer_stce_changed(env, true, !!(val & MENVCFG_STCE)); + } + return RISCV_EXCP_NONE; } =20 @@ -3212,6 +3222,12 @@ static RISCVException write_menvcfgh(CPURISCVState *= env, int csrno, (cfg->ext_smcdeleg ? MENVCFG_CDE : 0) | (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); uint64_t valh =3D (uint64_t)val << 32; + bool stce_changed =3D false; + + if (cfg->ext_sstc && + ((env->menvcfg & MENVCFG_STCE) !=3D (valh & MENVCFG_STCE))) { + stce_changed =3D true; + } =20 if ((valh & MENVCFG_DTE) =3D=3D 0) { env->mstatus &=3D ~MSTATUS_SDT; @@ -3220,6 +3236,10 @@ static RISCVException write_menvcfgh(CPURISCVState *= env, int csrno, env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32); =20 + if (stce_changed) { + riscv_timer_stce_changed(env, true, !!(valh & MENVCFG_STCE)); + } + return RISCV_EXCP_NONE; } =20 @@ -3297,8 +3317,10 @@ static RISCVException read_henvcfg(CPURISCVState *en= v, int csrno, static RISCVException write_henvcfg(CPURISCVState *env, int csrno, target_ulong val) { + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; RISCVException ret; + bool stce_changed =3D false; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); if (ret !=3D RISCV_EXCP_NONE) { @@ -3324,6 +3346,11 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, get_field(val, HENVCFG_PMM) !=3D PMM_FIELD_RESERVED) { mask |=3D HENVCFG_PMM; } + + if (cfg->ext_sstc && + ((env->henvcfg & HENVCFG_STCE) !=3D (val & HENVCFG_STCE))) { + stce_changed =3D true; + } } =20 env->henvcfg =3D val & mask; @@ -3331,6 +3358,10 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, env->vsstatus &=3D ~MSTATUS_SDT; } =20 + if (stce_changed) { + riscv_timer_stce_changed(env, false, !!(val & HENVCFG_STCE)); + } + return RISCV_EXCP_NONE; } =20 @@ -3352,19 +3383,32 @@ static RISCVException read_henvcfgh(CPURISCVState *= env, int csrno, static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, target_ulong val) { + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | HENVCFG_DTE); uint64_t valh =3D (uint64_t)val << 32; RISCVException ret; + bool stce_changed =3D false; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); if (ret !=3D RISCV_EXCP_NONE) { return ret; } + + if (cfg->ext_sstc && + ((env->henvcfg & HENVCFG_STCE) !=3D (valh & HENVCFG_STCE))) { + stce_changed =3D true; + } + env->henvcfg =3D (env->henvcfg & 0xFFFFFFFF) | (valh & mask); if ((env->henvcfg & HENVCFG_DTE) =3D=3D 0) { env->vsstatus &=3D ~MSTATUS_SDT; } + + if (stce_changed) { + riscv_timer_stce_changed(env, false, !!(val & HENVCFG_STCE)); + } + return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index aebf0798d0..400e917354 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -140,6 +140,52 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEM= UTimer *timer, timer_mod(timer, next); } =20 +/* + * When disabling xenvcfg.STCE, the S/VS Timer may be disabled at the same= time. + * It is safe to call this function regardless of whether the timer has be= en + * deleted or not. timer_del() will do nothing if the timer has already + * been deleted. + */ +static void riscv_timer_disable_timecmp(CPURISCVState *env, QEMUTimer *tim= er, + uint32_t timer_irq) +{ + /* Disable S-mode Timer IRQ and HW-based STIP */ + if ((timer_irq =3D=3D MIP_STIP) && !get_field(env->menvcfg, MENVCFG_ST= CE)) { + riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0)); + timer_del(timer); + return; + } + + /* Disable VS-mode Timer IRQ and HW-based VSTIP */ + if ((timer_irq =3D=3D MIP_VSTIP) && + (!get_field(env->menvcfg, MENVCFG_STCE) || + !get_field(env->henvcfg, HENVCFG_STCE))) { + env->vstime_irq =3D 0; + riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0)); + timer_del(timer); + return; + } +} + +/* Enable or disable S/VS-mode Timer when xenvcfg.STCE is changed */ +void riscv_timer_stce_changed(CPURISCVState *env, bool is_m_mode, bool ena= ble) +{ + if (enable) { + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } else { + riscv_timer_disable_timecmp(env, env->vstimer, MIP_VSTIP); + } + + if (is_m_mode) { + if (enable) { + riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, = MIP_STIP); + } else { + riscv_timer_disable_timecmp(env, env->stimer, MIP_STIP); + } + } +} + void riscv_timer_init(RISCVCPU *cpu) { CPURISCVState *env; diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h index cacd79b80c..af1f634f89 100644 --- a/target/riscv/time_helper.h +++ b/target/riscv/time_helper.h @@ -25,6 +25,7 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, uint64_t timecmp, uint64_t delta, uint32_t timer_irq); +void riscv_timer_stce_changed(CPURISCVState *env, bool is_m_mode, bool ena= ble); void riscv_timer_init(RISCVCPU *cpu); =20 #endif --=20 2.17.1