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Sun, 06 Apr 2025 00:03:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGK83NiUKusGHrImAn/fedmFxsiLcV7iOlirFE8wN/6cS1mdJ4pziw/oPnZBUlY0F+CFs2Tfg== X-Received: by 2002:a05:600c:3586:b0:43d:649:4e50 with SMTP id 5b1f17b1804b1-43ecf86a99emr84236615e9.13.1743923031162; Sun, 06 Apr 2025 00:03:51 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: alistair23@gmail.com Subject: [PATCH 22/27] target/riscv: generalize custom CSR functionality Date: Sun, 6 Apr 2025 09:02:49 +0200 Message-ID: <20250406070254.274797-23-pbonzini@redhat.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250406070254.274797-1-pbonzini@redhat.com> References: <20250406070254.274797-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.359, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1743923202511019000 Content-Type: text/plain; charset="utf-8" While at it, constify it so that the RISCVCSR array in RISCVCPUDef can also be const. Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 15 ++++++++++++--- target/riscv/cpu.c | 25 ++++++++++++++++++++++++- target/riscv/csr.c | 2 +- target/riscv/th_csr.c | 21 +++------------------ 4 files changed, 40 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 54dc4cc85d0..679f417336c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -541,6 +541,8 @@ struct ArchCPU { const GPtrArray *decoders; }; =20 +typedef struct RISCVCSR RISCVCSR; + typedef struct RISCVCPUDef { RISCVMXL misa_mxl_max; /* max mxl for this cpu */ RISCVCPUProfile *profile; @@ -549,6 +551,7 @@ typedef struct RISCVCPUDef { int32_t vext_spec; RISCVCPUConfig cfg; bool bare; + const RISCVCSR *custom_csrs; } RISCVCPUDef; =20 /** @@ -900,6 +903,12 @@ typedef struct { uint32_t min_priv_ver; } riscv_csr_operations; =20 +struct RISCVCSR { + int csrno; + bool (*insertion_test)(RISCVCPU *cpu); + riscv_csr_operations csr_ops; +}; + /* CSR function table constants */ enum { CSR_TABLE_SIZE =3D 0x1000 @@ -954,7 +963,7 @@ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; =20 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); -void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); +void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops); =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 @@ -963,8 +972,8 @@ target_ulong riscv_new_csr_seed(target_ulong new_value, =20 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); =20 -/* Implemented in th_csr.c */ -void th_register_custom_csrs(RISCVCPU *cpu); +/* In th_csr.c */ +extern const RISCVCSR th_csr_list[]; =20 const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6f516163486..9669e9822b2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -486,6 +486,19 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 +#ifndef CONFIG_USER_ONLY +static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_= list) +{ + for (size_t i =3D 0; csr_list[i].csr_ops.name; i++) { + int csrno =3D csr_list[i].csrno; + const riscv_csr_operations *csr_ops =3D &csr_list[i].csr_ops; + if (!csr_list[i].insertion_test || csr_list[i].insertion_test(cpu)= ) { + riscv_set_csr_ops(csrno, csr_ops); + } + } +} +#endif + #if defined(TARGET_RISCV64) static void rv64_thead_c906_cpu_init(Object *obj) { @@ -512,7 +525,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); - th_register_custom_csrs(cpu); + riscv_register_custom_csrs(cpu, th_csr_list); #endif =20 /* inherited from parent obj via riscv_cpu_init() */ @@ -1310,6 +1323,11 @@ static void riscv_cpu_init(Object *obj) if (mcc->def->vext_spec !=3D RISCV_PROFILE_ATTR_UNUSED) { cpu->env.vext_ver =3D mcc->def->vext_spec; } +#ifndef CONFIG_USER_ONLY + if (mcc->def->custom_csrs) { + riscv_register_custom_csrs(cpu, mcc->def->custom_csrs); + } +#endif } =20 typedef struct misa_ext_info { @@ -2910,6 +2928,11 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , void *data) mcc->def->misa_ext |=3D def->misa_ext; =20 riscv_cpu_cfg_merge(&mcc->def->cfg, &def->cfg); + + if (def->custom_csrs) { + assert(!mcc->def->custom_csrs); + mcc->def->custom_csrs =3D def->custom_csrs; + } } =20 if (!object_class_is_abstract(c)) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 60de716a2a5..560b45d10d0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -38,7 +38,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operations *o= ps) *ops =3D csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; } =20 -void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) +void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops) { csr_ops[csrno & (CSR_TABLE_SIZE - 1)] =3D *ops; } diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c index 969a9fe3c80..49eb7bbab5f 100644 --- a/target/riscv/th_csr.c +++ b/target/riscv/th_csr.c @@ -27,12 +27,6 @@ #define TH_SXSTATUS_MAEE BIT(21) #define TH_SXSTATUS_THEADISAEE BIT(22) =20 -typedef struct { - int csrno; - bool (*insertion_test)(RISCVCPU *cpu); - riscv_csr_operations csr_ops; -} riscv_csr; - static RISCVException smode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS)) { @@ -55,20 +49,11 @@ static RISCVException read_th_sxstatus(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 -static riscv_csr th_csr_list[] =3D { +const RISCVCSR th_csr_list[] =3D { { .csrno =3D CSR_TH_SXSTATUS, .insertion_test =3D test_thead_mvendorid, .csr_ops =3D { "th.sxstatus", smode, read_th_sxstatus } - } + }, + { } }; -void th_register_custom_csrs(RISCVCPU *cpu) -{ - for (size_t i =3D 0; i < ARRAY_SIZE(th_csr_list); i++) { - int csrno =3D th_csr_list[i].csrno; - riscv_csr_operations *csr_ops =3D &th_csr_list[i].csr_ops; - if (!th_csr_list[i].insertion_test || th_csr_list[i].insertion_tes= t(cpu)) { - riscv_set_csr_ops(csrno, csr_ops); - } - } -} --=20 2.49.0