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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec366a699sm76334805e9.38.2025.04.05.09.13.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869607; x=1744474407; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ANZQVjU67KVuQJeoPfw/89aw1dlWs89ZP1DiG1XztSM=; b=lIxNC42pArGQ15dV3rf4zjzf9VftHLgSKwhsfJA1Ow0KZKLqHdtfmJpkfN5RbFEJ/w pntrEe8HI5VwL8G29PMkXjZkJC21iXUoANPJMEKgsQ18DoyEYNSlDNAeT2BYUia76t5E /jH9kQ6A7DTXAkKDTcevYyReWwANovJAELH0vKGyK+AV4/IgF+EsWJ3vfXadHcTuvDP+ m3rXPGl1ba/uBEoNXbCWsuYyMgUELsmxwa4/1RXOd9mYXYvt8ef9/Dwxmc1LycR5kUw8 Dpuq/LIE/BmNKzh/7AEm03wq9MsPS1c0EEcwsMDSS2QYVPOKmlfOgUEH6eDcxLOus16d YPhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869607; x=1744474407; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ANZQVjU67KVuQJeoPfw/89aw1dlWs89ZP1DiG1XztSM=; b=tZEcql6jTqugvyGlScjowVLh3pYts4d/NtnB/G5r+KMWkmCeKxjNLvRvX9IOowV/Qs Yo2Ac1H1t3FQjbYGSnYUQPi0jfisqHKmXum5gQ2u+j3hJNatVFzW+NmVgFKkZKLQ6b2e vZ5860JuZNUR/oBlQUpMReeo65XTgA/rsDHkG6EMRxTj7Xz+LDjutp8uLM84a5hY1zSd v7K46uiqAVxbDJdJU74oFY2WPOQGgySbXSjXTjdZXdg/CPrsSpMJw9bzRsx0WQHIx+7J bKLgg5v+Ngc11dT5o20lovoJ96XGvj3gSWzK+3BzSWzAtyXmvoCsqv+FfcQ/+PAW1m3F YBEA== X-Gm-Message-State: AOJu0YwqA+mftijFkcPGOP9pg05ml9LnSSYPppjnfTln3NJ7ncknNkrS aTQohPuDXiOYIiO6T1L9lXi187VDIvHFJFkdyHarANtGNsFBealTAoUQ8StHU6pZVLh3NP+wsrb K X-Gm-Gg: ASbGnct/qtgq6+/lLk9hf0AWQ4AVc66RSQ17mI/TpTF2AUrELAOZ5s7kTUpq7gWphYp iMpI2+hor7OShOrkwqTAsc+5R6SIrA+UwNfhMz9WzUacjGa+LG3qSHdHh822y/GQb5R4zMuWaIY EErwt9Uaq9dgm9a+IJHeDjnhRrqZnf4+Ez9BStSMS9FeqRJuZO7iTn2pqBqTnruf5CvzuiIdLqW a9NbxDDnUnRgByWdHafFvcDnWh3PYwPlE69RaMK4YdnyPZ9kk8l6oBHxeUe6xLIdkNjUnbPNpZD Y6sxek2c69qi/pK8pk2FYD3f5pv2VaP08TTT4T6SSVn/pIJbMM9eDreWg4b1c8EheGHcXtn4F2d A6i+C5999PTXJCDEUpuUqBWiZ X-Google-Smtp-Source: AGHT+IH/PdqEfYYIj7CgeMsupEBgL87K6yrRLVU6Rw4edNe4M2zhybiNogJ24e+3qXW11z7wwh+xRA== X-Received: by 2002:a5d:59ae:0:b0:39c:27cc:7ba3 with SMTP id ffacd0b85a97d-39cb35aa8ecmr6867752f8f.33.1743869606962; Sat, 05 Apr 2025 09:13:26 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 01/16] target/riscv: Remove AccelCPUClass::cpu_class_init need Date: Sat, 5 Apr 2025 18:13:05 +0200 Message-ID: <20250405161320.76854-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869646671019000 Expose riscv_tcg_ops symbol, then directly set it as CPUClass::tcg_ops in TYPE_RISCV_CPU's class_init(), using CONFIG_TCG #ifdef'ry. No need for the AccelCPUClass::cpu_class_init() handler anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/tcg/tcg-cpu.h | 2 ++ target/riscv/cpu.c | 3 +++ target/riscv/tcg/tcg-cpu.c | 16 +--------------- 3 files changed, 6 insertions(+), 15 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h index ce94253fe42..a23716a5acf 100644 --- a/target/riscv/tcg/tcg-cpu.h +++ b/target/riscv/tcg/tcg-cpu.h @@ -26,6 +26,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Err= or **errp); void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp); bool riscv_cpu_tcg_compatible(RISCVCPU *cpu); =20 +extern const TCGCPUOps riscv_tcg_ops; + struct DisasContext; struct RISCVCPUConfig; typedef struct RISCVDecoder { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ad534cee51f..2b830b33178 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3054,6 +3054,9 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, void *data) cc->get_arch_id =3D riscv_get_arch_id; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; +#ifdef CONFIG_TCG + cc->tcg_ops =3D &riscv_tcg_ops; +#endif /* CONFIG_TCG */ =20 device_class_set_props(dc, riscv_cpu_properties); } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5d0429b4d00..6a87367f239 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -139,7 +139,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->excp_uw2 =3D data[2]; } =20 -static const TCGCPUOps riscv_tcg_ops =3D { +const TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, @@ -1524,24 +1524,10 @@ static void riscv_tcg_cpu_instance_init(CPUState *c= s) } } =20 -static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) -{ - /* - * All cpus use the same set of operations. - */ - cc->tcg_ops =3D &riscv_tcg_ops; -} - -static void riscv_tcg_cpu_class_init(CPUClass *cc) -{ - cc->init_accel_cpu =3D riscv_tcg_cpu_init_ops; -} - static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 - acc->cpu_class_init =3D riscv_tcg_cpu_class_init; acc->cpu_instance_init =3D riscv_tcg_cpu_instance_init; acc->cpu_target_realize =3D riscv_tcg_cpu_realize; } --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869646; cv=none; d=zohomail.com; s=zohoarc; b=kyrAZNdJxxVQM5o12/G3K9/0+gzWF6qWuQYg7w8U2rf4j4Kfa5T3NV71OCFX9XFLV61DdSdgwfDGFhVNJ7bKLG2Vjus0TB38Sr4l21SIbLN6By2WWJmTQnEAUguDgWHfaQpVrG3bQRy8CeXEvzSpjD0QhkawFjEuYt58l52K5Bg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869646; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SfypuBuFqBrJN/RG4a0oTJgQCsI2EHmEmRAR6WvMt9k=; b=aioa4A6RWAinIsSxx7r502AS4byeSyvVo77B2d0ihcoVbKNQS5AmCO33gIgVZLJrcEVnxmKQTwcigbtoUvcZw7kplXRVorRtm3cTaRnKN2tOwyHFfXg57/+NjFSZfHATw0xUkHfwEEgySY8gL1WbXNHIbRh+4wVmNCnA+dtXsj0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869646199903.3558611100653; Sat, 5 Apr 2025 09:14:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u169K-0000VR-Kt; Sat, 05 Apr 2025 12:13:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u169H-0000V8-8K for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:13:35 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u169F-0005D1-D5 for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:13:35 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3913d129c1aso2084858f8f.0 for ; Sat, 05 Apr 2025 09:13:32 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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No need for the AccelCPUClass::cpu_class_init() handler anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/tcg/tcg-cpu.h | 4 ++++ target/i386/cpu.c | 4 ++++ target/i386/tcg/tcg-cpu.c | 14 +------------- 3 files changed, 9 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h index 7580f8afb4f..85bcd61678f 100644 --- a/target/i386/tcg/tcg-cpu.h +++ b/target/i386/tcg/tcg-cpu.h @@ -19,6 +19,8 @@ #ifndef TCG_CPU_H #define TCG_CPU_H =20 +#include "cpu.h" + #define XSAVE_FCW_FSW_OFFSET 0x000 #define XSAVE_FTW_FOP_OFFSET 0x004 #define XSAVE_CWD_RIP_OFFSET 0x008 @@ -76,6 +78,8 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state)= !=3D XSAVE_ZMM_HI256_OFF QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) !=3D XSAVE_HI16_Z= MM_OFFSET); QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=3D XSAVE_PKRU_OFFSE= T); =20 +extern const TCGCPUOps x86_tcg_ops; + bool tcg_cpu_realizefn(CPUState *cs, Error **errp); =20 int x86_mmu_index_pl(CPUX86State *env, unsigned pl); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d930ebd262e..31487f4b282 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -43,6 +43,7 @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "tcg/tcg-cpu.h" =20 #include "disas/capstone.h" #include "cpu-internal.h" @@ -8903,6 +8904,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ +#ifdef CONFIG_TCG + cc->tcg_ops =3D &x86_tcg_ops; +#endif /* CONFIG_TCG */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; #ifdef TARGET_X86_64 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 35b17f2b183..27c163d17e2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -124,7 +124,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) =20 #include "accel/tcg/cpu-ops.h" =20 -static const TCGCPUOps x86_tcg_ops =3D { +const TCGCPUOps x86_tcg_ops =3D { .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, @@ -148,17 +148,6 @@ static const TCGCPUOps x86_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 -static void x86_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) -{ - /* for x86, all cpus use the same set of operations */ - cc->tcg_ops =3D &x86_tcg_ops; -} - -static void x86_tcg_cpu_class_init(CPUClass *cc) -{ - cc->init_accel_cpu =3D x86_tcg_cpu_init_ops; -} - static void x86_tcg_cpu_xsave_init(void) { #define XO(bit, field) \ @@ -207,7 +196,6 @@ static void x86_tcg_cpu_accel_class_init(ObjectClass *o= c, void *data) acc->cpu_target_realize =3D tcg_cpu_realizefn; #endif /* CONFIG_USER_ONLY */ =20 - acc->cpu_class_init =3D x86_tcg_cpu_class_init; acc->cpu_instance_init =3D x86_tcg_cpu_instance_init; } static const TypeInfo x86_tcg_cpu_accel_type_info =3D { --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869734; cv=none; d=zohomail.com; s=zohoarc; b=Z5BsRIyTiI80SYis8FcFFO09sWpRIQ0k8HKQfO5d9Hc1FmrdUqo38u3aKK+yMbQJo6xBFJnxTjZ7CO8/wsyVAQTBEnEcYoMOXH5A6/gJKXSN0T0LwjgCXY9jSLOBAQOrcHkvvySsHh8NRgPeNEchO+46AHODPs8AuzALKp11atY= ARC-Message-Signature: i=1; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/accel/accel-cpu-target.h | 1 - accel/accel-target.c | 3 --- 2 files changed, 4 deletions(-) diff --git a/include/accel/accel-cpu-target.h b/include/accel/accel-cpu-tar= get.h index 37dde7fae3e..e983fa1dac3 100644 --- a/include/accel/accel-cpu-target.h +++ b/include/accel/accel-cpu-target.h @@ -33,7 +33,6 @@ typedef struct AccelCPUClass { ObjectClass parent_class; /*< public >*/ =20 - void (*cpu_class_init)(CPUClass *cc); void (*cpu_instance_init)(CPUState *cpu); bool (*cpu_target_realize)(CPUState *cpu, Error **errp); } AccelCPUClass; diff --git a/accel/accel-target.c b/accel/accel-target.c index 33a539b4cbb..a45a7317758 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -74,9 +74,6 @@ static void accel_init_cpu_int_aux(ObjectClass *klass, vo= id *opaque) * TCGCPUOps depending on the CPU type. */ cc->accel_cpu =3D accel_cpu; - if (accel_cpu->cpu_class_init) { - accel_cpu->cpu_class_init(cc); - } if (cc->init_accel_cpu) { cc->init_accel_cpu(accel_cpu, cc); } --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869815; cv=none; d=zohomail.com; s=zohoarc; b=BzxwpqqBeVm2QzmPySR2//H6Sq4yVIBxjIPdr0Xb2b+SWjsl0wS0xwXjFm9UN5INQukYTU/j1N8a0hjkHoXuLFqEo5bL0B3Ocm8RpMxv9E82c8yeEDAQSrnK8uujSk82OmTySufIY3q6tbRsJGTQhXNXF1WKJpMk2+rtc6Z/9+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869815; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=U3DRTmhLmbjPLSrOpbcOACaj65qViLoVjxZHvJ/pQ1o=; b=R+b8sdxBiIy0Gq26p1yfslreBAU2a7nX2vjpUJHRJFqGbTSarn0ZjQYTlpMUZjEc6S2LNaLen3pauuIsbmQAJO6brMAvfQrwioLY+fA70lSx0EbZCstxPVj42bUj9v+Z+y6XiZ16PJLnFb5VHmz7L7g2P6AryH+S1jkJjbVIW6U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869815490636.871854312012; Sat, 5 Apr 2025 09:16:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u169T-0000Wv-9j; Sat, 05 Apr 2025 12:13:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u169Q-0000W7-Sx for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:13:44 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u169O-0005Du-Bc for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:13:43 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3912fdddf8fso2542097f8f.1 for ; Sat, 05 Apr 2025 09:13:41 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Sat, 05 Apr 2025 09:13:40 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Brian Cain , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 04/16] target/hexagon: Add memory order definition Date: Sat, 5 Apr 2025 18:13:08 +0200 Message-ID: <20250405161320.76854-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869817462019100 From: Brian Cain Signed-off-by: Brian Cain Message-ID: <20250404025203.335025-7-brian.cain@oss.qualcomm.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/hexagon/cpu-param.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e743..22bffa78816 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,4 +25,9 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 +/* + * Hexagon processors have a strong memory model. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL) + #endif --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec364ec90sm76948075e9.27.2025.04.05.09.13.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869625; x=1744474425; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=22lxwaDoEwngFmE/+xTqkjd0CAM2fFfU6hC2em0g/bA=; b=nOmVKJ4zaATB7GL6dATMvWX7fxkCPbFJlqz4Hm+IEg2326ds8Odw8u5z/5DBUUJ2qo rnLz5Pu5PRE7K6N7udqmfYSw7sMq3sDKxFqWGZ4mv8wbJvK23TiqDKNTk4s7TpShu6x+ qe4YAsy1EXapo1dyA5hEDoKxBy5jmfO6ITJMGA6OxZeLPvphK9aM5IiE7tM/p01A6vQf q3LJHrZSpPzQ2lKS2G9dXbmtnCgBpGHQrRfMP/ljOgXt/pUMZhRKg6MoXOjN+il7WlGq GjqRL4d8SWiR4dRtD4jKJm/1KUs+gYxpI0S6xUSNAjX+n9qwV1yw713ebediS2ujvu3F 2qqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869625; x=1744474425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=22lxwaDoEwngFmE/+xTqkjd0CAM2fFfU6hC2em0g/bA=; b=svl7ektJqBJnKiwYy+UlnN+QvzH2qNv+nToQLKTV7CXNJpfCkWbb4QSCj2yscsM4Qi GEgQXJwWmrIxDHMMAyAuUNYkSvDFK5fdKuiJ30RL8b1FtCZ4FIlCKTtRxecFmS/odzVh y8nldheeIgVOO+XYBeOc6jTuY4YHPM2V+PkRIhZvn5/cnzeRbzkNPLg6ogs1TbKL3z8J spr+8pRGSc9mvKt9ENy0gpKukvO91DkbgV/AiF5bFKh7FgOP1hYVrhPulx2FsIX0Zxro DRP1I3LwgnRUhkdTVc8Bsiduno98nN3tP/shd8SUYnoZApXahLyyIgxmU5C3HsIdqTEi Sj9Q== X-Gm-Message-State: AOJu0YyXzRGxmCK0go5LknvQb1NRfsMWz271hkbH1x9KYPCRpETHoBTC bjnUpaAbowiYojbQ9MmFSHqlvL/YuuiZagX+LScgrRU255PZUoI1MvO2gMKkaakakkfsfIETJAO + X-Gm-Gg: ASbGncvuCnFRa+zj7ZY5RRZhrYBbrBp9mpLNq4cgvutD9rtQ+V/i53elDhOaIFFv9KA RRL+9cS2X+/ZeacJeA+qizfvzkbgBpwKl3TlX8YTXRltIWWR6FtuDcLPCjh+8L8BgSJb1Se4qrJ 0gxhbpLUvFHbTPSrzL/YJOBH2Nw1DIzdktPJy2l9IkS4Ag7AOYum8Lr8jIwHpCFT0bPZf+5TUPr sZTLkitCzr4B6fIg60AdboIYEELTcWGc+gpKapvWSaVPka5qQgFadXq6LBp37j2F0iy+mvytipo K5wg93UjFknn6v5fUNeS1tKO2jawZYpVSOjUU649+kRykJQ56wkUKIrJcHBR3WAU0cxb8bAf5NB Tv+d7XxGXsNFVGbA0FOKWiy1F X-Google-Smtp-Source: AGHT+IGSrm/mb4PJDDqFvoc7hQEWBmgUAFUhSrSe+kLbllRmaM6IX9G01WoRq3TRgZ9QBaUl3UsZRg== X-Received: by 2002:a05:600c:c0e:b0:43c:ed61:2c26 with SMTP id 5b1f17b1804b1-43ee0694e51mr34531615e9.17.1743869625214; Sat, 05 Apr 2025 09:13:45 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 05/16] tcg: Always define TCG_GUEST_DEFAULT_MO Date: Sat, 5 Apr 2025 18:13:09 +0200 Message-ID: <20250405161320.76854-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869670199019100 We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled frontends, otherwise we use a default value of TCG_MO_ALL. In order to simplify, require the definition for all targets, defining it for hexagon, m68k, rx, sh4 and tricore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/m68k/cpu-param.h | 3 +++ target/rx/cpu-param.h | 3 +++ target/sh4/cpu-param.h | 3 +++ target/tricore/cpu-param.h | 3 +++ accel/tcg/translate-all.c | 4 ---- 5 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 256a2b5f8b2..10a8d74bfa9 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -19,4 +19,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 84934f3bcaf..fe39a77ca38 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -26,4 +26,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index f328715ee86..acdf2397495 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -18,4 +18,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index eb33a67c419..45fde756b6a 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -14,4 +14,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c5590eb6955..7467255f6e4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -353,11 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; -#ifdef TCG_GUEST_DEFAULT_MO tcg_ctx->guest_mo =3D TCG_GUEST_DEFAULT_MO; -#else - tcg_ctx->guest_mo =3D TCG_MO_ALL; -#endif =20 restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869688; cv=none; d=zohomail.com; s=zohoarc; b=k77D1r/5zMBFycDez6nDXFUthlqWxxzATWsRZARvIOobQJRRc2EuOBQbT9cVDZYZQ+lkb0H6pIvOZVkmVeqRAHymA7+QNCDmGLW7lLOPGwQeKNPHq9CUT6/Z8V/crf1jwtm4K4ba9mHBy/2hohNRKvvvoNgVRT+OVQikajmvKTo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869688; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VUBhKNJ33VGc0tAXVv72Kq3hUC0BPxTHmotqIBCHglo=; b=R/BVisHWo/1m3VY6VcBVQ0ybhvRbUpC58L6Pco0OmgYZd7mNfxaYxFnqmLx6k424pawzC4gBvNkw8G6LmdyoSlq5lFEDegfxU8WGyYshF3w7hD24aCulCsQeBEDAAj7gc9M9gw29AuUjD+iYVTDwDjgGxK/1H7MFoX0lN6k1St8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869688790617.0803831410739; Sat, 5 Apr 2025 09:14:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u169b-0000Xv-6N; Sat, 05 Apr 2025 12:13:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u169Z-0000Xh-Iq for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:13:53 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u169Y-0005Er-01 for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:13:53 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3995ff6b066so1632352f8f.3 for ; Sat, 05 Apr 2025 09:13:51 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301a67b7sm7124528f8f.25.2025.04.05.09.13.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869630; x=1744474430; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VUBhKNJ33VGc0tAXVv72Kq3hUC0BPxTHmotqIBCHglo=; b=DantRVHwtu842+rh/6bFTywAsNRxAsazbIAV2AmODzxaQmlScYvOjV2N3hQcxIYFCs 8x9wjzY8O1yP5aRuV02s4eqVswoHis7X6umQ90oMqXMB/6ef4JrEPWqTKu7b1f+iT2Io yC1QXT+F5c9+/lAj7NS6gY3L+B6U1P+pHVJiP/8+DlqD4vJcEtMlGOmuQNkPtZU+VMOJ iuu+lHCqFxAxWp1tzkvGckxPywkWTDajNcr20S6pNGi5p56o1ySXIuXJspPuQEFy9lFf 5JvFuyMiaJK8QEP7mN+ksLmfnCRXz/cVv2OeNk4mx7aOo4r91QNbJHFXSj3U2yK4KHZW NR0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869630; x=1744474430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VUBhKNJ33VGc0tAXVv72Kq3hUC0BPxTHmotqIBCHglo=; b=B8+wUrfabLE3ETonLpnVyMdIQ4msMKSapVt34THv1C8XO/2YNKauafeZPNVZLPcgrS yBW0a1x0UVdkaxG0Fwu4zPIZOTqleO7uqRPT20nzTc9zvGSHgdGgDGVaqDd3hwtlywBQ YSe/BkVv15DIp2jWiNDKxQSzjHVV+gpRBakUUJF2lSR1IvyxeWBmYNfjH4Klg6sEE0s0 QZoAn0le6kEhcs5LdM2zi8aJQ2NRKhVjGq793JV+mfDXYHaAWgNE++ZidPI+qodYGVQR zArfQLqP9bc4iZqHbqToqmoDTxWr7c/+7RSMqWje5qXavqNdPvWNswvN/FzIPGAC3YAf ykcQ== X-Gm-Message-State: AOJu0YwlmWCqHISnEuFeGFM00DQbXNpuHaVUEwIcc1cdnjraEjouTmtm GEVT2KSSTTJ0c9XGTKgmmfPJQZaY8FAFUyJRCb0TWpLU57oF0pcQOF4Ozrux8ZniWCOHO/oM++U G X-Gm-Gg: ASbGncuI/1fpFtGDfs+wZtKNaXwurXAI678J5kzt1qEKyJFWwD1RR9YK0tr/+s3wVg+ yfDkuuuNYY2pxqz8xgcJAghBeGvYmxyiAUfVPIugYGWNmvBn+HJ2NrIY4IAfCk0aG3bgiSkLYqD m+sEK9GVxJhkElYxZA7p3zNgkxHuxCglV/FVHNO6keW4yeIoeYGLF/533WxhSgus/lcXzvZRyvu 34FfseIUz4o2UhVD+hJi3OtJn3K9FdWBg8rWjqkFkyncacCoHl42YeyB9+U5yCAB+j5eN4MhTFf vohhLoR5pyp3L8RaEh73mhZ5hzNfWEgP34vq9QvqnuN2KXSTwtxmBpb4J/FqMyccPXN37H3/yFQ hZDEL5EW6Y+A/TugqhulXGYuP X-Google-Smtp-Source: AGHT+IGmbs3GdNz7lwqzvWivopRAvn+yEA5dQsxptJf8E2OU/CB23zkxyl/lzjmkhuZLxj67HQqD7A== X-Received: by 2002:a5d:64cd:0:b0:391:2f15:c1f4 with SMTP id ffacd0b85a97d-39cba93d7e4mr6060196f8f.55.1743869629960; Sat, 05 Apr 2025 09:13:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 06/16] tcg: Simplify tcg_req_mo() macro Date: Sat, 5 Apr 2025 18:13:10 +0200 Message-ID: <20250405161320.76854-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869690636019000 Now that TCG_GUEST_DEFAULT_MO is always defined, simplify the tcg_req_mo() macro. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/internal-target.h | 9 +-------- accel/tcg/tcg-all.c | 3 --- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 05abaeb8e0e..1a46a7c87dc 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -52,17 +52,10 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); * memory ordering vs the host memory ordering. A non-zero * result indicates that some barrier is required. * - * If TCG_GUEST_DEFAULT_MO is not defined, assume that the - * guest requires strict ordering. - * * This is a macro so that it's constant even without optimization. */ -#ifdef TCG_GUEST_DEFAULT_MO -# define tcg_req_mo(type) \ +#define tcg_req_mo(type) \ ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) -#else -# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO) -#endif =20 /** * cpu_req_mo: diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 7a5b810b88c..a5a1fd6a11e 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -77,9 +77,6 @@ static bool default_mttcg_enabled(void) return false; } #ifdef TARGET_SUPPORTS_MTTCG -# ifndef TCG_GUEST_DEFAULT_MO -# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO" -# endif return true; #else return false; --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869716; cv=none; d=zohomail.com; s=zohoarc; b=A5Qb3Dc/rBZavPUt19i8X0KcJxQUsF4LElZo4WOoX9MZcDdBKtVaI91NDD3/JiNn+H136xX3zlVXANzdmlqMzbmWcyehdtvPhJRg6Hq+0+EAzkS3ds9DQI9lbNhd7BChTpZOuUoIIcSvT90nU7tNl2zOAyV2gUKhrj1OryAY2bY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869716; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=l6oG33dd0c008198OrmG4EKmpqvfjOdVYAYzlzpnP7o=; b=mt0S0ryg0fEIY4KA5K/sWUaRhyATTfGJS0kxUSxhY8z8ibTiuxDeGNVBHu2VE/C4v+FLuDqrIV3ecQQM+ac6zLUha16WkB3V/R+kRe6teh9o+3iFEySPuWU6ImQ4T0sGj9aW0Kg9cJqN7g14HErgW/Tn5LyEFmma2t2RM7lx4F4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869716056866.0394333872259; Sat, 5 Apr 2025 09:15:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u169g-0000Ym-UO; Sat, 05 Apr 2025 12:14:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u169f-0000YP-4I for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:13:59 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u169c-0005FJ-FO for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:13:58 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-39c13fa05ebso1746199f8f.0 for ; Sat, 05 Apr 2025 09:13:56 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec342827fsm78018465e9.6.2025.04.05.09.13.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:13:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869634; x=1744474434; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l6oG33dd0c008198OrmG4EKmpqvfjOdVYAYzlzpnP7o=; b=A7NKQvz+vtDSVHfVrmzUrywf/Qr903NEqYCtR6OQtgfQ2w72vzzbevpUyf7MlpyOOK W/HZSqiaZg/FUQqT33r9EBQEFGL2yIUiFVVcbu4q0AGEQdSCNDMNna3T9mTohIK7UjpA u4OXH9gFwB1YCksZ0wIwpDqgnOBjazsRMbSYOAZ4nRvKY3kFeBvHphw4H1Q4m/2kysm5 LN4DWVeUE6j5+3t7nGLV4v3pu23MWzmmoIPDAUAiDH3/CxnltD8/bB20aQSvV/xvoVPu +o9UvdZnLtzJURcL2vhF5JwSUKyjLoxj6CwdyYYtfXKcWH7RWl7QjZuw7pfNlo9a4eIR ZLJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869634; x=1744474434; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l6oG33dd0c008198OrmG4EKmpqvfjOdVYAYzlzpnP7o=; b=rwbcddITLXzgua5drWdRKISCt15p0KOa3UU7M5kUlmSeFaKoXKAjpPYqFJS7ZLPJ/G 5/TdYtO4Qhycddm4Yb6BMSAU4J6PRhtg2kQ2tsM7BxTjeZiqgGChHEZieaocrVO11dNd cFIj6iGy72rliGJkPPUpA9E2C4oyea9qlbYCXRuu2W6v6qmIvckgJ9GnGqBzfgXGNOzH darI3QVcAIt77ATsyNQWYY0+hYWH9xuYoszXTsrP2b4QnocknVkb5KHr5qEbQ7HZJqW4 mQzz82PpSQdLVJ/gxZmzyMJkNsB4ryMbvtCXcKEXvWTwa8++K5tR8N74upidRdwzz7nH 37ug== X-Gm-Message-State: AOJu0Yw7jlwkncbHq+RT//6rWd4EbcCrgdGkY5BSEd8PS9jgC0cHuN5E NvyK4QbLIyFg7t1Nz9gB86JtHurwF2gfrH2+lPMYDD30ZWXrpPHPyl5rhp1NmzHclXV/pJz+wi2 b X-Gm-Gg: ASbGncvAWYFORChQcxhNPMkyirjJvsrGnqZ9fhoWepdO6bbulReGxLsUDHkk6qqwJ2N 12wAZDm9wCtNmV2YzNyY7RQeklp/cM+UQhgCyBi1xuAYC+i29KgE8m3S+54Sc/WsyIT1FrlHiYu nHQMzlTJVoTsyoC7CijBuPgY7fw/Pg8tPMl1bzZpDiirFX4CVdPOiARWfOD0qdOvrFVOtlnCQl5 7OqxgITeaTxfjVXLARTkbAfZvFP6VZ5/G33iO6ortqQpljHxBfOZWUB9ywj5DJzFOKWRt0oU04+ mRFDGo5pxD34Ds6Z1uOc+BSPdI3In2P+Tndcog08CMQzA3+lTPyt5IIgvOVwJocVmBJZAvgj/NW E/PCv7s6gRx6RO+IAv3Be/H3t X-Google-Smtp-Source: AGHT+IGwJ7PMIA3NByNyxuRHG44/RJ7i+jMvzGF8vqZYCSUK9oCI4ay8Sw2byKhXhNIqBprDOmUVOg== X-Received: by 2002:a05:6000:2a0a:b0:39c:30d8:a67 with SMTP id ffacd0b85a97d-39cba93fed3mr4470295f8f.55.1743869634577; Sat, 05 Apr 2025 09:13:54 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 07/16] tcg: Define guest_default_memory_order in TCGCPUOps Date: Sat, 5 Apr 2025 18:13:11 +0200 Message-ID: <20250405161320.76854-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869717522019100 Add the TCGCPUOps::guest_default_memory_order field and have each target initialize it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/accel/tcg/cpu-ops.h | 8 ++++++++ target/alpha/cpu.c | 2 ++ target/arm/cpu.c | 2 ++ target/arm/tcg/cpu-v7m.c | 2 ++ target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 2 ++ target/i386/tcg/tcg-cpu.c | 2 ++ target/loongarch/cpu.c | 2 ++ target/m68k/cpu.c | 2 ++ target/microblaze/cpu.c | 2 ++ target/mips/cpu.c | 2 ++ target/openrisc/cpu.c | 2 ++ target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 2 ++ target/rx/cpu.c | 2 ++ target/s390x/cpu.c | 2 ++ target/sh4/cpu.c | 2 ++ target/sparc/cpu.c | 2 ++ target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 2 ++ 21 files changed, 44 insertions(+) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 106a0688da8..a4932fc5d7c 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -16,8 +16,16 @@ #include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" +#include "tcg/tcg-mo.h" =20 struct TCGCPUOps { + + /** + * @guest_default_memory_order: default barrier that is required + * for the guest memory ordering. + */ + TCGBar guest_default_memory_order; + /** * @initialize: Initialize TCG state * diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 99d839a2792..6f931117a25 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,6 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps alpha_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, .synchronize_from_tb =3D alpha_cpu_synchronize_from_tb, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c9e043bc9b5..3f20e258fd0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { =20 #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 1a913faa50f..4553fe9de07 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,6 +232,8 @@ static void cortex_m55_initfn(Object *obj) } =20 static const TCGCPUOps arm_v7m_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index feb73e722b3..67918684faf 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,6 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps avr_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ad1f303fbcf..b12e0dccd09 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -325,6 +325,7 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hexagon_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 51bff0c5d62..ac4560febea 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,6 +253,8 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hppa_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 27c163d17e2..e58084b12f6 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,8 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 const TCGCPUOps x86_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 4cc8e02f70b..ee74509a664 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,6 +864,8 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps loongarch_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 4409d8941ce..bfde9b85948 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,6 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps m68k_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, .restore_state_to_opc =3D m68k_restore_state_to_opc, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d10ae0702ad..e46863574c6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,6 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps mb_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 269d3d69bd5..860ec398229 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,6 +550,8 @@ static const Property mips_cpu_properties[] =3D { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index dc55594a7de..e62c698a407 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,6 +243,8 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps openrisc_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, .synchronize_from_tb =3D openrisc_cpu_synchronize_from_tb, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 740d8b92c0b..57565c9a2f2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7478,6 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps ppc_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, .restore_state_to_opc =3D ppc_restore_state_to_opc, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6a87367f239..832a5172ee9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,6 +140,8 @@ static void riscv_restore_state_to_opc(CPUState *cs, } =20 const TCGCPUOps riscv_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index e14d9cbef93..d7eac551fd4 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,6 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps rx_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d15b1943e0e..f232d82fa34 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,8 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } =20 static const TCGCPUOps s390_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, .restore_state_to_opc =3D s390x_restore_state_to_opc, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index df093988cb1..29f4be7ba9c 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,6 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps superh_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index af3cec43e78..ef04efcb183 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,6 +1001,8 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps sparc_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 833a93d37af..3bf399335ac 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,6 +172,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps tricore_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 51f9ee9e89a..23471064957 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,6 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps xtensa_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D xtensa_translate_init, .translate_code =3D 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7467255f6e4..c007b9a1902 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -353,7 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; - tcg_ctx->guest_mo =3D TCG_GUEST_DEFAULT_MO; + tcg_ctx->guest_mo =3D cpu->cc->tcg_ops->guest_default_memory_order; =20 restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869698; cv=none; d=zohomail.com; s=zohoarc; b=Up3LNU+QrVOmV7iIXaxJXvJR4WK8EH2Q7AEhw3T6yp27S39c2f0DjKtthI+qiWG7znF6FVi4SPEoxVAmIr4mitivXcSWGgs+iFlZ9L9dA4xkzfO6hfEVwYc/nWYA578qlKfOpOqb+28ztFPoANMEhtYZcTUJ1/el0H30lflocoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869698; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rcpj2tcbvjBZshPtyS3/CSwa5AEapPfd25KE2HwFvNA=; b=XtYuXbl+yuDpLa/g1zdqaHzS6JNyPTKqltEj3bt4V0n8t0hqR6yhHoUnxSNI+dpiCTwO0Q9YtPMXagJkv4qSAlFlm3qpIJljOokc694Vjsr7sBJ6z55HngMjDvhNdj6qHl3HFGX4uOAHI9y+qJFR8z2zRVMl8k+u51JYA9SUvLA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869698930167.64892323647234; Sat, 5 Apr 2025 09:14:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u169q-0000f1-IV; Sat, 05 Apr 2025 12:14:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u169o-0000dV-72 for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:08 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u169m-0005GK-3R for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:07 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-43cfa7e7f54so18749495e9.1 for ; Sat, 05 Apr 2025 09:14:05 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ea97904b7sm92433845e9.1.2025.04.05.09.14.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869644; x=1744474444; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rcpj2tcbvjBZshPtyS3/CSwa5AEapPfd25KE2HwFvNA=; b=BK4NVrKOqDtZrwDyb0tzZEKfn/SPg+heKRpvR3W25qbtkdevP0j9J5OAoM73y5+6DU beWjCJuGpnTkvyBY+MStlsp4D6CIBNgNd/rodhu+QI9SVxn9kefo0C5WXlmXdG5fDHhW WjUamFu9DPw1zCzEt1WIpESeRJzDF2zMeT80OQIVaB3eXxAG2NNOH6jQU42617VGZhKm ZQcID/zCXCGBWQx960VeQzLXKRBYZtnj62OOUsdQwCargYDdpijazzBsxoHGTyAUgSl7 DPOkysjL8Lpeq5eebLW4iu4Miom8myvP1OTawcW4TNdIf9hyVBx+pBEHWwkkx4hIRRcr xSLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869644; x=1744474444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rcpj2tcbvjBZshPtyS3/CSwa5AEapPfd25KE2HwFvNA=; b=XDOBRj3fr2f2u7VcYP8QQzY2fAS7qsOnQPpqILrsYxT98Up+phBqjlyfkek3tgO3L3 nFhL/qIIPHkxy954Xqv24msJxROY5hyegrolHFCv36SeV4fCENte5UbqTlHmufvmcCjU 2RTWkejCZ4g2+XJBJQE/gu18d6MrSAlgJ40PFwkcgsTlZIJjTxyqwK55KSYvI8k9Potw a8/mcYx4GEp2V1pyIJ6HQ+7eIkSdfsYE3VBrCkbcP/krCP+5BQM2Ck3hJNRZNq+z0MqS iUcZ4sxvJzZsHcwd7IgQp4DWT3l6GV/rz0SqzTnBw78uKPi554zvQaGhoPlP3nwjAExq z+5g== X-Gm-Message-State: AOJu0YxBbVqyig0v0zMkw91977dKe5v70vEYhU7mASXsSTECAqJ+EJUS g6hlkp8kRlfYwqv38mvCzweA9Hx7GOuwBrs9ldg6zmK0TZFYJ/yGDoyTIH7RbMejBbToQLlKfpz G X-Gm-Gg: ASbGncv4hxgrgaqXvP/6I/7byW7ZgclCpJhPFrebcYzAPDrD09hzgKkWq3EvWWHovBI imDU3Xq15v1XSzqcJzodGr4x+asluwtj8eX15ILipIIWa/lysCO49j7cZB4V5F3pWOXj6AJUCzw sjf5lgu0nho4X+BTm43Wg3/o7GN0qlbaGPmE+00NNppPQXTDXPGdmmuQuueS8PcXvWwBcAn+Z6o +sg/mofHhF/dq1FPQka5bajLtpU7UsalMLOgmXoK1nAVj1dkhNLSW9R6tLPCbdmelYMwKFMpl0J wOpWWBjUxQuFASVs4IVFb35TeVPuOZf2e3XqXix29M0t5Flt7LI+d0pwBJeU32ws0ntO5bcsQW2 vnyYNZbJek0CJhBKMvicxZA7O X-Google-Smtp-Source: AGHT+IH3lv5OAeYSgdqWi4iRDKK0NUPUg0dNcE4eK7rKdDILO2dd7BQYtxerzNYEtR0ednneeLZy7A== X-Received: by 2002:a05:600c:1d8e:b0:43d:fa5f:7d30 with SMTP id 5b1f17b1804b1-43ecef0230cmr65034035e9.16.1743869643651; Sat, 05 Apr 2025 09:14:03 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 09/16] tcg: Propagate CPUState argument to cpu_req_mo() Date: Sat, 5 Apr 2025 18:13:13 +0200 Message-ID: <20250405161320.76854-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869701384019100 In preparation of having tcg_req_mo() access CPUState in the next commit, pass it to cpu_req_mo(), its single caller. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/internal-target.h | 3 ++- accel/tcg/cputlb.c | 20 ++++++++++---------- accel/tcg/user-exec.c | 20 ++++++++++---------- 3 files changed, 22 insertions(+), 21 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 1a46a7c87dc..23aac39b572 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -59,12 +59,13 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); =20 /** * cpu_req_mo: + * @cpu: CPUState * @type: TCGBar * * If tcg_req_mo indicates a barrier for @type is required * for the guest memory model, issue a host memory barrier. */ -#define cpu_req_mo(type) \ +#define cpu_req_mo(cpu, type) \ do { \ if (tcg_req_mo(type)) { \ smp_mb(); \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2cafd38d2af..35b1ff03a51 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2324,7 +2324,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); tcg_debug_assert(!crosspage); =20 @@ -2339,7 +2339,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2363,7 +2363,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint32_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2384,7 +2384,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint64_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2407,7 +2407,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, Int128 ret; int first; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { @@ -2735,7 +2735,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); tcg_debug_assert(!crosspage); =20 @@ -2749,7 +2749,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, bool crosspage; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2771,7 +2771,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2792,7 +2792,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2815,7 +2815,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, uint64_t a, b; int first; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1b878ead7a7..3f4d6824460 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1061,7 +1061,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, void *haddr; uint8_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, access_type); ret =3D ldub_p(haddr); clear_helper_retaddr(); @@ -1075,7 +1075,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_2(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1093,7 +1093,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint32_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_4(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1111,7 +1111,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint64_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_8(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1130,7 +1130,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr, MemOp mop =3D get_memop(oi); =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_LOAD); ret =3D load_atom_16(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1146,7 +1146,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, { void *haddr; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, MMU_DATA_STORE); stb_p(haddr, val); clear_helper_retaddr(); @@ -1158,7 +1158,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1174,7 +1174,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1190,7 +1190,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1206,7 +1206,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, void *haddr; MemOpIdx mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34be2ffsm76593335e9.22.2025.04.05.09.14.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869649; x=1744474449; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZtZrrkt2ntmoiQ4mVP99KUX/c8Ppft+k9zep++rss8s=; b=I46AHA4SouzmJg5Q5XokUgff3TaWwwUm1mtvrksYlf2Hb+g+WG00YVgRtigmykKK4a xkoZsXk0oEZfjvaZsKOLVtUuO4k7nQN8YlLKJdpZE7rgLDTyQitJJgpMNEy5nQAu158g LqBIwnLDCftPYXKCOyWaoHlGHLH68x4xuD8g0gDD4l6ieLYvgx7zUi6V6lCjk1i9BQ5H udUkxNYww+u28zc5uGDWUnAb90v0IVucom9uT7uXV3qY3cs+btffV+B3TZEp5N2xFJwQ /PbM2x1y2pMaDMBC/k9IfbUx7zgdgxd1SeinOCAP6lFae9/EvifKVtgNnXxZbrTool5v 7vVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869649; x=1744474449; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZtZrrkt2ntmoiQ4mVP99KUX/c8Ppft+k9zep++rss8s=; b=D3oR9l8Wh05eN1uausu7Pd5QhI1jLXYhh7iEIXdvUOWeuxNw7CE2ZOyGAJ96YesAJQ TLuC5RzfdYxz4Q43JWeVM+Zx4AKa6aEq6LW/nmJF/3lQy9K3shCx3Hg3ojJjVX6Y5Zw8 kNvjNn0BN04OBk1DlQsMuc7tVdP4hsipVmwk3RHvIbIii4gPAA0vC9iBSLQFYy/GLQPD Jbdiz+U1qwSfZoCurCqMwCEtiVyFJeLK9+0t7/otOhqgIzLuKVjB1mpwRcKiXsHRUsWc i1iAg/Z6BSMG3GLMBVQ6LihrKz7q49Kt+P5ixmXWqSFjE66HOg1IN29mBLmXstSZHLjx Eafw== X-Gm-Message-State: AOJu0YxMLOiWQ5Z5LfS2St1OPPUz6ATwTmTcHYMmxzwErXt8o+ZnSqU9 PhyjcTG8mdQ/H3sfWqMRcHBca9HnpSzGKA5XLhvBl0dXxxvY6YiF6U5+yMAe+EDQQcW7IkE5+tb L X-Gm-Gg: ASbGncs4Bip8ykZ+Y1GI6eLmfconuhVB+GAVWbKESWasiwbc31MMta1tQ/3bQI3yAkG Jz9uG+ALZqzRuz2qReC9yHKBwcan4bLemtVR4fCEHybuL4Oud8YAFxcR4QDe/3NADR/YkfQgmTI NmGon4en1LyMqcAvwfF/iDX2kWqUiufciYBnIrOfzL7/rWkw9G+2L0hbIgXRXVBgWiIu49Mi9Ft j0t7t7RYCOy0uVV4HtAExLPMsL+ECHW0hPsCJQMd+4qfwB3tOpM74obFrfSbLS+wkqVCRe3jc9R YOLNKYLHmISLdyvf0SpjBHTaq+aT19PbL6y9qCapwJt0y95LSWDm6ZJNYSQpbQ1ZC6COjiuefOV BswJwDxQG1hM1byjXzYDdFc0G X-Google-Smtp-Source: AGHT+IGRxjjryaIQqVRYRdbKj/EpsAJKimNz9sl47phK88XbFx96DIzwGFO4T0fcTj0m+BFwieolhg== X-Received: by 2002:a05:600c:35d6:b0:439:91dd:cf9c with SMTP id 5b1f17b1804b1-43ecf85db98mr77995345e9.10.1743869648798; Sat, 05 Apr 2025 09:14:08 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 10/16] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order Date: Sat, 5 Apr 2025 18:13:14 +0200 Message-ID: <20250405161320.76854-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869673162019100 In order to use TCG with multiple targets, replace the compile time use of TCG_GUEST_DEFAULT_MO by a runtime access to TCGCPUOps::guest_default_memory_order via CPUState. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/internal-target.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 23aac39b572..f5a3fd7e402 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -46,16 +46,15 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); =20 /** * tcg_req_mo: + * @guest_mo: Guest default memory order * @type: TCGBar * * Filter @type to the barrier that is required for the guest * memory ordering vs the host memory ordering. A non-zero * result indicates that some barrier is required. - * - * This is a macro so that it's constant even without optimization. */ -#define tcg_req_mo(type) \ - ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) =20 /** * cpu_req_mo: @@ -67,7 +66,7 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t= retaddr); */ #define cpu_req_mo(cpu, type) \ do { \ - if (tcg_req_mo(type)) { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)= ) { \ smp_mb(); \ } \ } while (0) --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869806; cv=none; d=zohomail.com; s=zohoarc; b=b+QGkb0YKUs7Oy+GB0UAx5MVFoDjA/bLpKZWLQmeE1B3C33/cCYozzOIqpeJbLSfSQ++IwsPI9eXq8vUY4614xsxmeKPcfCwdHff4vclQVZq9VhtKEZT0AV9SRkwHzcHID+gOWM6ErH+6OKtAgq5QPnp1T39B843npwK4Q9iSIo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869806; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jbeIlrtLd2jXBN6pnVLjy0Ez8TgEHAsNX4HbXOjA0NA=; b=nivhrT7LwtzFwW917VHdM+d4dMxvpZxQegIi8k6hVmuDWcwNxMtJAwZ17WgcRMkn5atU0HbHE+MFdbaM2eLXp70UIgKUFp/eSE9bogPa6cUbI3fO4tuFjaY0lI8NxDaKCZXKJT2WNFd58LDubncyqGuErIOSzyNEbduoJ1CBclI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17438698064801009.9193184334907; Sat, 5 Apr 2025 09:16:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u16A2-0000mL-Re; Sat, 05 Apr 2025 12:14:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u16A0-0000l1-9c for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:20 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u169x-0005HJ-1H for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:19 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-39ac8e7688aso2268296f8f.2 for ; Sat, 05 Apr 2025 09:14:15 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- docs/devel/multi-thread-tcg.rst | 4 ++-- include/exec/poison.h | 1 - target/alpha/cpu-param.h | 3 --- target/arm/cpu-param.h | 3 --- target/avr/cpu-param.h | 2 -- target/hexagon/cpu-param.h | 5 ----- target/hppa/cpu-param.h | 8 -------- target/i386/cpu-param.h | 3 --- target/loongarch/cpu-param.h | 2 -- target/m68k/cpu-param.h | 3 --- target/microblaze/cpu-param.h | 3 --- target/mips/cpu-param.h | 2 -- target/openrisc/cpu-param.h | 2 -- target/ppc/cpu-param.h | 2 -- target/riscv/cpu-param.h | 2 -- target/rx/cpu-param.h | 3 --- target/s390x/cpu-param.h | 6 ------ target/sh4/cpu-param.h | 3 --- target/sparc/cpu-param.h | 23 ----------------------- target/tricore/cpu-param.h | 3 --- target/xtensa/cpu-param.h | 3 --- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 3 ++- target/arm/tcg/cpu-v7m.c | 3 ++- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 5 ++++- target/hppa/cpu.c | 8 +++++++- target/i386/tcg/tcg-cpu.c | 5 ++++- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 3 ++- target/s390x/cpu.c | 6 +++++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 23 ++++++++++++++++++++++- target/tricore/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- 41 files changed, 68 insertions(+), 104 deletions(-) diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.= rst index b0f473961dd..14a2a9dc7b5 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -28,8 +28,8 @@ vCPU Scheduling We introduce a new running mode where each vCPU will run on its own user-space thread. This is enabled by default for all FE/BE combinations where the host memory model is able to accommodate the -guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the -guest has had the required work done to support this safely +guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is z= ero) +and the guest has had the required work done to support this safely (TARGET_SUPPORTS_MTTCG). =20 System emulation will fall back to the original round robin approach diff --git a/include/exec/poison.h b/include/exec/poison.h index a09e0c12631..0f336cdc618 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -37,7 +37,6 @@ #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN -#pragma GCC poison TCG_GUEST_DEFAULT_MO #pragma GCC poison TARGET_HAS_PRECISE_SMC =20 #pragma GCC poison TARGET_LONG_BITS diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index dd44feb1793..a799f42db31 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -26,7 +26,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* Alpha processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 2cee4be6938..5c5bc8a009e 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -44,7 +44,4 @@ */ #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -/* ARM processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 9d37848d97d..f74bfc25804 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -27,6 +27,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 22bffa78816..635d509e743 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,9 +25,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* - * Hexagon processors have a strong memory model. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL) - #endif diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 68ed84e84af..9bf7ac76d0c 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -21,12 +21,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -/* PA-RISC 1.x processors have a strong memory model. */ -/* - * ??? While we do not yet implement PA-RISC 2.0, those processors have - * a weak memory model, but with TLB bits that force ordering on a per-page - * basis. It's probably easier to fall back to a strong memory model. - */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 0c8efce8619..ebb844bcc83 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,7 +24,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* The x86 has a strong memory model with some store-after-load re-orderin= g */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index dbe414bb35a..58cc45a377e 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -15,6 +15,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 10a8d74bfa9..256a2b5f8b2 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -19,7 +19,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 5d55e0e3c4a..e0a37945136 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -29,7 +29,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* MicroBlaze is always in-order. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 99ca8d1684c..58f450827f7 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -22,6 +22,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 7ea0ecb55a6..b4f57bbe692 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -14,6 +14,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index d0651d2ac89..e4ed9080ee9 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -39,6 +39,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index ff4ba81965a..cfdc67c258c 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -34,6 +34,4 @@ * - M mode HLV/HLVX/HSV 0b111 */ =20 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index fe39a77ca38..84934f3bcaf 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -26,7 +26,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index a8a4377f4ff..abfae3bedfb 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -14,10 +14,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -/* - * The z/Architecture has a strong memory model with some - * store-after-load re-ordering. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index acdf2397495..f328715ee86 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -18,7 +18,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 62d47b804bb..45eea9d6bac 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -23,27 +23,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* - * From Oracle SPARC Architecture 2015: - * - * Compatibility notes: The PSO memory model described in SPARC V8 and - * SPARC V9 compatibility architecture specifications was never implemen= ted - * in a SPARC V9 implementation and is not included in the Oracle SPARC - * Architecture specification. - * - * The RMO memory model described in the SPARC V9 specification was - * implemented in some non-Sun SPARC V9 implementations, but is not - * directly supported in Oracle SPARC Architecture 2015 implementations. - * - * Therefore always use TSO in QEMU. - * - * D.5 Specification of Partial Store Order (PSO) - * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. - * - * D.6 Specification of Total Store Order (TSO) - * ... PSO with the additional requirement that all [stores] are followed - * by an implied MEMBAR #StoreStore. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) - #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 45fde756b6a..eb33a67c419 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -14,7 +14,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index e7cb747aaae..7a0c22c9005 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -18,7 +18,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 6f931117a25..eeaf3a81c1a 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,7 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps alpha_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* Alpha processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3f20e258fd0..3e9760b5518 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,7 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { =20 #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* ARM processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 4553fe9de07..89d4e4b4a2f 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,7 +232,8 @@ static void cortex_m55_initfn(Object *obj) } =20 static const TCGCPUOps arm_v7m_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* ARM processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 67918684faf..8f79cf4c08b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,7 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps avr_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b12e0dccd09..e54f10c2294 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -325,7 +325,10 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hexagon_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * Hexagon processors have a strong memory model. + */ + .guest_default_memory_order =3D TCG_MO_ALL, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ac4560febea..dfbd9330565 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,7 +253,13 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hppa_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* PA-RISC 1.x processors have a strong memory model. */ + /* + * ??? While we do not yet implement PA-RISC 2.0, those processors have + * a weak memory model, but with TLB bits that force ordering on a per= -page + * basis. It's probably easier to fall back to a strong memory model. + */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e58084b12f6..5295fcea5c3 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,7 +125,10 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 const TCGCPUOps x86_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * The x86 has a strong memory model with some store-after-load re-ord= ering + */ + .guest_default_memory_order =3D TCG_MO_ALL & ~TCG_MO_ST_LD, =20 .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ee74509a664..f5b8ef29ab0 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,7 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps loongarch_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index bfde9b85948..b2d8c8f1dea 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,7 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps m68k_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index e46863574c6..4efba0dddb2 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,7 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps mb_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MicroBlaze is always in-order. */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 860ec398229..010773405a8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,7 +550,7 @@ static const Property mips_cpu_properties[] =3D { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e62c698a407..87fe779042c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,7 +243,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps openrisc_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 57565c9a2f2..8300fa5777e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7478,7 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps ppc_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, .restore_state_to_opc =3D ppc_restore_state_to_opc, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 832a5172ee9..e146c76e6aa 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,7 +140,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } =20 const TCGCPUOps riscv_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index d7eac551fd4..f073fe8fc98 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,7 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps rx_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index f232d82fa34..1e101b5afeb 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,7 +345,11 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *p= c, } =20 static const TCGCPUOps s390_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * The z/Architecture has a strong memory model with some + * store-after-load re-ordering. + */ + .guest_default_memory_order =3D TCG_MO_ALL & ~TCG_MO_ST_LD, =20 .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 29f4be7ba9c..7a05301c6ff 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,7 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps superh_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ef04efcb183..56d9417ae3f 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,7 +1001,28 @@ static const struct SysemuCPUOps sparc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps sparc_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * From Oracle SPARC Architecture 2015: + * + * Compatibility notes: The PSO memory model described in SPARC V8 a= nd + * SPARC V9 compatibility architecture specifications was never + * implemented in a SPARC V9 implementation and is not included in t= he + * Oracle SPARC Architecture specification. + * + * The RMO memory model described in the SPARC V9 specification was + * implemented in some non-Sun SPARC V9 implementations, but is not + * directly supported in Oracle SPARC Architecture 2015 implementati= ons. + * + * Therefore always use TSO in QEMU. + * + * D.5 Specification of Partial Store Order (PSO) + * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadSt= ore. + * + * D.6 Specification of Total Store Order (TSO) + * ... PSO with the additional requirement that all [stores] are fol= lowed + * by an implied MEMBAR #StoreStore. + */ + .guest_default_memory_order =3D TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_S= T_ST, =20 .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 3bf399335ac..c68954b4096 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,7 +172,8 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps tricore_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 23471064957..2cbf4e30108 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,7 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps xtensa_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* Xtensa processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869734; cv=none; d=zohomail.com; s=zohoarc; b=KGM02MVh/O5CSJMh0npAyTP9wIHARdQQUeq8P3YfqzzilvhGhDcZW7VoBUYZKhq0YjkiIgzzE4KIcy7rjkcUGyVWBe8HDKl49bc+lUrmpaYXZaGWm9z/44K5G/x00ACcsrPHy0OCf9xy8V2GyAP2pgnZULXjPDaL/dBlfYQVsYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869734; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FyHyqUVPAmJjyMO6Sr/Bf3FWzhnRIjw+jQa7gHGhFEQ=; b=KZaqg2plIFbRKG/mG32FFSnQfldjmhtEUvt+fwxB7I/4k4CfsQwbzXPJzo06ux0VwjO6iXJPg/pvx1RF1K1RYUEBmnzpPkNV8eEQxyXCKa08EQ1CRcXFaPRfUUFgrhSaRXGvUe9tQpXwutgVMjY3cqhZp8RzPHctSpBkafNY3/Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869734912260.35811905800074; Sat, 5 Apr 2025 09:15:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u16AA-00010A-LX; Sat, 05 Apr 2025 12:14:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u16A2-0000m7-Gm for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:22 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u16A0-0005Hl-Jk for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:22 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-43cf06eabdaso27241035e9.2 for ; Sat, 05 Apr 2025 09:14:20 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec364ec90sm76959905e9.27.2025.04.05.09.14.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869659; x=1744474459; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FyHyqUVPAmJjyMO6Sr/Bf3FWzhnRIjw+jQa7gHGhFEQ=; b=OK49d9lX1FT+kF/t7hLHhGBWOtCoFzzT3nzIdmQZn/xsbpL353eFtTxaP5dxsTotdw ae6iPvcIdY7UEebcbg/CFmbYkF3Ujm1jAurpfF10u6Uue7AWq8IZnuOZQxgkweIriiWI 1zBqe/V3EatRrOn5dxTUbgM1bwdl+fsjf7vvbWsp6ds/KndjWWESC65RqOz/oRMres83 qbhqwtuEB+KWiZaECqt4P4C7eTXI4Sw8Yz3YAjPz4M4Jxlryk8/qu9ve1Jqio1AIp7mh +elM460bQYaVaVjtJv9HA5ozQfBj4PQcitg1Ehh0GJjYB4uHTK5M1yQ6bRfoXOzWpu0f A6YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869659; x=1744474459; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FyHyqUVPAmJjyMO6Sr/Bf3FWzhnRIjw+jQa7gHGhFEQ=; b=xTY8psDI18MkryqK4hKDEn5eotDHqXknmadbmEmL1pONxeNE2yaELMkDkmwxH6LXUs nN2hyxZWXrp3ftH1aTfugwjYWhVjVPeeC+7R0a+iLOeu+E4AYeeX6edIoD2TNlHfdD25 FFj8BScbDx7/nzokhetZfn6wdgCcgGbN/1viPxIkojvISOWWt3oFEPBbsVPBpylAvsBe Lszv/PHs5SWMil/sMOsy32to2U2WK6GpdeaJzogpuPKuYsgBW+GZOoNZMbaeS1G+pJuw tS9BYC4ZTkF1qo9dwe4UuRPr7jgOtcH50cDSm/PRe3hZx6wk8ZJXnt1XykgOCmo9PTVk YNtg== X-Gm-Message-State: AOJu0Yx3yLnaq998YwkWGaqjz89qwbG4N5c40mBK7CBJNOQOx9lTuFeL ad+uZ1Y2p9wAa9wepi86B84PFxe1QBSP+z7DjIqy0Hhga1xBpwsLme29ByXngmDwIr/SzYc/MWh l X-Gm-Gg: ASbGncujN5ZKH30o18HZKl7OBSxfh+4dyA4O0v1rYbSQm9SDrGoYrh7SFBZEDRMdwW2 Irv0DgxBUothE3pGtN15vODbYAFfqRXNv+XZ+qfr0DgDq5zuZW4riaVFGttTCjqUSozeYLRsY2B EtKdhpQ18mFin+1d8WaHg6x+Ya5nnmHZdReWZtFTKqS4KP4TaYIVWUECTItlWwR2rTl0pfmk8WP KL60qkHeG30k7nPvPqi6sr7K/tpvzzxlqfg7rPGdb7WGdu69QJU+welE+rTXvmAo9GIJ51XNtVu 0tucXADYBIc53L8ozLnO4ibQlfhle45BA44Io/KzEQ9lIhSeXY4YdrC8NfozsEOKwF1SJZ6/NLo kJyiqTVPjDxp9gIC9WrJ0+Bz0 X-Google-Smtp-Source: AGHT+IG1xYrq95nrV5Lt4x7VkObg0TZgbj0CZhbN9dRZGD9iDg1LNG9y4exR3qA6QwdjEcoB7CW3Rw== X-Received: by 2002:a05:600c:a07:b0:43c:fb95:c752 with SMTP id 5b1f17b1804b1-43ecf843e91mr78422055e9.3.1743869658654; Sat, 05 Apr 2025 09:14:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 12/16] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Date: Sat, 5 Apr 2025 18:13:16 +0200 Message-ID: <20250405161320.76854-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869737337019100 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/backend-ldst.h | 41 +++++++++++++++++++++++++++++++++++++ accel/tcg/internal-target.h | 28 ------------------------- accel/tcg/cputlb.c | 1 + accel/tcg/user-exec.c | 1 + 4 files changed, 43 insertions(+), 28 deletions(-) create mode 100644 accel/tcg/backend-ldst.h diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h new file mode 100644 index 00000000000..9c3a407a5af --- /dev/null +++ b/accel/tcg/backend-ldst.h @@ -0,0 +1,41 @@ +/* + * Internal memory barrier helpers for QEMU (target agnostic) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_BACKEND_LDST_H +#define ACCEL_TCG_BACKEND_LDST_H + +#include "tcg-target-mo.h" + +/** + * tcg_req_mo: + * @guest_mo: Guest default memory order + * @type: TCGBar + * + * Filter @type to the barrier that is required for the guest + * memory ordering vs the host memory ordering. A non-zero + * result indicates that some barrier is required. + */ +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) + +/** + * cpu_req_mo: + * @cpu: CPUState + * @type: TCGBar + * + * If tcg_req_mo indicates a barrier for @type is required + * for the guest memory model, issue a host memory barrier. + */ +#define cpu_req_mo(cpu, type) \ + do { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)= ) { \ + smp_mb(); \ + } \ + } while (0) + +#endif diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index f5a3fd7e402..9a9cef31406 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -13,7 +13,6 @@ #include "exec/exec-all.h" #include "exec/translation-block.h" #include "tb-internal.h" -#include "tcg-target-mo.h" #include "exec/mmap-lock.h" =20 /* @@ -44,31 +43,4 @@ void page_table_config_init(void); G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); #endif /* CONFIG_USER_ONLY */ =20 -/** - * tcg_req_mo: - * @guest_mo: Guest default memory order - * @type: TCGBar - * - * Filter @type to the barrier that is required for the guest - * memory ordering vs the host memory ordering. A non-zero - * result indicates that some barrier is required. - */ -#define tcg_req_mo(guest_mo, type) \ - ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) - -/** - * cpu_req_mo: - * @cpu: CPUState - * @type: TCGBar - * - * If tcg_req_mo indicates a barrier for @type is required - * for the guest memory model, issue a host memory barrier. - */ -#define cpu_req_mo(cpu, type) \ - do { \ - if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)= ) { \ - smp_mb(); \ - } \ - } while (0) - #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 35b1ff03a51..d9fb68d7198 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -48,6 +48,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" =20 =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f4d6824460..5eef8e7f186 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -37,6 +37,7 @@ #include "qemu/int128.h" #include "trace.h" #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" #include "internal-common.h" #include "internal-target.h" #include "tb-internal.h" --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869741; cv=none; d=zohomail.com; s=zohoarc; b=TwyRci6oGgT2buTkOAQpUZ1d4HzWJp+23RIuPM42uLConrkJuViUbzjrXiiNDm16H/+G9O6OMC4/bhWEsiRp3XJVNn9ovFXaH/JqpOQsOBQHRe/t3P+Xagx5/jNzqXTWw9oT9IInkS2YihVv+buu3vuAiYlhO76W/dtMI74uyGI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869741; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=G/LTVfYsOIJ5re5/xeDsdKiBrQeXn6HocLb4nBW7R3Q=; b=Ek59FXPDFhLNF0z1/HOfPsw68/saLe01VjXWmBiY8G8CuPsZ+eQp9rkK8Zv2tz4kifgXC4YbHcxbD0bW9YIhib2cxTaoY0sBDq1bbA+TXlwH2GC2+qwUVFkQw1MyAzmzxicjvqiLww+846DX7G0YLzpKWIthIVgbmOYBEUFKSWY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869741431137.78922364599237; Sat, 5 Apr 2025 09:15:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u16AE-0001CW-2X; Sat, 05 Apr 2025 12:14:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u16A8-00010U-Gn for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:29 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u16A6-0005IJ-MF for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:28 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-39c1efc457bso1760124f8f.2 for ; Sat, 05 Apr 2025 09:14:25 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec17b3572sm80270355e9.39.2025.04.05.09.14.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869664; x=1744474464; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G/LTVfYsOIJ5re5/xeDsdKiBrQeXn6HocLb4nBW7R3Q=; b=gqf/1rffEbG3fBdaHZNEBsUSwuEGRxoI6+eYZlHwSicK2s6r49J0+vxdXs1YBNdvFY XAglZtH9ZCdSBOvAX1mXWkujoOQeXE9PNDPoXl+pb9pKzWSHFP0cGksUV0Tw/z1ky4za JGtZVvoO1VCIYBOPrxDeEVVylI90bRFj8sPoxUm7sIlbAtGDHKue9Bg9Ihoy9NPiuD3E ZNWaucWivGTRisxhW2+PbsQ63b2/qjVFk45pkl1tOGCMfwJ96+ezemEN1WppWm/ZKmyW Sld9nPsgmUGflIW5sHqPMVKCot2CbA1buegF8LeeQ9XHs8O92jBQ9gLxTKhx1ronHLDB Qm4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869664; x=1744474464; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G/LTVfYsOIJ5re5/xeDsdKiBrQeXn6HocLb4nBW7R3Q=; b=Lrfv7dzS5m0e0NDlFxnW8jPiJRzVKgH4BkXyrgQDtr9n2yfvbo8FjEkaIeldIBgeCa sRAUr1ZIS1NPc6DPynWfbNeRkr4zeXhTZfmHbymOFC6LMcKxqxRkeojuPsc+w6DoJwrp vzUFWNNeLpeKCqvfVZBvcd6Meijver5IJ2FjBFmSk9Rb/BGbH4aHf8jfDgS3sJgIV9yI UyLXnSashdexBf5Ala2EBfcGO9IXJ64kE50dWi0qTz3NZkRbF1noPPh7Qu3qLjDU7cPa NfwHKbmmLn60uX16YZ9VIS8dE0kKZ0S0G530h2Fidsrwf8mFRvZNKfbUuVqwb1gFsQcD nE8g== X-Gm-Message-State: AOJu0YxOQ2hnt33lo6LDH3DimD4BoYjv5AcAQ1WhqisnhJJVfiLA2VyQ PrT4Ld+xINSikXHSKeX0H0/DAKuzkGldm2cp2jPAqv3SfOfmilkc72/nTeDx8X8Bg3mRfQ7EwRD J X-Gm-Gg: ASbGncuYOq8lq9FUvLzi5NXWACwf80Z+k63pl9XxcQHOWfG7nxLXUgo5dn9eDTxTlDg 1yWZY6xdjvCxjrXtaYGRjnI6i1i4ctbGyIil3n2Z3Hv+QFV7GyKyC5LfKVq3+PSM/t80Lcu6AfZ eiW/9oiIHrwPp1qay+6zkD1mTfmwYn24CUYXdUohsUxu7JfUBeqrBrLlz92ol9VI7CuxyUnFfj7 j3FWWvwAnZ5D5j56+hm3KJrLvhqJpf/yTE5/vynpjAp+4JipN1aZfxipq/6IxJYRKAWGrUADKRb Qg/KOHV0jifVSBv8Cz+fZEezWXQTapG1u1W2XnQQgNvxMTbxlSD1UHnGlie7PZ/Ik/z+gN+7NLQ N0P7fdIs038kUeBRK9zxkpB6a X-Google-Smtp-Source: AGHT+IFKOYw0um4cvwg8CFrVDq63ghBopicARmqwLR0mGQkHnCBFWSNo4vFO189tXh3Zu6xkULuBpg== X-Received: by 2002:a05:6000:440e:b0:39c:266c:d82 with SMTP id ffacd0b85a97d-39cb3575971mr4271768f8f.10.1743869664362; Sat, 05 Apr 2025 09:14:24 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 13/16] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Date: Sat, 5 Apr 2025 18:13:17 +0200 Message-ID: <20250405161320.76854-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869742808019000 qemu_tcg_mttcg_enabled() is specific to 1/ TCG and 2/ system emulation. Move the prototype declaration to "system/tcg.h", reducing 'mttcg_enabled' variable scope. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 9 --------- include/system/tcg.h | 8 ++++++++ accel/tcg/tcg-all.c | 16 ++++++++++++++-- target/riscv/tcg/tcg-cpu.c | 1 + tcg/region.c | 4 +++- 5 files changed, 26 insertions(+), 12 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 10b6b25b344..c8d6abff19a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,15 +594,6 @@ extern CPUTailQ cpus_queue; =20 extern __thread CPUState *current_cpu; =20 -/** - * qemu_tcg_mttcg_enabled: - * Check whether we are running MultiThread TCG or not. - * - * Returns: %true if we are in MTTCG mode %false otherwise. - */ -extern bool mttcg_enabled; -#define qemu_tcg_mttcg_enabled() (mttcg_enabled) - /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/include/system/tcg.h b/include/system/tcg.h index 73229648c63..7622dcea302 100644 --- a/include/system/tcg.h +++ b/include/system/tcg.h @@ -17,4 +17,12 @@ extern bool tcg_allowed; #define tcg_enabled() 0 #endif =20 +/** + * qemu_tcg_mttcg_enabled: + * Check whether we are running MultiThread TCG or not. + * + * Returns: %true if we are in MTTCG mode %false otherwise. + */ +bool qemu_tcg_mttcg_enabled(void); + #endif diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index a5a1fd6a11e..b8874430d30 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -38,6 +38,7 @@ #include "hw/qdev-core.h" #else #include "hw/boards.h" +#include "system/tcg.h" #endif #include "internal-common.h" #include "cpu-param.h" @@ -58,6 +59,17 @@ typedef struct TCGState TCGState; DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, TYPE_TCG_ACCEL) =20 +#ifndef CONFIG_USER_ONLY + +static bool mttcg_enabled; + +bool qemu_tcg_mttcg_enabled(void) +{ + return mttcg_enabled; +} + +#endif /* !CONFIG_USER_ONLY */ + /* * We default to false if we know other options have been enabled * which are currently incompatible with MTTCG. Otherwise when each @@ -97,7 +109,6 @@ static void tcg_accel_instance_init(Object *obj) #endif } =20 -bool mttcg_enabled; bool one_insn_per_tb; =20 static int tcg_init_machine(MachineState *ms) @@ -107,10 +118,11 @@ static int tcg_init_machine(MachineState *ms) unsigned max_cpus =3D 1; #else unsigned max_cpus =3D ms->smp.max_cpus; + + mttcg_enabled =3D s->mttcg_enabled; #endif =20 tcg_allowed =3D true; - mttcg_enabled =3D s->mttcg_enabled; =20 page_init(); tb_htable_init(); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e146c76e6aa..44fdf6c4cf1 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" +#include "system/tcg.h" #endif =20 /* Hash that stores user set extensions */ diff --git a/tcg/region.c b/tcg/region.c index 478ec051c4b..56d2e988719 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -34,7 +34,9 @@ #include "exec/translation-block.h" #include "tcg-internal.h" #include "host/cpuinfo.h" - +#ifndef CONFIG_USER_ONLY +#include "system/tcg.h" +#endif =20 /* * Local source-level compatibility with Unix. --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869750; cv=none; d=zohomail.com; s=zohoarc; b=Oj1/6RzHtBqBdHRk/kB/PNr+YmAsLiJRVBzv6/vItAWqg2XpubPjEp/KWeCQWaw7rfTCgBmpgIAfnoC6AyHiM8KPrPpO0O4BnEXD7+v0VBAE4Kg7wco/moup/IUTWVAE/v7szrSyK7uDrOCUkEI7nqnMB8YwYLSMpaHRZWBRXqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869750; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WxLf1qzYlIt55rERNGlTsLbACYfcGvHkqll/jBxBAw0=; b=iALQhQl95GZBONez7vVESE+V28b7Fp8EWTlPjD/BXi4qwnHoFWYT4vzpxrB9IOgMcjFaQ6+GNokzNckzUKWBXVI6ivXK8SJfq+3dgsNjquNSwPGNb+ASWI0Wc/468RT9vNzRexsd9Rv2SR7MFZ/oV3nceHRtlIAGX2dO3J4R8K8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869750015535.4245278783659; Sat, 5 Apr 2025 09:15:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u16AG-0001Pw-TJ; Sat, 05 Apr 2025 12:14:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u16AD-0001Cc-LG for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:33 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u16AB-0005Is-Se for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:33 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-43cfe574976so20278825e9.1 for ; Sat, 05 Apr 2025 09:14:31 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1630de9sm79905905e9.1.2025.04.05.09.14.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869670; x=1744474470; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WxLf1qzYlIt55rERNGlTsLbACYfcGvHkqll/jBxBAw0=; b=Ez0pbWsaUQeVmAt9Uk40HXZpmgmhQvKn/9W+E3QOOzU7E85awwFswKecp8WdOe3ykF fimhQrxZJAjynvs9ebJfUx4VHZQt0QHj7SktMywuMPSRA31iAnX7AkjISByavi16QMbQ rDnyIvqyHZFtxQXzFGY77mPv59eO2VNPTfYBTrNbhn+KkxQsuF4Yo8gJ1gyo2nSXWgW9 hngaviN7jami2TwDSWx15wUErGX73TChkgmrDGj5cm5hDN1cJLN4ZcoB31XayWtUYhzr iWipUEeuqc+te+idQGFfMiqjgECGHkRB1jmBRmeBjyall/SLv96lSy8uVIoHqxGkxLct oGXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869670; x=1744474470; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WxLf1qzYlIt55rERNGlTsLbACYfcGvHkqll/jBxBAw0=; b=VY+Y/pMS/P+dpywdIYy/Z5SrEVBZoq9U0Mdb+hfBUvxH6CO1agv3EXRSrMZSoE8jT7 4NiGUaGfJGyQZgz78KzAYSPy8PUvZjonBdnqeX7mUzJECglTOkoBQ0y4vRkk5Ng7W9Tt EaEUfqJrQfA6WeKB9k9F70xEx2wOa0X/E2zCrzW/g3B3G11PzRSISe6m/IhEteGuowLP TVsvLL9kDS2iyYuElGNX9KYRW2goWR8MS8mpZ0y4Zgx0mY56m4wBTo/J2KbltmpV8kMz wcCzoOR2sY3H7G4hydfFwVOI+L/FeEcXqi6gYBvA+4YLOwPjNOo1dudWZvrmTv7qMwRq f9Iw== X-Gm-Message-State: AOJu0Yxdpoatl3gtJhp1oYLRtJdaVKFtMRCIkpoXIbMYW8/4uvLLy9Yo Bl49xqyGGga0nnxBkCzJTCrYScjbkpaPE6LcfCifr0gJT81Zm/X5hYQKUKk54PYI4Eauyf8sxDz W X-Gm-Gg: ASbGncuzyx++Tns9SFqvXNSSLS7A8OQZOl2SU7MrIktw0B+rW0yVNCT77KqIk++mA/t wgzHgGLXXPj1BfgQykRJ6/3TAOqAoNggwjFhjfGSCtkw8A2FHn8pMKu21MVIiQqDlsx4bPdIqzn kC0AE9FgWjH1VzKpmbvy2YTkjnDl8HpEJLwsB4eMjutfwxa7iLx8eDPCezKtQVRW2dwhJJgtBlx YNHNSJlUHTVNDGirCuKZ7GB3i9oiDYxXQR9vNmCfeTkJ48KN9iV1SBS97Cx8LUIT5TtyGvK4e4H NCd/BVkkHsKbvBygbf9ZYIDrSzwnSjIE0qSA57703JcbuSaIvmYO+XGDHBhLAAll98JwJtSjHsS 4twYYH8QYnIa8SG+K22B4TumJ X-Google-Smtp-Source: AGHT+IHwMl71qxKC7xyYfvRdL+hL2VXjUKCRU0Gacm10ZstFUEus151D3Ek3ipHqZmceQFGwUibwUg== X-Received: by 2002:a05:600c:b89:b0:43d:7413:cb3e with SMTP id 5b1f17b1804b1-43ecf81bb90mr61366455e9.1.1743869669840; Sat, 05 Apr 2025 09:14:29 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH-for-10.1 v4 14/16] tcg: Convert TCGState::mttcg_enabled to TriState Date: Sat, 5 Apr 2025 18:13:18 +0200 Message-ID: <20250405161320.76854-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869751393019100 Use the OnOffAuto type as 3-state. Since the TCGState instance is zero-initialized, the mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO). In tcg_init_machine(), if mttcg_enabled is still AUTO, set a default value (effectively inlining the default_mttcg_enabled() method content). In the tcg_get_thread() getter, consider AUTO / OFF states as "single", otherwise ON is "multi". Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tcg-all.c | 60 ++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index b8874430d30..15d4e9232ae 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -32,6 +32,7 @@ #include "qemu/error-report.h" #include "qemu/accel.h" #include "qemu/atomic.h" +#include "qapi/qapi-types-common.h" #include "qapi/qapi-builtin-visit.h" #include "qemu/units.h" #if defined(CONFIG_USER_ONLY) @@ -47,7 +48,7 @@ struct TCGState { AccelState parent_obj; =20 - bool mttcg_enabled; + OnOffAuto mttcg_enabled; bool one_insn_per_tb; int splitwx_enabled; unsigned long tb_size; @@ -70,37 +71,10 @@ bool qemu_tcg_mttcg_enabled(void) =20 #endif /* !CONFIG_USER_ONLY */ =20 -/* - * We default to false if we know other options have been enabled - * which are currently incompatible with MTTCG. Otherwise when each - * guest (target) has been updated to support: - * - atomic instructions - * - memory ordering primitives (barriers) - * they can set the appropriate CONFIG flags in ${target}-softmmu.mak - * - * Once a guest architecture has been converted to the new primitives - * there is one remaining limitation to check: - * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) - */ - -static bool default_mttcg_enabled(void) -{ - if (icount_enabled()) { - return false; - } -#ifdef TARGET_SUPPORTS_MTTCG - return true; -#else - return false; -#endif -} - static void tcg_accel_instance_init(Object *obj) { TCGState *s =3D TCG_STATE(obj); =20 - s->mttcg_enabled =3D default_mttcg_enabled(); - /* If debugging enabled, default "auto on", otherwise off. */ #if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) s->splitwx_enabled =3D -1; @@ -118,7 +92,31 @@ static int tcg_init_machine(MachineState *ms) unsigned max_cpus =3D 1; #else unsigned max_cpus =3D ms->smp.max_cpus; +#ifdef TARGET_SUPPORTS_MTTCG + bool mttcg_supported =3D true; +#else + bool mttcg_supported =3D false; +#endif =20 + if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_AUTO) { + /* + * We default to false if we know other options have been enabled + * which are currently incompatible with MTTCG. Otherwise when each + * guest (target) has been updated to support: + * - atomic instructions + * - memory ordering primitives (barriers) + * they can set the appropriate CONFIG flags in ${target}-softmmu.= mak + * + * Once a guest architecture has been converted to the new primiti= ves + * there is one remaining limitation to check: + * - The guest can't be oversized (e.g. 64 bit guest on 32 bit h= ost) + */ + if (icount_enabled()) { + s->mttcg_enabled =3D ON_OFF_AUTO_OFF; + } else { + s->mttcg_enabled =3D mttcg_supported; + } + } mttcg_enabled =3D s->mttcg_enabled; #endif =20 @@ -147,7 +145,7 @@ static char *tcg_get_thread(Object *obj, Error **errp) { TCGState *s =3D TCG_STATE(obj); =20 - return g_strdup(s->mttcg_enabled ? "multi" : "single"); + return g_strdup(s->mttcg_enabled =3D=3D ON_OFF_AUTO_ON ? "multi" : "si= ngle"); } =20 static void tcg_set_thread(Object *obj, const char *value, Error **errp) @@ -162,10 +160,10 @@ static void tcg_set_thread(Object *obj, const char *v= alue, Error **errp) warn_report("Guest not yet converted to MTTCG - " "you may get unexpected results"); #endif - s->mttcg_enabled =3D true; + s->mttcg_enabled =3D ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") =3D=3D 0) { - s->mttcg_enabled =3D false; + s->mttcg_enabled =3D ON_OFF_AUTO_OFF; } else { error_setg(errp, "Invalid 'thread' setting %s", value); } --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869740; cv=none; d=zohomail.com; s=zohoarc; b=JNsvGdKjlLZpiQBltmEb0PJy3NsZN7Xv413OwVwv2Gng2a1iT6840A4x4X1edPfMSU73e3M7Xz7k56OB09ocjSLktxtYIj1PwjFJsjun4hl0AWvhPM6gkN44N953jK0uAh+I904hck8a6uNOzstG7uBQFTgX3hsKEiIPmqsCC2o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869740; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fLiC832/142ITmF1Yvgl6ilLfBOuUrOH271pHrSjNR0=; b=SGDW49DMpcWU2NItxLNsLZ/t6REV+VAeHEtSkDRCPu4tpFJXE2Gd+KxYQ/t3ybUJRD3jzsU3OUsM6OI5ktg7HWUSIzRCKcIArT7c6PPGvCK1JHzQEBXWQ1ZrvyH6Jd2i5y0VZVoiEvhM3zKEPpIaOmSsxJI1/nbomKh8rvV4QEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869740188632.1351334326382; Sat, 5 Apr 2025 09:15:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u16AK-0001kt-9d; Sat, 05 Apr 2025 12:14:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u16AI-0001Zj-3Z for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:38 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u16AG-0005JV-98 for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:37 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-43d0359b1fcso19472405e9.0 for ; Sat, 05 Apr 2025 09:14:35 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1794efesm80953835e9.28.2025.04.05.09.14.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869674; x=1744474474; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fLiC832/142ITmF1Yvgl6ilLfBOuUrOH271pHrSjNR0=; b=cOWh/9oi5gi2lP38S1D3WEpwbY5U12S6BXxfQ3YOetfScTr2kaELFUSKajYJdZarJl D64JPUhSL06cloWA3zhdXcMc4ab5LAD4aSZq9RPrtWMED3MR/Gv/kAjH/IzLoNwrGLw3 WGnFAsa5Mf1xYz9OxT5fp6kX4MTx8yleR9T/I2n31DOryismsOHPQoDyq9k4Lwy40Otn 98gG8YrIaqIzL0E+k7ysOUMBUFIqA5W+VpKMqR5WRPeZWhIwzN9zx9c5DBHEOhzL4LMN uZi6WW57pLDSjyurSGlsSHC2lriQXGlRK7rU21qOYn0pIZJ0MMe/bZABfbG1Z0En9azW GLuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869674; x=1744474474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fLiC832/142ITmF1Yvgl6ilLfBOuUrOH271pHrSjNR0=; b=uHQtd8kO7vhGFuBfV3KAi5ATItGOFdotUqr5IH47SDEnuKOF5WNflR8pONL85IfTZG IauNBknPZkiwIk9+gYWmWtjKdvyUhf7t5NuIpuUe03jaPWu7SFJ7Q0Jas02oQ2CIldUv rugmyVh0lnitsK2Uh4sQiUWCvHKumaiVp+yOX/nyB2qHSFN81nfTK6xMPKVbFI6Xd9da 1lpIlnB4zI9ne0rlcV9SYEYyRR5EpvbiX8s7OuCthSfPCy5CnybmRL03fA8hk3rGt6HV Kw9hzUCQdGXLXaW4oZA7BNgukE9AnlHkAFu7GaJKd61Az63OXoBrUBWJ3R/zBXEY4Iy5 9qUw== X-Gm-Message-State: AOJu0YwS6U9IMXP86aGNG5dW3uEJar6aSAQCwQFxEKNEXvEDWXLDK+Ct ND3sn+dP8lq0pLC1vlyxdk9rY2AQP7Q/0T1aETF4ExzdEFSR/A6a8ivFoEIKEGe3EOOWKJRAqgV Y X-Gm-Gg: ASbGnctdIkRyg8FtxwL6V2O7N2NAnbe+Ssds5ZMXAFRnpd1XEn8Rd4hT3WbTkxpv9Qa guVmgRRwS+VQkSBRd8lrTS+B+1Cs5ItVi5xukzfcCLs85VAGQ+1GiFLaGKxJzpMx+lIS9TYpsg9 fepecLsNQavJR+XL1uTVtjcug/iyptRLym6CB64hsCPMI+a/MRFkx53uyqqEBPpkAdzGkdEUd0c OGUh78qYmPBhbql837wqU/USF4KNFZJHmIxeKQJJRU9gE/3ZpbvLtDMQ0k5pfWlaKnbC5QMV+1x HxNZHzL+XVDl/oLlz6M1NaNqPFtbdSbVLGhzfZyVueqipAHDTQK9IKJjEay4vGn60irIREp8/0b efmUUnM+bf2qW6tN5usZvcZpx X-Google-Smtp-Source: AGHT+IGv1hVLSo1FtU1K8nbpF3tdnfp2mS5Q5F4nxhanYeUUPMoudAEgDwXRfuQ6eDdZeAdA6Cp3gw== X-Received: by 2002:a05:600c:6b71:b0:43b:baf7:76e4 with SMTP id 5b1f17b1804b1-43ebee73fb1mr89629385e9.1.1743869674377; Sat, 05 Apr 2025 09:14:34 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v4 15/16] tcg: Factor mttcg_init() out Date: Sat, 5 Apr 2025 18:13:19 +0200 Message-ID: <20250405161320.76854-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869740753019000 Keep MTTCG initialization code out of tcg_init_machine(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/tcg-all.c | 50 +++++++++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 15d4e9232ae..267830658ca 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -69,29 +69,8 @@ bool qemu_tcg_mttcg_enabled(void) return mttcg_enabled; } =20 -#endif /* !CONFIG_USER_ONLY */ - -static void tcg_accel_instance_init(Object *obj) +static void mttcg_init(TCGState *s) { - TCGState *s =3D TCG_STATE(obj); - - /* If debugging enabled, default "auto on", otherwise off. */ -#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) - s->splitwx_enabled =3D -1; -#else - s->splitwx_enabled =3D 0; -#endif -} - -bool one_insn_per_tb; - -static int tcg_init_machine(MachineState *ms) -{ - TCGState *s =3D TCG_STATE(current_accel()); -#ifdef CONFIG_USER_ONLY - unsigned max_cpus =3D 1; -#else - unsigned max_cpus =3D ms->smp.max_cpus; #ifdef TARGET_SUPPORTS_MTTCG bool mttcg_supported =3D true; #else @@ -118,6 +97,33 @@ static int tcg_init_machine(MachineState *ms) } } mttcg_enabled =3D s->mttcg_enabled; +} + +#endif /* !CONFIG_USER_ONLY */ + +static void tcg_accel_instance_init(Object *obj) +{ + TCGState *s =3D TCG_STATE(obj); + + /* If debugging enabled, default "auto on", otherwise off. */ +#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) + s->splitwx_enabled =3D -1; +#else + s->splitwx_enabled =3D 0; +#endif +} + +bool one_insn_per_tb; + +static int tcg_init_machine(MachineState *ms) +{ + TCGState *s =3D TCG_STATE(current_accel()); +#ifdef CONFIG_USER_ONLY + unsigned max_cpus =3D 1; +#else + unsigned max_cpus =3D ms->smp.max_cpus; + + mttcg_init(s); #endif =20 tcg_allowed =3D true; --=20 2.47.1 From nobody Mon Dec 15 16:17:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743869745; cv=none; d=zohomail.com; s=zohoarc; b=J5pRWIN8Zj9HHspgybWIoxHrI8EFz7bLlheYPqZy7Gpn/+XCBNuJmnw6h0mZQlo+RkiD+RivPkOn1/gTFCo9BtmOOt6GC62JHiLqGMDKt605b8uh+uQ+3eYd7W6sRgiqtEMBB9nsFqpyKEnDXie9LY+fW9GNbT+S9NyKtm0JK7Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743869745; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Za9SN5SGg/6VR8rTeUlc4Qwr/9ZnskfD9hV5+cRNuTY=; b=Bd845J7APmaKW6zFlIoTKzeJzAYfO674c+UAhYesFcgBWfZ5jepN5xMcynVGdgcyHjF8OFCOypydOAmowKz4MjNB3KszL1+gtFQodJWnpj7CVA1WHFMCE+oXSSNxNSJyZl0GmyxWteFL9lgqAPZS+C8bNqnIO8pi7/8Re8wcX10= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743869745727792.0365016844019; Sat, 5 Apr 2025 09:15:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u16AQ-0002Af-BQ; Sat, 05 Apr 2025 12:14:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u16AO-00023j-25 for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:44 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u16AL-0005KI-1T for qemu-devel@nongnu.org; Sat, 05 Apr 2025 12:14:43 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43ce71582e9so19047365e9.1 for ; Sat, 05 Apr 2025 09:14:40 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1795243sm81002725e9.32.2025.04.05.09.14.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 05 Apr 2025 09:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743869679; x=1744474479; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Za9SN5SGg/6VR8rTeUlc4Qwr/9ZnskfD9hV5+cRNuTY=; b=vG5fW6aFdbFSdhohC8TPQx4FC9jf+TRqr4rZzSjduiBm9gScUtTdo/ZFY/byGjY4RL Md9+O5r1QNwT/COdHbLtwwXYzdyRKxvCUeIq2jIbLDCJMkOTbr+X3piiCBAmHIKcfA7a rx8YFkbsXODMJYtb76Pa4YsnuhonVjCR/J8+JqRgs9hZsuz5h5PX+KQr5+0/puQqHqt3 1JCrO3tXLjpsrOxOJ/gnzII0cOpFCcy3oDFUcZyT/nXmg9S0ZaEdjxKuh8S8l21KoApE mYZrSMn9r2to1NygDNKKiwk1rT3zlNPXg8INTVg5ie579JfQL7M4EPJYiMIwUfrBg78l JGMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743869679; x=1744474479; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Za9SN5SGg/6VR8rTeUlc4Qwr/9ZnskfD9hV5+cRNuTY=; b=t8phYQrD6w1kyQkC7/qqabIxNg5WvbwBxP83kL68+hOHNlFeng+tRKsoxUvydvGAB9 87pMHl2STnkWzx0U4U3Bskc7rVmpzM5blt9UVcsynDcTzbd+BG/jio8UzhYQohJCfMxJ cUcdCCpgyymjAIEHV8WxkjoVO7o1EnV7f1R+O9EYcGufRJQgGqAFhwK2FwTvOwJABgIs bjVdbEIhS6jP44khO4QSmp6DsRbcgKpdEapIXWTiEam7Bl8M1cCKtrDSkBkDJfpuHMEK +KJfsZdxKIW7LqE5mNs+jfpks5PAEv/Gc97LDCaON2UZUJEoz4KpKULMWhjU4+CKAxJm grjg== X-Gm-Message-State: AOJu0Yx3dVYpnCoarhuyQxrrCfA/EbqwYEzdii67Vpx09pahuOh1uBoT jnuVKejh7wQFjYYcsYhYZVBWVb84cDqgSMwo9jVRYVmzwP5qKwbFxARqEKje63CtoGPna0m+Yeq L X-Gm-Gg: ASbGncsMIH8WsUbFcfixUSx88UXoqjGFddxfmARRCO9Gad1sKYg4YRD9xHz+kdT06zC 7in4Wph4fzzKVZcTpIya7Llxlb5YTWYYnXWAB7ZCNxvsOoZGvR+CLlLF2N5BlVbEbTGnzLiLgB+ lE3/IpaCSTcOIFxXFezsgPImJVkbw3OMcXGy3jQHn5cLKs5pG87Zl7pORMetBBkpDnAR6kUP410 oFF7o8WV4i+iEU4yDJ1LK4Y8+Df5tgKncTZb/zkYBqNlVeIBnWSppcLhknc6FHrnAfwAsUJ/fgF DL+QoXQ+omc3O94KDyr8t9sm3bYNzmnzTU+PaqvF7+qJpxCjaxvGyrsKVdnW1LwJjgGqM96aN9t QHjpvLLNvf/RTxApOZgvkjYtK X-Google-Smtp-Source: AGHT+IEQ+u0HTSvjZiFz1pqil/vMxjjHoPIXtuXhMaGUlRXqfTf293+8Ci+Nf+qmvJNwlvEnYbRsVw== X-Received: by 2002:a05:600c:3548:b0:43d:77c5:9c1a with SMTP id 5b1f17b1804b1-43ed0b5e285mr63911645e9.4.1743869679006; Sat, 05 Apr 2025 09:14:39 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Anton Johansson , Pierrick Bouvier Subject: [PATCH-for-10.1 v4 16/16] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Date: Sat, 5 Apr 2025 18:13:20 +0200 Message-ID: <20250405161320.76854-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250405161320.76854-1-philmd@linaro.org> References: <20250405161320.76854-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743869746763019000 Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition, have each target set the 'mttcg_supported' field in the TCGCPUOps structure. Since so far we only emulate one target architecture at a time, tcg_init_machine() gets whether MTTCG is supported via the current CPU class (CPU_RESOLVING_TYPE). Since TARGET_SUPPORTS_MTTCG isn't available anymore, instead of emiting a warning when the 'thread' property is set in tcg_set_thread(), emit it in tcg_init_machine() where it is consumed. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- docs/devel/multi-thread-tcg.rst | 2 +- configs/targets/aarch64-softmmu.mak | 1 - configs/targets/alpha-softmmu.mak | 1 - configs/targets/arm-softmmu.mak | 1 - configs/targets/hppa-softmmu.mak | 1 - configs/targets/i386-softmmu.mak | 1 - configs/targets/loongarch64-softmmu.mak | 1 - configs/targets/microblaze-softmmu.mak | 1 - configs/targets/microblazeel-softmmu.mak | 1 - configs/targets/mips-softmmu.mak | 1 - configs/targets/mipsel-softmmu.mak | 1 - configs/targets/or1k-softmmu.mak | 1 - configs/targets/ppc64-softmmu.mak | 1 - configs/targets/riscv32-softmmu.mak | 1 - configs/targets/riscv64-softmmu.mak | 1 - configs/targets/s390x-softmmu.mak | 1 - configs/targets/sparc-softmmu.mak | 1 - configs/targets/sparc64-softmmu.mak | 1 - configs/targets/x86_64-softmmu.mak | 1 - configs/targets/xtensa-softmmu.mak | 1 - configs/targets/xtensaeb-softmmu.mak | 1 - include/accel/tcg/cpu-ops.h | 8 ++++++++ include/exec/poison.h | 1 - accel/tcg/tcg-all.c | 17 ++++++++--------- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 44 files changed, 37 insertions(+), 31 deletions(-) diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.= rst index 14a2a9dc7b5..da9a1530c9f 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -30,7 +30,7 @@ user-space thread. This is enabled by default for all FE/= BE combinations where the host memory model is able to accommodate the guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is z= ero) and the guest has had the required work done to support this safely -(TARGET_SUPPORTS_MTTCG). +(TCGCPUOps::mttcg_supported). =20 System emulation will fall back to the original round robin approach if: diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-= softmmu.mak index 82cb72cb83d..5dfeb35af90 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sy= sregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-prof= ile-mve.xml gdb-xml/aarch64-pauth.xml # needed by boot.c diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-soft= mmu.mak index 89f3517aca0..5275076e50d 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dalpha -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.= mak index afc64f5927b..6a5a8eda949 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Darm -TARGET_SUPPORTS_MTTCG=3Dy TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml gdb-xml/arm-m-profile-mve.xml # needed by boot.c TARGET_NEED_FDT=3Dy diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmm= u.mak index 63ca74ed5e6..ea331107a08 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dhppa TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmm= u.mak index 5dd89217560..e9d89e8ab41 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Di386 -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy TARGET_XML_FILES=3D gdb-xml/i386-32bit.xml diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loon= garch64-softmmu.mak index 351341132f6..fc44c54233d 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=3Dloongarch64 TARGET_BASE_ARCH=3Dloongarch TARGET_KVM_HAVE_GUEST_DEBUG=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_XML_FILES=3D gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.= xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-l= asx.xml # all boards require libfdt TARGET_NEED_FDT=3Dy diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/micro= blaze-softmmu.mak index 99a33ed44a8..23457d0ae65 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Dmicroblaze TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3Dgdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-pr= otect.xml diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/mic= roblazeel-softmmu.mak index 52cdeae1a28..c82c509623d 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dmicroblaze -TARGET_SUPPORTS_MTTCG=3Dy # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3Dgdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-pr= otect.xml diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmm= u.mak index b62a0882499..c9588066b8d 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dmips TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-so= ftmmu.mak index 620ec681785..90e09bdc3e5 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dmips -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmm= u.mak index adfddb1a8ac..0e47d9878b0 100644 --- a/configs/targets/or1k-softmmu.mak +++ b/configs/targets/or1k-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dopenrisc -TARGET_SUPPORTS_MTTCG=3Dy TARGET_BIG_ENDIAN=3Dy # needed by boot.c and all boards TARGET_NEED_FDT=3Dy diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-soft= mmu.mak index 7cee0e97f43..74572864b36 100644 --- a/configs/targets/ppc64-softmmu.mak +++ b/configs/targets/ppc64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=3Dppc64 TARGET_BASE_ARCH=3Dppc TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml= /power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml # all boards require libfdt diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-= softmmu.mak index c828066ce6b..db55275b868 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Driscv32 TARGET_BASE_ARCH=3Driscv -TARGET_SUPPORTS_MTTCG=3Dy TARGET_XML_FILES=3D gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=3Dy diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-= softmmu.mak index 09f613d24a0..2bdd4a62cd2 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv= -32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-soft= mmu.mak index 5242ebe7c2e..76dd5de6584 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Ds390x TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/= s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml = gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=3D64 diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-soft= mmu.mak index 78c2e25bd13..57801faf1fc 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-= softmmu.mak index f7bab97a002..2504e31ae33 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dsparc64 TARGET_BASE_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index 1ceefde1313..5619b2bc686 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy TARGET_XML_FILES=3D gdb-xml/i386-64bit.xml diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-so= ftmmu.mak index 65845df4ffa..2a9797338a6 100644 --- a/configs/targets/xtensa-softmmu.mak +++ b/configs/targets/xtensa-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dxtensa -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/xtensaeb-softmmu.mak b/configs/targets/xtensae= b-softmmu.mak index f1f789d6971..5204729af8b 100644 --- a/configs/targets/xtensaeb-softmmu.mak +++ b/configs/targets/xtensaeb-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dxtensa TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index a4932fc5d7c..0e4352513d1 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,6 +19,14 @@ #include "tcg/tcg-mo.h" =20 struct TCGCPUOps { + /** + * mttcg_supported: multi-threaded TCG is supported + * + * Target (TCG frontend) supports: + * - atomic instructions + * - memory ordering primitives (barriers) + */ + bool mttcg_supported; =20 /** * @guest_default_memory_order: default barrier that is required diff --git a/include/exec/poison.h b/include/exec/poison.h index 0f336cdc618..413dfd16f24 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,7 +35,6 @@ =20 #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME -#pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN #pragma GCC poison TARGET_HAS_PRECISE_SMC =20 diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 267830658ca..bf27c5c0fb3 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -41,8 +41,10 @@ #include "hw/boards.h" #include "system/tcg.h" #endif +#include "accel/tcg/cpu-ops.h" #include "internal-common.h" #include "cpu-param.h" +#include "cpu.h" =20 =20 struct TCGState { @@ -71,11 +73,8 @@ bool qemu_tcg_mttcg_enabled(void) =20 static void mttcg_init(TCGState *s) { -#ifdef TARGET_SUPPORTS_MTTCG - bool mttcg_supported =3D true; -#else - bool mttcg_supported =3D false; -#endif + CPUClass *cc =3D CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE)); + bool mttcg_supported =3D cc->tcg_ops->mttcg_supported; =20 if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_AUTO) { /* @@ -96,6 +95,10 @@ static void mttcg_init(TCGState *s) s->mttcg_enabled =3D mttcg_supported; } } + if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_ON && !mttcg_supported) { + warn_report("Guest not yet converted to MTTCG - " + "you may get unexpected results"); + } mttcg_enabled =3D s->mttcg_enabled; } =20 @@ -162,10 +165,6 @@ static void tcg_set_thread(Object *obj, const char *va= lue, Error **errp) if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { -#ifndef TARGET_SUPPORTS_MTTCG - warn_report("Guest not yet converted to MTTCG - " - "you may get unexpected results"); -#endif s->mttcg_enabled =3D ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") =3D=3D 0) { diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index eeaf3a81c1a..35fb145d27f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -237,6 +237,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { static const TCGCPUOps alpha_tcg_ops =3D { /* Alpha processors have a weak memory model */ .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3e9760b5518..377791c84dd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,7 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { =20 #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops =3D { + .mttcg_supported =3D true, /* ARM processors have a weak memory model */ .guest_default_memory_order =3D 0, =20 diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 89d4e4b4a2f..f71560aa43b 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -234,6 +234,7 @@ static void cortex_m55_initfn(Object *obj) static const TCGCPUOps arm_v7m_tcg_ops =3D { /* ARM processors have a weak memory model */ .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8f79cf4c08b..84f3b839c9b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -225,6 +225,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { =20 static const TCGCPUOps avr_tcg_ops =3D { .guest_default_memory_order =3D 0, + .mttcg_supported =3D false, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index e54f10c2294..2de6911f5aa 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -329,6 +329,7 @@ static const TCGCPUOps hexagon_tcg_ops =3D { * Hexagon processors have a strong memory model. */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index dfbd9330565..10e18c945ef 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -260,6 +260,7 @@ static const TCGCPUOps hppa_tcg_ops =3D { * basis. It's probably easier to fall back to a strong memory model. */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D true, =20 .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 5295fcea5c3..c00a94fd582 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 const TCGCPUOps x86_tcg_ops =3D { + .mttcg_supported =3D true, /* * The x86 has a strong memory model with some store-after-load re-ord= ering */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index f5b8ef29ab0..fe9462b3b7e 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -865,6 +865,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) =20 static const TCGCPUOps loongarch_tcg_ops =3D { .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b2d8c8f1dea..99adc5eb910 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -591,6 +591,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { static const TCGCPUOps m68k_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, =20 .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4efba0dddb2..edfb05758b3 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -429,6 +429,7 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { static const TCGCPUOps mb_tcg_ops =3D { /* MicroBlaze is always in-order. */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D true, =20 .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 010773405a8..77bdb6db887 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,6 +550,7 @@ static const Property mips_cpu_properties[] =3D { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops =3D { + .mttcg_supported =3D TARGET_LONG_BITS =3D=3D 32, .guest_default_memory_order =3D 0, =20 .initialize =3D mips_tcg_init, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 87fe779042c..6601e0c0666 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -244,6 +244,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { =20 static const TCGCPUOps openrisc_tcg_ops =3D { .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 8300fa5777e..f95c731c97f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7478,6 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps ppc_tcg_ops =3D { + .mttcg_supported =3D TARGET_LONG_BITS =3D=3D 64, .guest_default_memory_order =3D 0, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 44fdf6c4cf1..426145c3b9f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -141,6 +141,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } =20 const TCGCPUOps riscv_tcg_ops =3D { + .mttcg_supported =3D true, .guest_default_memory_order =3D 0, =20 .initialize =3D riscv_translate_init, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index f073fe8fc98..0a7a2b55b5a 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -206,6 +206,7 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { static const TCGCPUOps rx_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, =20 .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 1e101b5afeb..41cccc1e692 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } =20 static const TCGCPUOps s390_tcg_ops =3D { + .mttcg_supported =3D true, /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 7a05301c6ff..861fdd47f76 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -264,6 +264,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { static const TCGCPUOps superh_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, =20 .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 56d9417ae3f..f7d231c6f8b 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1023,6 +1023,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { * by an implied MEMBAR #StoreStore. */ .guest_default_memory_order =3D TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_S= T_ST, + .mttcg_supported =3D true, =20 .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index c68954b4096..a4f93e7d910 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -174,6 +174,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { static const TCGCPUOps tricore_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, + .mttcg_supported =3D false, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 2cbf4e30108..971e67ad978 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -234,6 +234,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { static const TCGCPUOps xtensa_tcg_ops =3D { /* Xtensa processors have a weak memory model */ .guest_default_memory_order =3D 0, + .mttcg_supported =3D true, =20 .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, --=20 2.47.1