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([173.164.107.234]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-739da0b4851sm5554790b3a.146.2025.04.05.08.50.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Apr 2025 08:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743868257; x=1744473057; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u4pcTaOhdNSQrPCcgStjubsUIgw1IcwTve4W/3vZZ+s=; b=weumnnYetfb7L1mwX7ecRipYCJesPkQ657GxfyNcmznNkZGWMW+bgVaPJgvtvWGrgV iuC7rf3l01p+ftRzykrM2GT6vBZzvOfdQeRs6nQ76GK4v2baIqB5+GNBUjJx33XXmFBS h7c0fgCKXv1eaGcZQjY3UShC1h8Icl4frJlCIJb543cLqCcIuuhj39s18wBxNZhE3oC7 EXeTiwmLTkCrjfuvadfLRXbpZu6GbpMw7aHTJ5IEhcC2uusifC60vs22n/+tQuEhF/et caeP64Gyz0JgCu1rCz0qk1PWf5BftfpRCo4ERHOwj3VAiNnqetXAgo5bYCR+j/W2GO7Q H0vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743868257; x=1744473057; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u4pcTaOhdNSQrPCcgStjubsUIgw1IcwTve4W/3vZZ+s=; b=EoCVVwYXogl+6GNRiEJLOMJxmNZC3IdZm+4sIkdnHgmGbZ8pPrLZgyOJefu7Ou67BB tIv8siOwwoE2qNjYPqrHgYhIsyz2gjIBxuSJTzmpxg80MKt/q0qZapoVi/JqZ5sQ6Kx+ lqZ0ijbInE/zRLufMvzaHwrnZklELIhfFLpXQZ4qfPxNxnxP1xUor7LVyrqBoVevDVA7 cx90jdxExKSkDNRdz8bMnfan1i2DuSdJMDdYKke+lBbou82weR3VBkI6aWMOQkvds+IF nNDih3o8GhIoeVQ3+6krI9/tCfzQ166ed3XMwHlq0vDqL2gcNuZzbhmDBUhfjRIDLuvN YVKA== X-Gm-Message-State: AOJu0YwtDh0ykQ8OEKlmdWin/3EV0yMXieWb/FCa68sKOreU1xPQpgnK zkGDc40fX6auOAc/gf6TRG/Iiw0kT3gAzhfedIpjlNj64laYAKPSnop71jKFjPMG2kTMAOTu1G5 1 X-Gm-Gg: ASbGncvGczTZVNDGfKduiHpbhd0KK8RXOESz1Knb2Cl3PJKZjtdPcq8bMFDVgTnlqGI e4pE4nsnlwfEaSX/u8L56DLrqV2u5DnTyBh3yRxxOpNmwOXOibzWmyXmM8JsqkwP7/y/mYTEJNG ytYXkopWXSUeM84J5/FkKs/Kmn1Qts1KqAlSDMa4nMXIvE73ocPO8/7FtlrUsFJxgyHhKdCOP6q m7pWtNqXGcjxQrws/rbPat+/qr/ngz6QdGFgjyCOcY+RiopxSvYi8yd0rSyClT8wiqrToqZRTsV MUCeZXujnD+DzTT3eRfjdrif5wogztt5MLMkrpMvG3AHutOBbWp87sKYIvSpqss= X-Google-Smtp-Source: AGHT+IHmCQwaEZ9/V1EyayqsUkeY9GNUfcvidFKWGHhPojUNBP0S4iJRWCSlwQtA7C7rz7Gb5XPd3g== X-Received: by 2002:a05:6a00:2292:b0:739:b1df:2410 with SMTP id d2e1a72fcca58-739e4f73f8dmr9785942b3a.20.1743868257007; Sat, 05 Apr 2025 08:50:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH v2 1/3] accel/tcg: Add CPUState argument to page_unprotect Date: Sat, 5 Apr 2025 08:50:51 -0700 Message-ID: <20250405155054.967307-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250405155054.967307-1-richard.henderson@linaro.org> References: <20250405155054.967307-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743868306381019000 Content-Type: text/plain; charset="utf-8" In the next patch, page_unprotect will need to pass the CPUState to tb_invalidate_phys_page_unwind. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/user/page-protection.h | 2 +- accel/tcg/user-exec.c | 8 +++++--- linux-user/elfload.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/user/page-protection.h b/include/user/page-protection.h index d5c8748d49..1de72e31e6 100644 --- a/include/user/page-protection.h +++ b/include/user/page-protection.h @@ -16,7 +16,7 @@ #include "exec/target_long.h" #include "exec/translation-block.h" =20 -int page_unprotect(tb_page_addr_t address, uintptr_t pc); +int page_unprotect(CPUState *cpu, tb_page_addr_t address, uintptr_t pc); =20 int page_get_flags(target_ulong address); =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5eef8e7f18..90b345a0cf 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -128,7 +128,7 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_w= rite) bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, uintptr_t host_pc, abi_ptr guest_addr) { - switch (page_unprotect(guest_addr, host_pc)) { + switch (page_unprotect(cpu, guest_addr, host_pc)) { case 0: /* * Fault not caused by a page marked unwritable to protect @@ -584,7 +584,7 @@ bool page_check_range(target_ulong start, target_ulong = len, int flags) break; } /* Asking about writable, but has been protected: undo. */ - if (!page_unprotect(start, 0)) { + if (!page_unprotect(NULL, start, 0)) { ret =3D false; break; } @@ -704,11 +704,13 @@ void tb_lock_page0(tb_page_addr_t address) * immediately exited. (We can only return 2 if the 'pc' argument is * non-zero.) */ -int page_unprotect(tb_page_addr_t address, uintptr_t pc) +int page_unprotect(CPUState *cpu, tb_page_addr_t address, uintptr_t pc) { PageFlagsNode *p; bool current_tb_invalidated; =20 + assert((cpu =3D=3D NULL) =3D=3D (pc =3D=3D 0)); + /* * Technically this isn't safe inside a signal handler. However we * know this only ever happens in a synchronous SEGV handler, so in diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 99811af5e7..7519b6bcda 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -4245,7 +4245,7 @@ static int wmr_page_unprotect_regions(void *opaque, t= arget_ulong start, size_t step =3D MAX(TARGET_PAGE_SIZE, qemu_real_host_page_size()); =20 while (1) { - page_unprotect(start, 0); + page_unprotect(NULL, start, 0); if (end - start <=3D step) { break; } --=20 2.43.0 From nobody Tue Feb 10 05:12:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743868311; cv=none; d=zohomail.com; s=zohoarc; b=ErxYMfovvzvRcFXhVTgmDbe+YuyyGrbtbvKjgJq7MfYLy1tYQUmsvwhMKr3Z5EyAWH7QB5QEW0gjMhz1SGX7XtxrOS5G7djR3zqxhXqf3NRQZpVPzQChFLFwbC2TEfGrEaRMeXMw6kZloZMKP+586uufsywX8wQZx9zxy0PWilk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743868311; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vpl2ab9dTaditwWj6WYvgHB9ekBgYkRpHOJXzTSaFrI=; b=XBgEnuRA+V7srZtgePuVnTrDANO/8x06+5HhpW46OD2QKgAtBUXu6oALZPViqtkhwGz0eqUYSx/oM1AYhSNobHQ2TdZ6iNFcmap/iGBnT9BCqBR2hlhJhxRDkIGPgNsmAgCpIIwu0yZ4p6K01ZlCrqHGm0K2rSgItj/42flDgRQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743868311851983.3883801581868; Sat, 5 Apr 2025 08:51:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u15na-0006CW-Gz; Sat, 05 Apr 2025 11:51:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u15nQ-0006AG-T3 for qemu-devel@nongnu.org; Sat, 05 Apr 2025 11:51:01 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u15nP-0002gL-82 for qemu-devel@nongnu.org; Sat, 05 Apr 2025 11:51:00 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-736b34a71a1so3668538b3a.0 for ; Sat, 05 Apr 2025 08:50:58 -0700 (PDT) Received: from stoup.. ([173.164.107.234]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-739da0b4851sm5554790b3a.146.2025.04.05.08.50.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Apr 2025 08:50:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743868258; x=1744473058; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vpl2ab9dTaditwWj6WYvgHB9ekBgYkRpHOJXzTSaFrI=; b=pBe50kVCS4EbJZ7ZvBFjSNDOHbdAYqTyWoWRhp9jlAr1yf7ifXwcL1VvYZ8dg0RDqL xS51nW+HSFF3AKMEuGOV5H5oLyl8B+A2fcvN79DaKkqmI0Q4s2s9IQjos4724O51ybHn p7EXwXeiriHRb/LykAW6dR2BsdB9zMeKn07FQVYoiKekNu6AnM9mDxrAhqq4isl77sqB nybBMHINLsFSyjOsauEzxVuaeGykEf1PTBq+noWLAxNflb8WEo3h2dS6ZG3LV3tpUqWv JVSWyAMxq99uUmMsg+rXmiG2NN7cIGC5u3bp+8nElUgZLfPqCNrOlUT0aDFoNJ43xcu8 TNvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743868258; x=1744473058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vpl2ab9dTaditwWj6WYvgHB9ekBgYkRpHOJXzTSaFrI=; b=J8fUcgfoa2rICv3xfFuOG6yVyVrbOA8IlaPXVq6A1F0WAYkdeWCDK8PdvVNbP1KL9L Jix3QS+toRBri2vGFuU00SDi5YyHqmGvK18ooUHkLNzttPBnDuvjxvxuEbFNmN7ukwbO lrF+ME02CGi3xsB0OV31Kk9GkK1qpCMJ9tEQ2tM+2xQhqU8bMN4g+Mh1w4AGQxrQwH3/ dh3z3t3gaQnaaafr9iXAtujYzXZP1PNAig327qe/doUQ/eRHUe8uptRNlJHLeE9x3ori yQFoVAx3l/WfGUyd06PgliNOa72rwAtaTx67ELtTFT5ArC3sbkrFmh9YlcWKT8USZg6u ps+g== X-Gm-Message-State: AOJu0Yy10nBQ227dpIlCYPlNaMtw2k/VN5PyY0R8CH9S8i/DkUeJ5rTK QmDQgyTQbSJU1U5gi7lVl2aeYbGEQWQEGed304ZUqTDbfYEJnzLQodJ+84hNy/V5cZ9B4/uMGus H X-Gm-Gg: ASbGncu5oJ734DB7KtK0IdmWAw/2ihSWFP2Wl1XX74l4cVEs5T+LJGlkFe8Z0qksr1g Kg60A9+Uao3856uwmI8u/ZBqaLnU778dLZBzT18jp+ceQebDBpLcxFyPr7HrC3sUl1S2ZC58ROj IwgDi5HRBfPck0AnbPCdxoWIfShP94eFcjO1ZojxPpyNnZIJVacb4m38fK4qsqRJcTd9cWWppML K3GanI0tCKwfvkZNgp1TEbqyeHA95Q6CAmcnpmuy81aavVbmjwmMmyk3pB7Y/RCXPQseP/lhv3q rBq7+CqOwb3bX1Jv2cQVweyoc0Qf5+McYyyStNg16yUbrYkFfTw3 X-Google-Smtp-Source: AGHT+IFQOIhyeoMzNptn5MLTrWoVSvpB0CY7hetS8N+YGJyTd5DqJmujj0Fi1A7zS3gkG5VjzmaiFQ== X-Received: by 2002:a05:6a00:398f:b0:730:9752:d02a with SMTP id d2e1a72fcca58-739e48cefc2mr10706367b3a.4.1743868257766; Sat, 05 Apr 2025 08:50:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH v2 2/3] accel/tcg: Add CPUState argument to tb_invalidate_phys_page_unwind Date: Sat, 5 Apr 2025 08:50:52 -0700 Message-ID: <20250405155054.967307-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250405155054.967307-1-richard.henderson@linaro.org> References: <20250405155054.967307-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743868313291019100 Content-Type: text/plain; charset="utf-8" Replace existing usage of current_cpu. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tb-internal.h | 3 ++- accel/tcg/tb-maint.c | 8 ++++---- accel/tcg/user-exec.c | 5 +++-- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/accel/tcg/tb-internal.h b/accel/tcg/tb-internal.h index 08538e2896..1078de6c99 100644 --- a/accel/tcg/tb-internal.h +++ b/accel/tcg/tb-internal.h @@ -50,6 +50,7 @@ void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, uintptr_t retaddr); #endif /* CONFIG_SOFTMMU */ =20 -bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); +bool tb_invalidate_phys_page_unwind(CPUState *cpu, tb_page_addr_t addr, + uintptr_t pc); =20 #endif diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index d479f53ae0..714dcaedc9 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1045,7 +1045,8 @@ static void tb_invalidate_phys_page(tb_page_addr_t ad= dr) * TB (because it was modified by this store and the guest CPU has * precise-SMC semantics). */ -bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc) +bool tb_invalidate_phys_page_unwind(CPUState *cpu, tb_page_addr_t addr, + uintptr_t pc) { TranslationBlock *current_tb; bool current_tb_modified; @@ -1083,15 +1084,14 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t = addr, uintptr_t pc) * the CPU state. */ current_tb_modified =3D true; - cpu_restore_state_from_tb(current_cpu, current_tb, pc); + cpu_restore_state_from_tb(cpu, current_tb, pc); } tb_phys_invalidate__locked(tb); } =20 if (current_tb_modified) { /* Force execution of one insn next time. */ - CPUState *cpu =3D current_cpu; - cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(current_cpu); + cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(cpu); return true; } return false; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 90b345a0cf..39b76d9654 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -749,7 +749,8 @@ int page_unprotect(CPUState *cpu, tb_page_addr_t addres= s, uintptr_t pc) len =3D TARGET_PAGE_SIZE; prot =3D p->flags | PAGE_WRITE; pageflags_set_clear(start, start + len - 1, PAGE_WRITE, 0); - current_tb_invalidated =3D tb_invalidate_phys_page_unwind(star= t, pc); + current_tb_invalidated =3D + tb_invalidate_phys_page_unwind(cpu, start, pc); } else { start =3D address & -host_page_size; len =3D host_page_size; @@ -772,7 +773,7 @@ int page_unprotect(CPUState *cpu, tb_page_addr_t addres= s, uintptr_t pc) * the corresponding translated code. */ current_tb_invalidated |=3D - tb_invalidate_phys_page_unwind(addr, pc); + tb_invalidate_phys_page_unwind(cpu, addr, pc); } } if (prot & PAGE_EXEC) { --=20 2.43.0 From nobody Tue Feb 10 05:12:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743868316; cv=none; d=zohomail.com; s=zohoarc; b=WzRVlAeQSmhiizCbROmcFxaa17FE+WoSidjZAwTf9mqtbKr58E/icwdWXEGPR/1HuC68SetZVP02+PZsZoL2XvkEpOr6tlysagsi12Z1vofpudEINa7Qma7wdkpoh+lFvUqCQ6VoNfqQvVAb/saMIu54FydHSjK2/UCxXw0D1PI= ARC-Message-Signature: i=1; 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([173.164.107.234]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-739da0b4851sm5554790b3a.146.2025.04.05.08.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Apr 2025 08:50:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743868259; x=1744473059; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lGkY893pksSyJpWIAoZrw90Rpm6xbrrdV4WYhKep6Wk=; b=sWEPaFbd8oSNnJHYbbUHLEJIxsxoKJb9r4Y8pOCm097pFFBIz10aIHi95k5cMA1/90 4bZkZPgvMqPd+x5hlNMZZnrBP3VtZZK2XowYyDFk1lXeZpV9r0MTray6m9H6SWU8MqhC jEEVVW3KF3z7XfUv2jrDNguFMGHr9SKG1zhBEjYTFMrGyoica8M/7uq8Wf9Zfd576Sp9 8zW5c0fWpOWcVOWu36LVcxgBvj7DESqPnRVlW57dM0vs27zrvBDyonQ7hz3ubijErEDI T+M5o4kF8MEluKnnkfnR/uSO/B2Ns6r24heS4w87FbPBZ+9By1zrNZV0UFKb4oiqy20d zhig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743868259; x=1744473059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lGkY893pksSyJpWIAoZrw90Rpm6xbrrdV4WYhKep6Wk=; b=GUIuePspGhLZSRy6JubNDVGZb698Otz3hZ3oxwBWTkqtqlOACo1MogUQBE/BafqYPj nlEH5uqBe1IvG831zUwvh7IVm0OgwU8yN5R76Ad05mKXJK652EbMtmQvn4FywTxVWLzj UbemwzpQhF0LPOFEpt2E5sSaAJl8QwFg2K8JTSVFEQkJaAgjngij56Xmzi9iib0jmt3t Sh0vpidKfYsXr86YOKd24YvXY+cpWE4rLuuXQ1lnzig2azGnvuhiSaCe9AC4+13m4pWu gadLIxi0hqssul6PKVzenhn/PqUExjrVmwgQ0biYbZeJ+P8QUqxR/JLdxw/kxsg89jhn TAcg== X-Gm-Message-State: AOJu0YxazH/unqp42nSCTj1HIT01a9OKnymB68/LUzhsYCmkOmr27Usl 1kTAtuSP3sqGzfb0Dd9tJjvtJVgIr/Nb6mah8cWh0Tq/aRoGaOJB3Sd2jiS1lInYANL+iJdzQfm u X-Gm-Gg: ASbGncvWfC+ggaBS0kcsgTCMr/Ju/hWKm/zC3VFkiRFEwHUKoSxJSb1eBcMcOaFLMbr pQi5oMzJdUNspo+vJwgt6b+9WC1RaCcV1guEG8eTbJH69MAtVivGTUFyE8h8nH7tjRNiwZMf1za t+A42qajqHGo56e9CSw20BvDFQwX+16EahscaPpEYJB0eoJtQYPMgeAMmLNpwdpV6lQRkjlOU7U 7e60v7hSBIwHYloKVQXlHHBYFOtsoDyLilSf1RmkbnMCMcS1JoqRQeh1HOVpXqYS1cPp/Qwksio 4pOttIZ4Ur6UKuH8V36DNxC3OwI7MEd2zry/YDrjbnTRK2mZakt8 X-Google-Smtp-Source: AGHT+IFKR5n+Jso1uYfiiBWLppqfdzQ7xsagIX6dyfqaUSoGqLX1gI4tkpTu9g4G89d6KgfTqNyNeA== X-Received: by 2002:a05:6a00:1489:b0:736:7960:981f with SMTP id d2e1a72fcca58-739e4816ed1mr10498263b3a.8.1743868258660; Sat, 05 Apr 2025 08:50:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH v2 3/3] accel/tcg: Convert TARGET_HAS_PRECISE_SMC to TCGCPUOps.precise_smc Date: Sat, 5 Apr 2025 08:50:53 -0700 Message-ID: <20250405155054.967307-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250405155054.967307-1-richard.henderson@linaro.org> References: <20250405155054.967307-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743868318378019000 Content-Type: text/plain; charset="utf-8" Instead of having a compile-time TARGET_HAS_PRECISE_SMC definition, have each target set the 'precise_smc' field in the TCGCPUOps structure. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/accel/tcg/cpu-ops.h | 6 ++++++ include/exec/poison.h | 1 - target/i386/cpu.h | 4 ---- target/s390x/cpu.h | 2 -- accel/tcg/tb-maint.c | 26 ++++++++++---------------- target/i386/tcg/tcg-cpu.c | 1 + target/s390x/cpu.c | 1 + 7 files changed, 18 insertions(+), 23 deletions(-) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index a4932fc5d7..303753c43e 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,6 +19,12 @@ #include "tcg/tcg-mo.h" =20 struct TCGCPUOps { + /** + * @precise_smc: Stores which modify code within the current TB force + * the TB to exit; the next executed instruction will see + * the result of the store. + */ + bool precise_smc; =20 /** * @guest_default_memory_order: default barrier that is required diff --git a/include/exec/poison.h b/include/exec/poison.h index a09e0c1263..1593a56489 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -38,7 +38,6 @@ #pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN #pragma GCC poison TCG_GUEST_DEFAULT_MO -#pragma GCC poison TARGET_HAS_PRECISE_SMC =20 #pragma GCC poison TARGET_LONG_BITS #pragma GCC poison TARGET_FMT_lx diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 16d76df34b..5a2e4a8103 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -35,10 +35,6 @@ =20 #define XEN_NR_VIRQS 24 =20 -/* support for self modifying code even if the modified instruction is - close to the modifying instruction */ -#define TARGET_HAS_PRECISE_SMC - #ifdef TARGET_X86_64 #define I386_ELF_MACHINE EM_X86_64 #define ELF_MACHINE_UNAME "x86_64" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 90f64ee20c..ee59039879 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -35,8 +35,6 @@ =20 #define ELF_MACHINE_UNAME "S390X" =20 -#define TARGET_HAS_PRECISE_SMC - #define MMU_USER_IDX 0 =20 #define S390_MAX_CPUS 248 diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 714dcaedc9..2af6c6d451 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -28,6 +28,7 @@ #include "exec/mmap-lock.h" #include "exec/tb-flush.h" #include "exec/target_page.h" +#include "accel/tcg/cpu-ops.h" #include "tb-internal.h" #include "system/tcg.h" #include "tcg/tcg.h" @@ -1041,9 +1042,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t ad= dr) /* * Called with mmap_lock held. If pc is not 0 then it indicates the * host PC of the faulting store instruction that caused this invalidate. - * Returns true if the caller needs to abort execution of the current - * TB (because it was modified by this store and the guest CPU has - * precise-SMC semantics). + * Returns true if the caller needs to abort execution of the current TB. */ bool tb_invalidate_phys_page_unwind(CPUState *cpu, tb_page_addr_t addr, uintptr_t pc) @@ -1058,10 +1057,7 @@ bool tb_invalidate_phys_page_unwind(CPUState *cpu, t= b_page_addr_t addr, * Without precise smc semantics, or when outside of a TB, * we can skip to invalidate. */ -#ifndef TARGET_HAS_PRECISE_SMC - pc =3D 0; -#endif - if (!pc) { + if (!pc || !cpu->cc->tcg_ops->precise_smc) { tb_invalidate_phys_page(addr); return false; } @@ -1109,14 +1105,16 @@ tb_invalidate_phys_page_range__locked(struct page_c= ollection *pages, { TranslationBlock *tb; PageForEachNext n; -#ifdef TARGET_HAS_PRECISE_SMC bool current_tb_modified =3D false; - TranslationBlock *current_tb =3D retaddr ? tcg_tb_lookup(retaddr) : NU= LL; -#endif /* TARGET_HAS_PRECISE_SMC */ + TranslationBlock *current_tb =3D NULL; =20 /* Range may not cross a page. */ tcg_debug_assert(((start ^ last) & TARGET_PAGE_MASK) =3D=3D 0); =20 + if (retaddr && current_cpu->cc->tcg_ops->precise_smc) { + current_tb =3D tcg_tb_lookup(retaddr); + } + /* * We remove all the TBs in the range [start, last]. * XXX: see if in some cases it could be faster to invalidate all the = code @@ -1134,8 +1132,7 @@ tb_invalidate_phys_page_range__locked(struct page_col= lection *pages, tb_last =3D tb_start + (tb_last & ~TARGET_PAGE_MASK); } if (!(tb_last < start || tb_start > last)) { -#ifdef TARGET_HAS_PRECISE_SMC - if (current_tb =3D=3D tb && + if (unlikely(current_tb =3D=3D tb) && (tb_cflags(current_tb) & CF_COUNT_MASK) !=3D 1) { /* * If we are modifying the current TB, we must stop @@ -1147,7 +1144,6 @@ tb_invalidate_phys_page_range__locked(struct page_col= lection *pages, current_tb_modified =3D true; cpu_restore_state_from_tb(current_cpu, current_tb, retaddr= ); } -#endif /* TARGET_HAS_PRECISE_SMC */ tb_phys_invalidate__locked(tb); } } @@ -1157,15 +1153,13 @@ tb_invalidate_phys_page_range__locked(struct page_c= ollection *pages, tlb_unprotect_code(start); } =20 -#ifdef TARGET_HAS_PRECISE_SMC - if (current_tb_modified) { + if (unlikely(current_tb_modified)) { page_collection_unlock(pages); /* Force execution of one insn next time. */ current_cpu->cflags_next_tb =3D 1 | CF_NOIRQ | curr_cflags(current= _cpu); mmap_unlock(); cpu_loop_exit_noexc(current_cpu); } -#endif } =20 /* diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d941df0956..8e8ebe8aa2 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps x86_tcg_ops =3D { + .precise_smc =3D true, /* * The x86 has a strong memory model with some store-after-load re-ord= ering */ diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 1e101b5afe..f8f859cd30 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } =20 static const TCGCPUOps s390_tcg_ops =3D { + .precise_smc =3D true, /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. --=20 2.43.0