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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ea9a88b70sm49229865e9.3.2025.04.03.15.04.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717868; x=1744322668; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GS22WEeeGx00HzARJRM4WG6Tz81Z8nWUDKi4UP1ius4=; b=LrrfZcfcjkIuKsKvd4EZHjFjkNAYA4ev8wBhPrXP9DQVHfU+K5p8HxUSO5t5oB6kz7 ce6HvLRB2poC1xZO+nw9GJnQxWL6Hah0bLb2ReNhuBixMe67q60LJbxAyQauiKFy77uj Yif7eHQDRsfOr9Gjg0gbePPCNVhtzItVMihl9XR88C4mgFfLaL1vr+l1VcdKqWGtYIh8 hLTichvlWBUbAUlzLDW1KL+41gGztYBJ0R2ArA4yzboBugSDtmWVF1HrtxYcSobbcs9B LaPkiaRpTHKCcT+C6PlCHFNrXkoInTOHYXOv7fuXZ1S9kIWVeE6Y7UKL3v8oLd/nxyiW cIqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717868; x=1744322668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GS22WEeeGx00HzARJRM4WG6Tz81Z8nWUDKi4UP1ius4=; b=GrW4equUSApQTz+K22abBitlIcJETFt/dfkGVLQ8HflmDTAYHxdc/6j4tqGvZKeQIy ZN5atNFWhtQZlB/6mezP6NjPhfpwm+7wRcr/glqabR5bvogrey4TxJE6DJ5REL43lKgc zlwLinqkfVCOYUq+BGUkqAkJIAfhy0+yl67utHzwK3cLM5aPJkGkUtf2ZaXtzyCT4bYP YdwViPi/Iltl9aKsakbi8bQxUIJtQw7lsE1EZwPrUhrMr99A1StJg2e/8t7UQ1OksVnr 0sKUhhuA7hldMsRVFs2HvZ+0qUo0xI5/KKLe1HK//40UVDYRDU/XZBxvaayth9aGDi04 5Dnw== X-Gm-Message-State: AOJu0YxZDk8b/C/A7/sLUGobc2w7h8mcZ1z1laopZcYX6yx18rQnWtdV VOQPIoGAFhGAOMCmTsxm9hikAJaanMmdB8M1pirA9m9JeHex6zC6FXcSXwIVcqTIbOvm20QMnRq l X-Gm-Gg: ASbGncsvQeY7pRjd4krgMDpzMhIAhSPCpcRGksPhjolKJ0g2CnmShL9F9fhf3zvTRsB Uy3wJeRCE4YFxZWkmdQJPswP6sd6azQCM4fg9Ej+0PK/9Kgq/s//0gq38HLp0OH8al6REGEEDZJ AAJxEITGEOjYaMKPurpvlUsElKJ0Z0htRfR17KG+NCzbo1TohRfRNL+6XQ2HfpwsK9PE/32qU5Z kr/AvL8ZlJaaMxplGxSdR2cLftwJYViKCsmv6c0EMQ36SwGXIIiQxEajOQDJ5gizCyQ5bBkGAPE 7Ulgns34OZiMLGDMIWLaugogq1eFovdZNAgtyuGQCFZ5VbZSTqHmOwefogp8+RVeEGX3uGvGCef rk+kHyURwyEE55S0OmfmaFnML X-Google-Smtp-Source: AGHT+IEzzrz/YD50wq0HOq2LW7blQyejCX5UxSMlhMuLl9GPqJk3A7Fs8QKuPilKXWxBqKYiu3YfOQ== X-Received: by 2002:a05:6000:290d:b0:391:2e6a:30fe with SMTP id ffacd0b85a97d-39cba93333emr690288f8f.39.1743717867892; Thu, 03 Apr 2025 15:04:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 01/19] target/riscv: Do not expose rv128 CPU on user mode emulation Date: Fri, 4 Apr 2025 00:04:01 +0200 Message-ID: <20250403220420.78937-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717933545019000 As Richard mentioned: We should allow RV128 in user-mode at all until there's a kernel abi for it. Remove the experimental 'x-rv128' CPU on user emulation (since it is experimental, no deprecation period is required). Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 10 ++++------ target/riscv/tcg/tcg-cpu.c | 5 +++-- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 430b02d2a58..ad534cee51f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -697,7 +697,7 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj) #endif } =20 -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static void rv128_base_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -708,11 +708,9 @@ static void rv128_base_cpu_init(Object *obj) =20 /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); -#endif } -#endif /* CONFIG_TCG */ +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 static void rv64i_bare_cpu_init(Object *obj) { @@ -3255,9 +3253,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), -#endif /* CONFIG_TCG */ +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu= _init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 710449d17e8..5d0429b4d00 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1046,7 +1046,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(cs); - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); =20 if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name =3D riscv_cpu_get_name(cpu); @@ -1055,6 +1054,9 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) return false; } =20 +#ifndef CONFIG_USER_ONLY + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + if (mcc->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled()) { /* Missing 128-bit aligned atomics */ error_setg(errp, @@ -1063,7 +1065,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) return false; } =20 -#ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; =20 tcg_cflags_set(CPU(cs), CF_PCREL); --=20 2.47.1