From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717932; cv=none; d=zohomail.com; s=zohoarc; b=MfsgpByyZpbAek8X52ZVV71OlOEprJPPgb0mIAXV+d0/RsqX+nwhdZXc/ZYELqi+vaYWXA2yPSZC8VFjPHqf9akWxhXbZCby5K4wYhldqHj5Za7zDfOTA02X/RUeqCEen0AzU7B1OcHOcsc5u1MouTMFyOdckd3uiIOOOYb4r8w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717932; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GS22WEeeGx00HzARJRM4WG6Tz81Z8nWUDKi4UP1ius4=; b=a6tBjhJBovI//Kkhxjkioweu/a1ltvDbvZvgr3rHzYhZXg2GVSzrLUB/MNd92xsPLWKo/Dc1LSr6wr3BSt9hHEIZ8EFMoEkoXNfdfbmc5hFqifk+mZXmlJ2UeRwcc30ik/BVDrRpbYWBYQETwF58dxKMmhcLaf0Kuv0l+frzCjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743717932458124.49774145890547; Thu, 3 Apr 2025 15:05:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sfs-0008BD-Ce; Thu, 03 Apr 2025 18:04:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sfn-0008Ae-EN for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:32 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sfl-0003j4-Q7 for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:31 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-43948f77f1aso10576175e9.0 for ; Thu, 03 Apr 2025 15:04:29 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ea9a88b70sm49229865e9.3.2025.04.03.15.04.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717868; x=1744322668; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GS22WEeeGx00HzARJRM4WG6Tz81Z8nWUDKi4UP1ius4=; b=LrrfZcfcjkIuKsKvd4EZHjFjkNAYA4ev8wBhPrXP9DQVHfU+K5p8HxUSO5t5oB6kz7 ce6HvLRB2poC1xZO+nw9GJnQxWL6Hah0bLb2ReNhuBixMe67q60LJbxAyQauiKFy77uj Yif7eHQDRsfOr9Gjg0gbePPCNVhtzItVMihl9XR88C4mgFfLaL1vr+l1VcdKqWGtYIh8 hLTichvlWBUbAUlzLDW1KL+41gGztYBJ0R2ArA4yzboBugSDtmWVF1HrtxYcSobbcs9B LaPkiaRpTHKCcT+C6PlCHFNrXkoInTOHYXOv7fuXZ1S9kIWVeE6Y7UKL3v8oLd/nxyiW cIqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717868; x=1744322668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GS22WEeeGx00HzARJRM4WG6Tz81Z8nWUDKi4UP1ius4=; b=GrW4equUSApQTz+K22abBitlIcJETFt/dfkGVLQ8HflmDTAYHxdc/6j4tqGvZKeQIy ZN5atNFWhtQZlB/6mezP6NjPhfpwm+7wRcr/glqabR5bvogrey4TxJE6DJ5REL43lKgc zlwLinqkfVCOYUq+BGUkqAkJIAfhy0+yl67utHzwK3cLM5aPJkGkUtf2ZaXtzyCT4bYP YdwViPi/Iltl9aKsakbi8bQxUIJtQw7lsE1EZwPrUhrMr99A1StJg2e/8t7UQ1OksVnr 0sKUhhuA7hldMsRVFs2HvZ+0qUo0xI5/KKLe1HK//40UVDYRDU/XZBxvaayth9aGDi04 5Dnw== X-Gm-Message-State: AOJu0YxZDk8b/C/A7/sLUGobc2w7h8mcZ1z1laopZcYX6yx18rQnWtdV VOQPIoGAFhGAOMCmTsxm9hikAJaanMmdB8M1pirA9m9JeHex6zC6FXcSXwIVcqTIbOvm20QMnRq l X-Gm-Gg: ASbGncsvQeY7pRjd4krgMDpzMhIAhSPCpcRGksPhjolKJ0g2CnmShL9F9fhf3zvTRsB Uy3wJeRCE4YFxZWkmdQJPswP6sd6azQCM4fg9Ej+0PK/9Kgq/s//0gq38HLp0OH8al6REGEEDZJ AAJxEITGEOjYaMKPurpvlUsElKJ0Z0htRfR17KG+NCzbo1TohRfRNL+6XQ2HfpwsK9PE/32qU5Z kr/AvL8ZlJaaMxplGxSdR2cLftwJYViKCsmv6c0EMQ36SwGXIIiQxEajOQDJ5gizCyQ5bBkGAPE 7Ulgns34OZiMLGDMIWLaugogq1eFovdZNAgtyuGQCFZ5VbZSTqHmOwefogp8+RVeEGX3uGvGCef rk+kHyURwyEE55S0OmfmaFnML X-Google-Smtp-Source: AGHT+IEzzrz/YD50wq0HOq2LW7blQyejCX5UxSMlhMuLl9GPqJk3A7Fs8QKuPilKXWxBqKYiu3YfOQ== X-Received: by 2002:a05:6000:290d:b0:391:2e6a:30fe with SMTP id ffacd0b85a97d-39cba93333emr690288f8f.39.1743717867892; Thu, 03 Apr 2025 15:04:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 01/19] target/riscv: Do not expose rv128 CPU on user mode emulation Date: Fri, 4 Apr 2025 00:04:01 +0200 Message-ID: <20250403220420.78937-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717933545019000 As Richard mentioned: We should allow RV128 in user-mode at all until there's a kernel abi for it. Remove the experimental 'x-rv128' CPU on user emulation (since it is experimental, no deprecation period is required). Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 10 ++++------ target/riscv/tcg/tcg-cpu.c | 5 +++-- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 430b02d2a58..ad534cee51f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -697,7 +697,7 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj) #endif } =20 -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static void rv128_base_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -708,11 +708,9 @@ static void rv128_base_cpu_init(Object *obj) =20 /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; -#ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); -#endif } -#endif /* CONFIG_TCG */ +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 static void rv64i_bare_cpu_init(Object *obj) { @@ -3255,9 +3253,9 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, MXL_RV64, rv64_xiangshan_= nanhu_cpu_init), -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), -#endif /* CONFIG_TCG */ +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu= _init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu= _init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 710449d17e8..5d0429b4d00 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1046,7 +1046,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(cs); - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); =20 if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name =3D riscv_cpu_get_name(cpu); @@ -1055,6 +1054,9 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) return false; } =20 +#ifndef CONFIG_USER_ONLY + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + if (mcc->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled()) { /* Missing 128-bit aligned atomics */ error_setg(errp, @@ -1063,7 +1065,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) return false; } =20 -#ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; =20 tcg_cflags_set(CPU(cs), CF_PCREL); --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717924; cv=none; d=zohomail.com; s=zohoarc; b=MDGTCe6fuDwabiKLAu3dzyuafo1bAAfKc9EzGnGysLgwmDdlbqo432JDmkvdNs754tdVi2gI8eXQ+Mm3lsgWQvqLb19VDh5m8hncMNCOOqcFqKjEPAiVGXwCioQECBDkn8CPBeLV0rUk+JGFHET8V31tQ/Cv8Rdql7Igk9iB3OU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717924; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=doR/P2MXSgLBBH6RNtR26uKFBCyyOQhBDOm0tf03ZUU=; b=XaheR6ljDUxpM6q1S+BdRRsW5UCrTJs39ZvYyucv3QfmC50IOH9yc9QzDarQdep+IFCnjV1mN2odhpDBnDISetjPvuAcYC7Z5c22tyftk7CBbAMfsU9MHOT3OwMjPiZSto3+OWmMrRaBW09MVHY3kgHXB/cbSe0RLrfggRCtoiY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174371792443134.35753362674109; Thu, 3 Apr 2025 15:05:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sfz-0008EQ-WF; Thu, 03 Apr 2025 18:04:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sfs-0008Bk-G1 for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:36 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sfq-0003jY-CM for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:35 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-39c1efc4577so824293f8f.0 for ; Thu, 03 Apr 2025 15:04:33 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34bbd9csm29067355e9.20.2025.04.03.15.04.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:04:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717872; x=1744322672; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=doR/P2MXSgLBBH6RNtR26uKFBCyyOQhBDOm0tf03ZUU=; b=BN6sBbNrh/+GkiPrvdImg0pQwD648IpUi6c0W3/7TdCeoRXl+o/+NbUAen4QMCUap+ 9rk2Md8itnBCACxjLgYqLKMDSXILK6xydHeuzvs5pOVrW2qyzitIJTbZindwl1j/+IJW bQuXbt/u9nu0nrg/wRv5RLjUPQLax/1V9O1/MbwWE4SHDcmB7tyV7cSEbr1TiGralG6H 11Zkbi2+K0PHk7KvtFscF6T9D50hMJ7AC7aFVW1qiHDByflQoDz5LZ+1X1bRPOT2X7E/ +qcS6wOcwJVTGxzDSJFtPm5jH2wkbu0fboOmI6xZ0rAaHxrCQW1lTvARCzDqqnjHONp4 hbQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717872; x=1744322672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=doR/P2MXSgLBBH6RNtR26uKFBCyyOQhBDOm0tf03ZUU=; b=KZET/4bbGW77AW6eQBAmYJLJ3R09G5OmvwuxCI1yPaQbj3ZxCrWTGYj6R5WfUXCQCI JhAae/l3v8WsJ2rEnVhMkzB07tN2oWzcCc4VMZ1o3iBvmN9688FBqzfQ1sD5Xkj1hKHC wNmvpX9ZNM23uEslpIdUyO0l8VDkKke72zITRjITQWZIccxdQ+t/ICmoiO2FlUYZLPXK EaavgdeG+XD8RHV6ix4tNwHtylhLZ33ygAcO5O6ShQNcKDgVF+VsW3VzSefr5kSe1YoS xULzel89f6MDXt/06L+oBmrbHjoMIRq+RyzF5+qyltTpgayFtqnHbXI3f6aTbeVP5J5/ +7Cw== X-Gm-Message-State: AOJu0Yz/b/x1tu2Ec46TcJzBNkeW7snAJ3HML9JV/B4MrI0zQ65Li+Vz oJ6f/NHf370DVoWtv7RVFCLaiSTNQ7M53FO2XRbp8CohqrPF5XDlPFuC8SPthSp5rWz2I8GWY1w 1 X-Gm-Gg: ASbGncveg33vML1w+0HngU7kCLgDjAPyB08rJMRyGUVMJMMMlhlavZd6CA3f4SxP9jj JhqqPWhKV+P2O8+ePxHEQooK5lfNhJeuKb1r9YZOXYMSJo7HdJPxhuf+WV1ZsxhkWp0xvnoF4vz Pd+YUy37lqesHXMgw03gclZWiEKefTZjRLN24DTbjOV78OD43Nzm162axYWA+dhLr2HB95ncUt4 G10FhNK7z+ow9S86SfJXGzHNApkuJ3CkCkOECTklDWIWGMl8WAS7Tdhr0UOmn4MSN6B9zGQTjSg V02YcAmQz7D3prNudAWLG5cfnKn8gHGSTaElG2G4f7gfCo7vRfBCImZKCOEJ+R/oRwgkEhVO5WF Yv0ZT8CbbZ2/Qi/JmiJ76Hzn+nAnzAXOSzt4= X-Google-Smtp-Source: AGHT+IFOkYUpVSPkc2bAR8n2N3fXRVwKd2t82FH1yKd7cmz4w1UTFtbrjNsDvVTncdDWVzBtmnl1hQ== X-Received: by 2002:a05:6000:248a:b0:391:39fb:59c8 with SMTP id ffacd0b85a97d-39cba93245dmr653739f8f.25.1743717872586; Thu, 03 Apr 2025 15:04:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 02/19] tcg: Include missing 'cpu.h' in translate-all.c Date: Fri, 4 Apr 2025 00:04:02 +0200 Message-ID: <20250403220420.78937-3-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717925972019000 tb_check_watchpoint() calls cpu_get_tb_cpu_state(), which is declared in each "cpu.h" header. It is indirectly included via "tcg/insn-start-words.h". Since we want to rework "tcg/insn-start-words.h", removing "cpu.h" in the next commit, add the missing header now, otherwise we'd get: accel/tcg/translate-all.c:598:9: error: call to undeclared function 'cpu_= get_tb_cpu_state' [-Wimplicit-function-declaration] 598 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/translate-all.c | 1 + 1 file changed, 1 insertion(+) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ed41fc5d0cc..c5590eb6955 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -69,6 +69,7 @@ #include "internal-target.h" #include "tcg/perf.h" #include "tcg/insn-start-words.h" +#include "cpu.h" =20 TBContext tb_ctx; =20 --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717938; cv=none; d=zohomail.com; s=zohoarc; b=EN4bk0Jy1MCG+Saqqacooe+KJJRNnDl3wPczgfDPqUgULeC705MfHoEub4+5WIvLF2Zt9OnsbUv1TJCq8x83uIJkpGvJroCaz7cBB3yPcXFdnYaHrxFNzRbsngomnfXJ9t8pPnAg4NB8D51vjZNG6TBOwuXSvnG4lEf3EVF+Ikw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717938; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mHeTYglzmD8BrZIK9Mnh/ewYhuzHvjJofyPQpxBIxgw=; b=BI+xVj47BDkEQR0lkgNWkxaQppQ+hhBDTqb1L9AZ//5Y/7XwVX9keAsHkEe8xnhprVmdqnFC0cTBF4+IPjqIgsfujx8DRvfL/pEGe/APdf/DjNQb//7yDHJLAd1s8IRjh+NLztOYhd0NP+EF2itWYW/XF0qwGNeIGyo3niJRaI0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743717938850525.3553022641751; Thu, 3 Apr 2025 15:05:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sg2-0008F9-Sa; Thu, 03 Apr 2025 18:04:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sfy-0008EM-Aq for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:42 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sfw-0003k6-1S for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:42 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4394036c0efso9978095e9.2 for ; Thu, 03 Apr 2025 15:04:38 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec17b3572sm32420555e9.39.2025.04.03.15.04.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:04:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717877; x=1744322677; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mHeTYglzmD8BrZIK9Mnh/ewYhuzHvjJofyPQpxBIxgw=; b=e8XfsoZSKe81cVcDKmNwmLqYfKE53+XrJbF+5PtWgb/DpjdptqoySGu/wMBkfJYHb7 EiFZ1b/hcCiKQ4L7+oyiw67jxhhKwJNj7lmHUjOxxhmvbpC7QgGJs375nJUuN1Zx/lRI nx73vT37KuQVFgSfUyGTbuTs438UKVfn9QeSxQMzLETQX0qVj9QKg3UqtrH9ouoW/ulM lbg+xwPlFbTTcA3n+ssGRIU7R6HlZiliAdJ+iLiCFDd2Cz3L1oFKEQZ4Ap0cOvPWnP2t 1FQyolOt4DkHW/X2WOhNz+uCpHQ7/5XyOUcgfEkhRXInJnH9zX6XRxoViB7nKKGN1jNe /oHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717877; x=1744322677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mHeTYglzmD8BrZIK9Mnh/ewYhuzHvjJofyPQpxBIxgw=; b=Hta/nkEOKIQhwPNmxz91Cu2aexkvoSvgig9wvHiWwYPgKGBmnq+X7I0icE+dNOP4E7 NtC99nga4ee+lnYIK79JjcgXEWjcwz53KTo73m5Ey1Bh64+BBI/P9cnnAuPMYNxM3owI ZqrVjOzqNyiE3c91cBCiqVfVttxkmD+MBaZ9UTY1fG2dVx2dGnPjwqCs9h3L4EqpzNr2 nNa8hyp2Ql+lffAMFcxwC0ApQ1hJ12n7IQAe+cvKBj2KHehvFvp86rLcDl5qoepamggI ug1mDdlo6HKxSS+HVMZgEllIouGAWXu3k0JHOOtSUvatrctmsUSwOVm4IGFxjB6TOx3s rjEw== X-Gm-Message-State: AOJu0Yxosq5jwZXFIMBNE+myvcicmjF0NyLSOsrFgP8fBJyHBE0EqnUE OqX6aKM7PEOstsPHeKKtrlscCP4kYj1Trpt1R9D1vhvqsQ9/KAMeRGVGf1EDQniB7Re/5w/WDNa x X-Gm-Gg: ASbGncu7zRrei21j5cRKPm9zuBB/z2ogsfVa17rqVVsgaXm3X2yktMm/JPgTPKqcJNr 6vlpDWGCIhk1nCCApsJ7QsEKlJJKbsrTcOg+QnPtudXHteulx7s/9vLkKzJcUkY3XF0VeH4qbiN nd8ggg8ejRiLlgZ3yjFrvrN2CSN/3AuLuL0e/oGfySOwJ4a22Wm2O/BD6UAIyxId/KXp/Qc76Qt oRJwsdefGGUkPUm4scQdM/XIU1dB5FyrxdHT4zuZ4ut0/Axgeyon/+2KXT8SexHbUI4Bp24hs4O 4KjrdB/tGK/1dj7A02S6S0NIpubWfCvL9ueNRvOh7MKGE0zP4xrcAb/ec2gm7eJLEBiMUYQfNQw 7NeB/rC5dlIyOouzjyqB+v+wn X-Google-Smtp-Source: AGHT+IFvzYwsBYymxWQ3e0i/lDsstowCcQ3op1aMJwNZAJXlmGjILNtzteeJr6O8zcP/iYlI0cDDpw== X-Received: by 2002:a05:600c:1994:b0:43c:fc04:6d48 with SMTP id 5b1f17b1804b1-43ed07bdfc1mr3262785e9.0.1743717877113; Thu, 03 Apr 2025 15:04:37 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 03/19] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h' Date: Fri, 4 Apr 2025 00:04:03 +0200 Message-ID: <20250403220420.78937-4-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717939750019000 To avoid including the huge "cpu.h" for a simple definition, move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/insn-start-words.h | 2 +- target/arm/cpu-param.h | 7 +++++++ target/arm/cpu.h | 6 ------ target/hppa/cpu-param.h | 2 ++ target/hppa/cpu.h | 2 -- target/i386/cpu-param.h | 2 ++ target/i386/cpu.h | 2 -- target/m68k/cpu-param.h | 2 ++ target/m68k/cpu.h | 2 -- target/microblaze/cpu-param.h | 2 ++ target/microblaze/cpu.h | 2 -- target/mips/cpu-param.h | 2 ++ target/mips/cpu.h | 2 -- target/openrisc/cpu-param.h | 2 ++ target/openrisc/cpu.h | 2 -- target/riscv/cpu-param.h | 8 ++++++++ target/riscv/cpu.h | 6 ------ target/s390x/cpu-param.h | 2 ++ target/s390x/cpu.h | 2 -- target/sh4/cpu-param.h | 2 ++ target/sh4/cpu.h | 2 -- target/sparc/cpu-param.h | 2 ++ target/sparc/cpu.h | 1 - 23 files changed, 34 insertions(+), 30 deletions(-) diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h index 50c18bd326d..c439c09f2fe 100644 --- a/include/tcg/insn-start-words.h +++ b/include/tcg/insn-start-words.h @@ -6,7 +6,7 @@ =20 #ifndef TARGET_INSN_START_WORDS =20 -#include "cpu.h" +#include "cpu-param.h" =20 #ifndef TARGET_INSN_START_EXTRA_WORDS # define TARGET_INSN_START_WORDS 1 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index a7ae42d17dc..2cee4be6938 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -37,6 +37,13 @@ # define TARGET_PAGE_BITS_LEGACY 10 #endif /* !CONFIG_USER_ONLY */ =20 +/* + * ARM-specific extra insn start words: + * 1: Conditional execution bits + * 2: Partial exception syndrome for data aborts + */ +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1a0faed3ad..3705b34285b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -98,12 +98,6 @@ #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif =20 -/* ARM-specific extra insn start words: - * 1: Conditional execution bits - * 2: Partial exception syndrome for data aborts - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - /* The 2nd extra word holding syndrome info for data aborts does not use * the upper 6 bits nor the lower 13 bits. We mask and shift it down to * help the sleb128 encoder do a better job. diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 7ed6b5741e7..68ed84e84af 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -19,6 +19,8 @@ =20 #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* PA-RISC 1.x processors have a strong memory model. */ /* * ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 2269d1c1064..1c8b610647b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -48,8 +48,6 @@ #define PRIV_KERNEL 0 #define PRIV_USER 3 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - /* No need to flush MMU_ABS*_IDX */ #define HPPA_MMU_FLUSH_MASK \ (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \ diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index b0e884c5d70..0c8efce8619 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -22,6 +22,8 @@ #endif #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + /* The x86 has a strong memory model with some store-after-load re-orderin= g */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 35c16302bdc..16d76df34b2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1610,8 +1610,6 @@ typedef struct { #define MAX_FIXED_COUNTERS 3 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #define NB_OPMASK_REGS 8 =20 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 7afbf6d302d..256a2b5f8b2 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -17,4 +17,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + #endif diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 0b70e8c6ab6..39d0b9d6d73 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -78,8 +78,6 @@ #define M68K_MAX_TTR 2 #define TTR(type, index) ttr[((type & ACCESS_CODE) =3D=3D ACCESS_CODE) * 2= + index] =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - typedef CPU_LDoubleU FPReg; =20 typedef struct CPUArchState { diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index c866ec6c149..5d55e0e3c4a 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -27,6 +27,8 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + /* MicroBlaze is always in-order. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 2bfa396c96d..d511f22a559 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -233,8 +233,6 @@ typedef struct CPUArchState CPUMBState; #define STREAM_CONTROL (1 << 3) #define STREAM_NONBLOCK (1 << 4) =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - /* use-non-secure property masks */ #define USE_NON_SECURE_M_AXI_DP_MASK 0x1 #define USE_NON_SECURE_M_AXI_IP_MASK 0x2 diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 8fcb1b4f5f2..99ca8d1684c 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -20,6 +20,8 @@ #endif #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 2 + #define TCG_GUEST_DEFAULT_MO (0) =20 #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 20f31370bcb..d16f9a7220e 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -100,8 +100,6 @@ struct CPUMIPSFPUContext { #define FP_UNIMPLEMENTED 32 }; =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { int32_t CP0_MVPControl; diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 37627f2c394..7ea0ecb55a6 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -12,6 +12,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + #define TCG_GUEST_DEFAULT_MO (0) =20 #endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 19ee85ff5a0..569819bfb0b 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -40,8 +40,6 @@ struct OpenRISCCPUClass { ResettablePhases parent_phases; }; =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - enum { MMU_NOMMU_IDX =3D 0, MMU_SUPERVISOR_IDX =3D 1, diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index fba30e966a8..ff4ba81965a 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -16,6 +16,14 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ + +/* + * RISC-V-specific extra insn start words: + * 1: Original instruction opcode + * 2: more information about instruction + */ +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* * The current MMU Modes are: * - U mode 0b000 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 867e539b53a..167909c89bc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -45,12 +45,6 @@ typedef struct CPUArchState CPURISCVState; # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 #endif =20 -/* - * RISC-V-specific extra insn start words: - * 1: Original instruction opcode - * 2: more information about instruction - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 /* * b0: Whether a instruction always raise a store AMO or not. */ diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index 5c331ec424c..a8a4377f4ff 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -12,6 +12,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 =20 +#define TARGET_INSN_START_EXTRA_WORDS 2 + /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 940eda8dd12..90f64ee20cc 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -37,8 +37,6 @@ =20 #define TARGET_HAS_PRECISE_SMC =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #define MMU_USER_IDX 0 =20 #define S390_MAX_CPUS 248 diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index 2b6e11dd0ac..f328715ee86 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -16,4 +16,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 7752a0c2e1a..906f99ddf00 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -127,8 +127,6 @@ typedef struct tlb_t { #define UTLB_SIZE 64 #define ITLB_SIZE 4 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - enum sh_features { SH_FEATURE_SH4A =3D 1, SH_FEATURE_BCR3_AND_BCR4 =3D 2, diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 6952ee2b826..62d47b804bb 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -21,6 +21,8 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 1 + /* * From Oracle SPARC Architecture 2015: * diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 734dfdb1d3d..83ac818933b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -223,7 +223,6 @@ typedef struct trap_state { uint32_t tt; } trap_state; #endif -#define TARGET_INSN_START_EXTRA_WORDS 1 =20 typedef struct sparc_def_t { const char *name; --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743718162; cv=none; d=zohomail.com; s=zohoarc; b=Rctf1J92y9YVg68iaJRbejL1rPel1bgKtVuUrCOieZSLmhKnUUJojd23FhB7DcRJQisA9a3St12upMBWchwOCD1kugrISLWRM5mscmgJorIsjCvvUqv+ER7sDfv5eDQLjceKU825Eo/vbzMrCSI0YnS7W7jayVoGPLeAbKU6BxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743718162; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GGrFJ4R/UrCSTPkLctl7uvnpTFEBVznWA25W+AuvYOI=; b=FI2r9tFVusiwuq2t3/dlpYaiW5HghjWbJMNNUVIRZn1VHpZ4o49O9bnQvUbY6KM20EDlp7moxA9pHU6m3plSm0Jndnxb/knx5vIbs+wN5p6XxTTdrn0UCYDip2XxbKXecv4aI2yPkwRbq4PqYBqyBBV2x8Za+hXNwTuFf8UzZUM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743718162946224.9508409466648; Thu, 3 Apr 2025 15:09:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sg4-0008Fk-Hc; Thu, 03 Apr 2025 18:04:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sg1-0008Ex-K4 for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:45 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sfz-0003kY-L7 for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:45 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3996af42857so1720502f8f.0 for ; Thu, 03 Apr 2025 15:04:43 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096861sm2867966f8f.14.2025.04.03.15.04.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:04:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717882; x=1744322682; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GGrFJ4R/UrCSTPkLctl7uvnpTFEBVznWA25W+AuvYOI=; b=kroefLfLWs4XvRTkD5kxLBpYsE6r9NEBlwZgsn7vWVLbYLntuXJUkT9jV+BRbaCMFK F11gqZZHz0JfKeSilWoo5uJg6Iki1+FU0WoiZZ71jeKJ151TFSplCemm5B6jkdzwpdK+ pNydrZx0vBcPFJVELqPeRn0EmrQKdDFaXi6ejCFTJsGUS4VC4ig135QAUdoKLDetWJr6 IsLfAGpHUcb1C2mZgFTLF85+g1LvjKXysTYcS4t3wZnWci6tFaaqp3rw7cV5Fmi74aw7 qyID4SrDvNC2Wx6726/ecUmrpnoy1084M/uI61p/tCOebFYVWTBY+z0pT+zftVGRFJfV gwUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717882; x=1744322682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GGrFJ4R/UrCSTPkLctl7uvnpTFEBVznWA25W+AuvYOI=; b=RTzNRTqyoRmt1Xaw0RLA1PAJn7t5EH6/TmzcJjT4rAU/OX3HjbAvr+IjCFkocSyGue rrUf0IdjJ2t6+qVbaT0ZijZiewr7wsHjxLhokCvnN/lOiAk8FbW4KbKQR4lYEXk1mSqq 80t2xkuwNKWad8hGBwpqlfbPah5agXbMsWILeBAZS3lva/v3J8iEj9SUES3v2xq718BT wDhBggMm5hrXtgyxVYv5HWvalYWEqhWYlsYYxynMNFTNtR5B6WSPTHjA+1wcOA1o9A4H u6e6eHZ+GdUKjuwYA/AWflYSVsOoLfSgU3BDvcy18RTp1csqSfjCqbNu/PVTJXJy8xUI yTRw== X-Gm-Message-State: AOJu0YyihWPjqaBUnVOsIBCCrBPAQ9EorEcl/rZWSN/2AcvO6nkGpoMy 84/X+XrMP7pnq3A0et4xcK9YDa32jJeBo40H3+vjrSArqTG+D2T27v56T4ZgbV0aL8ByUkcLoFd U X-Gm-Gg: ASbGncu77oxrW71f5Xdne5vTJgigqc7mn/bqd+BLtW4duXJp34JX8ULD2y89oBLMrJx cZy4BS3aNEvwVSBSRBoGW2WhSUEtiPfW8SOpj+73XHuI9kR0eKnH6rImRSXb7Es8qCpPMMC2iNs MDIHZOvtRgrOGuk1ZLhwlzSeh0YeUcJfk7enpZLf/5aznn8qiaqUAsjRidPAQqv+5iKQY7bXeSx +6YKP4Q30JkagsPjoAsK/0pyxLD/0dkZhPhgMg3joHTrz+Pm0NrJp0wONVmN5lLo463n1Y1KxTD lGBdfa47fcgOjvTzZkfQsKiS9rNMWeOInXLykyYHzvrO1tHwTOyKZB71g9VYz9jB7Ge3U9sNPGB 9d4FHqVAW2bwz15WLwvFuCi4o X-Google-Smtp-Source: AGHT+IH0h0wnuUERf6CwMGHWgxQDlLzwQXjJQ0zOSi5PUkSuWCVRVO+eClgyVkBxd4gVFDm5gqS79A== X-Received: by 2002:a5d:5f8e:0:b0:39b:32fc:c025 with SMTP id ffacd0b85a97d-39c2e5f50f4mr3901408f8f.2.1743717881841; Thu, 03 Apr 2025 15:04:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 04/19] tcg: Always define TARGET_INSN_START_EXTRA_WORDS Date: Fri, 4 Apr 2025 00:04:04 +0200 Message-ID: <20250403220420.78937-5-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743718163731019100 Do not define TARGET_INSN_START_EXTRA_WORDS under the hood, have each target explicitly define it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/tcg/insn-start-words.h | 4 ---- include/tcg/tcg-op.h | 2 +- target/alpha/cpu-param.h | 2 ++ target/avr/cpu-param.h | 2 ++ target/hexagon/cpu-param.h | 2 ++ target/loongarch/cpu-param.h | 2 ++ target/ppc/cpu-param.h | 2 ++ target/rx/cpu-param.h | 2 ++ target/tricore/cpu-param.h | 2 ++ target/xtensa/cpu-param.h | 2 ++ 10 files changed, 17 insertions(+), 5 deletions(-) diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h index c439c09f2fe..d416d19bcf9 100644 --- a/include/tcg/insn-start-words.h +++ b/include/tcg/insn-start-words.h @@ -8,10 +8,6 @@ =20 #include "cpu-param.h" =20 -#ifndef TARGET_INSN_START_EXTRA_WORDS -# define TARGET_INSN_START_WORDS 1 -#else # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) -#endif =20 #endif /* TARGET_INSN_START_WORDS */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index bc46b5570c4..cded92a4479 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -23,7 +23,7 @@ # error #endif =20 -#ifndef TARGET_INSN_START_EXTRA_WORDS +#if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 static inline void tcg_gen_insn_start(target_ulong pc) { TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BIT= S); diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index 63989e71c06..dd44feb1793 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -24,6 +24,8 @@ # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f5248ce9e79..9d37848d97d 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -25,6 +25,8 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO 0 =20 #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 45ee7b46409..635d509e743 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -23,4 +23,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 52437946e56..dbe414bb35a 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -13,6 +13,8 @@ =20 #define TARGET_PAGE_BITS 12 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO (0) =20 #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index 553ad2f4c6a..d0651d2ac89 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -37,6 +37,8 @@ # define TARGET_PAGE_BITS 12 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #define TCG_GUEST_DEFAULT_MO 0 =20 #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index ef1970a09e9..84934f3bcaf 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -24,4 +24,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 790242ef3d2..eb33a67c419 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -12,4 +12,6 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 5e4848ad059..e7cb747aaae 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -16,6 +16,8 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +#define TARGET_INSN_START_EXTRA_WORDS 0 + /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) =20 --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743718155; cv=none; d=zohomail.com; s=zohoarc; b=TJLiJeD7qXWCELpuBhHUyyXHjHG5Ii8h09o1xi7KZxx3nv/kvIagN9V8hd2RfEe1DLur8g0h0B+owR1zG6vcwO8iVVi2o/O9lRrLUHF6qlqwgEu9h2QlIjJjQniBBs1BpnctBz+q7cY8SIGq2tmKS7o3mN7FAD+Q/jUvdS+v53U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743718155; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EVyO4Mxkb0F/UGcN3gePDsdWIGD9Ydr6wuyRdXDPD+Q=; b=lOBrUGgwUkp/Odlpk7Yhqfsb3E9+QXOA2asODdPr61SVAmtRl7ISD1JMu3f//7NizAJD9dmiLTjTvDrlIeuF1GX398vZmkNWE3M3osjzu0+aoNk5xhOcXhx8RubkBJ9kL/8gZ3yKMTiq+Fz4vObsylDtruPYnL88NqwVBx0dm0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743718155755179.4158252434762; Thu, 3 Apr 2025 15:09:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sg8-0008GC-Jy; Thu, 03 Apr 2025 18:04:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sg7-0008Fx-0u for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:51 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sg5-0003kr-7J for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:50 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-391342fc0b5so1103051f8f.3 for ; Thu, 03 Apr 2025 15:04:48 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096ed7sm2737003f8f.8.2025.04.03.15.04.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:04:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717887; x=1744322687; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EVyO4Mxkb0F/UGcN3gePDsdWIGD9Ydr6wuyRdXDPD+Q=; b=URdunBJh8DY80KX5Beg43D7egiIaHQF4oTM8S9ezIQJ9UVrkr4aiB2dYhWgUtA94qW m32ECmOWVt9ZTptlGwg0Ui02OMZajZtoaIaF3u8OLE96jY8qWO914qccwSfRX0GP9SVQ pD7O9nvZ7KVpeuTpsXIgcaJZud+KFBjJ28v4BGxLiazpdtD8OLwXQu1AsuaXrH2zyO8E L9QcNoWhB4xCcRq596xUleQrDz/lIxa+9Yaij0QsSJTuMblFQwg0+fVRTUAXPeXecXZV ZhbATexFvuQN/3IKEnEaZwUTsM+ZZ2e/RhydkhzCzM/tn8cfIqlPwF+vkquZRSK4Zky6 2W5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717887; x=1744322687; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EVyO4Mxkb0F/UGcN3gePDsdWIGD9Ydr6wuyRdXDPD+Q=; b=HMF8VZiAqIQ+qkis0OCScCqfWMKH0rpcwrgLjiCVC3rOjjFE9duggKhf6zJ3r/wnLm RSPg03RdQoghwK3gOeneFgIznNwvbDTApfdc0caDHcjdjMc0ZIDH0joOdVyuIktwoktt P7j5bJkM/07a+nNGJN5L4n/YxzYgFpH/C9Pua/llHy3fkNuog5i38eQJGuKIX9UalJ2W VW4A83berGH0Lk7YXUh0ISjImbBu8wdZpXlIRUP2z91p3+ogQd/q0NG7nCLU/TEpDNmw b4N85kpZVmUFYqq5Zel7DKoLoJ5D6nVDw4zm0tuW7GY9QVBj5NFZGMIN3As3Uivqivg/ uDBg== X-Gm-Message-State: AOJu0Yyrq+IAldPoU7yiPdRoQm0ag4pKx8gzs/dhXCBgNqKu8w95qps0 hSusxC9TIgDEDeV0OUY8DYeigQxIhgiwQqXuUN3xPDCFf4U+a+esHu9gop4XQWE56z5vRAUYrC+ Q X-Gm-Gg: ASbGncsS6NNHg6MM7IEweuweOtH/AJeGPy9bNBzK9xQXsbZGhKi629iAEBYBlAj/PHV iiKhF/a+DMcePRciUGAHTjuVDN1RnMZBMifdJDbaGpaMJFLZzk/H/RXIUOZSLBfxKVNa1oWXFop 8iM+uBUPLUpCrldMQULXzl+w2KmUhRJDhA53mVKaaltuuTPIHjfYeHR7hpP/MIea2lgF19wjvdH 8TIKv9K9oUxelDW8SMH8aFjAKK6npAE+KKzf4NdxZAOQGP5mGSycIGARTmS0YObRweF8Xs4Exjz O69e6MNNZi61HsDTPqtxDDDXeEI4B/vKWtUlzbyKm+TumAw7xgPfmNQBXwnXekT/ysIGo/dr6N1 z7O+Yw75y7WGdrfDEJg5WznPB X-Google-Smtp-Source: AGHT+IES0mUMLoE+3N5qi3N1Djr4XiyGGgr0Sn2Ycr5lt6KM0+rUCdFcbzNhV9x9GD+va3GNOU2clA== X-Received: by 2002:a5d:64ce:0:b0:391:3915:cffb with SMTP id ffacd0b85a97d-39cba9825d3mr679089f8f.43.1743717887087; Thu, 03 Apr 2025 15:04:47 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 05/19] exec: Restrict 'cpu-ldst-common.h' to accel/tcg/ Date: Fri, 4 Apr 2025 00:04:05 +0200 Message-ID: <20250403220420.78937-6-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743718156745019000 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/{exec =3D> accel/tcg}/cpu-ldst-common.h | 6 +++--- include/exec/cpu_ldst.h | 2 +- accel/tcg/translator.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) rename include/{exec =3D> accel/tcg}/cpu-ldst-common.h (97%) diff --git a/include/exec/cpu-ldst-common.h b/include/accel/tcg/cpu-ldst-co= mmon.h similarity index 97% rename from include/exec/cpu-ldst-common.h rename to include/accel/tcg/cpu-ldst-common.h index c46a6ade5db..8bf17c2fab0 100644 --- a/include/exec/cpu-ldst-common.h +++ b/include/accel/tcg/cpu-ldst-common.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ =20 -#ifndef CPU_LDST_COMMON_H -#define CPU_LDST_COMMON_H +#ifndef ACCEL_TCG_CPU_LDST_COMMON_H +#define ACCEL_TCG_CPU_LDST_COMMON_H =20 #ifndef CONFIG_TCG #error Can only include this header with TCG @@ -119,4 +119,4 @@ uint32_t cpu_ldl_code_mmu(CPUArchState *env, vaddr addr, uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra); =20 -#endif /* CPU_LDST_COMMON_H */ +#endif /* ACCEL_TCG_CPU_LDST_COMMON_H */ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 63847f6e618..74761ba5f30 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -67,7 +67,7 @@ #endif =20 #include "exec/cpu-common.h" -#include "exec/cpu-ldst-common.h" +#include "accel/tcg/cpu-ldst-common.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/abi_ptr.h" =20 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index c53bbdef99f..034f2f359ef 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -11,7 +11,7 @@ #include "qemu/bswap.h" #include "qemu/log.h" #include "qemu/error-report.h" -#include "exec/cpu-ldst-common.h" +#include "accel/tcg/cpu-ldst-common.h" #include "accel/tcg/cpu-mmu-index.h" #include "exec/target_page.h" #include "exec/translator.h" --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717938; cv=none; d=zohomail.com; s=zohoarc; b=OWTO/dxSK+dod1idh1WopA30wSW+F6OfgzPU9dUV6xMSHJ0S7H42QyVjPzACcYET166NVHh76EKW0O1lseglJdrR7Mbd4XFMnVE6Kxs5cvqlFPnNDG2+tmpoxQ6ectHVxxwxevTjRpBuhoX3nNZ0OnPFUN5hpnDRw2fbn9armhc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717938; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2KXOzDB2gse2g7W4UaWCuE7+DNS89zrd8hUtTGN3caM=; b=U+kSjgzcjF4uZiL39k1WQHen9zdT0M/8roNJd00KBuaQi1Tj4KWtQPGlsV9EHU4KL7npQ7G4VZyb8lmQko7J5fx6MjJ+xV4bpRS7zbykmL00cWNZONSMvWemrNMhPihgNRyDParhvD38rD0mTFyQ4CcAH/wFgWS3lkoK2KaB3W0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743717938820792.3640061700834; Thu, 3 Apr 2025 15:05:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0SgF-0008Gy-St; Thu, 03 Apr 2025 18:04:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0SgD-0008Gj-Rg for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:58 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0SgA-0003lS-3c for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:57 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-39129fc51f8so1165321f8f.0 for ; Thu, 03 Apr 2025 15:04:53 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301a0a90sm2791321f8f.21.2025.04.03.15.04.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717892; x=1744322692; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2KXOzDB2gse2g7W4UaWCuE7+DNS89zrd8hUtTGN3caM=; b=VXDCEbT+NQ7Y5dSsZJiNcMTdJo9EA7yLUrWWoSOhmRN84eexLyYdmOj8Uviu9RKl6C lUQIj/T27SVohvWBwaseACVa4krjTNifRCXmiL9TRJMGlrfDuR8ESjbYYJvTYai02TpB zHYFbsNX//yJmdi60JUcMFzGnKYkAiHgwdkktCF/tpVcEFY5TVdTzlGLZZJ9r8AcbK4r uy4jJEhbIYv+1h++RwG8XGGUdrlMVzSCM+rKdB2TvUyVAJJgNWGrGoby3KtyKEVcBfDT AJVfYH5FQCWW7LPHTOCib5wL6IdfSwHq8Kvi1AG5iVXyNw5gDx1xcm2VWolQH4Y6gZjD JXbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717892; x=1744322692; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2KXOzDB2gse2g7W4UaWCuE7+DNS89zrd8hUtTGN3caM=; b=KwZ2TKbo8aUTS0AWTSL6/Fel5ueVWni1Sgw2E1EBjI9BS1MW7v/XeF69+8m7WDq0PR GHOy0zjQiCOEwgoba2N9QFaXce+u/gInqtj/KHAvtewKuOiAwfTihB7HiUkpupvVeoMr 4yxA8pj/n/hichsKaOyW0uRGkZJGIxPQ6XcWMoLQXr0kbd29E5nod9V0L4lIOvIEzhGk 4kEIxXBXpp1jU/JbEuZAqYYQ+1oTYxq1wjktRvZjg/3qoUl/PN8SNsnehX4adTWXGfSy ftGSYp6fzxLlzyKG+YoFaAXmqw2KsmdhxidK4Z+ZDDicg+I9wNCZxsVzibUhPqZilSq7 yrLw== X-Gm-Message-State: AOJu0YwMucJWyWpXfh0ZY+JUZkFbQhExPMshzGP3tZF+hbSJdfgonx9h dSPAbmpIpE7qQlwGFvErwcYFiE5ygFgCfjFxppm/jiozYNQ9ZduoRCEkC1qmXI210e2YOWSoq6V G X-Gm-Gg: ASbGncsbuiyb9VMA67zObc/dYq6I6WF8/NYfH0PFwKB9L5EMlSBQygL8ID0XgwcZBZ4 n6rkweu+R4EAtmz6s7g4K/ARFEdwEWzElmpOvWqk4DnPCS5lvVgdSV0eesB+XmXe/EwFWVPd8Oo SCNPm1wGm0Z7am3IoLnDfEL1nQlHRPJEPbM9CQKsnsTPUL9ZgJcJAS66H9zTg/IBVnW+EQSRvO3 Zw4eGG+10qNGemoRH61DWO+tqHFOLvDILk+LPE9ioUMPaPRKI5oro5gHeNGJZqXtdGV8atVHkhs UevA4I0M0P73f/QM71BNOP5LqNvSJM+0cYlaDCvZwrYk6QuIUMJ/yVY3vSs8y5UdBilUKyuobEa QAmW5goedPwFAFC4ewnvJti69 X-Google-Smtp-Source: AGHT+IED2z1J1h4rz3EMwQfQDOw4vBFlt5ZtEPdyK+VG50epgKnBRFKM+BUorV21TQQzKa2lCvT9LQ== X-Received: by 2002:a5d:5c84:0:b0:390:f552:d291 with SMTP id ffacd0b85a97d-39d0de1b814mr300595f8f.22.1743717891824; Thu, 03 Apr 2025 15:04:51 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 06/19] exec: Restrict 'cpu_ldst.h' to accel/tcg/ Date: Fri, 4 Apr 2025 00:04:06 +0200 Message-ID: <20250403220420.78937-7-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717939604019000 Mechanical change using: $ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \ $(git grep -l exec/cpu_ldst.h) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- bsd-user/qemu.h | 2 +- include/{exec/cpu_ldst.h =3D> accel/tcg/cpu-ldst.h} | 6 +++--- include/exec/exec-all.h | 2 +- linux-user/qemu.h | 2 +- target/arm/tcg/sve_ldst_internal.h | 2 +- accel/tcg/cputlb.c | 2 +- accel/tcg/user-exec.c | 2 +- target/alpha/mem_helper.c | 2 +- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/mve_helper.c | 2 +- target/arm/tcg/op_helper.c | 2 +- target/arm/tcg/pauth_helper.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/avr/helper.c | 2 +- target/hexagon/op_helper.c | 2 +- target/hexagon/translate.c | 2 +- target/hppa/op_helper.c | 2 +- target/i386/tcg/access.c | 2 +- target/i386/tcg/fpu_helper.c | 2 +- target/i386/tcg/mem_helper.c | 2 +- target/i386/tcg/mpx_helper.c | 2 +- target/i386/tcg/seg_helper.c | 2 +- target/i386/tcg/system/excp_helper.c | 2 +- target/i386/tcg/system/misc_helper.c | 2 +- target/i386/tcg/system/seg_helper.c | 2 +- target/i386/tcg/system/svm_helper.c | 2 +- target/i386/tcg/user/seg_helper.c | 2 +- target/loongarch/cpu.c | 2 +- target/loongarch/tcg/csr_helper.c | 2 +- target/loongarch/tcg/fpu_helper.c | 2 +- target/loongarch/tcg/iocsr_helper.c | 2 +- target/loongarch/tcg/op_helper.c | 2 +- target/loongarch/tcg/tlb_helper.c | 2 +- target/m68k/fpu_helper.c | 2 +- target/m68k/op_helper.c | 2 +- target/microblaze/cpu.c | 2 +- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/tcg/ldst_helper.c | 2 +- target/mips/tcg/msa_helper.c | 2 +- target/mips/tcg/system/tlb_helper.c | 2 +- target/ppc/mem_helper.c | 2 +- target/ppc/mmu_helper.c | 2 +- target/ppc/tcg-excp_helper.c | 2 +- target/riscv/op_helper.c | 2 +- target/riscv/vector_helper.c | 2 +- target/riscv/zce_helper.c | 2 +- target/rx/helper.c | 2 +- target/rx/op_helper.c | 2 +- target/s390x/tcg/crypto_helper.c | 2 +- target/s390x/tcg/int_helper.c | 2 +- target/s390x/tcg/mem_helper.c | 2 +- target/s390x/tcg/misc_helper.c | 2 +- target/s390x/tcg/vec_helper.c | 2 +- target/sh4/op_helper.c | 2 +- target/sparc/int32_helper.c | 2 +- target/sparc/ldst_helper.c | 2 +- target/tricore/op_helper.c | 2 +- target/tricore/translate.c | 2 +- 61 files changed, 63 insertions(+), 63 deletions(-) rename include/{exec/cpu_ldst.h =3D> accel/tcg/cpu-ldst.h} (99%) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index c1c508281a8..244670dd24d 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -22,7 +22,7 @@ #include "qemu/int128.h" #include "cpu.h" #include "qemu/units.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" =20 #include "user/abitypes.h" diff --git a/include/exec/cpu_ldst.h b/include/accel/tcg/cpu-ldst.h similarity index 99% rename from include/exec/cpu_ldst.h rename to include/accel/tcg/cpu-ldst.h index 74761ba5f30..f97a730703e 100644 --- a/include/exec/cpu_ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -59,8 +59,8 @@ * The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the * MemOp including alignment requirements. The alignment will be enforced. */ -#ifndef CPU_LDST_H -#define CPU_LDST_H +#ifndef ACCEL_TCG_CPU_LDST_H +#define ACCEL_TCG_CPU_LDST_H =20 #ifndef CONFIG_TCG #error Can only include this header with TCG @@ -560,4 +560,4 @@ static inline void clear_helper_retaddr(void) #define clear_helper_retaddr() do { } while (0) #endif =20 -#endif /* CPU_LDST_H */ +#endif /* ACCEL_TCG_CPU_LDST_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f52a680f42b..70608a11b60 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -21,7 +21,7 @@ #define EXEC_ALL_H =20 #if defined(CONFIG_USER_ONLY) -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #endif #include "exec/mmu-access-type.h" #include "exec/translation-block.h" diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 948de8431a5..0b19fa43e65 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -2,7 +2,7 @@ #define QEMU_H =20 #include "cpu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 #include "user/abitypes.h" #include "user/page-protection.h" diff --git a/target/arm/tcg/sve_ldst_internal.h b/target/arm/tcg/sve_ldst_i= nternal.h index 4f159ec4adf..f2243daf370 100644 --- a/target/arm/tcg/sve_ldst_internal.h +++ b/target/arm/tcg/sve_ldst_internal.h @@ -20,7 +20,7 @@ #ifndef TARGET_ARM_SVE_LDST_INTERNAL_H #define TARGET_ARM_SVE_LDST_INTERNAL_H =20 -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 /* * Load one element into @vd + @reg_off from @host. diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0de46903dd9..2cafd38d2af 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -23,7 +23,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "system/memory.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/cputlb.h" #include "exec/tb-flush.h" #include "system/ram_addr.h" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7f57d8f1aff..1b878ead7a7 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -26,7 +26,7 @@ #include "tcg/tcg.h" #include "qemu/bitops.h" #include "qemu/rcu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "user/cpu_loop.h" #include "qemu/main-loop.h" #include "user/page-protection.h" diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c index 872955f5e74..a4d5adb40c6 100644 --- a/target/alpha/mem_helper.c +++ b/target/alpha/mem_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t = retaddr) { diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 507dbc1a440..08d8f63ffea 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -30,7 +30,7 @@ #include "qemu/crc32c.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "qemu/int128.h" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index f7354f3c6e0..37dc98dc35c 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -18,7 +18,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #ifdef CONFIG_TCG -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "semihosting/common-semi.h" #endif #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 888c6707547..7dc5fb776b3 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -29,7 +29,7 @@ #else #include "system/ram_addr.h" #endif -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 274003e2e5b..f9f67d1f88e 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -22,7 +22,7 @@ #include "internals.h" #include "vec_internal.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "tcg/tcg.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 71ba406782f..38d49cbb9d8 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -24,7 +24,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "cpregs.h" =20 #define SIGNBIT (uint32_t)0x80000000 diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index c4b143024f3..59bf27541dc 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -22,7 +22,7 @@ #include "internals.h" #include "cpu-features.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index dcc48e43db3..96b84c37a2d 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -22,7 +22,7 @@ #include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" #include "fpu/softfloat.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index 32cbf179195..afa591470fe 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -27,7 +27,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" =20 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 6da8db8ea5c..3f3d86db2b2 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -18,7 +18,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "cpu.h" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index fe7858703c8..dd26801e647 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -23,7 +23,7 @@ #include "exec/helper-gen.h" #include "exec/helper-proto.h" #include "exec/translation-block.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "internal.h" #include "attribs.h" diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index beb8f88799e..2398ce2c648 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "qemu/timer.h" #include "trace.h" #ifdef CONFIG_USER_ONLY diff --git a/target/i386/tcg/access.c b/target/i386/tcg/access.c index 5a4721dcee1..0fdd587eddf 100644 --- a/target/i386/tcg/access.c +++ b/target/i386/tcg/access.c @@ -3,7 +3,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "exec/target_page.h" #include "access.h" diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index c1184ca2198..1cbadb14533 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "tcg-cpu.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 3ef84e90d94..84a08152171 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "qemu/int128.h" #include "qemu/atomic128.h" #include "tcg/tcg.h" diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index b942665adcf..a0f816dfae0 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "exec/target_page.h" #include "helper-tcg.h" diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 9dfbc4208cd..3af902e0ec5 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -23,7 +23,7 @@ #include "qemu/log.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "helper-tcg.h" #include "seg_helper.h" diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index a563c9b35ea..93614aa3e54 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/= misc_helper.c index 67896c8c875..9c3f5cc99b3 100644 --- a/target/i386/tcg/system/misc_helper.c +++ b/target/i386/tcg/system/misc_helper.c @@ -21,7 +21,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "system/address-spaces.h" #include "system/memory.h" #include "exec/cputlb.h" diff --git a/target/i386/tcg/system/seg_helper.c b/target/i386/tcg/system/s= eg_helper.c index b07cc9f9b12..d4ea890c124 100644 --- a/target/i386/tcg/system/seg_helper.c +++ b/target/i386/tcg/system/seg_helper.c @@ -23,7 +23,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/helper-tcg.h" #include "../seg_helper.h" =20 diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/s= vm_helper.c index f9982b72d17..b27049b9ed1 100644 --- a/target/i386/tcg/system/svm_helper.c +++ b/target/i386/tcg/system/svm_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/helper-tcg.h" =20 /* Secure Virtual Machine helpers */ diff --git a/target/i386/tcg/user/seg_helper.c b/target/i386/tcg/user/seg_h= elper.c index c45f2ac2ba6..5692dd51953 100644 --- a/target/i386/tcg/user/seg_helper.c +++ b/target/i386/tcg/user/seg_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/helper-tcg.h" #include "tcg/seg_helper.h" =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index cb96b17911a..4cc8e02f70b 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -29,7 +29,7 @@ #include #endif #ifdef CONFIG_TCG -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/tcg.h" #endif =20 diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 6a7a65c860b..2942d7feb81 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -13,7 +13,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "hw/irq.h" #include "cpu-csr.h" =20 diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_h= elper.c index a83acf64b08..fc3fd0561e3 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -9,7 +9,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" #include "internals.h" =20 diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/ioc= sr_helper.c index b6916f53d20..e62170de3ce 100644 --- a/target/loongarch/tcg/iocsr_helper.c +++ b/target/loongarch/tcg/iocsr_helper.c @@ -10,7 +10,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 #define GET_MEMTXATTRS(cas) \ ((MemTxAttrs){.requester_id =3D env_cpu(cas)->cpu_index}) diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_hel= per.c index b17208e5b96..94e3b28016a 100644 --- a/target/loongarch/tcg/op_helper.c +++ b/target/loongarch/tcg/op_helper.c @@ -11,7 +11,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "internals.h" #include "qemu/crc32c.h" #include /* for crc32 */ diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 0d6c9844a6f..9a76a2a205f 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -16,7 +16,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "cpu-csr.h" =20 diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index eb1cb8c6872..ac4a0d85be5 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "softfloat.h" =20 /* diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 15bad5dd465..242aecccbbc 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "semihosting/semihost.h" =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 88baeb6807a..d10ae0702ad 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -28,7 +28,7 @@ #include "qemu/module.h" #include "hw/qdev-properties.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/gdbstub.h" #include "exec/translation-block.h" #include "fpu/softfloat-helpers.h" diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f6378030b7a..4624ce5b672 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -24,7 +24,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" =20 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4bb867c9695..7dcad6cf0d7 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index f92a923d7ad..2fb879fcbcc 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -24,7 +24,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/memop.h" #include "internal.h" =20 diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 969dd34b3e6..14de4a71ff6 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -22,7 +22,7 @@ #include "internal.h" #include "tcg/tcg.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "exec/memop.h" #include "exec/target_page.h" diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index d239fa93536..e477ef812ae 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -25,7 +25,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/target_page.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "exec/helper-proto.h" =20 diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 0967624afee..d7e8d678f4b 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,7 +24,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "helper_regs.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "internal.h" #include "qemu/atomic128.h" =20 diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index c90ceb7d60d..2138666122b 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -37,7 +37,7 @@ #include "mmu-radix64.h" #include "mmu-booke.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 /* #define FLUSH_ALL_TLBS */ =20 diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index c422648cfdd..2b15e5f2f07 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -20,7 +20,7 @@ #include "qemu/main-loop.h" #include "qemu/log.h" #include "target/ppc/cpu.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "system/runstate.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f3d26b6b957..5b0db2c45ab 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -23,7 +23,7 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "trace.h" diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7de6cbae5cc..b8ae7044578 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c index b433bda16dc..50d65f386c7 100644 --- a/target/riscv/zce_helper.c +++ b/target/riscv/zce_helper.c @@ -20,7 +20,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index) { diff --git a/target/rx/helper.c b/target/rx/helper.c index e8aabf40ffb..0640ab322b5 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -20,7 +20,7 @@ #include "qemu/bitops.h" #include "cpu.h" #include "exec/log.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "hw/irq.h" =20 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index b3ed822dd11..a2f1f3824d9 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" =20 diff --git a/target/s390x/tcg/crypto_helper.c b/target/s390x/tcg/crypto_hel= per.c index 93aabd236f4..642c1b18c4c 100644 --- a/target/s390x/tcg/crypto_helper.c +++ b/target/s390x/tcg/crypto_helper.c @@ -18,7 +18,7 @@ #include "tcg_s390x.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 static uint64_t R(uint64_t x, int c) { diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 2af970f2c8b..253c0364157 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -25,7 +25,7 @@ #include "exec/exec-all.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" =20 /* #define DEBUG_HELPER */ #ifdef DEBUG_HELPER diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index d5eece4384b..0cdfd380ce4 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -28,7 +28,7 @@ #include "exec/exec-all.h" #include "exec/cputlb.h" #include "exec/page-protection.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index e02f4438508..d5088493ead 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -28,7 +28,7 @@ #include "qemu/timer.h" #include "exec/exec-all.h" #include "exec/cputlb.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/target_page.h" #include "qapi/error.h" #include "tcg_s390x.h" diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c index dafc4c3582c..781ccc565bd 100644 --- a/target/s390x/tcg/vec_helper.c +++ b/target/s390x/tcg/vec_helper.c @@ -16,7 +16,7 @@ #include "tcg/tcg.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/exec-all.h" =20 void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3, diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 99394b714c9..e7fcad3c1b7 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -20,7 +20,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "fpu/softfloat.h" =20 #ifndef CONFIG_USER_ONLY diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c index f0266061023..39db4ffa70a 100644 --- a/target/sparc/int32_helper.c +++ b/target/sparc/int32_helper.c @@ -21,7 +21,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "trace.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "exec/log.h" #include "system/runstate.h" =20 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 10cc6f7835d..ca5a4d38ac2 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -27,7 +27,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "system/memory.h" #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index a0d5a0da1df..ae559b69220 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -19,7 +19,7 @@ #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include /* for crc32 */ =20 =20 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 5c7ed395caa..7cd26d8eaba 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -22,7 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" +#include "accel/tcg/cpu-ldst.h" #include "qemu/qemu-print.h" =20 #include "exec/helper-proto.h" --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717959; cv=none; d=zohomail.com; s=zohoarc; b=lgy91c0e09CHb5OkVxkFWk7RWRalsF1c/OY/FCMuHRqsFcVMNZGAHQcbuSS6pnemOPLReXyEUqzkaStvqvpQeTa4uScOZetECwfNQ1kPAhKYCyu+CVE/RdIIsdb6Hmvk3ppdsmnhXwuVBmilSv9p5k7PF9GBe27E8moOsOYP1VQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717959; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2CuFRMF8tGsrdfqJ5EAiHOu7bINkhnIQDSuUKCH5uiE=; b=FSNVb8AMdpksD5A+OlWoS3GshnlZqaQue8Do34ghs7b1lKO/Kdd/sT6zn6V2ON7J/D3eVOnOHDZRBK6sPzbX3cBN/XgK2PfSh6SmmQN0UMRvrZNK05VlsyZpiCpLOnEG+K4Y1glf/ZqRRl3cBiuusyeFAEIIJp9iMOdsB5ClAmE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743717959807369.5598599953347; Thu, 3 Apr 2025 15:05:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0SgH-0008HP-G1; Thu, 03 Apr 2025 18:05:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0SgG-0008HD-5y for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:00 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0SgE-0003lk-4y for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:04:59 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-39ac56756f6so1153593f8f.2 for ; Thu, 03 Apr 2025 15:04:57 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301b8ae1sm2860098f8f.51.2025.04.03.15.04.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:04:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717896; x=1744322696; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2CuFRMF8tGsrdfqJ5EAiHOu7bINkhnIQDSuUKCH5uiE=; b=O/E6Ba0CfytTXTC0n1TUihrdN5a7vmcNclrzXl1KPIhVZAHj/UcSsBS5JdrOpBgbqD ZKfa64yOTQxnM5MqwwYwvbGXBjMJ/JIKykOpv6jGqV6lJnQ4i7T2NfHZ9OIKURSVV16o 2cKbUw6F8NICNzOt5VedoFiU+n3FxqG4HRZrgOmCgcObT1HzbYx8UKN374h034Z9uty1 PmzJQWRZDooEjlmlv9DMXWl7sWFj98iAhFG1Y2axHAO5fi22SvBFbVLNpwuy7oIMwq0F pJViUaIFc5hKb43uRJrMs1X8BYe/WhYmkHOgkAasa7t7CS8PYInXcxwSlpqcUhEQyD4F RYqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717896; x=1744322696; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2CuFRMF8tGsrdfqJ5EAiHOu7bINkhnIQDSuUKCH5uiE=; b=mhAmthLrjjGxEWrr2uNB36FAMYWMz1HQ4Jk0Rdp35dzXmYXIqW9UI5KXzZZoRuFGPE TErovpeGjhWEVSwImjlyTcv7yXlabKs2eOcMZCl+MMjlWvxeg4PvbXcpysIXR7MwdwGa 2ILVI3gDC6Ye5zQaL3Nm2DDf5ikKx3WMf7sAvrBxDRJK9+yAl2GR8pYCqEMlYRWjOs8j divVO/Ek9zFNcPlrMWFdUjH7JcaJ06JwO1MEu7TS7T+Lz1eK9OwHjzPOIsF4KAxzkQGv 7G9F5JpIGESBqveRq9YjoBDWnQM6c5TFmOmHefRAB2NMAl2apyxZ3nhVWSJFwxWZ/RD4 4gBw== X-Gm-Message-State: AOJu0YzZlyTiz8AYYiexp9cnTnDIr2qQNbuu/88cm5MfR+PWnWY8+QY0 QLSeWwF0ZuscyFywgq2ahtBFVES6GuaqjbNcrIh7IzO2H78KNOV9rEWA6OrlyIlaMSzLJDZGSJ8 5 X-Gm-Gg: ASbGncuy+vHJV+Zt1qCm6bB/cJnQbdX9RYlOvjo23UkvRBUFN8laWVv2CKlXIyZejL4 mX18I4V5JqdCE5fIRuIfE19cfDoTqkuPTLKxahh7x1T8mYYHDIb1ZVUzclCqQgC/oSSTN1oh+z+ rqf9yxHTvuHa7yFieyfYILa3QfOmyCJ0Raa8oSvfkFT0XSX3ggwgrWl4jfuSH46pQiWiwl7LlD6 RIywNGsdyZ3Q2SDIUxe0S1xgd4ELC43i7ahpuaNKk9D7p4nGNwzdAapr72pv46b5zVPSXmfGqtw UMEg6c6Z5hXv2B0R75GWIvXdIMyAMZmbcUEKYRcG/ez5Ms8sNe6HzPB0dYWxrkdmZ5aRQLPnc0g pXxwv6A8FAootYZ0ljKUVT/7J X-Google-Smtp-Source: AGHT+IHHVI0ooM+Q/gY/JdaeGOrZTbJOQj6mIwIbQavncB5QD5oLgjeCsMzDN8ma9ZDwNTaJ3jR7eQ== X-Received: by 2002:a05:6000:2508:b0:39c:16a0:feef with SMTP id ffacd0b85a97d-39cba9826eemr648340f8f.38.1743717896357; Thu, 03 Apr 2025 15:04:56 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 07/19] exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h' Date: Fri, 4 Apr 2025 00:04:07 +0200 Message-ID: <20250403220420.78937-8-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717961025019100 Only 2 files requiring "accel/tcg/cpu-ldst.h" API do not include it: - accel/tcg/cpu-exec.c - target/arm/tcg/sve_helper.c Include it there and remove it from "exec/exec-all.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/exec-all.h | 3 --- accel/tcg/cpu-exec.c | 1 + target/arm/tcg/sve_helper.c | 1 + 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 70608a11b60..944b579d91c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -20,9 +20,6 @@ #ifndef EXEC_ALL_H #define EXEC_ALL_H =20 -#if defined(CONFIG_USER_ONLY) -#include "accel/tcg/cpu-ldst.h" -#endif #include "exec/mmu-access-type.h" #include "exec/translation-block.h" =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5ced3879ac4..b00f046b29f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -22,6 +22,7 @@ #include "qapi/error.h" #include "qapi/type-helpers.h" #include "hw/core/cpu.h" +#include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" #include "trace.h" #include "disas/disas.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 9b0d40c9e18..87b6b4b3e64 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -30,6 +30,7 @@ #include "tcg/tcg.h" #include "vec_internal.h" #include "sve_ldst_internal.h" +#include "accel/tcg/cpu-ldst.h" #include "accel/tcg/cpu-ops.h" #ifdef CONFIG_USER_ONLY #include "user/page-protection.h" --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743718024; cv=none; d=zohomail.com; s=zohoarc; b=ECzw04p2Sww3ZBrLiGMMGinvdJNxrf3TylC2y7ocVqrp6B+SgNFBqX1GYxsMeukToAwYLPm9zOaFc6mDmCFqe0Som/FxmwYvoVUeBm+IGrYEq5lnrCU8iKJK4ojWW5znsd3cQxdZbuT46sFL+4Au7IOZulxh19Ry44UMVej0lEc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743718024; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=L93zIKGNWPzjVCaNqO2VF85pjiuQ80Aoywgp0S0CVlQ=; b=ifVM1fQ2W0+js7L12LZOyBrFNLuLPIfs+A2Ji6qFY0cLPcELCZfFdALVGanta08AtobjTSRcEcdELtYq5WbWau77wvTZphskrkGlkeaMojd+DeykMNPH/h/gJFVl59CEmScjIA/zNnFMB9yW9WGipHw2E2Jv+Rk7RWylzLB2KW8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743718024942400.9544003805082; Thu, 3 Apr 2025 15:07:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0SgM-0008IR-Pm; Thu, 03 Apr 2025 18:05:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0SgK-0008I3-Pv for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:04 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0SgI-0003mJ-PX for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:04 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43cf0d787eeso13569475e9.3 for ; Thu, 03 Apr 2025 15:05:02 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec17b0d06sm32770185e9.35.2025.04.03.15.05.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717901; x=1744322701; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L93zIKGNWPzjVCaNqO2VF85pjiuQ80Aoywgp0S0CVlQ=; b=AVwRHH9UvxpfJQATya4kp29VN/BKronQ+5jQs2KCmqxKxU2qUr9R+Ez5t5YvtUNWvi b3kMN8oR1lC59QM53O/PRUWbVuk4Wt1+9gAzeLilCFpdDPz1su5iK5WIcpGfMnl86DOh dq0kGmeTnN4LnI/IlHodX9HZ4F/HbJtTOMcbGNKVx/lZMfiN5NBti/zMzGcx9zy+MF1t Wx6f3aDI+Q9eOFk59Wp6w/JQjyfHzXK7dqRN9RSW8B7REWISL/OVX0PmC9geA+8gaTvR iH17Y2+BtwCA9YY2xpK+duroJAYXhHnPHQ/YBq8orCli7TqJkkgn4lqhpxC2ScvQmSM4 AEFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717901; x=1744322701; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L93zIKGNWPzjVCaNqO2VF85pjiuQ80Aoywgp0S0CVlQ=; b=jME3xaQ1qIQgVM4YVyG2CZv1Zej56/cjYxQ5uhZMC07OFofBHMEbbcqJq1JggDIFLS 0Ykag5mhZVk77NLYDbkECj8Z7SAo9THBy8FdYF4uanSSEZ3osgHNv2scfrb/p7JhaSp1 iEtqc+q8QUhFovvqp5Gv/eqsdSkKkKyUwgp9FIB6wgNiXBw6qVgHQLYUVJx2J81ADDN9 d7/jrlH9yh/aythG8xZastN0pPH77SUyDxD/yhjy+MDySdueL0eDIu9tYYyE17iNvqAV FWbEtndZoSO4d9c+UhoYteMt/1hYKy+7NZRMHhxo7QoY2gqgFb+pOG9esbuiybnNIcV1 zqjA== X-Gm-Message-State: AOJu0Yy80JEMsOuynBm+VO4Gh7zvHCPv40R/ewEpFhT0ck55CmTCJaKc vpffwbBNhZRnQ8IDx4lTTN6Y2EL0Lgm4g5cV/lKSFQ1lgPajzW/az6mjP4TJMoV3YWmjEeQgbFB o X-Gm-Gg: ASbGncuUGpkArWj8QSqFwQz6D9WIXMfI1KSfTZ/KwuCQy6WJFxTbHSjrqR3+89JA2gb iJ1xI6N6lp9u2Tog9WmrchYDA5vTXej7Wv65p5FsrrF+mmg/fTZGwAPIxl/uekEg3VDMj+f2WtU kRZi4fzmGCIJwdj4tXgio+W8DP5Bg3jHRdK39kYgd5G2NoYDXRlfHzKqMUsew5JYWzYl7BmZH/5 HE9F8cTJJDrbl1d0Pe7EogQjpq7UhtfBXr8wDC/xf5+Uixj7PC5VDL49JnR8Hznb3QTVUt6TdMv n6MkEFa4cZG4mkHYwQkox+hUVPd2Yn3F+8s6udYnSkl+Gm9Eau+htE9soVL2KbZEOon18deJERM gAEDFnuDVplVdGvxkFoRj0Fi6 X-Google-Smtp-Source: AGHT+IGDYrLMJL0j3pOiwsLEfcwN/Y2NWF74o295XSODIcP3HOROla0Nzmbz8Dl8dypVjMnTSY/DWQ== X-Received: by 2002:a05:600c:3b14:b0:43c:ec97:75db with SMTP id 5b1f17b1804b1-43ed0bf6aeemr3106965e9.11.1743717900923; Thu, 03 Apr 2025 15:05:00 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 08/19] tcg: Always define TCG_GUEST_DEFAULT_MO Date: Fri, 4 Apr 2025 00:04:08 +0200 Message-ID: <20250403220420.78937-9-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743718026085019000 We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled frontends, otherwise we use a default value of TCG_MO_ALL. In order to simplify, require the definition for all targets, defining it for hexagon, m68k, rx, sh4 and tricore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/hexagon/cpu-param.h | 3 +++ target/m68k/cpu-param.h | 3 +++ target/rx/cpu-param.h | 3 +++ target/sh4/cpu-param.h | 3 +++ target/tricore/cpu-param.h | 3 +++ accel/tcg/translate-all.c | 4 ---- 6 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e743..7cc63a01d4b 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,4 +25,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 256a2b5f8b2..10a8d74bfa9 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -19,4 +19,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 84934f3bcaf..fe39a77ca38 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -26,4 +26,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index f328715ee86..acdf2397495 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -18,4 +18,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index eb33a67c419..45fde756b6a 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -14,4 +14,7 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 +/* MTTCG not yet supported: require strict ordering */ +#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL + #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index c5590eb6955..7467255f6e4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -353,11 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; -#ifdef TCG_GUEST_DEFAULT_MO tcg_ctx->guest_mo =3D TCG_GUEST_DEFAULT_MO; -#else - tcg_ctx->guest_mo =3D TCG_MO_ALL; -#endif =20 restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743718195; cv=none; d=zohomail.com; s=zohoarc; b=mOORogqYtnum8eBwj+JOqEq5/UrAq7j1PELQe//+ByjgQ9eEjfqcWSc/0M4iXUiFdgjHg0v6XG4v5BmmIjR8HDn/OAQWoyyA5wG0u04V9hJ1ybCC3xgLitwl+tglZBcJBhbfx48sT9taVLGkHYL0FMoyjx6mtnYjZHRM2bMTDH4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743718195; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VUBhKNJ33VGc0tAXVv72Kq3hUC0BPxTHmotqIBCHglo=; b=AP/1Hk7bU9sgovDaBHplwWBkGDVKhjubxkRvhWsPQxtW7Z6ykMSEGo1mvxfkWkQPXvBos5Q6HrEGcSNdDUk/9WQ5KU0k5QKp+ySXlg/2K2M+6tvdRMaPZ9h+Hm8RTI+WKOLw6fJllbYjLn7iwakd7VhsdT335I5gfdIDBQ67hnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743718195356788.2853357282029; Thu, 3 Apr 2025 15:09:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0SgR-0008J3-2r; Thu, 03 Apr 2025 18:05:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0SgP-0008Il-OH for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:09 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0SgO-0003xg-11 for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:09 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-43cfe63c592so13613195e9.2 for ; Thu, 03 Apr 2025 15:05:07 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301ba2dfsm2824683f8f.60.2025.04.03.15.05.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717906; x=1744322706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VUBhKNJ33VGc0tAXVv72Kq3hUC0BPxTHmotqIBCHglo=; b=LjBdltdtGSMgtNCb9tSVYRr5qTe8staTUkE2OauFlK3h24m9oHBDiuIUBtPrXAzMrw qBjlikmV8cB3jiIWsosKOSP7bipGis+xmDTuvCbW+9Hl5e4VqCki0v9nT45mZSxfXpuw +/YlmJ/rfa8K599cKnBoSNA+hbH5oP+zH1HGKcCsPQRqyjQKZeb9eDWfvpWXbCsm3b0k 9nW4wTkhgUlEOdbr8uv7PWQnBkHyUFwhvoEXSio7yt/tUKFzW2q5jJTgAsC9BL7LvnHq 5rD221gdt0FIuDCj7Ve/EbExO28JifK/XR/IsxWkFTSyFArUg1M5ybSpL3RHRGY3dZWQ jsIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717906; x=1744322706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VUBhKNJ33VGc0tAXVv72Kq3hUC0BPxTHmotqIBCHglo=; b=lLu90EYkMfljGTVD5HVUNgdDKq/HV9sH4hfIRGzkaolifeUy+Gwmn5wisxSiiHqqCc SM0pMRpeQv8dqrHY8YiwKmawwzFpxqi5kMQ/JMZF2BkB/T+MtgkiroiYp00Kx4BXL2Xx l48gKfMFTDsaw7sMxJMvXGupPgHaQnizW5+c7OuFoO7/1iJoRgyF+ZEjkwyU6w+fhoLt 6blm5PjJ3ry/f7kAw+Wz5TToxfbME1+cFJ0FHvB2Or4Gu5IfsjZUlZpzPrnkHnELNkF3 9lZUWVZwojTStzA2H2paKAxKh3ADgW2mGxB0axpavxOxDf8oA1h7VmacWbLU3s4tg+eg A21g== X-Gm-Message-State: AOJu0Yysc35B55tBDeXwXXcxMXGntDrYs3seZI5JC/bw+PqLTXcJCzY6 Fz/eG41ommxPViJVyFSD/kvUaOKkg9i84LhvHgpZfSf6+lw/wm4uQMNhd7E9/hh6i+vlOSG5KtJ + X-Gm-Gg: ASbGncsQ9MeMu2j2CYtVMdWrTbJIjveogBpaevugjXUCqwMNUZ1d+MtM7s9VaV8ZntH xE1TGqy1x90sq+Aldk7MQAG3YDSm+RLcb5aowmK1EspTF2kfmR+4YQXeOoVPAuBLU7tLA1z9c2i 4ZGNMPgb6xwAx5jfngM3GSfNBYrsclGJBIcAG4sFBB0PU1IS9QN692QqMVc+HNuPzwxQYJ3eENg FaURMg6VxbN92eLqqQdJAX3l99I+wHxWDBMKpJBtS9SQY/ykXe6gmPKC2EsPw47rrKcRHJjCqOW wU42cDMWvYjM7V4cfQvDu7coPzxCMR80EVL2RupaAzP+wuXyuW3iSCuOUzq4kEa7aHe/4E7Zq8p oTB4TSy1rUAscbjPmHlhdZ/n7 X-Google-Smtp-Source: AGHT+IGpxkOacXMIFCNXPTXtbODqtbRhVu+F/tN2FdYy5jxoYNLsYx9BsZ5cj/YzY87fkI5+12J73g== X-Received: by 2002:a5d:5983:0:b0:391:2e31:c7e1 with SMTP id ffacd0b85a97d-39d0864b971mr320332f8f.4.1743717906243; Thu, 03 Apr 2025 15:05:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 09/19] tcg: Simplify tcg_req_mo() macro Date: Fri, 4 Apr 2025 00:04:09 +0200 Message-ID: <20250403220420.78937-10-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743718196771019000 Now that TCG_GUEST_DEFAULT_MO is always defined, simplify the tcg_req_mo() macro. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/internal-target.h | 9 +-------- accel/tcg/tcg-all.c | 3 --- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 05abaeb8e0e..1a46a7c87dc 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -52,17 +52,10 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); * memory ordering vs the host memory ordering. A non-zero * result indicates that some barrier is required. * - * If TCG_GUEST_DEFAULT_MO is not defined, assume that the - * guest requires strict ordering. - * * This is a macro so that it's constant even without optimization. */ -#ifdef TCG_GUEST_DEFAULT_MO -# define tcg_req_mo(type) \ +#define tcg_req_mo(type) \ ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) -#else -# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO) -#endif =20 /** * cpu_req_mo: diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 7a5b810b88c..a5a1fd6a11e 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -77,9 +77,6 @@ static bool default_mttcg_enabled(void) return false; } #ifdef TARGET_SUPPORTS_MTTCG -# ifndef TCG_GUEST_DEFAULT_MO -# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO" -# endif return true; #else return false; --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743718089; cv=none; d=zohomail.com; s=zohoarc; b=EAkcI2pKAy0WVCDwJmrLmIhenA6yIb2X7j/mo85y5ILaUGbFQsyb70nco5DWSvQT2Xieic+QTZ3HcDvXcrA7NrfGWXM/zkecOPr9QVELDdOGg9YYxTpTGDcb5RR1mHR+HihnCDLbHJvxXnQSH+Wn3oIjt5LRd7u+me7apd/b4kg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743718089; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wzvvKD67dGmGHSwnMZ3wOcfLPFevPnPtS38dzad8SEI=; b=KbQlkyVYmx6Wz0vq+/gXmgzFgelk1IFKNL9SZQAJYD3yi6dw55gSsOq0tV7fj1/+1UMBG1LBTYr8LauuPTImd+j/AgbpkzKWgd4x0jQTbtebOoa57SlvJsOCX/dESZs9+M3xkY25S8cHRhKkhYHZ9hehymONfrI/tHx2w29MfA4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743718089351381.6171020064394; Thu, 3 Apr 2025 15:08:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0SgY-00004u-Fr; Thu, 03 Apr 2025 18:05:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0SgV-0008KX-As for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:15 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0SgS-0003yJ-TH for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:14 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4394345e4d5so9295745e9.0 for ; Thu, 03 Apr 2025 15:05:12 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020d980sm2840084f8f.61.2025.04.03.15.05.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717911; x=1744322711; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wzvvKD67dGmGHSwnMZ3wOcfLPFevPnPtS38dzad8SEI=; b=dv6U8MHWwbGztLE4eUAAgT7dD86gmtX31Vum9t5Wmlp9HiPCeh9jwHUaQ2aBK/a6EP S0kUdaOp5wHFvm3SZNQJMetlazxhFN8Oh/0fbbQV5rgOXqqhQek3Hu6cvBZuOuE7LPGp SCOfuSEd0J2MrmwpO1MrlBTDVWbsFxvGfNvgV25aklAWAxLXexngD7Fokf19av+3iIjT 9h0X02K72vTzpQFzvKLnO2ILeWnporW/gbrqIjt5mSfOtjz91CYLuukNlWEFumQakkTD z+VtzdSXiQwtjEzEKIxZl7DPhKRTqYGePrgBq28JcTQe5teyw/tKgKWYQ+3dFiWJGKID AIiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717911; x=1744322711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wzvvKD67dGmGHSwnMZ3wOcfLPFevPnPtS38dzad8SEI=; b=fU8tIIkhV8iVYmHe/mfOX+t+f/xioFMvqig5+4rOACC81QYDjt7EaYXGNjXPolQXFp 3+2Ww6MobpGMUGnGtnwOk1+970HpYtjTAaWCD9h2SH1ZGryzK75P5hleINPdp2scJCIS tCIj59Gh+V6QVSik49seAJcyzyN8zFDt8qwTLGB4KUJrBbGAVak+p/w/1j6H0vMrdZsC AQOGsl9ozzXkImxiS/b81TH6DeAPYRn0dsrjmH7wjYBgZD+dMxQRG6qV1+2WQNU+rVyo mS9z3HiSAvFW3ABdgcz5In6wH29but8ETRdHQUC9LWCO/IItw3n8B2kcizY8igJunZLs sWxw== X-Gm-Message-State: AOJu0YwhkH6KWHRd1+ZV/CbJ42TAUC0/QqCQ/Br+DqN8xN77H3myYQtO 1+O/efzFXZd/g/IeMKpET61mMPUQexhRBoOvt2bhDjy3aXpZrGBB0ygFrfIiilpbjTWWrqmhFKp 7 X-Gm-Gg: ASbGncs43K5IFfxnpRI+FLJv46sn2yguNfA/iKS982cagnZKsfTi//+kwRL6pnQpm/W +VgAveB6rJVkL26/IwS1pfQ0+SVntaw3rf9G6Blj3ZMWGPTMVZwD/hBlxGTFl0HquUvbSrh+0gB 3C/e3ChOen6zCPKx0UgH7lEB8Ba0mIdpLohE6Z3FITfcbKWuW5vbnZK2ARQ0C1DHhDou6X4BfHs kba/LsqKhLG26H4Zm1kIyNj3Jr2qjgV01IHzsFigDb209hoV8yEvRgKh0CK3e4YfavUdvz+iGRo 4FjZRp4y+/ze1wQgvQ/xAqVk5wReQEqv2xnFAh0loElE8iWPVJ2WyvfJ+LA9xgwVL5ElvvOR8aX rj64Llh+48qxIEiKeWFSHkAyn X-Google-Smtp-Source: AGHT+IHm6pvXCInltCGuAi8vvUFUrcDEyAF6iZy9RYL+Q/rGsAY1rUJpadvpffi6njSJQY8juo5Usg== X-Received: by 2002:a05:600c:468b:b0:43d:7413:cb3f with SMTP id 5b1f17b1804b1-43ecf83ffe9mr3587815e9.5.1743717910844; Thu, 03 Apr 2025 15:05:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 10/19] tcg: Define guest_default_memory_order in TCGCPUOps Date: Fri, 4 Apr 2025 00:04:10 +0200 Message-ID: <20250403220420.78937-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743718091764019100 Add the TCGCPUOps::guest_default_memory_order field and have each target initialize it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/accel/tcg/cpu-ops.h | 8 ++++++++ target/alpha/cpu.c | 2 ++ target/arm/cpu.c | 2 ++ target/arm/tcg/cpu-v7m.c | 2 ++ target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 2 ++ target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 2 ++ target/m68k/cpu.c | 2 ++ target/microblaze/cpu.c | 2 ++ target/mips/cpu.c | 2 ++ target/openrisc/cpu.c | 2 ++ target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 2 ++ target/rx/cpu.c | 2 ++ target/s390x/cpu.c | 2 ++ target/sh4/cpu.c | 2 ++ target/sparc/cpu.c | 2 ++ target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 2 ++ 21 files changed, 43 insertions(+) diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index 106a0688da8..a4932fc5d7c 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -16,8 +16,16 @@ #include "exec/memop.h" #include "exec/mmu-access-type.h" #include "exec/vaddr.h" +#include "tcg/tcg-mo.h" =20 struct TCGCPUOps { + + /** + * @guest_default_memory_order: default barrier that is required + * for the guest memory ordering. + */ + TCGBar guest_default_memory_order; + /** * @initialize: Initialize TCG state * diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 99d839a2792..6f931117a25 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,6 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps alpha_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, .synchronize_from_tb =3D alpha_cpu_synchronize_from_tb, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c9e043bc9b5..3f20e258fd0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { =20 #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 1a913faa50f..4553fe9de07 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,6 +232,8 @@ static void cortex_m55_initfn(Object *obj) } =20 static const TCGCPUOps arm_v7m_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index feb73e722b3..67918684faf 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,6 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps avr_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ad1f303fbcf..b12e0dccd09 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -325,6 +325,7 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hexagon_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 51bff0c5d62..ac4560febea 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,6 +253,8 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hppa_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 35b17f2b183..3e1b315340c 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps x86_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 4cc8e02f70b..ee74509a664 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,6 +864,8 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps loongarch_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, .synchronize_from_tb =3D loongarch_cpu_synchronize_from_tb, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 4409d8941ce..bfde9b85948 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,6 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps m68k_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, .restore_state_to_opc =3D m68k_restore_state_to_opc, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d10ae0702ad..e46863574c6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,6 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps mb_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 269d3d69bd5..860ec398229 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,6 +550,8 @@ static const Property mips_cpu_properties[] =3D { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index dc55594a7de..e62c698a407 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,6 +243,8 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps openrisc_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, .synchronize_from_tb =3D openrisc_cpu_synchronize_from_tb, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 740d8b92c0b..57565c9a2f2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7478,6 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps ppc_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, .restore_state_to_opc =3D ppc_restore_state_to_opc, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5d0429b4d00..ded2d68ad78 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,6 +140,8 @@ static void riscv_restore_state_to_opc(CPUState *cs, } =20 static const TCGCPUOps riscv_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index e14d9cbef93..d7eac551fd4 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,6 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps rx_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d15b1943e0e..f232d82fa34 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,8 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } =20 static const TCGCPUOps s390_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, .restore_state_to_opc =3D s390x_restore_state_to_opc, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index df093988cb1..29f4be7ba9c 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,6 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps superh_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index af3cec43e78..ef04efcb183 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,6 +1001,8 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps sparc_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 833a93d37af..3bf399335ac 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,6 +172,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps tricore_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 51f9ee9e89a..23471064957 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,6 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps xtensa_tcg_ops =3D { + .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, .debug_excp_handler =3D xtensa_breakpoint_handler, --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743718024; cv=none; d=zohomail.com; s=zohoarc; b=mtFHoztkh3G238KnEPAmWUv9nMbUNCS0gHO2teeSKBLvwTeQ/0Q/19NlwLYmrDZbPMeesenOv74MhSZoCdmseHSOmMZuKE14k+vhTS+GFtKa2NNozlvgoJQkCvZrnSvvhYTLUP9Y8AqDCbvq780zRLEbDAArPxXRuoOqERijlvk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743718024; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Z9hjvUeWbVz+/CYEuU3h1CcQqcFWfFRSfQhQvW00JOQ=; b=HaWo9E+hbrarflFlTBrJ6gWGK3fVQyKwGQQo4R9yxoXfgnGoxj5y0Kb08uM7g3PmrZR9J2tznFN2yCE7CIDUIcHIw5yBwR4JW2p3I17h91wKefB3VaxTZjn+kSMyWhiZQ+/qdJ9vsivxMTZMh4wSRoRvDlGtyxuT1NFZH6H1/jk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743718024923927.9571998546537; Thu, 3 Apr 2025 15:07:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sgd-0000QL-2M; Thu, 03 Apr 2025 18:05:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sga-0000Gn-HP for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:20 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0SgY-0003ys-Rd for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:20 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-43d0618746bso9928745e9.2 for ; Thu, 03 Apr 2025 15:05:18 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec17b0d06sm32774765e9.35.2025.04.03.15.05.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717917; x=1744322717; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z9hjvUeWbVz+/CYEuU3h1CcQqcFWfFRSfQhQvW00JOQ=; b=B98AKiPKVm24ZJrn4Pgm++BkkXxHSQSamlDbL8t5ih69hvarkeZ/Oum3s02rg7fryU EYgvhhz2eXKy8x1tOYyJs/mArJRR9jBjWsoLjKU1hjiAx/fqPCPnZj+5h52eYqkdge/c aQroYmkWF9u7pfbBY8o0U/XuUzQSs6KuCDqOuu2K1T1vzVadYuGfvudoVW5SpLPOBJX9 8esmmzVPc3Lgyj5Q9Su3NvJZyv5nx22DwotikFVhZtx2CldX2OMZoYFjncBS7e+wjScf p3/cHW+NuPf9HseMr1JZ8OhY8S8mzbjXczd6SjM9NIoTZZbTmIEa+wULyeiqvuGSLaN8 NyXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717917; x=1744322717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z9hjvUeWbVz+/CYEuU3h1CcQqcFWfFRSfQhQvW00JOQ=; b=Ke3EUz1GSQIKQ2GTI6DIdwtMAsQEG/y9dNYmY+ATf3Ho9hwSiKRFMWwlVIkGku5dyM gW9zJrKteQE8FHJM4eRP+pS46GZxrPhixgvAKjCNHyBzBLyzBoOv2gPSP0CqEgZPIUuD rhV5Inls/pI1Y3wp92W15SZ4WNRyfWItGRn8dHVnZQZwFJCSGSkdG7qXNCf4UNNfg5Py NEHXrGOMAkYoNJ2o7tTIbax0XaQPWQJYZn/tKvDK6/k4vU2sJVvztIhQC5sYtgxF+5cV hPJIASh8WK+MAqKZY9DbBNUpAATrJ6qjf20rUfEOieev2B4KgLIDhjt/2nHxzdkNGvoo Mb+w== X-Gm-Message-State: AOJu0YyFCCOoNOcupzlqXaN4yc/QYJ0KLX60Ks8XMQWbv6rYOCJLO+0h x9DU/DeW9j8df1aurOwrELOcC0hTY2vAFd3pTvMmgeyg52Ek3qP4cJHeQ/L7HaK7WaZ70oluA03 z X-Gm-Gg: ASbGncuSx7bYUChWUTj6QZjtxd/wCmgBrSj5C4k1IQm3eJTJy3Ngap7KNON4Xc7Cm1p WXQosE5PL5R9oGhNEQa+INZk0FDeNHza8I3nLM8FlAyuJo0vKIYhG+r4FZRs9u72AiPtTiJdNFq gy+XgNDVMFXOXEk+Ra3q1CWGn4wlCKEHezW4XXL5lKFKg+66S6cxLqXRxrfcjyj9F8dlIx0DbKs JqJylsJEmFQzpZXPiVd4jnSkVCLEhkHYpVVYxx9XGUP2qRoK9K9jW62I4H3QkuLGZmOtrpw8i84 2V7XCUnv+F6eVzYzCYzMRj4nndLf/Uf1LdzhfckO7NQx049LD0qL2wTy/im5DHW6u9U9gioW+fR w6moSleB7ljmmlGMjH0KJa+Pn X-Google-Smtp-Source: AGHT+IEZL0dZVEzKHPrsX1jEJkmQ6QTIw3uOLUo/w3bssSwpimc72WKm3ryUn6b/NYrPRKzEBuOaDA== X-Received: by 2002:a05:600c:1f0c:b0:43d:4e9:27f3 with SMTP id 5b1f17b1804b1-43ecf85f4bamr6368125e9.9.1743717916825; Thu, 03 Apr 2025 15:05:16 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 11/19] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code() Date: Fri, 4 Apr 2025 00:04:11 +0200 Message-ID: <20250403220420.78937-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743718025978019000 Use TCGCPUOps::guest_default_memory_order to set TCGContext::guest_mo. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7467255f6e4..c007b9a1902 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -353,7 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; - tcg_ctx->guest_mo =3D TCG_GUEST_DEFAULT_MO; + tcg_ctx->guest_mo =3D cpu->cc->tcg_ops->guest_default_memory_order; =20 restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717983; cv=none; d=zohomail.com; s=zohoarc; b=FZULoTn5OCUywEewT5HKyfJUvFBj1MPiHcI9qHjIsmBDfk/N0IplFC58R9SRVHXL9l04S/ByjBl9SdXkKLiWJmY2API9O2ecq8teA6mqd4tMRJ7X22g/hEQmXood1pf2NASyUxgwWinr1c++owqHj5bk0IKm8GMaeiVnWuxpZZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717983; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rcpj2tcbvjBZshPtyS3/CSwa5AEapPfd25KE2HwFvNA=; b=Wwn5ya4+4KlrA6RcCtimCejN5JWP05qC3T2fMWZUtJ15B+Ncthj8F9mPi5kjjELvwe36exeGEUz9W0h4bW9sqDSNmVyDTb/9qjV49V9eMtroBUqqI///UHFli7I8OPvgh1KSbf/1m/GyICwHcg70BtDTy6FI5O/8ka/Oi63d/RA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 174371798338352.0872590228264; Thu, 3 Apr 2025 15:06:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sgi-0000nQ-I6; Thu, 03 Apr 2025 18:05:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sgg-0000g3-6X for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:26 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sgd-0003zV-VV for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:25 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-43cf257158fso9395735e9.2 for ; Thu, 03 Apr 2025 15:05:23 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec34a92desm28790655e9.14.2025.04.03.15.05.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717922; x=1744322722; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rcpj2tcbvjBZshPtyS3/CSwa5AEapPfd25KE2HwFvNA=; b=Wjglruph0MCqu1JTsPUBoEPveaUfYutwkKsuV55gMCjPzjHGSl34qatf4qeEovYQHF 8FaKVmWvARn2d9wummd2ru96riZwE0OVwBecvRfVUYbXwzlKuKL2KI4eboWIgr59+QOj PCEP0OhGy3zMTLgwlBuyQ+ERpU1AxZcAjiLgeLD3/5+Sk4VAeCG65VfiBlojdfl9rHB5 aGrT04SnGx2PWrKzdNjYw9dnPHUB5HbBjdPjY/6uAxvSjcZaEyDJIMF6z+zvCh5iS/iS JhQYp7lOZz8MmokAAAhy64BtNKeS4YLLpJ2yIYYCF2WiNFeMbFZl5xrp9nODczzDKwyy hIwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717922; x=1744322722; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rcpj2tcbvjBZshPtyS3/CSwa5AEapPfd25KE2HwFvNA=; b=T0lOwaqSFitqKYZQFok40u8MyE9wnwZ1BoZ84EITv2LMLu1sUzwEPJQ0A70c54p5zh t0zakCsjFPeWLZGZc8Q+GCM76stplhlz899aq/jUp0lqArjZtLhxiR3EawSPZQd3uuKp K5KeT7WjXT4NuYYCHOSjHAvFERfO3gdo03kDd8MmGhZo76T95QwrQApnVAk/q3ChhsXR b6gI3Ym1dFNqU1VVVj3EOryw7xwxKleYGSij7bHcbAAGi824LsTma1OorMQ6HXUgmsnN /3dqKcL3QrkLnFpyc5HMYBiiHy6ZH0bcZSCchuBije8xlxNE8iWl2nbTSd3JRJ0AvMWk +TDg== X-Gm-Message-State: AOJu0Yxn72YG6xDGJz1PDt24aFfdaQuIJ0FvoEocbnU8yZof7Sm11Djm 4HFMHjFjRjXJ+1XkuJwkYRJARR3uBoftCXvKUNGHU3gNKJ61eOJNLkNQyawwpMkvEbsKD1dG+xi G X-Gm-Gg: ASbGncvCdNRhgr0zIp8xfyDtey9C3pRSl4+i4dTHlkeIN8lrlqS5KI759/sZ6FqsK+d 6lrVKNrveGqReo6lWURhkU3gHrBp7/mHnqBhYqLwHtzTGcZgHGR4IRLXQL/tTTDbSKuMZPmy1SG qfNxJq5EU1SreEu5cev+PNlR+QjhojxDn/tAgOxEpJNCk1LVyeSVyAXTyY+XZXj9xotPcr1B+Dy h5+DpoTPk/kYyAdQ2ipO8toW0JgZKBN44SLZ+PHzU8qbQuaMybT8LJj99zkZ+DELzMTc11pajIe BRv16AOLPcyx/2Qw54Bd7LtqruCrqhsnksh15ibCy2cvKRSFVkqagzgohu9sikfUYddyZRYCs1d lx0dW8jz1+dowgKXGL6n4ba1f X-Google-Smtp-Source: AGHT+IFXMow78jI+Cwvt4AZgSZeEB/0UYMCr+Z+ORfbkDmzI6/wDtnhhfN+zSdhuptKXDErfoJY/2w== X-Received: by 2002:a05:600c:502b:b0:43d:fa58:8378 with SMTP id 5b1f17b1804b1-43ecfa4285dmr5514765e9.33.1743717922131; Thu, 03 Apr 2025 15:05:22 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 12/19] tcg: Propagate CPUState argument to cpu_req_mo() Date: Fri, 4 Apr 2025 00:04:12 +0200 Message-ID: <20250403220420.78937-13-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717984013019000 In preparation of having tcg_req_mo() access CPUState in the next commit, pass it to cpu_req_mo(), its single caller. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/internal-target.h | 3 ++- accel/tcg/cputlb.c | 20 ++++++++++---------- accel/tcg/user-exec.c | 20 ++++++++++---------- 3 files changed, 22 insertions(+), 21 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 1a46a7c87dc..23aac39b572 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -59,12 +59,13 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); =20 /** * cpu_req_mo: + * @cpu: CPUState * @type: TCGBar * * If tcg_req_mo indicates a barrier for @type is required * for the guest memory model, issue a host memory barrier. */ -#define cpu_req_mo(type) \ +#define cpu_req_mo(cpu, type) \ do { \ if (tcg_req_mo(type)) { \ smp_mb(); \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2cafd38d2af..35b1ff03a51 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2324,7 +2324,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); tcg_debug_assert(!crosspage); =20 @@ -2339,7 +2339,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2363,7 +2363,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint32_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2384,7 +2384,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, bool crosspage; uint64_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); @@ -2407,7 +2407,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, Int128 ret; int first; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { @@ -2735,7 +2735,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); tcg_debug_assert(!crosspage); =20 @@ -2749,7 +2749,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, bool crosspage; uint8_t a, b; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2771,7 +2771,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2792,7 +2792,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, MMULookupLocals l; bool crosspage; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); @@ -2815,7 +2815,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, uint64_t a, b; int first; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1b878ead7a7..3f4d6824460 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1061,7 +1061,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, = MemOpIdx oi, void *haddr; uint8_t ret; =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, access_type); ret =3D ldub_p(haddr); clear_helper_retaddr(); @@ -1075,7 +1075,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint16_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_2(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1093,7 +1093,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint32_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_4(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1111,7 +1111,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, uint64_t ret; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); ret =3D load_atom_8(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1130,7 +1130,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr, MemOp mop =3D get_memop(oi); =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); - cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_LOAD); ret =3D load_atom_16(cpu, ra, haddr, mop); clear_helper_retaddr(); @@ -1146,7 +1146,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uin= t8_t val, { void *haddr; =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, MMU_DATA_STORE); stb_p(haddr, val); clear_helper_retaddr(); @@ -1158,7 +1158,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uin= t16_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1174,7 +1174,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uin= t32_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1190,7 +1190,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uin= t64_t val, void *haddr; MemOp mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { @@ -1206,7 +1206,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, void *haddr; MemOpIdx mop =3D get_memop(oi); =20 - cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST); haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717943; cv=none; d=zohomail.com; s=zohoarc; b=X7NQmMGjA0ORpa7swmzpFaCc6QTGGOpp9ZAf6bz0YISy5zIjF/pHweQ6K/UjHPE2yB9N5Yzf2uNB2Vck4ENcgVatiZ660xM5E/xWWZbLXALYVaySjgoABa4sXrs8uO04Iy7o766TWvP/sEo5q7DfudIJw35W3O7mX1YhpR+0yks= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717943; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZtZrrkt2ntmoiQ4mVP99KUX/c8Ppft+k9zep++rss8s=; b=gUaFxQIeWaP1hhCynGHP8A37RtP2Ikjym3XPndCE53pZe/v1+OsT7P5xl1yFEl0Jo5u/XQ+fRovZChQAUUxoyeVSSVHQt7Ny9+OcmPR5VEHexgvKtbuzr+o1IaXzmH9J+dc23wBh/kjVFU4r4pcLEy96GuZ9Fv5xOZYv5/deDRc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743717943345443.51294631483006; Thu, 3 Apr 2025 15:05:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sgn-00018S-UW; Thu, 03 Apr 2025 18:05:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sgl-000107-EW for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:31 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sgj-0003zt-N2 for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:31 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-43948021a45so13194545e9.1 for ; Thu, 03 Apr 2025 15:05:28 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ea8d16049sm60441215e9.0.2025.04.03.15.05.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717927; x=1744322727; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZtZrrkt2ntmoiQ4mVP99KUX/c8Ppft+k9zep++rss8s=; b=Nm6QjevMu/mc6NgtzyCe/Wg/OIhvti6R/FovHhID1bKB95dRALyzHVAZbcGTSRQKpk qmUnS2Xn+4PJITnwdNMMl9biMhtwdJatMFSP88/UTt7doAcWzE1mDFXMJbF+tQFLYjXJ CsZedmkk4je3l6WWB36fxMIAjktVsc4ZY8z3b8bMl391gyNEecYdyYttAMoXq7KX1iy2 AeMFYfWN/iLnoRKhEkM4/7bgpF9qud25IcrfsiU1Ymb5GcGDt8pZJguoPkigE4UsGPHy naE/iUr9KK3EVVTElpaDuTeh8lDhjIQQlGPBmCv7p7N1J3hFeoWX1VIdvXK/OGZJQ7Dl pk7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717927; x=1744322727; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZtZrrkt2ntmoiQ4mVP99KUX/c8Ppft+k9zep++rss8s=; b=P8RQql3KSkD1WCaOUUTnjE0mjK1l/s2lGWwjQzZ13n1IWWMOHW3XLRjh9r2WnPKPO1 D/bgudESUGnKucWp0/RN3lLZuAGrHUElhhUDr/THw80PQwV2mbOv9AVm0WWjA/hZrtL9 pxB8A2ANml2tlU8V6kslgiuKVSzTnKllW5u5L7Ny8pezKX5CwFp95NDCgT03AR/l5FSZ rJvS5WVUdPP1lKhhyVvgqPLI1xUd8DYEcFIp35i9zCmBs0vklkdshDPdjQDdI4Zl6oDw Q+0+gqrYLL373U2p8A+SL1IckMxj0Mw0q/1Aq5QCodHb1YH3oPIxEt5X9yEN1s6igIo/ xGVw== X-Gm-Message-State: AOJu0YxV6AhA6oQM/IeOiqSnP2KWKIRr/UetGBYQzN+EmEx6puU21Pl6 M8glvnhrETQ/w36nHOO6un/TXrxbLE/FD1fp+DGYhqShQHudyyTJ4HR1fCRpYxZfyllVtU5yO8C M X-Gm-Gg: ASbGncvqfUvZbksIRSolL1xLzaFhuZhwanUmQfKZgLx9zIJQs5X4giNoxAHlyz0zcpJ D/IXHqw6fY0uyYDMIuZNDTTClWxIrw9bfbZDt1ZkrOxkgFay3LYfAOwGau3fPYSIvmB7vitCDMY uy41a+f+/OjLy62FtbBcE3CmLNJOANKytExlqIGEFxQIN16Niz26h93I+uUVAqoRM3FjRdkkme7 fOkAqNPtBFfcZnX9nxjXRbOAkKvTwN+GYm28z+lWlAVKuPvlqSwr2pZ4mIOpQFJ6cE8fIW63uha 6ednMCmOgk3tuW8EiM9Q6XzoFczM6vwrVtPNGQ4zalbzCk93cXuJfzk9ofbNjXWr2dDPN1kIK3j 0u9CL8UXEW4if1Zcmx+DGXVce X-Google-Smtp-Source: AGHT+IH7MoWwihKJS+RDY0C8G0yMIApAZ14lJ3hnmc3lJMcmb01OVsZR1dAmULDsDxYtfS1+o55MhQ== X-Received: by 2002:a05:6000:40cf:b0:391:4977:5060 with SMTP id ffacd0b85a97d-39d14662f92mr310914f8f.53.1743717927503; Thu, 03 Apr 2025 15:05:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 13/19] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order Date: Fri, 4 Apr 2025 00:04:13 +0200 Message-ID: <20250403220420.78937-14-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717945272019100 In order to use TCG with multiple targets, replace the compile time use of TCG_GUEST_DEFAULT_MO by a runtime access to TCGCPUOps::guest_default_memory_order via CPUState. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/internal-target.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 23aac39b572..f5a3fd7e402 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -46,16 +46,15 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr= _t retaddr); =20 /** * tcg_req_mo: + * @guest_mo: Guest default memory order * @type: TCGBar * * Filter @type to the barrier that is required for the guest * memory ordering vs the host memory ordering. A non-zero * result indicates that some barrier is required. - * - * This is a macro so that it's constant even without optimization. */ -#define tcg_req_mo(type) \ - ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO) +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) =20 /** * cpu_req_mo: @@ -67,7 +66,7 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t= retaddr); */ #define cpu_req_mo(cpu, type) \ do { \ - if (tcg_req_mo(type)) { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)= ) { \ smp_mb(); \ } \ } while (0) --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717955; cv=none; d=zohomail.com; s=zohoarc; b=O07iKkshWJq+UHKs3lU7bjREPDzRnRZfijZFuLT4KiaOcqd8VXy1j2d9Lg+Q+f2u9AuAIOs3DQVEOodXKqnbFBWvoWJFW4HIE6DcL7aii9/36hI+ItbczkldTleJE8OlrPldYxziLOX6SCMrBODBz3ATPj4uY4BfUslbMjJCdSI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717955; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HslCu5n/a0mX39bWsSNFIxIjBHZodyJmu9d4dYt6eBs=; b=PE1q/68ygF7mlWcM+F5fvzcdtzmr4I0eriguBiUumJXMUKby+6G3kfGBjfcnDnfrz58d/7vSjJAJo26fZ3yAbbChHgnynT8cv6ONySCmzJVIogboGE1JC+3BCifx/yYTf0yiRZvQ2wNVjfqkSnNu/aWg24ek7EmzYgHpoXGKuA4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743717955718314.3570987551042; Thu, 3 Apr 2025 15:05:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sgv-0001O6-II; Thu, 03 Apr 2025 18:05:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sgs-0001Jm-T6 for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:38 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sgp-00040F-LW for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:38 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4394036c0efso9981175e9.2 for ; Thu, 03 Apr 2025 15:05:35 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301a0a90sm2792495f8f.21.2025.04.03.15.05.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717933; x=1744322733; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HslCu5n/a0mX39bWsSNFIxIjBHZodyJmu9d4dYt6eBs=; b=qSB4MwPVUQdxIC7zGSUE1EgCux47TFJnRA0kjhgUuZVyVY+VSRFlgSlvYbFOc18wJs A9Q8jpXXYK547xcUR+Qzih/brOHky8Q/NVEnDrDw3BysEmwuMBYlylsGGlM37Pu+ueC3 XQ7AI0pYDMvINjS9ONF2ablqoHivT5pqd36wVi1XGfXuxXDzi/KLXUVcDrlg/dEgOSPp rKcfDRMWubme6iczDrp3s5suYvi1/uIpCG28BMUe3aSsx95UIDiA0vsbDFCDLfyEqFYz vNDOsq4aPvTWT1c01fv/5P78OxhR6EIMv3exKmpr/LSF6tIH48qUvIq9Df4b7cXzYxy5 MUyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717933; x=1744322733; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HslCu5n/a0mX39bWsSNFIxIjBHZodyJmu9d4dYt6eBs=; b=lCCh0vJdW+d1kH+Ki3RaBSB4JM1mBvhNntsy2jtvicVM6BOPxBzshxdWY1jOzLrdOH Syn+rWAeDcisGXtJxpgfqh3QXbdieDL8mZWYzRR3ILOu9wrCalxXlgJjFHA8An7WTQ5K 5yaIWQ8EvZUE7Hhr9GnO8YfB1XvdtbSRDxyWxi1YyksEfQQRYJEU/q9n2Agk1ZehdJ4t gxrg+Q1FozA+rZ1wFm/ZbY7LoA3GGIKfdbaSdC1chsCsfhKkgHa56HQYx5S2tkYnTnUW cy6UWFwbRqUwH+sjeMN9mWshxlzyUlLDlN5CcYAqKynulWOVirMIV2WclKN/+458+LJ2 2+tw== X-Gm-Message-State: AOJu0YypT+4Kg39Zb1g4Sr92Gbbes9lVR6Y/p0PdPsx9yAClyDzeojK2 LqUIOr4JVgBtZ527eHlSlJwlD5/5AWN4ci8WevfUjDNQU6vm6GYN4jEhpZ+qhRpJyWGAyKPvrCh + X-Gm-Gg: ASbGnctmInq1Zrdt4d/enJGMz+e8C7P8dD8vIGt1gksWwKM2sw4HGMysYTSWcCuQxII DGUX+NTST+0CANDASHhlKddCZGWU32CYX8JfxtuRhvzqNvQr6P1PFXoM7wSB9XtIWR1gDjST+LM 6yHvmUssXe6g2ue0sSMpgGkI/qYRI4lhIzJpWO5uqWWySycFz3Pp9SfmvuEXIv3Gqv6Q/Ki2d3S qMGbyNoG9FIbMEsv7lfTSFoWj/1DR4OcWABsO2zE8TLSrBGAWHU20xUigIphsE6crRGbVuFyeLg cyWwyzoMQgqJFApsB+VcjjE7s57TXRJTHxgj7fZDaV+iP8d5iHXvTyahZD5jG0wJ1jh6Y+xV6mB PSUeD9i3pY3BBQ11GqusbHnDu X-Google-Smtp-Source: AGHT+IF1smKuhTp2JB6KbecHB6fER/jNxIcLwtBxn46W6GzcGDD+OvVYFMimW54w6zogYKwtu3U2uQ== X-Received: by 2002:a05:6000:270d:b0:39c:1257:dba9 with SMTP id ffacd0b85a97d-39d14762337mr195820f8f.57.1743717933521; Thu, 03 Apr 2025 15:05:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 14/19] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally Date: Fri, 4 Apr 2025 00:04:14 +0200 Message-ID: <20250403220420.78937-15-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717957235019100 By directly using TCGCPUOps::guest_default_memory_order, we don't need the TCG_GUEST_DEFAULT_MO definition anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- docs/devel/multi-thread-tcg.rst | 4 ++-- target/alpha/cpu-param.h | 3 --- target/arm/cpu-param.h | 3 --- target/avr/cpu-param.h | 2 -- target/hexagon/cpu-param.h | 3 --- target/hppa/cpu-param.h | 8 -------- target/i386/cpu-param.h | 3 --- target/loongarch/cpu-param.h | 2 -- target/m68k/cpu-param.h | 3 --- target/microblaze/cpu-param.h | 3 --- target/mips/cpu-param.h | 2 -- target/openrisc/cpu-param.h | 2 -- target/ppc/cpu-param.h | 2 -- target/riscv/cpu-param.h | 2 -- target/rx/cpu-param.h | 3 --- target/s390x/cpu-param.h | 6 ------ target/sh4/cpu-param.h | 3 --- target/sparc/cpu-param.h | 23 ----------------------- target/tricore/cpu-param.h | 3 --- target/xtensa/cpu-param.h | 3 --- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 3 ++- target/arm/tcg/cpu-v7m.c | 3 ++- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 3 ++- target/hppa/cpu.c | 8 +++++++- target/i386/tcg/tcg-cpu.c | 5 ++++- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 3 ++- target/s390x/cpu.c | 6 +++++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 23 ++++++++++++++++++++++- target/tricore/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- 40 files changed, 66 insertions(+), 101 deletions(-) diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.= rst index b0f473961dd..14a2a9dc7b5 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -28,8 +28,8 @@ vCPU Scheduling We introduce a new running mode where each vCPU will run on its own user-space thread. This is enabled by default for all FE/BE combinations where the host memory model is able to accommodate the -guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the -guest has had the required work done to support this safely +guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is z= ero) +and the guest has had the required work done to support this safely (TARGET_SUPPORTS_MTTCG). =20 System emulation will fall back to the original round robin approach diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index dd44feb1793..a799f42db31 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -26,7 +26,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* Alpha processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 2cee4be6938..5c5bc8a009e 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -44,7 +44,4 @@ */ #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -/* ARM processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 9d37848d97d..f74bfc25804 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -27,6 +27,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 7cc63a01d4b..635d509e743 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,7 +25,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 68ed84e84af..9bf7ac76d0c 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -21,12 +21,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -/* PA-RISC 1.x processors have a strong memory model. */ -/* - * ??? While we do not yet implement PA-RISC 2.0, those processors have - * a weak memory model, but with TLB bits that force ordering on a per-page - * basis. It's probably easier to fall back to a strong memory model. - */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 0c8efce8619..ebb844bcc83 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,7 +24,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* The x86 has a strong memory model with some store-after-load re-orderin= g */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index dbe414bb35a..58cc45a377e 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -15,6 +15,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 10a8d74bfa9..256a2b5f8b2 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -19,7 +19,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index 5d55e0e3c4a..e0a37945136 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -29,7 +29,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* MicroBlaze is always in-order. */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 99ca8d1684c..58f450827f7 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -22,6 +22,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index 7ea0ecb55a6..b4f57bbe692 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -14,6 +14,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index d0651d2ac89..e4ed9080ee9 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -39,6 +39,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index ff4ba81965a..cfdc67c258c 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -34,6 +34,4 @@ * - M mode HLV/HLVX/HSV 0b111 */ =20 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index fe39a77ca38..84934f3bcaf 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -26,7 +26,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index a8a4377f4ff..abfae3bedfb 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -14,10 +14,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 2 =20 -/* - * The z/Architecture has a strong memory model with some - * store-after-load re-ordering. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index acdf2397495..f328715ee86 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -18,7 +18,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 62d47b804bb..45eea9d6bac 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -23,27 +23,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -/* - * From Oracle SPARC Architecture 2015: - * - * Compatibility notes: The PSO memory model described in SPARC V8 and - * SPARC V9 compatibility architecture specifications was never implemen= ted - * in a SPARC V9 implementation and is not included in the Oracle SPARC - * Architecture specification. - * - * The RMO memory model described in the SPARC V9 specification was - * implemented in some non-Sun SPARC V9 implementations, but is not - * directly supported in Oracle SPARC Architecture 2015 implementations. - * - * Therefore always use TSO in QEMU. - * - * D.5 Specification of Partial Store Order (PSO) - * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. - * - * D.6 Specification of Total Store Order (TSO) - * ... PSO with the additional requirement that all [stores] are followed - * by an implied MEMBAR #StoreStore. - */ -#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) - #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index 45fde756b6a..eb33a67c419 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -14,7 +14,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL - #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index e7cb747aaae..7a0c22c9005 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -18,7 +18,4 @@ =20 #define TARGET_INSN_START_EXTRA_WORDS 0 =20 -/* Xtensa processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 6f931117a25..eeaf3a81c1a 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,7 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps alpha_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* Alpha processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D alpha_translate_init, .translate_code =3D alpha_translate_code, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3f20e258fd0..3e9760b5518 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,7 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { =20 #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* ARM processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 4553fe9de07..89d4e4b4a2f 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,7 +232,8 @@ static void cortex_m55_initfn(Object *obj) } =20 static const TCGCPUOps arm_v7m_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* ARM processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D arm_translate_init, .translate_code =3D arm_translate_code, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 67918684faf..8f79cf4c08b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,7 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps avr_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b12e0dccd09..3d14e5cc6a0 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -325,7 +325,8 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hexagon_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, .initialize =3D hexagon_translate_init, .translate_code =3D hexagon_translate_code, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ac4560febea..dfbd9330565 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,7 +253,13 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hppa_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* PA-RISC 1.x processors have a strong memory model. */ + /* + * ??? While we do not yet implement PA-RISC 2.0, those processors have + * a weak memory model, but with TLB bits that force ordering on a per= -page + * basis. It's probably easier to fall back to a strong memory model. + */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D hppa_translate_init, .translate_code =3D hppa_translate_code, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 3e1b315340c..d941df09560 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,7 +125,10 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps x86_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * The x86 has a strong memory model with some store-after-load re-ord= ering + */ + .guest_default_memory_order =3D TCG_MO_ALL & ~TCG_MO_ST_LD, .initialize =3D tcg_x86_init, .translate_code =3D x86_translate_code, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ee74509a664..f5b8ef29ab0 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,7 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps loongarch_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D loongarch_translate_init, .translate_code =3D loongarch_translate_code, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index bfde9b85948..b2d8c8f1dea 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,7 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps m68k_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D m68k_tcg_init, .translate_code =3D m68k_translate_code, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index e46863574c6..4efba0dddb2 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,7 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps mb_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MicroBlaze is always in-order. */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D mb_tcg_init, .translate_code =3D mb_translate_code, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 860ec398229..010773405a8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,7 +550,7 @@ static const Property mips_cpu_properties[] =3D { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D mips_tcg_init, .translate_code =3D mips_translate_code, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e62c698a407..87fe779042c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,7 +243,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps openrisc_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D openrisc_translate_init, .translate_code =3D openrisc_translate_code, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 57565c9a2f2..8300fa5777e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7478,7 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps ppc_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, .restore_state_to_opc =3D ppc_restore_state_to_opc, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ded2d68ad78..50e81b2e521 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -140,7 +140,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } =20 static const TCGCPUOps riscv_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + .guest_default_memory_order =3D 0, =20 .initialize =3D riscv_translate_init, .translate_code =3D riscv_translate_code, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index d7eac551fd4..f073fe8fc98 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,7 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps rx_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D rx_translate_init, .translate_code =3D rx_translate_code, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index f232d82fa34..1e101b5afeb 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,7 +345,11 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *p= c, } =20 static const TCGCPUOps s390_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * The z/Architecture has a strong memory model with some + * store-after-load re-ordering. + */ + .guest_default_memory_order =3D TCG_MO_ALL & ~TCG_MO_ST_LD, =20 .initialize =3D s390x_translate_init, .translate_code =3D s390x_translate_code, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 29f4be7ba9c..7a05301c6ff 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,7 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps superh_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, =20 .initialize =3D sh4_translate_init, .translate_code =3D sh4_translate_code, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ef04efcb183..56d9417ae3f 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,7 +1001,28 @@ static const struct SysemuCPUOps sparc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps sparc_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* + * From Oracle SPARC Architecture 2015: + * + * Compatibility notes: The PSO memory model described in SPARC V8 a= nd + * SPARC V9 compatibility architecture specifications was never + * implemented in a SPARC V9 implementation and is not included in t= he + * Oracle SPARC Architecture specification. + * + * The RMO memory model described in the SPARC V9 specification was + * implemented in some non-Sun SPARC V9 implementations, but is not + * directly supported in Oracle SPARC Architecture 2015 implementati= ons. + * + * Therefore always use TSO in QEMU. + * + * D.5 Specification of Partial Store Order (PSO) + * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadSt= ore. + * + * D.6 Specification of Total Store Order (TSO) + * ... PSO with the additional requirement that all [stores] are fol= lowed + * by an implied MEMBAR #StoreStore. + */ + .guest_default_memory_order =3D TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_S= T_ST, =20 .initialize =3D sparc_tcg_init, .translate_code =3D sparc_translate_code, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 3bf399335ac..c68954b4096 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,7 +172,8 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps tricore_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* MTTCG not yet supported: require strict ordering */ + .guest_default_memory_order =3D TCG_MO_ALL, .initialize =3D tricore_tcg_init, .translate_code =3D tricore_translate_code, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 23471064957..2cbf4e30108 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,7 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps xtensa_tcg_ops =3D { - .guest_default_memory_order =3D TCG_GUEST_DEFAULT_MO, + /* Xtensa processors have a weak memory model */ + .guest_default_memory_order =3D 0, =20 .initialize =3D xtensa_translate_init, .translate_code =3D xtensa_translate_code, --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717954; cv=none; d=zohomail.com; s=zohoarc; b=ijWmbINCB15U1tQmpKhDw4VrlB1cvEv97nETQg1LdK6Wv6Om2YOL9MALfNhiqFhflVlHFUTpM6jjJuLvqrBa1Z4+quxHGsTeTiLonOVpEri5tFiwDIfseFdz3rynOSxTdklt7yPcbFLAJCt/BcJAgqi46s/z34gKsHz7Im50c7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717954; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FyHyqUVPAmJjyMO6Sr/Bf3FWzhnRIjw+jQa7gHGhFEQ=; b=CyNO+zOlul7+yp8unV+VYifgRpYmZUtQwUhP8NCkRN5TnPHHyVgVYPyZP3LQbJZnV3DQck9bUKGZHftXHIFzDCbU/PwfHMWkyQOPTlr2iWzEThm0pB0B7A+jlJr0arJPSIN0pColRA96w+42XM7/qN+4jcLNU2j5z/+AeMbCbTA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743717954330313.2190447735435; Thu, 3 Apr 2025 15:05:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Sgy-0001Uf-OP; Thu, 03 Apr 2025 18:05:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sgw-0001Py-Mb for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:42 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sgu-00040m-Js for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:42 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-43cfe574976so9676975e9.1 for ; Thu, 03 Apr 2025 15:05:40 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec169b4e4sm32600865e9.20.2025.04.03.15.05.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717939; x=1744322739; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FyHyqUVPAmJjyMO6Sr/Bf3FWzhnRIjw+jQa7gHGhFEQ=; b=yuNZ2OuYTrqAbBtFQPGQhYIXUlmoh5+88Jb2I6h8TJwGg0dNGRM5j8Ayq6uoHywmfC hJA8LTy4kMcu9mnVPd0MPlp1EPh+vNwMcC/D1xTjdGgtdubwQGyHUoyUod1FJhxqmtQO hegeCxin8XjB2Llh3ShTyfDeIlXpj81nZHF0eP7px7cU15wVCfwLWQMF/qGrL82NomZ9 t2JbWF9jM+NyjjYc7A7zFCNAoN302ufjAPgCr7mPPUHsjTBiMV/yx2EOZT0iabLhnVbA qj4LgN242/27lr2EqJztULjbnn2evVKNiy/6ABum+OGu0RnkCMbDOyZdv7zKkgwxBH2X eZAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717939; x=1744322739; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FyHyqUVPAmJjyMO6Sr/Bf3FWzhnRIjw+jQa7gHGhFEQ=; b=hQv88y1Znh0QNYBQUMP2kY3ulg+Cp7ixxfSdzr1YxxD2nia/5J/nSmA+Qwjq7zKWP4 nXKFMUrfHhFhdCLfKscDKNF8UHWQUueOeXWLuJi+p1QAERec7Y/f0yjvWUqr+lfVe0Tw ofszL6/Erk0oDzoV7SaZSukUVrt+gAh+zGEyUKyVHejyynA0ozQVbA0ugRridhKzgx+l n7IB/QPHz8v6xCfH7R0IaQb0Dwu71sk5Z8kgrufvcLzuIJpAFN5Q7RhkAemOw/hFAdp/ zhy7FwOEAExfcO5XzjK3Ypau8I+jb2w5mKlXS28pyiz5VHolFouGm4iUDMrVmE/hjNpv TxoQ== X-Gm-Message-State: AOJu0YyP2rHzwFIIDnkSLt+Ko5LocJNXH8ErZuyKsUCZj17psAqAPJi5 nzVtf0PS3VbOIVpvGOZLNotgf7YdlvyLlqYPimzMVgVzReAG7KrGPWL6MzVJ4f4/wIZzv4u509l 2 X-Gm-Gg: ASbGncta36+anET/T6p89lPn6NrHgo67anjfzPgQSxvEsmfH+vHZHyv2yFFPvHDBXm3 QRiLt9FKLUc0aJf4c2WmUHmH1JH2VpOHrE4f5spxhE2Zwf5J8GLkUHHCNk3ImwNpjPu24BnMm1U T6l/hvTXvc1r/P2dFTHkhiPWpfO54AhUn08ZpLiZ8VQYgbwJJulktkb7a8xYIlMOanPxZSYjRAE OcHxVUeHXhYyhvuDGWP8zjcjEa2gqTr7WhbTkXUpVONLiEzLL+7vQCMcFshJ1bYxuEldpUWh7T2 9A7MIM1xkKA5pKyA0RodV40s6u5koRNLHZSWEVrVDDYudUMMB8LceVIALaK62W8L4SGQgCsrICG RijWuPtSILKOrh/y9twMHniUa X-Google-Smtp-Source: AGHT+IGoa28LNTQUqBGHzhQywr9zfKp1WvboX0jrO+iygYKMwS9qIjRIp7DXSS6Ppy26eqPCvldduA== X-Received: by 2002:a05:600c:510d:b0:43c:fe90:1279 with SMTP id 5b1f17b1804b1-43ecf9c36f6mr4033495e9.21.1743717938790; Thu, 03 Apr 2025 15:05:38 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 15/19] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Date: Fri, 4 Apr 2025 00:04:15 +0200 Message-ID: <20250403220420.78937-16-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717957068019100 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/backend-ldst.h | 41 +++++++++++++++++++++++++++++++++++++ accel/tcg/internal-target.h | 28 ------------------------- accel/tcg/cputlb.c | 1 + accel/tcg/user-exec.c | 1 + 4 files changed, 43 insertions(+), 28 deletions(-) create mode 100644 accel/tcg/backend-ldst.h diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h new file mode 100644 index 00000000000..9c3a407a5af --- /dev/null +++ b/accel/tcg/backend-ldst.h @@ -0,0 +1,41 @@ +/* + * Internal memory barrier helpers for QEMU (target agnostic) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_BACKEND_LDST_H +#define ACCEL_TCG_BACKEND_LDST_H + +#include "tcg-target-mo.h" + +/** + * tcg_req_mo: + * @guest_mo: Guest default memory order + * @type: TCGBar + * + * Filter @type to the barrier that is required for the guest + * memory ordering vs the host memory ordering. A non-zero + * result indicates that some barrier is required. + */ +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) + +/** + * cpu_req_mo: + * @cpu: CPUState + * @type: TCGBar + * + * If tcg_req_mo indicates a barrier for @type is required + * for the guest memory model, issue a host memory barrier. + */ +#define cpu_req_mo(cpu, type) \ + do { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)= ) { \ + smp_mb(); \ + } \ + } while (0) + +#endif diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index f5a3fd7e402..9a9cef31406 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -13,7 +13,6 @@ #include "exec/exec-all.h" #include "exec/translation-block.h" #include "tb-internal.h" -#include "tcg-target-mo.h" #include "exec/mmap-lock.h" =20 /* @@ -44,31 +43,4 @@ void page_table_config_init(void); G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); #endif /* CONFIG_USER_ONLY */ =20 -/** - * tcg_req_mo: - * @guest_mo: Guest default memory order - * @type: TCGBar - * - * Filter @type to the barrier that is required for the guest - * memory ordering vs the host memory ordering. A non-zero - * result indicates that some barrier is required. - */ -#define tcg_req_mo(guest_mo, type) \ - ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) - -/** - * cpu_req_mo: - * @cpu: CPUState - * @type: TCGBar - * - * If tcg_req_mo indicates a barrier for @type is required - * for the guest memory model, issue a host memory barrier. - */ -#define cpu_req_mo(cpu, type) \ - do { \ - if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)= ) { \ - smp_mb(); \ - } \ - } while (0) - #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 35b1ff03a51..d9fb68d7198 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -48,6 +48,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" =20 =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f4d6824460..5eef8e7f186 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -37,6 +37,7 @@ #include "qemu/int128.h" #include "trace.h" #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" #include "internal-common.h" #include "internal-target.h" #include "tb-internal.h" --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717997; cv=none; d=zohomail.com; s=zohoarc; b=huPWeflWB1rxmtm5DiNsmlgEKgQpDGNBJXO8ozK6Jvc9x4E7x3tSvc6QC8/1VS8ZCpgCTgY2/EMbY36Db77IwnPfuVwm847DtRfriBrc0q0dAptN1Tw+BtDuEU3lFvAGVrtd8e6yIbpCh4xYOvCS8FfGD92KFkckUZTtWokDjZs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717997; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=k0hPjVpMeOEGtb5tikd80FZUadFKvG8IWWz5+z4zreQ=; b=W2PQCXYedqTnT+T0KFJdAWi40G2+Ff1FB/ZWQCG//iC8oJ/MKP0oPSVVCqbWczCdf4ymBScru4bqUaTjqaQmKVQ/JaRqg370gUeztVsIOlZcVkO2UUJbPj3Z6iKGfRKlkKYoi/dty9AEn6+F8CoeN5Za0R1ngx75g3LMIeYv8Z8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743717997912224.24463325815395; Thu, 3 Apr 2025 15:06:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0ShK-00022w-HG; Thu, 03 Apr 2025 18:06:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sh2-0001mS-5u for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:48 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sh0-00041Q-9L for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:47 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-43cfba466b2so14085115e9.3 for ; Thu, 03 Apr 2025 15:05:45 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301b6a1esm2841726f8f.45.2025.04.03.15.05.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717944; x=1744322744; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k0hPjVpMeOEGtb5tikd80FZUadFKvG8IWWz5+z4zreQ=; b=An8OTESjKBxgKCUy0ILV/V/2wCFQYReoCMwDHdvTHXmxjz5PNXDnZNr0UbYEg+DmAV rqsiXEDwdFBoqbeZmvSdy6DDrRZkNTbXxqtMGj3YRVPgfwrJEZ+ODV/K8nKMt8QjXdKD SKIhzaTfMGfGyrIXaG6tXSOxmXmu5RMnf1HN/PHaAHsE0GuD+1Vr5LdG22K9nrgljPx9 DnApTSnNzOORp4206F5daL8/zQS7zK68xEgnw4xmrhTWHNYVIgp12ez6TXF5oEV+hegv uJhyXs68bvAIn+z7qpN/RUwKSZhNTjVkDxL1lm9/RPrqrwuF+i28g/30nwEsg03M/2O0 nKcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717944; x=1744322744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k0hPjVpMeOEGtb5tikd80FZUadFKvG8IWWz5+z4zreQ=; b=dGTP6YffR5WzJ/7E+bH2Nrd8n2wB0uDGR82IFRbFViyaNL/gUPoVQY6OX8rg8bysGz DG0iMkm7k5kbjgeitMHm6yRU+oOdPW/PTtFOlBVGgajHVfyGGLhZSlSp4PJ9f8MB/6gO KhXeR8Ow/iSWSRmqLj4cAaOA/NjO/YCjh2aMAWn61pxL3dA93O+pHMgT13lk52ALCTmq y9VivjUZUuUmuvmKx17yUdoRv0B1yDtn9sxhLBLdhfIbiO1VnyeGYZlhPqfLmqzMtSMY Wtu97HCgQWmqUTJXey+3DBf5yw4vSm7Az+cTYXCLDSX4PH3CX8iOerIQ4xl4eLAxCHto +rXw== X-Gm-Message-State: AOJu0Yylj5hYlXQ8ipfLMhRSD9L4LiS6IA5tvSsy9XZEr+BE5eHwdLep s6X1mEiBhIfSZ5AAJFWj8yygqFA+axtczxXjJt4sbmWg9aDjjuJVuZiK/ep7DQjIn+aX/v2Angg K X-Gm-Gg: ASbGncv70yCsH5WuY1Dq9rWemqujiTWaYVpzqLo2r0NAZ88h3teCKnp2UCtewCT+koW +E2btk7GHdL63eLvssMUSGn9wdC7yNMhbaDd8sct/tAB2ybNQU3As4ddOs8Q9Rxj6BCJn4Kk9gy qTx5Npa5hUpCRLCr4YKdYsbtEQk2YNHLr5j7XwcriaWkgGovnbefjgoiUlYvO/ejNn26m00h+e8 WNU2K8x3NxjAsB2fkIy9nckTtUIHMnkAtv8KOKL0DPTqiauKEHyT19zqD33s5kDpUmpzDYsHgyu gBr/GxE5PLOhzTrMCLjvKvkinku6eAhDe++ounN2XY0nkstUjfxCmunDILp2vboBsTjXHU5hK1M TMT732T4M849rU32oh8vd7HVP X-Google-Smtp-Source: AGHT+IF1kjnQ3a7qpml9Oy4IrAFXFGwNzma5rW6C+2Dg9pimAozyzKBpNLpGq/s/9H3jUxbLk7w2oQ== X-Received: by 2002:a05:6000:2210:b0:39a:c832:4f46 with SMTP id ffacd0b85a97d-39cba93c081mr754122f8f.26.1743717944183; Thu, 03 Apr 2025 15:05:44 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 16/19] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Date: Fri, 4 Apr 2025 00:04:16 +0200 Message-ID: <20250403220420.78937-17-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717999907019000 qemu_tcg_mttcg_enabled() is specific to 1/ TCG and 2/ system emulation. Move the prototype declaration to "system/tcg.h", reducing 'mttcg_enabled' variable scope. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 9 --------- include/system/tcg.h | 8 ++++++++ accel/tcg/tcg-all.c | 16 ++++++++++++++-- target/riscv/tcg/tcg-cpu.c | 1 + tcg/region.c | 4 +++- 5 files changed, 26 insertions(+), 12 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 10b6b25b344..c8d6abff19a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,15 +594,6 @@ extern CPUTailQ cpus_queue; =20 extern __thread CPUState *current_cpu; =20 -/** - * qemu_tcg_mttcg_enabled: - * Check whether we are running MultiThread TCG or not. - * - * Returns: %true if we are in MTTCG mode %false otherwise. - */ -extern bool mttcg_enabled; -#define qemu_tcg_mttcg_enabled() (mttcg_enabled) - /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/include/system/tcg.h b/include/system/tcg.h index 73229648c63..7622dcea302 100644 --- a/include/system/tcg.h +++ b/include/system/tcg.h @@ -17,4 +17,12 @@ extern bool tcg_allowed; #define tcg_enabled() 0 #endif =20 +/** + * qemu_tcg_mttcg_enabled: + * Check whether we are running MultiThread TCG or not. + * + * Returns: %true if we are in MTTCG mode %false otherwise. + */ +bool qemu_tcg_mttcg_enabled(void); + #endif diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index a5a1fd6a11e..b8874430d30 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -38,6 +38,7 @@ #include "hw/qdev-core.h" #else #include "hw/boards.h" +#include "system/tcg.h" #endif #include "internal-common.h" #include "cpu-param.h" @@ -58,6 +59,17 @@ typedef struct TCGState TCGState; DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE, TYPE_TCG_ACCEL) =20 +#ifndef CONFIG_USER_ONLY + +static bool mttcg_enabled; + +bool qemu_tcg_mttcg_enabled(void) +{ + return mttcg_enabled; +} + +#endif /* !CONFIG_USER_ONLY */ + /* * We default to false if we know other options have been enabled * which are currently incompatible with MTTCG. Otherwise when each @@ -97,7 +109,6 @@ static void tcg_accel_instance_init(Object *obj) #endif } =20 -bool mttcg_enabled; bool one_insn_per_tb; =20 static int tcg_init_machine(MachineState *ms) @@ -107,10 +118,11 @@ static int tcg_init_machine(MachineState *ms) unsigned max_cpus =3D 1; #else unsigned max_cpus =3D ms->smp.max_cpus; + + mttcg_enabled =3D s->mttcg_enabled; #endif =20 tcg_allowed =3D true; - mttcg_enabled =3D s->mttcg_enabled; =20 page_init(); tb_htable_init(); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 50e81b2e521..88f7cdb887c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -36,6 +36,7 @@ #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" +#include "system/tcg.h" #endif =20 /* Hash that stores user set extensions */ diff --git a/tcg/region.c b/tcg/region.c index 478ec051c4b..56d2e988719 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -34,7 +34,9 @@ #include "exec/translation-block.h" #include "tcg-internal.h" #include "host/cpuinfo.h" - +#ifndef CONFIG_USER_ONLY +#include "system/tcg.h" +#endif =20 /* * Local source-level compatibility with Unix. --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743717985; cv=none; d=zohomail.com; s=zohoarc; b=IHOcrToXVsf4y0xSeJC2wXjadutv+oo+pUIKs8jQbQO/jxkbA0ODCAthCp8KE3pm0WsCqOIycDewx9+lYJbYL/xoanLu/4BkRB8LXq1gwx3VDIJLcQyBwkIwYjDsNx/dAtIDCvNY9vvyubpn57R+t/VWSyVhfPGwW15UQqbEfhE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743717985; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WxLf1qzYlIt55rERNGlTsLbACYfcGvHkqll/jBxBAw0=; b=NOT/eHtrAu/gQYSB4gkBaZYFr8heiJ/OdzfpFrqln6wSPBs9JAo9HD1KkCf7Q7U43ZsbPxCN/+qysEa0wux5vCBfWMbamrSRydpsjKblEfyWaSuO6yywyciSGcHe8GotG9006oMq3bcW9uv5qJ3Hgx579fpjgAUME1XAn1rZPvc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743717985934827.8622660319228; Thu, 3 Apr 2025 15:06:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0ShS-0002b8-1s; Thu, 03 Apr 2025 18:06:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0Sh7-0001w3-SK for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:54 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0Sh5-000426-Tr for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:53 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4394345e4d5so9298745e9.0 for ; Thu, 03 Apr 2025 15:05:51 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec342a3dfsm29444105e9.4.2025.04.03.15.05.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717949; x=1744322749; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WxLf1qzYlIt55rERNGlTsLbACYfcGvHkqll/jBxBAw0=; b=Korbj5vGBxWX9BDYVIQewZSH1rVYwet+rIbrpzQHjqSm/+bqSzMivODE96hm7OS8BR VQnaj+8iG7yfyXE8stsAvQw8Ec4N3bTLO0/QjXyJ8W9UuI+eCH2XL9OSm5T5MXBSMIA5 YIY9MJi58w0pzs6J2VZKAQ3Mg4Svt2lJEbKyUHwbLaivWEcO0qDB9lKPU/2xcd8oqihR 0gMRv1YjsUpmoI38xU7t/ta2hRr7YUd4tiI4htJIL1wu0zlXqvZR7zus8wVDLSfR/1gz QfBOfS3etmmVRdNdGCZZt/OXzajWkaUB9h5Fp29Xl5AXLPF8M2f9RxpV6PPrTcG5OGbu 3jIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717949; x=1744322749; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WxLf1qzYlIt55rERNGlTsLbACYfcGvHkqll/jBxBAw0=; b=PGqyzNDk+RSpZHulXvFsB2KgX0IUktPG9q3TZ6Kb8tt58qhT5aovZrRl2FZBE8SdjC MKUIpHu/+mbROHYK98tHeUKYGY+XKK09DzKE571B0iWv1TsUS/U1U619mnYe+PFt6rN6 4rvq9GJGeeKd2nFxQrC/JJiXzT+m0Pa8SNsPpS5TlovDAJgyYKMsaqguM6zRx0Szfncj 6lRK2RSd6v0e94PhhxEEZ8YxldOhAplNkOX7lxLj8O+Nz0mKa877aYj5CbL9+B6IbL/d ho7eM5SYLKH1AWhsDhJZID92aBtALHphRdMOZ6lTX20h5KivMbokiwGrw1nHZUVLtrDV /yQA== X-Gm-Message-State: AOJu0YzvTZmx7d1LyB7fudSnSacWotjoKJrQgfGWG1y3GXzW857PPabD 69VeKk2J4CkQLAh+oWVwdFi7m2oEraRgp2jKIHd/WK388tlNI1UhGlvh1t1L+4ijV/Luj/5HYMy V X-Gm-Gg: ASbGncvZD0w0GdSA0YbeLCMSZHvSxLdRyvryxBral/UCUFukNotepefb7wI2/vLLhEl Ue+ZQA2ffrZTTkEGWwsyLjtKdmCH3eA6D5e8bJaN/cqCurInTDcgHgYS1YkGxDC6lsCqHr2EutL VBstbrEaj5JOwimlFa1fMRvUuB/oezUpKsUnToK2qrXn1JI/bXuKIFRnCY8gLXAKaVXGHCfRgFg IE9vzSzgV170dW9I5NRkDjUI97ScjEnxLkHw8Bu96ZUUfXWGBJdhgFoFqTL5KGGjOFg8fXT/p5K 5DCIpIrtGw7GjMF8RjFz8Hr2neiSdLz5mn8XDmZMMQIoM2Xoxg2UOHNxCftdBg13yvcdceEJqwh tbadOrYZkpv0MyhWH04dWQfCN X-Google-Smtp-Source: AGHT+IEIKM/8xkF+LYo5ZYm1WjaaDxmRkXTk9PYtSPPcMLEExJcSefuw7IN92/fEkI1es6ZrCKF4Wg== X-Received: by 2002:a05:600c:3c8d:b0:43c:f5e4:895e with SMTP id 5b1f17b1804b1-43ecf841d5dmr5406035e9.1.1743717949557; Thu, 03 Apr 2025 15:05:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 17/19] tcg: Convert TCGState::mttcg_enabled to TriState Date: Fri, 4 Apr 2025 00:04:17 +0200 Message-ID: <20250403220420.78937-18-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743717988056019000 Use the OnOffAuto type as 3-state. Since the TCGState instance is zero-initialized, the mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO). In tcg_init_machine(), if mttcg_enabled is still AUTO, set a default value (effectively inlining the default_mttcg_enabled() method content). In the tcg_get_thread() getter, consider AUTO / OFF states as "single", otherwise ON is "multi". Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tcg-all.c | 60 ++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index b8874430d30..15d4e9232ae 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -32,6 +32,7 @@ #include "qemu/error-report.h" #include "qemu/accel.h" #include "qemu/atomic.h" +#include "qapi/qapi-types-common.h" #include "qapi/qapi-builtin-visit.h" #include "qemu/units.h" #if defined(CONFIG_USER_ONLY) @@ -47,7 +48,7 @@ struct TCGState { AccelState parent_obj; =20 - bool mttcg_enabled; + OnOffAuto mttcg_enabled; bool one_insn_per_tb; int splitwx_enabled; unsigned long tb_size; @@ -70,37 +71,10 @@ bool qemu_tcg_mttcg_enabled(void) =20 #endif /* !CONFIG_USER_ONLY */ =20 -/* - * We default to false if we know other options have been enabled - * which are currently incompatible with MTTCG. Otherwise when each - * guest (target) has been updated to support: - * - atomic instructions - * - memory ordering primitives (barriers) - * they can set the appropriate CONFIG flags in ${target}-softmmu.mak - * - * Once a guest architecture has been converted to the new primitives - * there is one remaining limitation to check: - * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host) - */ - -static bool default_mttcg_enabled(void) -{ - if (icount_enabled()) { - return false; - } -#ifdef TARGET_SUPPORTS_MTTCG - return true; -#else - return false; -#endif -} - static void tcg_accel_instance_init(Object *obj) { TCGState *s =3D TCG_STATE(obj); =20 - s->mttcg_enabled =3D default_mttcg_enabled(); - /* If debugging enabled, default "auto on", otherwise off. */ #if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) s->splitwx_enabled =3D -1; @@ -118,7 +92,31 @@ static int tcg_init_machine(MachineState *ms) unsigned max_cpus =3D 1; #else unsigned max_cpus =3D ms->smp.max_cpus; +#ifdef TARGET_SUPPORTS_MTTCG + bool mttcg_supported =3D true; +#else + bool mttcg_supported =3D false; +#endif =20 + if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_AUTO) { + /* + * We default to false if we know other options have been enabled + * which are currently incompatible with MTTCG. Otherwise when each + * guest (target) has been updated to support: + * - atomic instructions + * - memory ordering primitives (barriers) + * they can set the appropriate CONFIG flags in ${target}-softmmu.= mak + * + * Once a guest architecture has been converted to the new primiti= ves + * there is one remaining limitation to check: + * - The guest can't be oversized (e.g. 64 bit guest on 32 bit h= ost) + */ + if (icount_enabled()) { + s->mttcg_enabled =3D ON_OFF_AUTO_OFF; + } else { + s->mttcg_enabled =3D mttcg_supported; + } + } mttcg_enabled =3D s->mttcg_enabled; #endif =20 @@ -147,7 +145,7 @@ static char *tcg_get_thread(Object *obj, Error **errp) { TCGState *s =3D TCG_STATE(obj); =20 - return g_strdup(s->mttcg_enabled ? "multi" : "single"); + return g_strdup(s->mttcg_enabled =3D=3D ON_OFF_AUTO_ON ? "multi" : "si= ngle"); } =20 static void tcg_set_thread(Object *obj, const char *value, Error **errp) @@ -162,10 +160,10 @@ static void tcg_set_thread(Object *obj, const char *v= alue, Error **errp) warn_report("Guest not yet converted to MTTCG - " "you may get unexpected results"); #endif - s->mttcg_enabled =3D true; + s->mttcg_enabled =3D ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") =3D=3D 0) { - s->mttcg_enabled =3D false; + s->mttcg_enabled =3D ON_OFF_AUTO_OFF; } else { error_setg(errp, "Invalid 'thread' setting %s", value); } --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743718020; cv=none; d=zohomail.com; s=zohoarc; b=daWG5+21ANmrLECgZAYnQhJSiNdUwfyWUBhmYEHgOi5/En5Tz1gRnAc+yhM8SxIXk/RnDvyW2b1kFpuBHLs27zXRD2DWzuYZ8FLf64WSJaIYKQAncorasE5uHq17p+Xg0vwtEJzZj6WJ3BsR51GeimjdHnpXrFbnhXr/2SbTcSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743718020; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fLiC832/142ITmF1Yvgl6ilLfBOuUrOH271pHrSjNR0=; b=ZvDet2A3o4lg9AVLIwzLBJB5t1UVqltEFodJzPmRtXZjjkJOiVxXvgwQX/5DgCglyJa6amwn1+kYR6bT9I03qE78jgjDwjT4RbyR1EXII1X4Baefkdp+a67EAo0q0uFt8q2OLIx7WvUEmK92G5KZoKpnBNAakigEGZJyrOfBEDE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743718020872358.079179457053; Thu, 3 Apr 2025 15:07:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0ShX-0002sT-9L; Thu, 03 Apr 2025 18:06:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0ShE-00024z-Gz for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:06:02 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0ShA-000438-Tf for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:05:59 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3996af42857so1720903f8f.0 for ; Thu, 03 Apr 2025 15:05:56 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30226ecdsm2910634f8f.99.2025.04.03.15.05.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717955; x=1744322755; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fLiC832/142ITmF1Yvgl6ilLfBOuUrOH271pHrSjNR0=; b=NvoLT5R8isA25NDIg3hW5UKUZVjZIPzfp4qLrBxwkL50X7FQ5BcD2vnbUuw9PZTzu2 5HnC//AbfpeDcgkSJIF6IQLx1TdEmi5OhiD8qQD+K94GAvTwi7d4DqgYK7x7qJDUmD9C 0nTNPJRO0S5rJB18owJ6i3F4TkCQvH03JpDL/EDT2DQP0Mx0HXSXAun12724prlg5SMd PmcDDnvuwN4fcxoOJHN+ZcJZFf62Zx6NQHPNW3G+V1YB4Q4xaZSww0ZqPEQ+EP+qb2jD z5W3e16sQCeflW2H8Cd6W/TM51qO9TN6BzZFc1NPhEpqySpp6de8+YaFohxcoG+6plxt X8fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717955; x=1744322755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fLiC832/142ITmF1Yvgl6ilLfBOuUrOH271pHrSjNR0=; b=AWSoRsQM8N8Gw70P2rKaR+bRY5xi04rLgKOGjG9puBStcw/ppt4zQ49TIhMvwOVPUI knJGiZ7Uo7fYM5mHZbKc/u5siHDcBIPe0IwOoevWMizywZYKm+CXgOzcsD+1OBIzs2Cy VikrX7sJrf1qsG4FDQ1PBT3gmFPmRT2lRosaKOHwG5wLSZXY/Mz6mbWcjmOK4QHmENX8 E74Ko4SlMxDTVSQDfKX2Kb/oukcPv8Fn3CzAZwXsuA1Qdo/8eE25h2wfmUBa1wAY87Be XZk3jD2YF33guyZ9R1R8+ghprPyJHmmjvE//lwDPXfdPZz7cFgFpxdvuPVLFEMits4lc 9b/w== X-Gm-Message-State: AOJu0Yxg3dOEEZ1lBGNIfUkW1yxpP1NTIoYuCfFiPKa2Cjd+O75EOSlj f/baiuVuJGQHPC81z/S+go/wKIosFt+Ez1SdvbcWY4cvCPFZ42I1zRmutPDZxxldfBSGaP5scKw 0 X-Gm-Gg: ASbGnct8hkGOrQ3g6+v/Gj1tlXpwE4ZWoA8ns0tTHlS4SfgcwgL3RhYuR8aT1jYAh9R rrb7MPq4CeZyBsUxh54C1L4HmoYKWp2XB2W1DE72KH/MnCbpx0xecFEKjmK8YRaHZEoD5+fJqNQ E8VPAMDZrpm58h5ZtPQ13x5ex1pfmQV1tL14l3W3u3XU5gh2n6xwJSiqJ+QxN+socGab+fGQtnl ePcIgmcm9BLnGmD5h2s8TUCsH+lnTv4yi4pqZu5woFUoQTlXQQTN+eyLXChyd5kz9eoAlDczeal d6Ylxsb8I59QTVAmOMwgkxB4+VZ4jH8CCMc4MQoxWI5MMxjiOL4I77spZsBoIICQqmq80amMsi7 z6YSDeth/t3pVay2r9RLLiRRu X-Google-Smtp-Source: AGHT+IG+cug/dAzyhePydZgG8rvz9J0+0SnG5F9ND7jIrqZoVBLs5JIW2JK4AaMFnjBAMbR6rWbGnA== X-Received: by 2002:a05:6000:1869:b0:39a:c9ae:a198 with SMTP id ffacd0b85a97d-39c2e5f512fmr4586418f8f.1.1743717954850; Thu, 03 Apr 2025 15:05:54 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 18/19] tcg: Factor mttcg_init() out Date: Fri, 4 Apr 2025 00:04:18 +0200 Message-ID: <20250403220420.78937-19-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743718021925019000 Keep MTTCG initialization code out of tcg_init_machine(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/tcg-all.c | 50 +++++++++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 22 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 15d4e9232ae..267830658ca 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -69,29 +69,8 @@ bool qemu_tcg_mttcg_enabled(void) return mttcg_enabled; } =20 -#endif /* !CONFIG_USER_ONLY */ - -static void tcg_accel_instance_init(Object *obj) +static void mttcg_init(TCGState *s) { - TCGState *s =3D TCG_STATE(obj); - - /* If debugging enabled, default "auto on", otherwise off. */ -#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) - s->splitwx_enabled =3D -1; -#else - s->splitwx_enabled =3D 0; -#endif -} - -bool one_insn_per_tb; - -static int tcg_init_machine(MachineState *ms) -{ - TCGState *s =3D TCG_STATE(current_accel()); -#ifdef CONFIG_USER_ONLY - unsigned max_cpus =3D 1; -#else - unsigned max_cpus =3D ms->smp.max_cpus; #ifdef TARGET_SUPPORTS_MTTCG bool mttcg_supported =3D true; #else @@ -118,6 +97,33 @@ static int tcg_init_machine(MachineState *ms) } } mttcg_enabled =3D s->mttcg_enabled; +} + +#endif /* !CONFIG_USER_ONLY */ + +static void tcg_accel_instance_init(Object *obj) +{ + TCGState *s =3D TCG_STATE(obj); + + /* If debugging enabled, default "auto on", otherwise off. */ +#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY) + s->splitwx_enabled =3D -1; +#else + s->splitwx_enabled =3D 0; +#endif +} + +bool one_insn_per_tb; + +static int tcg_init_machine(MachineState *ms) +{ + TCGState *s =3D TCG_STATE(current_accel()); +#ifdef CONFIG_USER_ONLY + unsigned max_cpus =3D 1; +#else + unsigned max_cpus =3D ms->smp.max_cpus; + + mttcg_init(s); #endif =20 tcg_allowed =3D true; --=20 2.47.1 From nobody Sun Nov 16 04:02:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743718155; cv=none; d=zohomail.com; s=zohoarc; b=ZKWOuF/elC8xpygkx0i38DVyTix+T6Cs1M6LENcnkTnGlIHZqMlxgxavwYvbGggDrj97q/UZ6xx/tgBk+C4gIAWCatYo/hnkU44sD1MU911Ttc19d9FqV3UFQJ/q+J8jp/8uBQ0tueZUF7SZMj7Sqg5T7WUUQYwJ1Yl3yfWdEZM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743718155; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DkZfUGTIHPJoFuoXNJAvYpwK7HYaDnYB6xEqZqBEDyc=; b=PU/RObZmRUKGmg8J/N0dh0Y1mW9mFbpMGeR0tsTwTqe3t/Q4jIhAEHWSrsMeV9sHl4aqHkQF+LrF/kqKR0nj3vCTa9lVn9mB8YwH2DOVLm6h9g/FJnXlE/qJopxvhXg3fHuqcSlhOl6oeynejSzE48NI+aGmHdgU4RViXa49Y54= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743718155815525.8815227168507; Thu, 3 Apr 2025 15:09:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u0Shf-0003O1-OA; Thu, 03 Apr 2025 18:06:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u0ShJ-00029D-0D for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:06:06 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u0ShF-000443-R3 for qemu-devel@nongnu.org; Thu, 03 Apr 2025 18:06:04 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-43cf034d4abso14827745e9.3 for ; Thu, 03 Apr 2025 15:06:01 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020d64dsm2853743f8f.70.2025.04.03.15.05.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Apr 2025 15:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743717960; x=1744322760; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DkZfUGTIHPJoFuoXNJAvYpwK7HYaDnYB6xEqZqBEDyc=; b=DvHN15Slr9HhVn4mF6I2org1aPd9KQnVRbi2ky+3aUUsRoI9ncAfocyidrUA1df+eE a0YTDyvGYlhr/GWL2SOwpbtJEWsU+nwwGxitWfCjELwlSZJGZ4pclZhYo0jwZdng4V+d OiWTaMEReziUf2QDfmcKbVaglt/a30SXHo0zJRQn2LjhW91PSJS873abLbTlI3U/ox6I bv2pqSyq+5RSK+Nsl1y76K9E6p9NluyaPV9Hrcx467esZ/3Gm2xHylZTHcunpACnBNl/ AJpzw94VG/4LpRqRSP3Mw0wp23hG+hKArBGAsfjsSqIt+p8o5l1qv8WnmCqKV/H7Wl1Q sxUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743717960; x=1744322760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DkZfUGTIHPJoFuoXNJAvYpwK7HYaDnYB6xEqZqBEDyc=; b=a/wRZIPkWgO10TpgG0gDj7tKRcU/j+A7+SvZkymGLK9EzO2c8hHd1mJ4C2RnaMzC4O rhscqB4miIB1VBzrgvX+jEDpEINC4fPW7vMkJQZWBVNrrfyYrU9RNZjuI4zNJfw6paN4 O8LpFx6eXcRDEbQ/Z1Z2pVYfJVQYP4CNOyfZLW9/LTuhd8vuUKoK7TdDou1b/Jt4TqEr /Tnkz39JjpNPJNc/uVC/EpbiC2zsqHhYaIGBQiBpxKkKRMjKFkmbFX9imZKhYSysKBwr hsi3c8x+iBzjrHyJpL9Asr5PZHi2cxEWhic0IQXDlX4zDC2uejzCZty+Z4TepL7R8zo7 dqNQ== X-Gm-Message-State: AOJu0YzwpMEg4ZacF7xv820ctG4Gx0wVkUvhMYgIwDd0x5yfAW5+nwq6 rhAhq+bJM7JDaMQpG+4wbIiWv8DGOsHvBcaWwBj5g7lr0p4Z3sj6cg4UvR5umGpZuRM1LPYU75B Q X-Gm-Gg: ASbGncuTun+yc4LS3fCPL5EvUd7TlHKteAYl2hELB/DsEPOr8inyQHqPA4GNYsmSEyX X/5+8Ev2wcbnzEkwV2ZDQ1Uq1KMaUBMXGl82THbnFTG0ArPcY3tIpqmFUgz/QF5NnTrQfjr369E vu59PuOrHwJThYzLO8OC2qBg2LPq0qfrTVLUL7CfwdvRCzAbl4lAxjVwhN44oK2xc1ZOw2b7hrF goI+kfgvkDB2l9Av+c47Ah8LWCcZkHFkwXlLUx41lranpGnWxjaBpAvnrNpIfxmkC2Kl277MMx3 5JW5tlhj+MyuT+oZSSrqONMtDuR1a67x/enH0yZc0HqTmMj83W3c7ysD0628iW9i9enT+mwyD1C 6yaJltuRz8UpR7Hx4WPNeNTZ3mw3as8QY/kM= X-Google-Smtp-Source: AGHT+IHJeig6XKx1mZLIYAkmxZM50KoC+sSdVL1mdtxT6pvzyEIo206N6nkuZ4wQiNlGlloNUbImfA== X-Received: by 2002:a05:600c:1d88:b0:43d:7a:471f with SMTP id 5b1f17b1804b1-43ecf8ece15mr7175675e9.18.1743717959450; Thu, 03 Apr 2025 15:05:59 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier Subject: [PATCH-for-10.1 v3 19/19] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Date: Fri, 4 Apr 2025 00:04:19 +0200 Message-ID: <20250403220420.78937-20-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250403220420.78937-1-philmd@linaro.org> References: <20250403220420.78937-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743718156782019000 Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition, have each target set the 'mttcg_supported' field in the TCGCPUOps structure. Since so far we only emulate one target architecture at a time, tcg_init_machine() gets whether MTTCG is supported via the current CPU class (CPU_RESOLVING_TYPE). Since TARGET_SUPPORTS_MTTCG isn't available anymore, instead of emiting a warning when the 'thread' property is set in tcg_set_thread(), emit it in tcg_init_machine() where it is consumed. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- docs/devel/multi-thread-tcg.rst | 2 +- configs/targets/aarch64-softmmu.mak | 1 - configs/targets/alpha-softmmu.mak | 1 - configs/targets/arm-softmmu.mak | 1 - configs/targets/hppa-softmmu.mak | 1 - configs/targets/i386-softmmu.mak | 1 - configs/targets/loongarch64-softmmu.mak | 1 - configs/targets/microblaze-softmmu.mak | 1 - configs/targets/microblazeel-softmmu.mak | 1 - configs/targets/mips-softmmu.mak | 1 - configs/targets/mipsel-softmmu.mak | 1 - configs/targets/or1k-softmmu.mak | 1 - configs/targets/ppc64-softmmu.mak | 1 - configs/targets/riscv32-softmmu.mak | 1 - configs/targets/riscv64-softmmu.mak | 1 - configs/targets/s390x-softmmu.mak | 1 - configs/targets/sparc-softmmu.mak | 1 - configs/targets/sparc64-softmmu.mak | 1 - configs/targets/x86_64-softmmu.mak | 1 - configs/targets/xtensa-softmmu.mak | 1 - configs/targets/xtensaeb-softmmu.mak | 1 - include/accel/tcg/cpu-ops.h | 8 ++++++++ include/exec/poison.h | 1 - accel/tcg/tcg-all.c | 17 ++++++++--------- target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 1 + target/riscv/tcg/tcg-cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 44 files changed, 37 insertions(+), 31 deletions(-) diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.= rst index 14a2a9dc7b5..da9a1530c9f 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -30,7 +30,7 @@ user-space thread. This is enabled by default for all FE/= BE combinations where the host memory model is able to accommodate the guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is z= ero) and the guest has had the required work done to support this safely -(TARGET_SUPPORTS_MTTCG). +(TCGCPUOps::mttcg_supported). =20 System emulation will fall back to the original round robin approach if: diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-= softmmu.mak index 82cb72cb83d..5dfeb35af90 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sy= sregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-prof= ile-mve.xml gdb-xml/aarch64-pauth.xml # needed by boot.c diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-soft= mmu.mak index 89f3517aca0..5275076e50d 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dalpha -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.= mak index afc64f5927b..6a5a8eda949 100644 --- a/configs/targets/arm-softmmu.mak +++ b/configs/targets/arm-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Darm -TARGET_SUPPORTS_MTTCG=3Dy TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-prof= ile.xml gdb-xml/arm-m-profile-mve.xml # needed by boot.c TARGET_NEED_FDT=3Dy diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmm= u.mak index 63ca74ed5e6..ea331107a08 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dhppa TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmm= u.mak index 5dd89217560..e9d89e8ab41 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Di386 -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy TARGET_XML_FILES=3D gdb-xml/i386-32bit.xml diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loon= garch64-softmmu.mak index 351341132f6..fc44c54233d 100644 --- a/configs/targets/loongarch64-softmmu.mak +++ b/configs/targets/loongarch64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=3Dloongarch64 TARGET_BASE_ARCH=3Dloongarch TARGET_KVM_HAVE_GUEST_DEBUG=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_XML_FILES=3D gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.= xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-l= asx.xml # all boards require libfdt TARGET_NEED_FDT=3Dy diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/micro= blaze-softmmu.mak index 99a33ed44a8..23457d0ae65 100644 --- a/configs/targets/microblaze-softmmu.mak +++ b/configs/targets/microblaze-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Dmicroblaze TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3Dgdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-pr= otect.xml diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/mic= roblazeel-softmmu.mak index 52cdeae1a28..c82c509623d 100644 --- a/configs/targets/microblazeel-softmmu.mak +++ b/configs/targets/microblazeel-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dmicroblaze -TARGET_SUPPORTS_MTTCG=3Dy # needed by boot.c TARGET_NEED_FDT=3Dy TARGET_XML_FILES=3Dgdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-pr= otect.xml diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmm= u.mak index b62a0882499..c9588066b8d 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dmips TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-so= ftmmu.mak index 620ec681785..90e09bdc3e5 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dmips -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmm= u.mak index adfddb1a8ac..0e47d9878b0 100644 --- a/configs/targets/or1k-softmmu.mak +++ b/configs/targets/or1k-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dopenrisc -TARGET_SUPPORTS_MTTCG=3Dy TARGET_BIG_ENDIAN=3Dy # needed by boot.c and all boards TARGET_NEED_FDT=3Dy diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-soft= mmu.mak index 7cee0e97f43..74572864b36 100644 --- a/configs/targets/ppc64-softmmu.mak +++ b/configs/targets/ppc64-softmmu.mak @@ -1,7 +1,6 @@ TARGET_ARCH=3Dppc64 TARGET_BASE_ARCH=3Dppc TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml= /power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml # all boards require libfdt diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-= softmmu.mak index c828066ce6b..db55275b868 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Driscv32 TARGET_BASE_ARCH=3Driscv -TARGET_SUPPORTS_MTTCG=3Dy TARGET_XML_FILES=3D gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c TARGET_NEED_FDT=3Dy diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-= softmmu.mak index 09f613d24a0..2bdd4a62cd2 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv= -32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml # needed by boot.c diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-soft= mmu.mak index 5242ebe7c2e..76dd5de6584 100644 --- a/configs/targets/s390x-softmmu.mak +++ b/configs/targets/s390x-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Ds390x TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_XML_FILES=3D gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/= s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml = gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml TARGET_LONG_BITS=3D64 diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-soft= mmu.mak index 78c2e25bd13..57801faf1fc 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-= softmmu.mak index f7bab97a002..2504e31ae33 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dsparc64 TARGET_BASE_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D64 diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-so= ftmmu.mak index 1ceefde1313..5619b2bc686 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Dx86_64 TARGET_BASE_ARCH=3Di386 -TARGET_SUPPORTS_MTTCG=3Dy TARGET_KVM_HAVE_GUEST_DEBUG=3Dy TARGET_KVM_HAVE_RESET_PARKED_VCPU=3Dy TARGET_XML_FILES=3D gdb-xml/i386-64bit.xml diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-so= ftmmu.mak index 65845df4ffa..2a9797338a6 100644 --- a/configs/targets/xtensa-softmmu.mak +++ b/configs/targets/xtensa-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dxtensa -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/configs/targets/xtensaeb-softmmu.mak b/configs/targets/xtensae= b-softmmu.mak index f1f789d6971..5204729af8b 100644 --- a/configs/targets/xtensaeb-softmmu.mak +++ b/configs/targets/xtensaeb-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dxtensa TARGET_BIG_ENDIAN=3Dy -TARGET_SUPPORTS_MTTCG=3Dy TARGET_LONG_BITS=3D32 diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index a4932fc5d7c..0e4352513d1 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -19,6 +19,14 @@ #include "tcg/tcg-mo.h" =20 struct TCGCPUOps { + /** + * mttcg_supported: multi-threaded TCG is supported + * + * Target (TCG frontend) supports: + * - atomic instructions + * - memory ordering primitives (barriers) + */ + bool mttcg_supported; =20 /** * @guest_default_memory_order: default barrier that is required diff --git a/include/exec/poison.h b/include/exec/poison.h index a09e0c12631..bc422719d80 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,7 +35,6 @@ =20 #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME -#pragma GCC poison TARGET_SUPPORTS_MTTCG #pragma GCC poison TARGET_BIG_ENDIAN #pragma GCC poison TCG_GUEST_DEFAULT_MO #pragma GCC poison TARGET_HAS_PRECISE_SMC diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 267830658ca..bf27c5c0fb3 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -41,8 +41,10 @@ #include "hw/boards.h" #include "system/tcg.h" #endif +#include "accel/tcg/cpu-ops.h" #include "internal-common.h" #include "cpu-param.h" +#include "cpu.h" =20 =20 struct TCGState { @@ -71,11 +73,8 @@ bool qemu_tcg_mttcg_enabled(void) =20 static void mttcg_init(TCGState *s) { -#ifdef TARGET_SUPPORTS_MTTCG - bool mttcg_supported =3D true; -#else - bool mttcg_supported =3D false; -#endif + CPUClass *cc =3D CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE)); + bool mttcg_supported =3D cc->tcg_ops->mttcg_supported; =20 if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_AUTO) { /* @@ -96,6 +95,10 @@ static void mttcg_init(TCGState *s) s->mttcg_enabled =3D mttcg_supported; } } + if (s->mttcg_enabled =3D=3D ON_OFF_AUTO_ON && !mttcg_supported) { + warn_report("Guest not yet converted to MTTCG - " + "you may get unexpected results"); + } mttcg_enabled =3D s->mttcg_enabled; } =20 @@ -162,10 +165,6 @@ static void tcg_set_thread(Object *obj, const char *va= lue, Error **errp) if (icount_enabled()) { error_setg(errp, "No MTTCG when icount is enabled"); } else { -#ifndef TARGET_SUPPORTS_MTTCG - warn_report("Guest not yet converted to MTTCG - " - "you may get unexpected results"); -#endif s->mttcg_enabled =3D ON_OFF_AUTO_ON; } } else if (strcmp(value, "single") =3D=3D 0) { diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index eeaf3a81c1a..851a3d10d59 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -235,6 +235,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps alpha_tcg_ops =3D { + .mttcg_supported =3D true, /* Alpha processors have a weak memory model */ .guest_default_memory_order =3D 0, =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3e9760b5518..377791c84dd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2671,6 +2671,7 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { =20 #ifdef CONFIG_TCG static const TCGCPUOps arm_tcg_ops =3D { + .mttcg_supported =3D true, /* ARM processors have a weak memory model */ .guest_default_memory_order =3D 0, =20 diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 89d4e4b4a2f..85d8db87f9b 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -232,6 +232,7 @@ static void cortex_m55_initfn(Object *obj) } =20 static const TCGCPUOps arm_v7m_tcg_ops =3D { + .mttcg_supported =3D true, /* ARM processors have a weak memory model */ .guest_default_memory_order =3D 0, =20 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8f79cf4c08b..064ee3ec3f1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -224,6 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps avr_tcg_ops =3D { + .mttcg_supported =3D false, .guest_default_memory_order =3D 0, .initialize =3D avr_cpu_tcg_init, .translate_code =3D avr_cpu_translate_code, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 3d14e5cc6a0..a8293749f3f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -325,6 +325,7 @@ static void hexagon_cpu_init(Object *obj) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hexagon_tcg_ops =3D { + .mttcg_supported =3D false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, .initialize =3D hexagon_translate_init, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index dfbd9330565..1bfd2a402a9 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,6 +253,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps hppa_tcg_ops =3D { + .mttcg_supported =3D true, /* PA-RISC 1.x processors have a strong memory model. */ /* * ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d941df09560..a0258f4739e 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps x86_tcg_ops =3D { + .mttcg_supported =3D true, /* * The x86 has a strong memory model with some store-after-load re-ord= ering */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index f5b8ef29ab0..19151651ae0 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -864,6 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps loongarch_tcg_ops =3D { + .mttcg_supported =3D true, .guest_default_memory_order =3D 0, =20 .initialize =3D loongarch_translate_init, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b2d8c8f1dea..2fda167b73e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -589,6 +589,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps m68k_tcg_ops =3D { + .mttcg_supported =3D false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4efba0dddb2..65c461265fb 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -427,6 +427,7 @@ static const struct SysemuCPUOps mb_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps mb_tcg_ops =3D { + .mttcg_supported =3D true, /* MicroBlaze is always in-order. */ .guest_default_memory_order =3D TCG_MO_ALL, =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 010773405a8..77bdb6db887 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -550,6 +550,7 @@ static const Property mips_cpu_properties[] =3D { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" static const TCGCPUOps mips_tcg_ops =3D { + .mttcg_supported =3D TARGET_LONG_BITS =3D=3D 32, .guest_default_memory_order =3D 0, =20 .initialize =3D mips_tcg_init, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 87fe779042c..51df212bd6b 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -243,6 +243,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps openrisc_tcg_ops =3D { + .mttcg_supported =3D true, .guest_default_memory_order =3D 0, =20 .initialize =3D openrisc_translate_init, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 8300fa5777e..f95c731c97f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7478,6 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps ppc_tcg_ops =3D { + .mttcg_supported =3D TARGET_LONG_BITS =3D=3D 64, .guest_default_memory_order =3D 0, .initialize =3D ppc_translate_init, .translate_code =3D ppc_translate_code, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 88f7cdb887c..3afbae9733b 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -141,6 +141,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } =20 static const TCGCPUOps riscv_tcg_ops =3D { + .mttcg_supported =3D true, .guest_default_memory_order =3D 0, =20 .initialize =3D riscv_translate_init, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index f073fe8fc98..654bf7ae5b2 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,6 +204,7 @@ static const struct SysemuCPUOps rx_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps rx_tcg_ops =3D { + .mttcg_supported =3D false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 1e101b5afeb..41cccc1e692 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -345,6 +345,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, } =20 static const TCGCPUOps s390_tcg_ops =3D { + .mttcg_supported =3D true, /* * The z/Architecture has a strong memory model with some * store-after-load re-ordering. diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 7a05301c6ff..e20e49fca8a 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,6 +262,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps superh_tcg_ops =3D { + .mttcg_supported =3D false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 56d9417ae3f..f6b3c0f129a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1001,6 +1001,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps sparc_tcg_ops =3D { + .mttcg_supported =3D true, /* * From Oracle SPARC Architecture 2015: * diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index c68954b4096..258f55a566f 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -172,6 +172,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops =3D= { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps tricore_tcg_ops =3D { + .mttcg_supported =3D false, /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, .initialize =3D tricore_tcg_init, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 2cbf4e30108..3f00e8e4239 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -232,6 +232,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops =3D { #include "accel/tcg/cpu-ops.h" =20 static const TCGCPUOps xtensa_tcg_ops =3D { + .mttcg_supported =3D true, /* Xtensa processors have a weak memory model */ .guest_default_memory_order =3D 0, =20 --=20 2.47.1