From nobody Sat Apr 5 15:03:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1743515842; cv=none; d=zohomail.com; s=zohoarc; b=h+1ikVBdLIhU149kddatkI6w2dhjn2zyYlPhl8q4q4xhXLdXGMxXRDDVX8EqW20S22gqW5bxVk8LwNY4IHguiR8xFyAPKw7jfwBx7CfF6UD7poNuiXLaareHaOfR0tmYFJHDqpWFSdBVBMfK8D/eLL2FO7SHuyMoCZMc+MWta90= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743515842; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cy1wawduOgy/K084rlWKYtg7gekj8ccbJvdpxSfqf3o=; b=XxJ3oCGf21AwJBVp1HstVbVxTeb05bdWAtLAoZgxl+yMSSigKoewjqCntK7Y50YwkbSYmu9cnpk1YPzVSL/AgoS3C/jiD5CLBKHLhWGBBmFFgyfCyTyzO5VH2YQKDwfc7vJDJP70qF2B3ntXY3Ax/gJlfQA7dBltlE365oAGgPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743515842703516.8629019629959; Tue, 1 Apr 2025 06:57:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tzbz5-0006YU-8Q; Tue, 01 Apr 2025 09:48:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tzbvB-0001aj-Ii for qemu-devel@nongnu.org; Tue, 01 Apr 2025 09:44:56 -0400 Received: from mgamail.intel.com ([192.198.163.16]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tzbv9-0006XQ-Ju for qemu-devel@nongnu.org; Tue, 01 Apr 2025 09:44:53 -0400 Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2025 06:43:20 -0700 Received: from lxy-clx-4s.sh.intel.com ([10.239.48.52]) by fmviesa008.fm.intel.com with ESMTP; 01 Apr 2025 06:43:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743515091; x=1775051091; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AcHHhoVG9se9MbdT2EDS9uPRBBoFYbEBeDYXAlLrBrg=; b=cKXNLKALVHC0KeDh5xsYzAyPtGOC+yTmCZ3BF4P3ddnvV3Us60w/cTri MQSyGpvd+gQDatBK3u2SSYLD7t2vZoA2ZSlcZOy5latU1Tg21wFedGbAj UIXtzT1uM13O5TzOGK+Jfo+hqbGb0ymq1sAWDouvWD/v/irHnZuX0YBq5 Dqm9m77b8oalyFWMqedb+XayQNPnTubgsAv0jnz4NLdFLtGx0Qkciy1bD TrNhuuvISysXjcV9aT2TMGfpDQyhwitdT2jXpQkUGLby7TnlYq3Ds1P5B v88pqNKB66c8yzF1jAMdUXkitfcDiSIHqlRDUXMFNdIkzb0SfzVDnjI6k w==; X-CSE-ConnectionGUID: OWqSvCoXT4iCcJmM5sBQWA== X-CSE-MsgGUID: RyNb2gLlSnGizx4QgUP3BA== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="32433583" X-IronPort-AV: E=Sophos;i="6.14,293,1736841600"; d="scan'208";a="32433583" X-CSE-ConnectionGUID: bLObRQfcSHK7Jyt7ZjG1hw== X-CSE-MsgGUID: VqFJBFAkT+2Fz68AuMw+xw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,293,1736841600"; d="scan'208";a="126640277" From: Xiaoyao Li To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Cc: "Michael S. Tsirkin" , Markus Armbruster , Francesco Lavra , Marcelo Tosatti , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Rick Edgecombe , Xiaoyao Li Subject: [PATCH v8 51/55] i386/tdx: Fetch and validate CPUID of TD guest Date: Tue, 1 Apr 2025 09:02:01 -0400 Message-Id: <20250401130205.2198253-52-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250401130205.2198253-1-xiaoyao.li@intel.com> References: <20250401130205.2198253-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.16; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.997, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1743515845210019100 Content-Type: text/plain; charset="utf-8" Use KVM_TDX_GET_CPUID to get the CPUIDs that are managed and enfored by TDX module for TD guest. Check QEMU's configuration against the fetched data. Print wanring message when 1. a feature is not supported but requested by QEMU or 2. QEMU doesn't want to expose a feature while it is enforced enabled. - If cpu->enforced_cpuid is not set, prints the warning message of both 1) and 2) and tweak QEMU's configuration. - If cpu->enforced_cpuid is set, quit if any case of 1) or 2). Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 33 ++++++++++++++- target/i386/cpu.h | 7 +++ target/i386/kvm/tdx.c | 99 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 137 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f09a1caac071..41407c8a7248 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5772,8 +5772,8 @@ static bool x86_cpu_have_filtered_features(X86CPU *cp= u) return false; } =20 -static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t= mask, - const char *verbose_prefix) +void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, + const char *verbose_prefix) { CPUX86State *env =3D &cpu->env; FeatureWordInfo *f =3D &feature_word_info[w]; @@ -5800,6 +5800,35 @@ static void mark_unavailable_features(X86CPU *cpu, F= eatureWord w, uint64_t mask, } } =20 +void mark_forced_on_features(X86CPU *cpu, FeatureWord w, uint64_t mask, + const char *verbose_prefix) +{ + CPUX86State *env =3D &cpu->env; + FeatureWordInfo *f =3D &feature_word_info[w]; + int i; + + if (!cpu->force_features) { + env->features[w] |=3D mask; + } + + cpu->forced_on_features[w] |=3D mask; + + if (!verbose_prefix) { + return; + } + + for (i =3D 0; i < 64; ++i) { + if ((1ULL << i) & mask) { + g_autofree char *feat_word_str =3D feature_word_description(f); + warn_report("%s: %s%s%s [bit %d]", + verbose_prefix, + feat_word_str, + f->feat_names[i] ? "." : "", + f->feat_names[i] ? f->feat_names[i] : "", i); + } + } +} + static void x86_cpuid_version_get_family(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a223e09a25c4..1600e826f372 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2227,6 +2227,9 @@ struct ArchCPU { /* Features that were filtered out because of missing host capabilitie= s */ FeatureWordArray filtered_features; =20 + /* Features that are forced enabled by underlying hypervisor, e.g., TD= X */ + FeatureWordArray forced_on_features; + /* Enable PMU CPUID bits. This can't be enabled by default yet because * it doesn't have ABI stability guarantees, as it passes all PMU CPUID * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and k= ernel @@ -2539,6 +2542,10 @@ void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); bool cpu_has_x2apic_feature(CPUX86State *env); bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg); +void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, + const char *verbose_prefix); +void mark_forced_on_features(X86CPU *cpu, FeatureWord w, uint64_t mask, + const char *verbose_prefix); =20 static inline bool x86_has_cpuid_0x1f(X86CPU *cpu) { diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 7382b53fcc51..58797470ba7e 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -764,6 +764,104 @@ static uint32_t tdx_adjust_cpuid_features(X86Confiden= tialGuest *cg, return value; } =20 +static struct kvm_cpuid2 *tdx_fetch_cpuid(CPUState *cpu) +{ + struct kvm_cpuid2 *fetch_cpuid; + int size =3D KVM_MAX_CPUID_ENTRIES; + Error *local_err =3D NULL; + int r; + + do { + error_free(local_err); + local_err =3D NULL; + + fetch_cpuid =3D g_malloc0(sizeof(*fetch_cpuid) + + sizeof(struct kvm_cpuid_entry2) * size); + fetch_cpuid->nent =3D size; + r =3D tdx_vcpu_ioctl(cpu, KVM_TDX_GET_CPUID, 0, fetch_cpuid, &loca= l_err); + if (r =3D=3D -E2BIG) { + g_free(fetch_cpuid); + size =3D fetch_cpuid->nent; + } + } while (r =3D=3D -E2BIG); + + if (r < 0) { + error_report_err(local_err); + return NULL; + } + + return fetch_cpuid; +} + +static int tdx_check_features(X86ConfidentialGuest *cg, CPUState *cs) +{ + uint64_t actual, requested, unavailable, forced_on; + g_autofree struct kvm_cpuid2 *fetch_cpuid; + const char *forced_on_prefix =3D NULL; + const char *unav_prefix =3D NULL; + struct kvm_cpuid_entry2 *entry; + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + FeatureWordInfo *wi; + FeatureWord w; + bool mismatch =3D false; + + fetch_cpuid =3D tdx_fetch_cpuid(cs); + if (!fetch_cpuid) { + return -1; + } + + if (cpu->check_cpuid || cpu->enforce_cpuid) { + unav_prefix =3D "TDX doesn't support requested feature"; + forced_on_prefix =3D "TDX forcibly sets the feature"; + } + + for (w =3D 0; w < FEATURE_WORDS; w++) { + wi =3D &feature_word_info[w]; + actual =3D 0; + + switch (wi->type) { + case CPUID_FEATURE_WORD: + entry =3D cpuid_find_entry(fetch_cpuid, wi->cpuid.eax, wi->cpu= id.ecx); + if (!entry) { + /* + * If KVM doesn't report it means it's totally configurable + * by QEMU + */ + continue; + } + + actual =3D cpuid_entry_get_reg(entry, wi->cpuid.reg); + break; + case MSR_FEATURE_WORD: + /* + * TODO: + * validate MSR features when KVM has interface report them. + */ + continue; + } + + requested =3D env->features[w]; + unavailable =3D requested & ~actual; + mark_unavailable_features(cpu, w, unavailable, unav_prefix); + if (unavailable) { + mismatch =3D true; + } + + forced_on =3D actual & ~requested; + mark_forced_on_features(cpu, w, forced_on, forced_on_prefix); + if (forced_on) { + mismatch =3D true; + } + } + + if (cpu->enforce_cpuid && mismatch) { + return -1; + } + + return 0; +} + static int tdx_validate_attributes(TdxGuest *tdx, Error **errp) { if ((tdx->attributes & ~tdx_caps->supported_attrs)) { @@ -1147,4 +1245,5 @@ static void tdx_guest_class_init(ObjectClass *oc, voi= d *data) x86_klass->kvm_type =3D tdx_kvm_type; x86_klass->cpu_instance_init =3D tdx_cpu_instance_init; x86_klass->adjust_cpuid_features =3D tdx_adjust_cpuid_features; + x86_klass->check_features =3D tdx_check_features; } --=20 2.34.1