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From: Xiaoyao Li <xiaoyao.li@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
=?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= <berrange@redhat.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
Markus Armbruster <armbru@redhat.com>,
Francesco Lavra <francescolavra.fl@gmail.com>,
Marcelo Tosatti <mtosatti@redhat.com>, qemu-devel@nongnu.org,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
Rick Edgecombe <rick.p.edgecombe@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>
Subject: [PATCH v8 47/55] i386/tdx: Add supported CPUID bits relates to XFAM
Date: Tue, 1 Apr 2025 09:01:57 -0400
Message-Id: <20250401130205.2198253-48-xiaoyao.li@intel.com>
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Some CPUID bits are controlled by XFAM. They are not covered by
tdx_caps.cpuid (which only contians the directly configurable bits), but
they are actually supported when the related XFAM bit is supported.
Add these XFAM controlled bits to TDX supported CPUID bits based on the
supported_xfam.
Besides, incorporate the supported_xfam into the supported CPUID leaf of
0xD.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
target/i386/cpu.c | 12 -------
target/i386/cpu.h | 16 ++++++++++
target/i386/kvm/tdx.c | 73 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+), 12 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4061d38d3fbe..f09a1caac071 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1673,15 +1673,6 @@ bool is_feature_word_cpuid(uint32_t feature, uint32_=
t index, int reg)
return false;
}
=20
-typedef struct FeatureMask {
- FeatureWord index;
- uint64_t mask;
-} FeatureMask;
-
-typedef struct FeatureDep {
- FeatureMask from, to;
-} FeatureDep;
-
static FeatureDep feature_dependencies[] =3D {
{
.from =3D { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILIT=
IES },
@@ -1850,9 +1841,6 @@ static const X86RegisterInfo32 x86_reg_info_32[CPU_NB=
_REGS32] =3D {
};
#undef REGISTER
=20
-/* CPUID feature bits available in XSS */
-#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
-
ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] =3D {
[XSTATE_FP_BIT] =3D {
/* x87 FP state component is always enabled if XSAVE is supported =
*/
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 0e984ec42bb6..132312d70a54 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -588,6 +588,7 @@ typedef enum X86Seg {
#define XSTATE_OPMASK_BIT 5
#define XSTATE_ZMM_Hi256_BIT 6
#define XSTATE_Hi16_ZMM_BIT 7
+#define XSTATE_PT_BIT 8
#define XSTATE_PKRU_BIT 9
#define XSTATE_ARCH_LBR_BIT 15
#define XSTATE_XTILE_CFG_BIT 17
@@ -601,6 +602,7 @@ typedef enum X86Seg {
#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
+#define XSTATE_PT_MASK (1ULL << XSTATE_PT_BIT)
#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
#define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
#define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
@@ -623,6 +625,11 @@ typedef enum X86Seg {
XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK |=
\
XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA=
_MASK)
=20
+/* CPUID feature bits available in XSS */
+#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
+
+#define CPUID_XSTATE_MASK (CPUID_XSTATE_XCR0_MASK | CPUID_XSTATE_XSS=
_MASK)
+
/* CPUID feature words */
typedef enum FeatureWord {
FEAT_1_EDX, /* CPUID[1].EDX */
@@ -671,6 +678,15 @@ typedef enum FeatureWord {
FEATURE_WORDS,
} FeatureWord;
=20
+typedef struct FeatureMask {
+ FeatureWord index;
+ uint64_t mask;
+} FeatureMask;
+
+typedef struct FeatureDep {
+ FeatureMask from, to;
+} FeatureDep;
+
typedef uint64_t FeatureWordArray[FEATURE_WORDS];
uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
=20
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index 5d72f1814606..c7b4a098d12f 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i386/kvm/tdx.c
@@ -23,6 +23,8 @@
=20
#include <linux/kvm_para.h>
=20
+#include "cpu.h"
+#include "cpu-internal.h"
#include "hw/i386/e820_memory_layout.h"
#include "hw/i386/tdvf.h"
#include "hw/i386/x86.h"
@@ -485,6 +487,32 @@ static TdxAttrsMap tdx_attrs_maps[] =3D {
},
};
=20
+typedef struct TdxXFAMDep {
+ int xfam_bit;
+ FeatureMask feat_mask;
+} TdxXFAMDep;
+
+/*
+ * Note, only the CPUID bits whose virtualization type are "XFAM & Native"=
are
+ * defiend here.
+ *
+ * For those whose virtualization type are "XFAM & Configured & Native", t=
hey
+ * are reported as configurable bits. And they are not supported if not in=
the
+ * configureable bits list from KVM even if the corresponding XFAM bit is
+ * supported.
+ */
+TdxXFAMDep tdx_xfam_deps[] =3D {
+ { XSTATE_YMM_BIT, { FEAT_1_ECX, CPUID_EXT_FMA }},
+ { XSTATE_YMM_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX2 }},
+ { XSTATE_OPMASK_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_AVX512_VBMI}},
+ { XSTATE_OPMASK_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AVX512_FP16}},
+ { XSTATE_PT_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT}},
+ { XSTATE_PKRU_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_PKU}},
+ { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_BF16 }},
+ { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }},
+ { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_INT8 }},
+};
+
static struct kvm_cpuid_entry2 *find_in_supported_entry(uint32_t function,
uint32_t index)
{
@@ -552,6 +580,50 @@ static void tdx_add_supported_cpuid_by_attrs(void)
}
}
=20
+static void tdx_add_supported_cpuid_by_xfam(void)
+{
+ struct kvm_cpuid_entry2 *e;
+ int i;
+
+ const TdxXFAMDep *xfam_dep;
+ const FeatureWordInfo *f;
+ for (i =3D 0; i < ARRAY_SIZE(tdx_xfam_deps); i++) {
+ xfam_dep =3D &tdx_xfam_deps[i];
+ if (!((1ULL << xfam_dep->xfam_bit) & tdx_caps->supported_xfam)) {
+ continue;
+ }
+
+ f =3D &feature_word_info[xfam_dep->feat_mask.index];
+ if (f->type !=3D CPUID_FEATURE_WORD) {
+ continue;
+ }
+
+ e =3D find_in_supported_entry(f->cpuid.eax, f->cpuid.ecx);
+ switch(f->cpuid.reg) {
+ case R_EAX:
+ e->eax |=3D xfam_dep->feat_mask.mask;
+ break;
+ case R_EBX:
+ e->ebx |=3D xfam_dep->feat_mask.mask;
+ break;
+ case R_ECX:
+ e->ecx |=3D xfam_dep->feat_mask.mask;
+ break;
+ case R_EDX:
+ e->edx |=3D xfam_dep->feat_mask.mask;
+ break;
+ }
+ }
+
+ e =3D find_in_supported_entry(0xd, 0);
+ e->eax |=3D (tdx_caps->supported_xfam & CPUID_XSTATE_XCR0_MASK);
+ e->edx |=3D (tdx_caps->supported_xfam & CPUID_XSTATE_XCR0_MASK) >> 32;
+
+ e =3D find_in_supported_entry(0xd, 1);
+ e->ecx |=3D (tdx_caps->supported_xfam & CPUID_XSTATE_XSS_MASK);
+ e->edx |=3D (tdx_caps->supported_xfam & CPUID_XSTATE_XSS_MASK) >> 32;
+}
+
static void tdx_setup_supported_cpuid(void)
{
if (tdx_supported_cpuid) {
@@ -567,6 +639,7 @@ static void tdx_setup_supported_cpuid(void)
=20
tdx_add_supported_cpuid_by_fixed1_bits();
tdx_add_supported_cpuid_by_attrs();
+ tdx_add_supported_cpuid_by_xfam();
}
=20
static int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp)
--=20
2.34.1