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Replace the definitions by their expanded value, making it closer to the Armv7-M Architecture Reference Manual (ARM DDI 0403E) description: The System Control Space (SCS, address range 0xE000E000 to 0xE000EFFF) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control. All accesses to the SCS are little endian. Fixes: d5d680cacc ("memory: Access MemoryRegion with endianness") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20250312104821.1012-1-philmd@linaro.org> --- hw/arm/armv7m.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 98a69846119..64009174b97 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -140,7 +140,7 @@ static MemTxResult v7m_sysreg_ns_write(void *opaque, hw= addr addr, /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; return memory_region_dispatch_write(mr, addr, value, - size_memop(size) | MO_TE, attr= s); + size_memop(size) | MO_LE, attr= s); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -160,7 +160,7 @@ static MemTxResult v7m_sysreg_ns_read(void *opaque, hwa= ddr addr, /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; return memory_region_dispatch_read(mr, addr, data, - size_memop(size) | MO_TE, attrs= ); + size_memop(size) | MO_LE, attrs= ); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -174,7 +174,7 @@ static MemTxResult v7m_sysreg_ns_read(void *opaque, hwa= ddr addr, static const MemoryRegionOps v7m_sysreg_ns_ops =3D { .read_with_attrs =3D v7m_sysreg_ns_read, .write_with_attrs =3D v7m_sysreg_ns_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static MemTxResult v7m_systick_write(void *opaque, hwaddr addr, @@ -187,7 +187,7 @@ static MemTxResult v7m_systick_write(void *opaque, hwad= dr addr, /* Direct the access to the correct systick */ mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); return memory_region_dispatch_write(mr, addr, value, - size_memop(size) | MO_TE, attrs); + size_memop(size) | MO_LE, attrs); } =20 static MemTxResult v7m_systick_read(void *opaque, hwaddr addr, @@ -199,14 +199,14 @@ static MemTxResult v7m_systick_read(void *opaque, hwa= ddr addr, =20 /* Direct the access to the correct systick */ mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_read(mr, addr, data, size_memop(size) | = MO_TE, - attrs); + return memory_region_dispatch_read(mr, addr, data, + size_memop(size) | MO_LE, attrs); } =20 static const MemoryRegionOps v7m_systick_ops =3D { .read_with_attrs =3D v7m_systick_read, .write_with_attrs =3D v7m_systick_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 /* --=20 2.47.1