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Mon, 31 Mar 2025 08:54:36 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Richard Henderson Subject: [RFC PATCH 2/3] target/ppc: define TARGET_HAS_LAZY_ICACHE Date: Tue, 1 Apr 2025 01:54:22 +1000 Message-ID: <20250331155423.619451-3-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331155423.619451-1-npiggin@gmail.com> References: <20250331155423.619451-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=npiggin@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1743436550930019000 Content-Type: text/plain; charset="utf-8" Use the new incoherent icache (incoherent TB) feature in the ppc target. Performance problems with notdirty write accesses have been encountered in two places now. One is where a large number of executable pages have been freed (typically in KVM when a guest exits) and are being cleared for reuse, most stores in a page will take the notdirty slowpath, which can cause such s slowdown that the OS reports lockups. The other case is PowerVM boot firmware which has real-mode interrupt handler code that stores to memory in the same page-sized region as interrupt handler code which causes significant slowdowns. ppc implements TARGET_HAS_LAZY_ICACHE by calling tb_flush_incoherent() from the ICBI instruction, which should conform to the ISA's CMODX (aka SMC) requirement. --- target/ppc/cpu.h | 16 ++++++++++++++++ target/ppc/mem_helper.c | 2 ++ target/ppc/translate.c | 1 + 3 files changed, 19 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 74ed28c8dac..de274d29637 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -34,6 +34,22 @@ #define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_16M 24 =20 +/* icaches are not kept coherent with dcaches. target is to call + * tb_flush_incoherent() to bring them into coherency */ +#define TARGET_HAS_LAZY_ICACHE +/* + * Note that this does not model implementation specific behaviour of all + * CPUs, notably recent Power CPUs do keep i/d coherent, and only require + * context synchronization after code modification to ensure CPU pipeline + * is coherent. The ISA and User Manuals do say that icbi (to any address)= ; + * isync should be used even for these CPUs, so tb_flush_incoherent() in + * icbi should work reasonably. The ppc target should continue to work wit= hout + * TARGET_HAS_LAZY_ICACHE, but some performance corner cases benefit (e.g., + * KVM when clearing a lot of memory freed from a guest that has a lot of = exec + * pages; PowerVM PFW/boot firmware that stores to globals in the same pag= e as + * it executes from). + */ + #if defined(TARGET_PPC64) #define PPC_ELF_MACHINE EM_PPC64 #else diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 51b137febd6..647d37195dd 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" +#include "exec/tb-flush.h" #include "internal.h" #include "qemu/atomic128.h" =20 @@ -335,6 +336,7 @@ void helper_icbi(CPUPPCState *env, target_ulong addr) * do the load "by hand". */ cpu_ldl_data_ra(env, addr, GETPC()); + tb_flush_incoherent(env_cpu(env)); } =20 void helper_icbiep(CPUPPCState *env, target_ulong addr) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7f933537aaa..5e610bf29a5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4565,6 +4565,7 @@ static void gen_dss(DisasContext *ctx) static void gen_icbi(DisasContext *ctx) { TCGv t0; + translator_io_start(&ctx->base); gen_set_access_type(ctx, ACCESS_CACHE); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); --=20 2.47.1