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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d914f1561sm82919785e9.1.2025.03.31.08.20.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 31 Mar 2025 08:20:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743434448; x=1744039248; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tHDVcIHyei1/5z2v4ais2OKqYJbZicKYgClVfwcyY94=; b=t+wR9wa7ZiGNA5yHpWw3ooleDvDbDBaT90hVLmD1vfPmw3pFkhyVlo6jcSmFum3VEP Yg6NhlXLKUT4e3FlDQBUlQvwTTifg6lmEvtWDT5EKn/nDZLEJwh5v4vICcgdPAy2YXkM vnWag8i1lIuyAvgDeDyGhyU6fCYWncbB5PTnW2cmAIj83Wi4XI2NnqZuFgI4KfMnzESj i9I0/HlXaiykjV4WjhhrIWvT3msToD5KVuvlR8N0IJjI3wsYG/ogOLvyuFi6Z3YrgOfb PEK2xxJ99sIxlEH9k6r9dNSG6hvV+UKfTL7wNccpv1u1yr0Y9A9BiRpfIUWRhBxytR+d WlYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743434448; x=1744039248; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tHDVcIHyei1/5z2v4ais2OKqYJbZicKYgClVfwcyY94=; b=UuhoFN5oWhKqnHWmwbdJfS3qHQR9YcaqYb0j+fO/slbvhIlgPv3oS+zkdZUkCJSd8J f5N+YkZx6EVSojGawjGtiEn8tjzqSmZvuKpbmw+kN2hJtxdkL8NQ6iDg5s121OAn7I5b Y3xYk79zwI+LKeA71hfhLFD+TdekJjuKSuJBX+lnckg/P5Bm0nwbXoDJBXeN1bb4rOqH 55xKefH/DLu7XoxT9JryHoyEVJaseF0M2wSUNMtlRjfBDBfpkp5DpcJlLeC5rs1Xy3wR 0XolfnKPMEdNek8Y7qTMoAf4Cuwpxg8LskQzNW91Wxatxt7f8eDmy6/FJue2qrSFd9bn 6m1w== X-Gm-Message-State: AOJu0YzS2aE5rvkMRQoOvw5AcQMs512/6ZYQjglHNXmrlXSsUm4Dxv+8 GTD2iB4VLJTcfHBxxzw0Tl105BEJYe+fm8pdgZUsKVTlA/tOxtY2LvhKcwOujKGYGlIjhqMr5nC H X-Gm-Gg: ASbGncsX3b6cZ76MaWpS0Wh/FKuRs673XF7h0jBDHvlqgDfgltYRHkOIUzVCA1AqXOo rxOaiZKeRFC6874afB5y+jGc+OzTgm4AX1uSZYmNT+8hz0ctGzuHzbvorV9YHBNOTGoOjDUp4/d IzgYduhCv9pDAicqSve/TwnV4bWvPa8ui2pnL9wqFeL3eR0L4TUoOkt6t2lfTqfaRD2hBIHQpgV OeFajHg4IV/5IVgo5zf+OZhQjrbXXZDqR5ZK9L0ZJV7VFfR+nUXsuaLy5Hzyc+MAuOqR1Qb0gyo MDqBdi0pnZ6d6258G1yl6F5k3sPl2VjNA1RXcmsRrnNFwlyZBnJpyPZ5hn5P/gNfqXrZrghN4QV PBLcEbF44YneGHEBTcPg= X-Google-Smtp-Source: AGHT+IFR8R4zvqHZ9xfh5Dx+rgNvydvh+UWi0MCgxYnxv1zzhiYEy517pjzzA0dky3IiTdIIDQBLcg== X-Received: by 2002:a05:600c:34d0:b0:43c:f5e4:895e with SMTP id 5b1f17b1804b1-43db61d7785mr73395325e9.1.1743434448530; Mon, 31 Mar 2025 08:20:48 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Gustavo Romero , Joey , qemu-arm@nongnu.org, Peter Maydell , Andrey Smirnov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org Subject: [PATCH-for-10.0 1/2] hw/pci-host/designware: Fix access to ATU_UPPER_TARGET register Date: Mon, 31 Mar 2025 17:20:40 +0200 Message-ID: <20250331152041.74533-2-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331152041.74533-1-philmd@linaro.org> References: <20250331152041.74533-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743434480104019000 Fix copy/paste error writing to the ATU_UPPER_TARGET register, we want to update the upper 32 bits. Cc: qemu-stable@nongnu.org Reported-by: Joey Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2861 Fixes: d64e5eabc4c ("pci: Add support for Designware IP block") Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Gustavo Romero --- hw/pci-host/designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index c07740bfaa4..5598d18f478 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -371,7 +371,7 @@ static void designware_pcie_root_config_write(PCIDevice= *d, uint32_t address, =20 case DESIGNWARE_PCIE_ATU_UPPER_TARGET: viewport->target &=3D 0x00000000FFFFFFFFULL; - viewport->target |=3D val; + viewport->target |=3D (uint64_t)val << 32; break; =20 case DESIGNWARE_PCIE_ATU_LIMIT: --=20 2.47.1 From nobody Fri Dec 19 19:54:40 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1743434522; cv=none; d=zohomail.com; s=zohoarc; b=TsBsrnvfWgiRltyBZ5H/Rg1hxuqgaWF+yj1dxzjfhp7NWs3cuawBHXoOOxUk6+pckPDmy3R4EVLLINORqBJgs1Ubs4pS65QEdYH39wxubtdK+rAHDjU8Q027HvZAL4Dw9Qx0yHukc9Q3lMy0RE5ULiAIf9VTJe2KhDn0ym+78CA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743434522; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hXIcLIfDAyhYrdj9+q8KiZNiZrZdeQAwoIn2YrKTzw8=; b=Gy0KzFatn/OeHSYf7kGLyrh5KJlw3/N1REj4daPEwtc+SAJP/3sg03midLd7FUZJId8t069FefIdfNZuJIjnO6m+zySo3sPDtBhM5/n79XXoOvzvAwgUF2F795h4xvqDoroKojpbd+ZgW3zYEb9Ic8TgWqrf8wzpEibzS1MsUJs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1743434522150177.34627280574557; Mon, 31 Mar 2025 08:22:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tzGwd-0007Fw-MF; Mon, 31 Mar 2025 11:20:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tzGwb-0007FA-D6 for qemu-devel@nongnu.org; Mon, 31 Mar 2025 11:20:58 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tzGwZ-0007QB-1y for qemu-devel@nongnu.org; Mon, 31 Mar 2025 11:20:57 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-43d0618746bso31586675e9.2 for ; Mon, 31 Mar 2025 08:20:54 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Gustavo Romero --- hw/pci-host/designware.c | 47 ++++++++++++++-------------------------- 1 file changed, 16 insertions(+), 31 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 5598d18f478..3f2282b2596 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -22,6 +22,7 @@ #include "qapi/error.h" #include "qemu/module.h" #include "qemu/log.h" +#include "qemu/bitops.h" #include "hw/pci/msi.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" @@ -162,11 +163,9 @@ designware_pcie_root_config_read(PCIDevice *d, uint32_= t address, int len) break; =20 case DESIGNWARE_PCIE_MSI_ADDR_LO: - val =3D root->msi.base; - break; - case DESIGNWARE_PCIE_MSI_ADDR_HI: - val =3D root->msi.base >> 32; + val =3D extract64(root->msi.base, + address =3D=3D DESIGNWARE_PCIE_MSI_ADDR_LO ? 0 : 3= 2, 32); break; =20 case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: @@ -190,19 +189,15 @@ designware_pcie_root_config_read(PCIDevice *d, uint32= _t address, int len) break; =20 case DESIGNWARE_PCIE_ATU_LOWER_BASE: - val =3D viewport->base; - break; - case DESIGNWARE_PCIE_ATU_UPPER_BASE: - val =3D viewport->base >> 32; + val =3D extract64(viewport->base, + address =3D=3D DESIGNWARE_PCIE_ATU_LOWER_BASE ? 0 = : 32, 32); break; =20 case DESIGNWARE_PCIE_ATU_LOWER_TARGET: - val =3D viewport->target; - break; - case DESIGNWARE_PCIE_ATU_UPPER_TARGET: - val =3D viewport->target >> 32; + val =3D extract64(viewport->target, + address =3D=3D DESIGNWARE_PCIE_ATU_LOWER_TARGET ? = 0 : 32, 32); break; =20 case DESIGNWARE_PCIE_ATU_LIMIT: @@ -321,14 +316,10 @@ static void designware_pcie_root_config_write(PCIDevi= ce *d, uint32_t address, break; =20 case DESIGNWARE_PCIE_MSI_ADDR_LO: - root->msi.base &=3D 0xFFFFFFFF00000000ULL; - root->msi.base |=3D val; - designware_pcie_root_update_msi_mapping(root); - break; - case DESIGNWARE_PCIE_MSI_ADDR_HI: - root->msi.base &=3D 0x00000000FFFFFFFFULL; - root->msi.base |=3D (uint64_t)val << 32; + root->msi.base =3D deposit64(root->msi.base, + address =3D=3D DESIGNWARE_PCIE_MSI_ADDR= _LO + ? 0 : 32, 32, val); designware_pcie_root_update_msi_mapping(root); break; =20 @@ -355,23 +346,17 @@ static void designware_pcie_root_config_write(PCIDevi= ce *d, uint32_t address, break; =20 case DESIGNWARE_PCIE_ATU_LOWER_BASE: - viewport->base &=3D 0xFFFFFFFF00000000ULL; - viewport->base |=3D val; - break; - case DESIGNWARE_PCIE_ATU_UPPER_BASE: - viewport->base &=3D 0x00000000FFFFFFFFULL; - viewport->base |=3D (uint64_t)val << 32; + viewport->base =3D deposit64(root->msi.base, + address =3D=3D DESIGNWARE_PCIE_ATU_LOWE= R_BASE + ? 0 : 32, 32, val); break; =20 case DESIGNWARE_PCIE_ATU_LOWER_TARGET: - viewport->target &=3D 0xFFFFFFFF00000000ULL; - viewport->target |=3D val; - break; - case DESIGNWARE_PCIE_ATU_UPPER_TARGET: - viewport->target &=3D 0x00000000FFFFFFFFULL; - viewport->target |=3D (uint64_t)val << 32; + viewport->target =3D deposit64(root->msi.base, + address =3D=3D DESIGNWARE_PCIE_ATU_LO= WER_TARGET + ? 0 : 32, 32, val); break; =20 case DESIGNWARE_PCIE_ATU_LIMIT: --=20 2.47.1