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Mon, 31 Mar 2025 05:04:10 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , Harsh Prateek Bora , qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH 1/2] target/ppc: Big-core scratch register fix Date: Mon, 31 Mar 2025 22:03:55 +1000 Message-ID: <20250331120357.584561-2-npiggin@gmail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250331120357.584561-1-npiggin@gmail.com> References: <20250331120357.584561-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1743422722362019100 Content-Type: text/plain; charset="utf-8" The per-core SCRATCH0-7 registers are shared between big cores, which was missed in the big-core implementation. It is difficult to model well with the big-core =3D=3D 2xPnvCore scheme we moved to, this fix uses the even PnvCore to store the scrach data. Also remove a stray log message that came in with the same patch that introduced patch. Fixes: c26504afd5f5c ("ppc/pnv: Add a big-core mode that joins two regular = cores") Cc: qemu-stable@nongnu.org Signed-off-by: Nicholas Piggin --- target/ppc/misc_helper.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 2d9512c116b..46ae454afd3 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -332,6 +332,10 @@ target_ulong helper_load_sprd(CPUPPCState *env) PnvCore *pc =3D pnv_cpu_state(cpu)->pnv_core; target_ulong sprc =3D env->spr[SPR_POWER_SPRC]; =20 + if (pc->big_core) { + pc =3D pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); + } + switch (sprc & 0x3e0) { case 0: /* SCRATCH0-3 */ case 1: /* SCRATCH4-7 */ @@ -368,6 +372,10 @@ void helper_store_sprd(CPUPPCState *env, target_ulong = val) PnvCore *pc =3D pnv_cpu_state(cpu)->pnv_core; int nr; =20 + if (pc->big_core) { + pc =3D pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); + } + switch (sprc & 0x3e0) { case 0: /* SCRATCH0-3 */ case 1: /* SCRATCH4-7 */ @@ -378,7 +386,6 @@ void helper_store_sprd(CPUPPCState *env, target_ulong v= al) * information. Could also dump these upon checkstop. */ nr =3D (sprc >> 3) & 0x7; - qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr); pc->scratch[nr] =3D val; break; default: --=20 2.47.1