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Mon, 31 Mar 2025 01:34:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=26biS eKyClnKK7tVS05KxYECIm8bQH64xTAw4ai6yEU=; b=AMP5BHPd/PsMMkVDhV612 YxuLbL38tNVM9mGC6uI2lDBSiim8QOAM2bqTfc46ySp+ctE/0GtRZIcJ8EJPemLP NYYDpZRihYdPcL+OXZ9sQVXOIk1+jY99MYdXNwVwslO9KK5ZgMzbMA4hKyUXjDdt K5/2BzW/zIYmxJMihUIsgJY8w3Ow/LrnX47ycDyQYDBb7IV93fa6TSIOc/blwtc5 IJwNHcuKsdgGZljd2K0zViGQWw4dSRdbBHiJobeQdEPeeKmJII56C4KWZlIpsFGZ vFxEn8uxQb1BpyDKi1Aqmj5ZWrue9C146korwTOZ3y7+4reNob/mqhJmL51loQel A== From: Dongli Zhang To: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: pbonzini@redhat.com, zhao1.liu@intel.com, mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com, likexu@tencent.com, like.xu.linux@gmail.com, groug@kaod.org, khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com, den@virtuozzo.com, davydov-max@yandex-team.ru, xiaoyao.li@intel.com, dapeng1.mi@linux.intel.com, joe.jin@oracle.com, peter.maydell@linaro.org, gaosong@loongson.cn, chenhuacai@kernel.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, arikalo@gmail.com, npiggin@gmail.com, danielhb413@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, pasic@linux.ibm.com, borntraeger@linux.ibm.com, richard.henderson@linaro.org, david@redhat.com, iii@linux.ibm.com, thuth@redhat.com, flavra@baylibre.com, ewanhai-oc@zhaoxin.com, ewanhai@zhaoxin.com, cobechen@zhaoxin.com, louisqi@zhaoxin.com, liamni@zhaoxin.com, frankzhu@zhaoxin.com, silviazhao@zhaoxin.com Subject: [PATCH v3 01/10] target/i386: disable PerfMonV2 when PERFCORE unavailable Date: Sun, 30 Mar 2025 18:32:20 -0700 Message-ID: <20250331013307.11937-2-dongli.zhang@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250331013307.11937-1-dongli.zhang@oracle.com> References: <20250331013307.11937-1-dongli.zhang@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-30_11,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2502280000 definitions=main-2503310009 X-Proofpoint-ORIG-GUID: fdBXOwDorZHqc51qL0PWU8uJIpssxPRs X-Proofpoint-GUID: fdBXOwDorZHqc51qL0PWU8uJIpssxPRs Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" When the PERFCORE is disabled with "-cpu host,-perfctr-core", it is reflected in in guest dmesg. [ 0.285136] Performance Events: AMD PMU driver. However, the guest CPUID indicates the PerfMonV2 is still available. CPU: Extended Performance Monitoring and Debugging (0x80000022): AMD performance monitoring V2 =3D true AMD LBR V2 =3D false AMD LBR stack & PMC freezing =3D false number of core perf ctrs =3D 0x6 (6) number of LBR stack entries =3D 0x0 (0) number of avail Northbridge perf ctrs =3D 0x0 (0) number of available UMC PMCs =3D 0x0 (0) active UMCs bitmask =3D 0x0 Disable PerfMonV2 in CPUID when PERFCORE is disabled. Suggested-by: Zhao Liu Fixes: 209b0ac12074 ("target/i386: Add PerfMonV2 feature bit") Signed-off-by: Dongli Zhang Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Reviewed-by: Sandipan Das --- Changed since v1: - Use feature_dependencies (suggested by Zhao Liu). Changed since v2: - Nothing. Zhao and Xiaoyao may move it to x86_cpu_expand_features() later. target/i386/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1b64ceaaba..2b87331be5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1808,6 +1808,10 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, .to =3D { FEAT_24_0_EBX, ~0ull }, }, + { + .from =3D { FEAT_8000_0001_ECX, CPUID_EXT3_PERFCORE }, + .to =3D { FEAT_8000_0022_EAX, CPUID_8000_0022_EAX_PERFMON_= V2 }, + }, }; =20 typedef struct X86RegisterInfo32 { --=20 2.39.3 From nobody Thu Apr 3 11:53:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1743385049; cv=none; d=zohomail.com; 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h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=fPfXD rOzaHcHS0nz37sj3IHcdYCKyF/+hei62PcUU+U=; b=j48wOII8nGH+cexuKH2Xs hLPeajw/H1B8BcT6ooCuFT41h6R+My4gEZNnI+9jfWXY4518Xky1SUVo10BaAYKL GNGvLmZe7FPXKKcSjAp2p44JqK8CzVxwBT6t/9zibJZwzrR61oOcbaolvPz6yer4 brSzqq8BFTHLERPIdkhlKmp/3zjfKo7H3G/Oearzjp6LiWmG/m9ie4WZn4dBeX7X cjyLcigj4k3FVq3qliFP6ewUkZPKroNhak6C2NaQWcVMc+fkGltazDewMLqb0pwJ k8wSdl9Ay5VqQR1IkKBi3TSoBi5DbZy0N+D60jPbag8ktjrlZoTZGp0t1xMHnkI7 w== From: Dongli Zhang To: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: pbonzini@redhat.com, zhao1.liu@intel.com, mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com, likexu@tencent.com, like.xu.linux@gmail.com, groug@kaod.org, khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com, den@virtuozzo.com, davydov-max@yandex-team.ru, xiaoyao.li@intel.com, dapeng1.mi@linux.intel.com, joe.jin@oracle.com, peter.maydell@linaro.org, gaosong@loongson.cn, chenhuacai@kernel.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, arikalo@gmail.com, npiggin@gmail.com, danielhb413@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, pasic@linux.ibm.com, borntraeger@linux.ibm.com, richard.henderson@linaro.org, david@redhat.com, iii@linux.ibm.com, thuth@redhat.com, flavra@baylibre.com, ewanhai-oc@zhaoxin.com, ewanhai@zhaoxin.com, cobechen@zhaoxin.com, louisqi@zhaoxin.com, liamni@zhaoxin.com, frankzhu@zhaoxin.com, silviazhao@zhaoxin.com Subject: [PATCH v3 02/10] target/i386: disable PERFCORE when "-pmu" is configured Date: Sun, 30 Mar 2025 18:32:21 -0700 Message-ID: <20250331013307.11937-3-dongli.zhang@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250331013307.11937-1-dongli.zhang@oracle.com> References: <20250331013307.11937-1-dongli.zhang@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-30_11,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2502280000 definitions=main-2503310009 X-Proofpoint-ORIG-GUID: 3D6zf21AIxxU6X9rNhPEAsUNEuh37aQA X-Proofpoint-GUID: 3D6zf21AIxxU6X9rNhPEAsUNEuh37aQA Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Currently, AMD PMU support isn't determined based on CPUID, that is, the "-pmu" option does not fully disable KVM AMD PMU virtualization. To minimize AMD PMU features, remove PERFCORE when "-pmu" is configured. To completely disable AMD PMU virtualization will be implemented via KVM_CAP_PMU_CAPABILITY in upcoming patches. As a reminder, neither CPUID_EXT3_PERFCORE nor CPUID_8000_0022_EAX_PERFMON_V2 is removed from env->features[] when "-pmu" is configured. Developers should query whether they are supported via cpu_x86_cpuid() rather than relying on env->features[] in future patches. Suggested-by: Zhao Liu Signed-off-by: Dongli Zhang Reviewed-by: Zhao Liu --- Changed since v2: - No need to check "kvm_enabled() && IS_AMD_CPU(env)". target/i386/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2b87331be5..acbd627f7e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7242,6 +7242,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, !(env->hflags & HF_LMA_MASK)) { *edx &=3D ~CPUID_EXT2_SYSCALL; } + + if (!cpu->enable_pmu) { + *ecx &=3D ~CPUID_EXT3_PERFCORE; + } break; case 0x80000002: case 0x80000003: --=20 2.39.3 From nobody Thu Apr 3 11:53:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1743385105; cv=none; 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h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=0EDp8 /O8chEXYfnRuxO7aZoAWTNGeHerTKEIocr4ftQ=; b=Xt2dEO2zBwlHAIWsTy1fS rSPoaqtQXVzOve+QdzIBU9d/r7sB0uPGOJw73X1eJMWHyX85qpb7ippSDewpa/5h EYbPiWHiXXO25MF3kESaNaSeOl+vN6bEphqcFZjN0Djoi28rLdEhZSOxlquHa5Pw nB0je5Cjp7hGlg2jgZdTlABES6aSZqVoJ6XEAbAQp0DQWlpqtK8IOkjr+6uzgyjF VCe2vRR37khkIjjJdEhp4MElBY6cSC82lPqneya+dSmenLJD+NBXmdgAt91F9LBe i9Y27uk7pzApWvHwbCCBemjbYlt+VpJqdq3Dh+jpnqdhvdRE5sUxSVRTiRsUz3n3 Q== From: Dongli Zhang To: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: pbonzini@redhat.com, zhao1.liu@intel.com, mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com, likexu@tencent.com, like.xu.linux@gmail.com, groug@kaod.org, khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com, den@virtuozzo.com, davydov-max@yandex-team.ru, xiaoyao.li@intel.com, dapeng1.mi@linux.intel.com, joe.jin@oracle.com, peter.maydell@linaro.org, gaosong@loongson.cn, chenhuacai@kernel.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, arikalo@gmail.com, npiggin@gmail.com, danielhb413@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, pasic@linux.ibm.com, borntraeger@linux.ibm.com, richard.henderson@linaro.org, david@redhat.com, iii@linux.ibm.com, thuth@redhat.com, flavra@baylibre.com, ewanhai-oc@zhaoxin.com, ewanhai@zhaoxin.com, cobechen@zhaoxin.com, louisqi@zhaoxin.com, liamni@zhaoxin.com, frankzhu@zhaoxin.com, silviazhao@zhaoxin.com Subject: [PATCH v3 03/10] kvm: Introduce kvm_arch_pre_create_vcpu() Date: Sun, 30 Mar 2025 18:32:22 -0700 Message-ID: <20250331013307.11937-4-dongli.zhang@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250331013307.11937-1-dongli.zhang@oracle.com> References: <20250331013307.11937-1-dongli.zhang@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-30_11,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2502280000 definitions=main-2503310009 X-Proofpoint-ORIG-GUID: lnlui7U5gyxdNAPQm5CLHCemFVHolOb3 X-Proofpoint-GUID: lnlui7U5gyxdNAPQm5CLHCemFVHolOb3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Xiaoyao Li Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent work prior to create any vcpu. This is for i386 TDX because it needs call TDX_INIT_VM before creating any vcpu. The specific implemnet of i386 will be added in the future patch. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann Signed-off-by: Dongli Zhang Reviewed-by: Zhao Liu --- Changed since v2: - Add my Signed-off-by. accel/kvm/kvm-all.c | 5 +++++ include/system/kvm.h | 1 + target/arm/kvm.c | 5 +++++ target/i386/kvm/kvm.c | 5 +++++ target/loongarch/kvm/kvm.c | 5 +++++ target/mips/kvm.c | 5 +++++ target/ppc/kvm.c | 5 +++++ target/riscv/kvm/kvm-cpu.c | 5 +++++ target/s390x/kvm/kvm.c | 5 +++++ 9 files changed, 41 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index f89568bfa3..df9840e53a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -540,6 +540,11 @@ int kvm_init_vcpu(CPUState *cpu, Error **errp) =20 trace_kvm_init_vcpu(cpu->cpu_index, kvm_arch_vcpu_id(cpu)); =20 + ret =3D kvm_arch_pre_create_vcpu(cpu, errp); + if (ret < 0) { + goto err; + } + ret =3D kvm_create_vcpu(cpu); if (ret < 0) { error_setg_errno(errp, -ret, diff --git a/include/system/kvm.h b/include/system/kvm.h index ab17c09a55..d7dfa25493 100644 --- a/include/system/kvm.h +++ b/include/system/kvm.h @@ -374,6 +374,7 @@ int kvm_arch_get_default_type(MachineState *ms); =20 int kvm_arch_init(MachineState *ms, KVMState *s); =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp); int kvm_arch_init_vcpu(CPUState *cpu); int kvm_arch_destroy_vcpu(CPUState *cpu); =20 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index da30bdbb23..93f1a7245b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1874,6 +1874,11 @@ static int kvm_arm_sve_set_vls(ARMCPU *cpu) =20 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6c749d4ee8..f41e190fb8 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2051,6 +2051,11 @@ full: abort(); } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c index 7f63e7c8fe..ed0ddf1cbf 100644 --- a/target/loongarch/kvm/kvm.c +++ b/target/loongarch/kvm/kvm.c @@ -1075,6 +1075,11 @@ static int kvm_cpu_check_pv_features(CPUState *cs, E= rror **errp) return 0; } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { uint64_t val; diff --git a/target/mips/kvm.c b/target/mips/kvm.c index d67b7c1a8e..ec53acb51a 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -61,6 +61,11 @@ int kvm_arch_irqchip_create(KVMState *s) return 0; } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { CPUMIPSState *env =3D cpu_env(cs); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 992356cb75..20fabccecd 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -479,6 +479,11 @@ static void kvmppc_hw_debug_points_init(CPUPPCState *c= env) } } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 4ffeeaa1c9..451c00f17c 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1389,6 +1389,11 @@ static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, C= PUState *cs) return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret =3D 0; diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 4d56e653dd..1f592733f4 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -404,6 +404,11 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu) return cpu->cpu_index; } =20 +int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) +{ + return 0; +} + int kvm_arch_init_vcpu(CPUState *cs) { unsigned int max_cpus =3D MACHINE(qdev_get_machine())->smp.max_cpus; --=20 2.39.3 From nobody Thu Apr 3 11:53:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1743385164; cv=none; d=zohomail.com; s=zohoarc; b=JiaHWXuchEElLrdqfPkuJPiHd4MyRhMLX7uyzkrH4EFjl9uQAzG9R0XdGUMum1N6KD4zGoYacR0zwcytp4/2xdl30on50HPGgV4T/BJ8qqJtHcq7xZWrW8HdyIe+Zo3B1i9iBEgK8kZGQ5BXa+NwMXXaVilwCtEB1hkNqaKVmIQ= ARC-Message-Signature: i=1; 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charset="utf-8" Although AMD PERFCORE and PerfMonV2 are removed when "-pmu" is configured, there is no way to fully disable KVM AMD PMU virtualization. Neither "-cpu host,-pmu" nor "-cpu EPYC" achieves this. As a result, the following message still appears in the VM dmesg: [ 0.263615] Performance Events: AMD PMU driver. However, the expected output should be: [ 0.596381] Performance Events: PMU not available due to virtualization,= using software events only. [ 0.600972] NMI watchdog: Perf NMI watchdog permanently disabled This occurs because AMD does not use any CPUID bit to indicate PMU availability. To address this, KVM_CAP_PMU_CAPABILITY is used to set KVM_PMU_CAP_DISABLE when "-pmu" is configured. Signed-off-by: Dongli Zhang Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu --- Changed since v1: - Switch back to the initial implementation with "-pmu". https://lore.kernel.org/all/20221119122901.2469-3-dongli.zhang@oracle.com - Mention that "KVM_PMU_CAP_DISABLE doesn't change the PMU behavior on Intel platform because current "pmu" property works as expected." Changed since v2: - Change has_pmu_cap to pmu_cap. - Use (pmu_cap & KVM_PMU_CAP_DISABLE) instead of only pmu_cap in if statement. - Add Reviewed-by from Xiaoyao and Zhao as the change is minor. target/i386/kvm/kvm.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index f41e190fb8..579c0f7e0b 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -176,6 +176,8 @@ static int has_triple_fault_event; =20 static bool has_msr_mcg_ext_ctl; =20 +static int pmu_cap; + static struct kvm_cpuid2 *cpuid_cache; static struct kvm_cpuid2 *hv_cpuid_cache; static struct kvm_msr_list *kvm_feature_msrs; @@ -2053,6 +2055,33 @@ full: =20 int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) { + static bool first =3D true; + int ret; + + if (first) { + first =3D false; + + /* + * Since Linux v5.18, KVM provides a VM-level capability to easily + * disable PMUs; however, QEMU has been providing PMU property per + * CPU since v1.6. In order to accommodate both, have to configure + * the VM-level capability here. + * + * KVM_PMU_CAP_DISABLE doesn't change the PMU + * behavior on Intel platform because current "pmu" property works + * as expected. + */ + if ((pmu_cap & KVM_PMU_CAP_DISABLE) && !X86_CPU(cpu)->enable_pmu) { + ret =3D kvm_vm_enable_cap(kvm_state, KVM_CAP_PMU_CAPABILITY, 0, + KVM_PMU_CAP_DISABLE); + if (ret < 0) { + error_setg_errno(errp, -ret, + "Failed to set KVM_PMU_CAP_DISABLE"); + return ret; + } + } + } + return 0; } =20 @@ -3351,6 +3380,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s) } } =20 + pmu_cap =3D kvm_check_extension(s, KVM_CAP_PMU_CAPABILITY); + return 0; } =20 --=20 2.39.3 From nobody Thu Apr 3 11:53:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; 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h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=bsYY7 7sPLtgFVkJTIcaQuh9O11DwYpZxE2oJZPuuUSU=; b=owaWBiZaLoEXFJNDRqBDX OxRRHJmcQnTucL2fcT3zPcwuj836+9dFbA8s+3+AA5J5xDFt7AIDJJaEuARagL1k jkFO49bk6roAThyxjkfHeJ1Scvl2Qc00EEmcVuq0NvL4af8jJrP4I79I0szoWOnA zFdZku0Kfm7DsBTaC36Z9O1CSdcmlbHwTDUGKtsI6GMLi6AapM9O7eS8Cmxoc3VJ cbcAega3V2t5hab32tMh/bdOfcX+5m8An8Ycmq3GrOuXRCQWpTB5bGyTS22xtjoQ n0S8LX/eVn/s+kaUB0rUwE+F45IUEEVOPTVGb9jUb7KMD/7HfnRUcMZa1DaTBaY5 w== From: Dongli Zhang To: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: pbonzini@redhat.com, zhao1.liu@intel.com, mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com, likexu@tencent.com, like.xu.linux@gmail.com, groug@kaod.org, khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com, den@virtuozzo.com, davydov-max@yandex-team.ru, xiaoyao.li@intel.com, dapeng1.mi@linux.intel.com, joe.jin@oracle.com, peter.maydell@linaro.org, gaosong@loongson.cn, chenhuacai@kernel.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, arikalo@gmail.com, npiggin@gmail.com, danielhb413@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, pasic@linux.ibm.com, borntraeger@linux.ibm.com, richard.henderson@linaro.org, david@redhat.com, iii@linux.ibm.com, thuth@redhat.com, flavra@baylibre.com, ewanhai-oc@zhaoxin.com, ewanhai@zhaoxin.com, cobechen@zhaoxin.com, louisqi@zhaoxin.com, liamni@zhaoxin.com, frankzhu@zhaoxin.com, silviazhao@zhaoxin.com Subject: [PATCH v3 05/10] target/i386/kvm: extract unrelated code out of kvm_x86_build_cpuid() Date: Sun, 30 Mar 2025 18:32:24 -0700 Message-ID: <20250331013307.11937-6-dongli.zhang@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250331013307.11937-1-dongli.zhang@oracle.com> References: <20250331013307.11937-1-dongli.zhang@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-30_11,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2502280000 definitions=main-2503310009 X-Proofpoint-GUID: CkD67ufuV0sL4g15oQOWxA2piRFtxYis X-Proofpoint-ORIG-GUID: CkD67ufuV0sL4g15oQOWxA2piRFtxYis Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" The initialization of 'has_architectural_pmu_version', 'num_architectural_pmu_gp_counters', and 'num_architectural_pmu_fixed_counters' is unrelated to the process of building the CPUID. Extract them out of kvm_x86_build_cpuid(). In addition, use cpuid_find_entry() instead of cpu_x86_cpuid(), because CPUID has already been filled at this stage. Signed-off-by: Dongli Zhang --- Changed since v1: - Still extract the code, but call them for all CPUs. Changed since v2: - Use cpuid_find_entry() instead of cpu_x86_cpuid(). - Didn't add Reviewed-by from Dapeng as the change isn't minor. target/i386/kvm/kvm.c | 62 ++++++++++++++++++++++++------------------- 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 579c0f7e0b..4d86c08c6c 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1959,33 +1959,6 @@ static uint32_t kvm_x86_build_cpuid(CPUX86State *env, } } =20 - if (limit >=3D 0x0a) { - uint32_t eax, edx; - - cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); - - has_architectural_pmu_version =3D eax & 0xff; - if (has_architectural_pmu_version > 0) { - num_architectural_pmu_gp_counters =3D (eax & 0xff00) >> 8; - - /* Shouldn't be more than 32, since that's the number of bits - * available in EBX to tell us _which_ counters are available. - * Play it safe. - */ - if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { - num_architectural_pmu_gp_counters =3D MAX_GP_COUNTERS; - } - - if (has_architectural_pmu_version > 1) { - num_architectural_pmu_fixed_counters =3D edx & 0x1f; - - if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNT= ERS) { - num_architectural_pmu_fixed_counters =3D MAX_FIXED_COU= NTERS; - } - } - } - } - cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); =20 for (i =3D 0x80000000; i <=3D limit; i++) { @@ -2085,6 +2058,39 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **= errp) return 0; } =20 +static void kvm_init_pmu_info(struct kvm_cpuid2 *cpuid) +{ + struct kvm_cpuid_entry2 *c; + + c =3D cpuid_find_entry(cpuid, 0xa, 0); + + if (!c) { + return; + } + + has_architectural_pmu_version =3D c->eax & 0xff; + if (has_architectural_pmu_version > 0) { + num_architectural_pmu_gp_counters =3D (c->eax & 0xff00) >> 8; + + /* + * Shouldn't be more than 32, since that's the number of bits + * available in EBX to tell us _which_ counters are available. + * Play it safe. + */ + if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { + num_architectural_pmu_gp_counters =3D MAX_GP_COUNTERS; + } + + if (has_architectural_pmu_version > 1) { + num_architectural_pmu_fixed_counters =3D c->edx & 0x1f; + + if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS)= { + num_architectural_pmu_fixed_counters =3D MAX_FIXED_COUNTER= S; + } + } + } +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { @@ -2267,6 +2273,8 @@ int kvm_arch_init_vcpu(CPUState *cs) cpuid_i =3D kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i); cpuid_data.cpuid.nent =3D cpuid_i; =20 + kvm_init_pmu_info(&cpuid_data.cpuid); + if (((env->cpuid_version >> 8)&0xF) >=3D 6 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) =3D=3D (CPUID_MCE | CPUID_MCA)) { --=20 2.39.3 From nobody Thu Apr 3 11:53:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; 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h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=corp-2023-11-20; bh=F+QHF Jtjx+28JGhYXKrFILOpFgt9z1RkF42hhyzkpYU=; b=iOCveRkn3JgJJcxxBqOwN 6EOFPVD9um8rZLULSgYSwLBtJjfdueLboxG5hGWxqmwV778CW1bRR4DPDzj8azxC 2w/XI34639Nr1tefliNRm+2rFOLvB/6jwLsHtnO7Wa9NjR/ZzBj7RWBgGnpAEzwA oGuuNyOp2BSKfDamVTan05VN+eNMGM/EDPiV8sroQmk+XXq61mqtcj7pdArRvrB7 WVaA09ajWTSC6aK1s7D7viz4LcVIYVnUmBkVH8KY6gnVjdyvpQgjzxl1c8eTA3UE VH7SKbhxX8OG7YNMi6XxcN3seRMYmpSD+DbTcxqEDXXVYVhyttq6fsy5U75xk94F g== From: Dongli Zhang To: qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: pbonzini@redhat.com, zhao1.liu@intel.com, mtosatti@redhat.com, sandipan.das@amd.com, babu.moger@amd.com, likexu@tencent.com, like.xu.linux@gmail.com, groug@kaod.org, khorenko@virtuozzo.com, alexander.ivanov@virtuozzo.com, den@virtuozzo.com, davydov-max@yandex-team.ru, xiaoyao.li@intel.com, dapeng1.mi@linux.intel.com, joe.jin@oracle.com, peter.maydell@linaro.org, gaosong@loongson.cn, chenhuacai@kernel.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, arikalo@gmail.com, npiggin@gmail.com, danielhb413@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, pasic@linux.ibm.com, borntraeger@linux.ibm.com, richard.henderson@linaro.org, david@redhat.com, iii@linux.ibm.com, thuth@redhat.com, flavra@baylibre.com, ewanhai-oc@zhaoxin.com, ewanhai@zhaoxin.com, cobechen@zhaoxin.com, louisqi@zhaoxin.com, liamni@zhaoxin.com, frankzhu@zhaoxin.com, silviazhao@zhaoxin.com Subject: [PATCH v3 06/10] target/i386/kvm: rename architectural PMU variables Date: Sun, 30 Mar 2025 18:32:25 -0700 Message-ID: <20250331013307.11937-7-dongli.zhang@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20250331013307.11937-1-dongli.zhang@oracle.com> References: <20250331013307.11937-1-dongli.zhang@oracle.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-30_11,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 phishscore=0 suspectscore=0 mlxscore=0 malwarescore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2502280000 definitions=main-2503310009 X-Proofpoint-ORIG-GUID: 9Ae6CC4bg6JV-j75qY7lfgliBnoQ10gA X-Proofpoint-GUID: 9Ae6CC4bg6JV-j75qY7lfgliBnoQ10gA Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" AMD does not have what is commonly referred to as an architectural PMU. Therefore, we need to rename the following variables to be applicable for both Intel and AMD: - has_architectural_pmu_version - num_architectural_pmu_gp_counters - num_architectural_pmu_fixed_counters For Intel processors, the meaning of pmu_version remains unchanged. For AMD processors: pmu_version =3D=3D 1 corresponds to versions before AMD PerfMonV2. pmu_version =3D=3D 2 corresponds to AMD PerfMonV2. Signed-off-by: Dongli Zhang Reviewed-by: Dapeng Mi Reviewed-by: Zhao Liu --- Changed since v2: - Change has_pmu_version to pmu_version. - Add Reviewed-by since the change is minor. - As a reminder, there are some contextual change due to PATCH 05, i.e., c->edx vs. edx. target/i386/kvm/kvm.c | 49 ++++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 4d86c08c6c..6b49549f1b 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -164,9 +164,16 @@ static bool has_msr_perf_capabs; static bool has_msr_pkrs; static bool has_msr_hwcr; =20 -static uint32_t has_architectural_pmu_version; -static uint32_t num_architectural_pmu_gp_counters; -static uint32_t num_architectural_pmu_fixed_counters; +/* + * For Intel processors, the meaning is the architectural PMU version + * number. + * + * For AMD processors: 1 corresponds to the prior versions, and 2 + * corresponds to AMD PerfMonV2. + */ +static uint32_t pmu_version; +static uint32_t num_pmu_gp_counters; +static uint32_t num_pmu_fixed_counters; =20 static int has_xsave2; static int has_xcrs; @@ -2068,24 +2075,24 @@ static void kvm_init_pmu_info(struct kvm_cpuid2 *cp= uid) return; } =20 - has_architectural_pmu_version =3D c->eax & 0xff; - if (has_architectural_pmu_version > 0) { - num_architectural_pmu_gp_counters =3D (c->eax & 0xff00) >> 8; + pmu_version =3D c->eax & 0xff; + if (pmu_version > 0) { + num_pmu_gp_counters =3D (c->eax & 0xff00) >> 8; =20 /* * Shouldn't be more than 32, since that's the number of bits * available in EBX to tell us _which_ counters are available. * Play it safe. */ - if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { - num_architectural_pmu_gp_counters =3D MAX_GP_COUNTERS; + if (num_pmu_gp_counters > MAX_GP_COUNTERS) { + num_pmu_gp_counters =3D MAX_GP_COUNTERS; } =20 - if (has_architectural_pmu_version > 1) { - num_architectural_pmu_fixed_counters =3D c->edx & 0x1f; + if (pmu_version > 1) { + num_pmu_fixed_counters =3D c->edx & 0x1f; =20 - if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS)= { - num_architectural_pmu_fixed_counters =3D MAX_FIXED_COUNTER= S; + if (num_pmu_fixed_counters > MAX_FIXED_COUNTERS) { + num_pmu_fixed_counters =3D MAX_FIXED_COUNTERS; } } } @@ -4037,25 +4044,25 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control= _msr); } =20 - if (has_architectural_pmu_version > 0) { - if (has_architectural_pmu_version > 1) { + if (pmu_version > 0) { + if (pmu_version > 1) { /* Stop the counter. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); } =20 /* Set the counter values. */ - for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { + for (i =3D 0; i < num_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, env->msr_fixed_counters[i]); } - for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { + for (i =3D 0; i < num_pmu_gp_counters; i++) { kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, env->msr_gp_counters[i]); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, env->msr_gp_evtsel[i]); } - if (has_architectural_pmu_version > 1) { + if (pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, env->msr_global_status); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, @@ -4515,17 +4522,17 @@ static int kvm_get_msrs(X86CPU *cpu) if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) { kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); } - if (has_architectural_pmu_version > 0) { - if (has_architectural_pmu_version > 1) { + if (pmu_version > 0) { + if (pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); } - for (i =3D 0; i < num_architectural_pmu_fixed_counters; i++) { + for (i =3D 0; i < num_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); } - for (i =3D 0; i < num_architectural_pmu_gp_counters; i++) { + for (i =3D 0; i < num_pmu_gp_counters; i++) { kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } --=20 2.39.3 From nobody Thu Apr 3 11:53:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1743385153; cv=none; d=zohomail.com; s=zohoarc; b=IOwgWtjQuqZMsEcBX6dSQUhKlAdEqCoY1I6sO4Xrv9ygispjWkfe3WAbiVoXl21LyTHfKWcgyA0NdXLOXuMfI3Y7Xnw7+fYS7EEA8hGskahdSuKlJk8OciZxax9yHSJzPMAT5LvzHS/BLGOISzOkQQLAKnBUHaYOYtHjVmjsa0E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1743385153; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" There is no way to distinguish between the following scenarios: (1) KVM_CAP_PMU_CAPABILITY is not supported. (2) KVM_CAP_PMU_CAPABILITY is supported but disabled via the module parameter kvm.enable_pmu=3DN. In scenario (1), there is no way to fully disable AMD PMU virtualization. In scenario (2), PMU virtualization is completely disabled by the KVM module. To help determine the scenario, read the kvm.enable_pmu value from the sysfs module parameter. There isn't any requirement to initialize 'pmu_version', 'num_pmu_gp_counters' or 'num_pmu_fixed_counters', if kvm.enable_pmu=3DN. In addition, return error when kvm.enable_pmu=3DN but the user wants to ena= ble vPMU. Signed-off-by: Dongli Zhang --- Changed since v2: - Rework the code flow following Zhao's suggestion. - Return error when: (*kvm_enable_pmu =3D=3D 'N' && X86_CPU(cpu)->enable_pmu) target/i386/kvm/kvm.c | 36 +++++++++++++++++++++++++++++------- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 6b49549f1b..f68d5a0578 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2051,13 +2051,35 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error *= *errp) * behavior on Intel platform because current "pmu" property works * as expected. */ - if ((pmu_cap & KVM_PMU_CAP_DISABLE) && !X86_CPU(cpu)->enable_pmu) { - ret =3D kvm_vm_enable_cap(kvm_state, KVM_CAP_PMU_CAPABILITY, 0, - KVM_PMU_CAP_DISABLE); - if (ret < 0) { - error_setg_errno(errp, -ret, - "Failed to set KVM_PMU_CAP_DISABLE"); - return ret; + if (pmu_cap) { + if ((pmu_cap & KVM_PMU_CAP_DISABLE) && + !X86_CPU(cpu)->enable_pmu) { + ret =3D kvm_vm_enable_cap(kvm_state, KVM_CAP_PMU_CAPABILIT= Y, 0, + KVM_PMU_CAP_DISABLE); + if (ret < 0) { + error_setg_errno(errp, -ret, + "Failed to set KVM_PMU_CAP_DISABLE"); + return ret; + } + } + } else { + /* + * KVM_CAP_PMU_CAPABILITY is introduced in Linux v5.18. For old + * linux, we have to check enable_pmu parameter for vPMU suppo= rt. + */ + g_autofree char *kvm_enable_pmu; + + /* + * The kvm.enable_pmu's permission is 0444. It does not change= until + * a reload of the KVM module. + */ + if (g_file_get_contents("/sys/module/kvm/parameters/enable_pmu= ", + &kvm_enable_pmu, NULL, NULL)) { + if (*kvm_enable_pmu =3D=3D 'N' && X86_CPU(cpu)->enable_pmu= ) { + error_setg(errp, "Failed to enable PMU since " + "KVM's enable_pmu parameter is disabled"); + return -EPERM; + } } } } --=20 2.39.3 From nobody Thu Apr 3 11:53:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1743385041; cv=none; d=zohomail.com; s=zohoarc; b=HuJhwyf98/m6bmFPxoaieecmdfgGz3DmwqH6S7+5OrjPBwTVwVtoCNi/zxhbPGZ3CH8V4MZ8ReSxbYIvn/n7l+at8jyEuLzX2oX2osbTtH6aWtDXj9Df7aUpdL2HGrMt+a5b+u+Woy9SurGj5tdmbcMTyiStyANfZ5eZrW7eGTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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charset="utf-8" QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM and kvm_put_msrs() to restore them to KVM. However, there is no support for AMD PMU registers. Currently, pmu_version and num_pmu_gp_counters are initialized based on cpuid(0xa), which does not apply to AMD processors. For AMD CPUs, prior to PerfMonV2, the number of general-purpose registers is determined based on the CPU version. To address this issue, we need to add support for AMD PMU registers. Without this support, the following problems can arise: 1. If the VM is reset (e.g., via QEMU system_reset or VM kdump/kexec) while running "perf top", the PMU registers are not disabled properly. 2. Despite x86_cpu_reset() resetting many registers to zero, kvm_put_msrs() does not handle AMD PMU registers, causing some PMU events to remain enabled in KVM. 3. The KVM kvm_pmc_speculative_in_use() function consistently returns true, preventing the reclamation of these events. Consequently, the kvm_pmc->perf_event remains active. 4. After a reboot, the VM kernel may report the following error: [ 0.092011] Performance Events: Fam17h+ core perfctr, Broken BIOS detect= ed, complain to your hardware vendor. [ 0.092023] [Firmware Bug]: the BIOS has corrupted hw-PMU resources (MSR= c0010200 is 530076) 5. In the worst case, the active kvm_pmc->perf_event may inject unknown NMIs randomly into the VM kernel: [...] Uhhuh. NMI received for unknown reason 30 on CPU 0. To resolve these issues, we propose resetting AMD PMU registers during the VM reset process. Signed-off-by: Dongli Zhang --- Changed since v1: - Modify "MSR_K7_EVNTSEL0 + 3" and "MSR_K7_PERFCTR0 + 3" by using AMD64_NUM_COUNTERS (suggested by Sandipan Das). - Use "AMD64_NUM_COUNTERS_CORE * 2 - 1", not "MSR_F15H_PERF_CTL0 + 0xb". (suggested by Sandipan Das). - Switch back to "-pmu" instead of using a global "pmu-cap-disabled". - Don't initialize PMU info if kvm.enable_pmu=3DN. Changed since v2: - Remove 'static' from host_cpuid_vendorX. - Change has_pmu_version to pmu_version. - Use object_property_get_int() to get CPU family. - Use cpuid_find_entry() instead of cpu_x86_cpuid(). - Send error log when host and guest are from different vendors. - Move "if (!cpu->enable_pmu)" to begin of function. Add comments to reminder developers. - Add support to Zhaoxin. Change is_same_vendor() to is_host_compat_vendor(). - Didn't add Reviewed-by from Sandipan because the change isn't minor. TODO: - This patch adds is_host_compat_vendor(), while there are something like is_host_cpu_intel() from target/i386/kvm/vmsr_energy.c. A rework may help move those helpers to target/i386/cpu*. target/i386/cpu.h | 8 ++ target/i386/kvm/kvm.c | 176 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 180 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 76f24446a5..84e497f5d3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -490,6 +490,14 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 +#define MSR_K7_EVNTSEL0 0xc0010000 +#define MSR_K7_PERFCTR0 0xc0010004 +#define MSR_F15H_PERF_CTL0 0xc0010200 +#define MSR_F15H_PERF_CTR0 0xc0010201 + +#define AMD64_NUM_COUNTERS 4 +#define AMD64_NUM_COUNTERS_CORE 6 + #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index f68d5a0578..3a35fd741d 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2087,7 +2087,7 @@ int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **e= rrp) return 0; } =20 -static void kvm_init_pmu_info(struct kvm_cpuid2 *cpuid) +static void kvm_init_pmu_info_intel(struct kvm_cpuid2 *cpuid) { struct kvm_cpuid_entry2 *c; =20 @@ -2120,6 +2120,97 @@ static void kvm_init_pmu_info(struct kvm_cpuid2 *cpu= id) } } =20 +static void kvm_init_pmu_info_amd(struct kvm_cpuid2 *cpuid, X86CPU *cpu) +{ + struct kvm_cpuid_entry2 *c; + int64_t family; + + family =3D object_property_get_int(OBJECT(cpu), "family", NULL); + if (family < 0) { + return; + } + + if (family < 6) { + error_report("AMD performance-monitoring is supported from " + "K7 and later"); + return; + } + + pmu_version =3D 1; + num_pmu_gp_counters =3D AMD64_NUM_COUNTERS; + + c =3D cpuid_find_entry(cpuid, 0x80000001, 0); + if (!c) { + return; + } + + if (!(c->ecx & CPUID_EXT3_PERFCORE)) { + return; + } + + num_pmu_gp_counters =3D AMD64_NUM_COUNTERS_CORE; +} + +static bool is_host_compat_vendor(CPUX86State *env) +{ + char host_vendor[CPUID_VENDOR_SZ + 1]; + uint32_t host_cpuid_vendor1; + uint32_t host_cpuid_vendor2; + uint32_t host_cpuid_vendor3; + + host_cpuid(0x0, 0, NULL, &host_cpuid_vendor1, &host_cpuid_vendor3, + &host_cpuid_vendor2); + + x86_cpu_vendor_words2str(host_vendor, host_cpuid_vendor1, + host_cpuid_vendor2, host_cpuid_vendor3); + + /* + * Intel and Zhaoxin are compatible. + */ + if ((g_str_equal(host_vendor, CPUID_VENDOR_INTEL) || + g_str_equal(host_vendor, CPUID_VENDOR_ZHAOXIN1) || + g_str_equal(host_vendor, CPUID_VENDOR_ZHAOXIN2)) && + (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { + return true; + } + + return env->cpuid_vendor1 =3D=3D host_cpuid_vendor1 && + env->cpuid_vendor2 =3D=3D host_cpuid_vendor2 && + env->cpuid_vendor3 =3D=3D host_cpuid_vendor3; +} + +static void kvm_init_pmu_info(struct kvm_cpuid2 *cpuid, X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + /* + * If KVM_CAP_PMU_CAPABILITY is not supported, there is no way to + * disable the AMD PMU virtualization. + * + * Assume the user is aware of this when !cpu->enable_pmu. AMD PMU + * registers are not going to reset, even they are still available to + * guest VM. + */ + if (!cpu->enable_pmu) { + return; + } + + /* + * It is not supported to virtualize AMD PMU registers on Intel + * processors, nor to virtualize Intel PMU registers on AMD processors. + */ + if (!is_host_compat_vendor(env)) { + error_report("host doesn't support requested feature: vPMU"); + return; + } + + if (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) { + kvm_init_pmu_info_intel(cpuid); + } else if (IS_AMD_CPU(env)) { + kvm_init_pmu_info_amd(cpuid, cpu); + } +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { @@ -2302,7 +2393,7 @@ int kvm_arch_init_vcpu(CPUState *cs) cpuid_i =3D kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i); cpuid_data.cpuid.nent =3D cpuid_i; =20 - kvm_init_pmu_info(&cpuid_data.cpuid); + kvm_init_pmu_info(&cpuid_data.cpuid, cpu); =20 if (((env->cpuid_version >> 8)&0xF) >=3D 6 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) =3D=3D @@ -4066,7 +4157,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control= _msr); } =20 - if (pmu_version > 0) { + if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) && pmu_version > 0)= { if (pmu_version > 1) { /* Stop the counter. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); @@ -4097,6 +4188,38 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_global_ctrl); } } + + if (IS_AMD_CPU(env) && pmu_version > 0) { + uint32_t sel_base =3D MSR_K7_EVNTSEL0; + uint32_t ctr_base =3D MSR_K7_PERFCTR0; + /* + * The address of the next selector or counter register is + * obtained by incrementing the address of the current selector + * or counter register by one. + */ + uint32_t step =3D 1; + + /* + * When PERFCORE is enabled, AMD PMU uses a separate set of + * addresses for the selector and counter registers. + * Additionally, the address of the next selector or counter + * register is determined by incrementing the address of the + * current register by two. + */ + if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE) { + sel_base =3D MSR_F15H_PERF_CTL0; + ctr_base =3D MSR_F15H_PERF_CTR0; + step =3D 2; + } + + for (i =3D 0; i < num_pmu_gp_counters; i++) { + kvm_msr_entry_add(cpu, ctr_base + i * step, + env->msr_gp_counters[i]); + kvm_msr_entry_add(cpu, sel_base + i * step, + env->msr_gp_evtsel[i]); + } + } + /* * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-= add, * only sync them to KVM on the first cpu @@ -4544,7 +4667,8 @@ static int kvm_get_msrs(X86CPU *cpu) if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) { kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); } - if (pmu_version > 0) { + + if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) && pmu_version > 0) { if (pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); @@ -4560,6 +4684,35 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 + if (IS_AMD_CPU(env) && pmu_version > 0) { + uint32_t sel_base =3D MSR_K7_EVNTSEL0; + uint32_t ctr_base =3D MSR_K7_PERFCTR0; + /* + * The address of the next selector or counter register is + * obtained by incrementing the address of the current selector + * or counter register by one. + */ + uint32_t step =3D 1; + + /* + * When PERFCORE is enabled, AMD PMU uses a separate set of + * addresses for the selector and counter registers. + * Additionally, the address of the next selector or counter + * register is determined by incrementing the address of the + * current register by two. + */ + if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE) { + sel_base =3D MSR_F15H_PERF_CTL0; + ctr_base =3D MSR_F15H_PERF_CTR0; + step =3D 2; + } + + for (i =3D 0; i < num_pmu_gp_counters; i++) { + kvm_msr_entry_add(cpu, ctr_base + i * step, 0); + kvm_msr_entry_add(cpu, sel_base + i * step, 0); + } + } + if (env->mcg_cap) { kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0); kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0); @@ -4871,6 +5024,21 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] =3D msrs[i].data; break; + case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL0 + AMD64_NUM_COUNTERS - 1: + env->msr_gp_evtsel[index - MSR_K7_EVNTSEL0] =3D msrs[i].data; + break; + case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR0 + AMD64_NUM_COUNTERS - 1: + env->msr_gp_counters[index - MSR_K7_PERFCTR0] =3D msrs[i].data; + break; + case MSR_F15H_PERF_CTL0 ... + MSR_F15H_PERF_CTL0 + AMD64_NUM_COUNTERS_CORE * 2 - 1: + index =3D index - MSR_F15H_PERF_CTL0; + if (index & 0x1) { + env->msr_gp_counters[index] =3D msrs[i].data; + } else { + env->msr_gp_evtsel[index] =3D msrs[i].data; + } + break; case HV_X64_MSR_HYPERCALL: env->msr_hv_hypercall =3D msrs[i].data; break; --=20 2.39.3 From nobody Thu Apr 3 11:53:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oracle.com ARC-Seal: i=1; a=rsa-sha256; t=1743385041; cv=none; d=zohomail.com; s=zohoarc; b=CSBCqxNBAiZWOE62EJL3XbexgZEgxc9ZBy/hRjgUtBq9nJvhBV7BW/I9WRUsdnG04iyGBgaPmKs8UwVuqoojshIeS/yNBVKuAhigS2IWQuV2Dvu7ou9XXLowQmfNEblqjfXLbnJTZnO9ou+1N/0epUYyxbMKvpS/YtryjMU56UA= ARC-Message-Signature: i=1; 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charset="utf-8" Since perfmon-v2, the AMD PMU supports additional registers. This update includes get/put functionality for these extra registers. Similar to the implementation in KVM: - MSR_CORE_PERF_GLOBAL_STATUS and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS both use env->msr_global_status. - MSR_CORE_PERF_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_CTL both use env->msr_global_ctrl. - MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR both use env->msr_global_ovf_ctrl. No changes are needed for vmstate_msr_architectural_pmu or pmu_enable_needed(). Signed-off-by: Dongli Zhang --- Changed since v1: - Use "has_pmu_version > 1", not "has_pmu_version =3D=3D 2". Changed since v2: - Use cpuid_find_entry() instead of cpu_x86_cpuid(). - Change has_pmu_version to pmu_version. - Cap num_pmu_gp_counters with MAX_GP_COUNTERS. target/i386/cpu.h | 4 ++++ target/i386/kvm/kvm.c | 48 +++++++++++++++++++++++++++++++++++-------- 2 files changed, 43 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 84e497f5d3..ab952ac5ad 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -490,6 +490,10 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 +#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 +#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 +#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 + #define MSR_K7_EVNTSEL0 0xc0010000 #define MSR_K7_PERFCTR0 0xc0010004 #define MSR_F15H_PERF_CTL0 0xc0010200 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 3a35fd741d..f4532e6f2a 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2149,6 +2149,16 @@ static void kvm_init_pmu_info_amd(struct kvm_cpuid2 = *cpuid, X86CPU *cpu) } =20 num_pmu_gp_counters =3D AMD64_NUM_COUNTERS_CORE; + + c =3D cpuid_find_entry(cpuid, 0x80000022, 0); + if (c && (c->eax & CPUID_8000_0022_EAX_PERFMON_V2)) { + pmu_version =3D 2; + num_pmu_gp_counters =3D c->ebx & 0xf; + + if (num_pmu_gp_counters > MAX_GP_COUNTERS) { + num_pmu_gp_counters =3D MAX_GP_COUNTERS; + } + } } =20 static bool is_host_compat_vendor(CPUX86State *env) @@ -4200,13 +4210,14 @@ static int kvm_put_msrs(X86CPU *cpu, int level) uint32_t step =3D 1; =20 /* - * When PERFCORE is enabled, AMD PMU uses a separate set of - * addresses for the selector and counter registers. - * Additionally, the address of the next selector or counter - * register is determined by incrementing the address of the - * current register by two. + * When PERFCORE or PerfMonV2 is enabled, AMD PMU uses a + * separate set of addresses for the selector and counter + * registers. Additionally, the address of the next selector or + * counter register is determined by incrementing the address + * of the current register by two. */ - if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE) { + if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE || + pmu_version > 1) { sel_base =3D MSR_F15H_PERF_CTL0; ctr_base =3D MSR_F15H_PERF_CTR0; step =3D 2; @@ -4218,6 +4229,15 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, sel_base + i * step, env->msr_gp_evtsel[i]); } + + if (pmu_version > 1) { + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, + env->msr_global_status); + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_C= LR, + env->msr_global_ovf_ctrl); + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL, + env->msr_global_ctrl); + } } =20 /* @@ -4695,13 +4715,14 @@ static int kvm_get_msrs(X86CPU *cpu) uint32_t step =3D 1; =20 /* - * When PERFCORE is enabled, AMD PMU uses a separate set of - * addresses for the selector and counter registers. + * When PERFCORE or PerfMonV2 is enabled, AMD PMU uses a separate + * set of addresses for the selector and counter registers. * Additionally, the address of the next selector or counter * register is determined by incrementing the address of the * current register by two. */ - if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE) { + if (num_pmu_gp_counters =3D=3D AMD64_NUM_COUNTERS_CORE || + pmu_version > 1) { sel_base =3D MSR_F15H_PERF_CTL0; ctr_base =3D MSR_F15H_PERF_CTR0; step =3D 2; @@ -4711,6 +4732,12 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, ctr_base + i * step, 0); kvm_msr_entry_add(cpu, sel_base + i * step, 0); } + + if (pmu_version > 1) { + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, 0); + kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, = 0); + } } =20 if (env->mcg_cap) { @@ -5007,12 +5034,15 @@ static int kvm_get_msrs(X86CPU *cpu) env->msr_fixed_ctr_ctrl =3D msrs[i].data; break; case MSR_CORE_PERF_GLOBAL_CTRL: + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: env->msr_global_ctrl =3D msrs[i].data; break; case MSR_CORE_PERF_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: env->msr_global_status =3D msrs[i].data; break; case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: env->msr_global_ovf_ctrl =3D msrs[i].data; break; case MSR_CORE_PERF_FIXED_CTR0 ... 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charset="utf-8" The kvm_put_msrs() sets the MSRs using KVM_SET_MSRS. The x86 KVM processes these MSRs one by one in a loop, only saving the config and triggering the KVM_REQ_PMU request. This approach does not immediately stop the event before updating PMC. In additional, PMU MSRs are set only at levels >=3D KVM_PUT_RESET_STATE, excluding runtime. Therefore, updating these MSRs without stopping events should be acceptable. Finally, KVM creates kernel perf events with host mode excluded (exclude_host =3D 1). While the events remain active, they don't increment the counter during QEMU vCPU userspace mode. No Fixed tag is going to be added for the commit 0d89436786b0 ("kvm: migrate vPMU state"), because this isn't a bugfix. Signed-off-by: Dongli Zhang --- target/i386/kvm/kvm.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 4c3908e09e..d9c6c9905e 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4170,13 +4170,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } =20 if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) && pmu_version > 0)= { - if (pmu_version > 1) { - /* Stop the counter. */ - kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); - } - - /* Set the counter values. */ for (i =3D 0; i < num_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, env->msr_fixed_counters[i]); @@ -4192,8 +4185,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_global_status); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, env->msr_global_ovf_ctrl); - - /* Now start the PMU. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, env->msr_fixed_ctr_ctrl); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, --=20 2.39.3