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From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, antonb@tenstorrent.com,
Max Chou <max.chou@sifive.com>
Subject: [PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to
vector slide instructions(OPIVI/OPIVX)
Date: Sat, 29 Mar 2025 22:44:41 +0800
Message-ID: <20250329144446.2619306-8-max.chou@sifive.com>
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Content-Type: text/plain; charset="utf-8"
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr=
ans/trans_rvv.c.inc
index 2282b89801c..f397ae46446 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -639,7 +639,9 @@ static bool vext_check_slide(DisasContext *s, int vd, i=
nt vs2,
{
bool ret =3D require_align(vs2, s->lmul) &&
require_align(vd, s->lmul) &&
- require_vm(vm, vd);
+ require_vm(vm, vd) &&
+ vext_check_input_eew(s, -1, 0, vs2, s->sew, vm);
+
if (is_over) {
ret &=3D (vd !=3D vs2);
}
--=20
2.43.0