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From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, antonb@tenstorrent.com,
Max Chou <max.chou@sifive.com>
Subject: [PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to
OPIVV/OPFVV(vext_check_sss) instructions
Date: Sat, 29 Mar 2025 22:44:40 +0800
Message-ID: <20250329144446.2619306-7-max.chou@sifive.com>
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Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr=
ans/trans_rvv.c.inc
index 3d02a2f9ec8..2282b89801c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -433,6 +433,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int =
vs, int vm)
static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int =
vm)
{
return vext_check_ss(s, vd, vs2, vm) &&
+ vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
require_align(vs1, s->lmul);
}
=20
--=20
2.43.0