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From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, antonb@tenstorrent.com,
Max Chou <max.chou@sifive.com>
Subject: [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to
OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
Date: Sat, 29 Mar 2025 22:44:39 +0800
Message-ID: <20250329144446.2619306-6-max.chou@sifive.com>
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Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr=
ans/trans_rvv.c.inc
index 4a0c9fbeff3..3d02a2f9ec8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -412,7 +412,9 @@ static bool vext_check_ss(DisasContext *s, int vd, int =
vs, int vm)
{
return require_vm(vm, vd) &&
require_align(vd, s->lmul) &&
- require_align(vs, s->lmul);
+ require_align(vs, s->lmul) &&
+ vext_check_input_eew(s, vs, s->sew, -1, s->sew, vm);
+
}
=20
/*
--=20
2.43.0