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Signed-off-by: Anton Blanchard Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 29 ++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index b9883a5d323..20b1cb127b4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -100,10 +100,33 @@ static bool require_scale_rvfmin(DisasContext *s) } } =20 -/* Destination vector register group cannot overlap source mask register. = */ -static bool require_vm(int vm, int vd) +/* + * Source and destination vector register groups cannot overlap source mask + * register: + * + * A vector register cannot be used to provide source operands with more t= han + * one EEW for a single instruction. A mask register source is considered = to + * have EEW=3D1 for this constraint. An encoding that would result in the = same + * vector register being read with two or more different EEWs, including w= hen + * the vector register appears at different positions within two or more v= ector + * register groups, is reserved. + * (Section 5.2) + * + * A destination vector register group can overlap a source vector + * register group only if one of the following holds: + * 1. The destination EEW equals the source EEW. + * 2. The destination EEW is smaller than the source EEW and the overlap + * is in the lowest-numbered part of the source register group. + * 3. The destination EEW is greater than the source EEW, the source EMUL + * is at least 1, and the overlap is in the highest-numbered part of + * the destination register group. + * For the purpose of determining register group overlap constraints, mask + * elements have EEW=3D1. + * (Section 5.2) + */ +static bool require_vm(int vm, int v) { - return (vm !=3D 0 || vd !=3D 0); + return (vm !=3D 0 || v !=3D 0); } =20 static bool require_nf(int vd, int nf, int lmul) --=20 2.43.0