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[71.42.197.3]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3ff0529511esm410338b6e.46.2025.03.28.10.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 10:55:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1743184530; x=1743789330; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EybSmwG1+RXjmkQtMMdAGfPYVQXdDRNwqAPKK7xa2Q8=; b=EmVlhyg8wA4bt9naE9DnU9LFT8UJTnzytSV9/4MPnEogCrvANdw5NIZbBwYvwk/Y9Y AhTa1KJ0nD18bj3EV098tsjz5auOreaO0iMxpGmp0NP/1GCZYjALc1DOjHMQejc/Nh9U 1OYMfuWeVvASJtWX31ZZGloHAprMEvwdSSMkz6ty7wRQg0FBHstuDx2gwiEVACpvKJQx pXC2w3ZjERf+j71B9MBAsnz6AQIIx9VO6HZa6LqprVgIERbY0FTdQFAAy6SU1xUi/OVA +yG5+GRdzRA/P9SzZebMHoHXRp2FXOyb1Vl4vrQig0bezbI3OOBoTie86Zu+rZGCMnwp hkHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743184530; x=1743789330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EybSmwG1+RXjmkQtMMdAGfPYVQXdDRNwqAPKK7xa2Q8=; b=P0lf1WYKCZF1ngQv4gmJvyrwEbgJxcr7y9cEObfclpTwOIKICGf5OtNWD3ltV5jVyF pMDkvbIywENG+rRyIIr5WnB4kNsh/6JjO6ctEdaRX0J1iKhwba7i+TqMYvsGeoMIhSeO KypcTAXhn2P/9nKcl3kjBeBLEmuT+WK7r3rnshT7QoviYtztzVz1JM6pGm0je3nNlTbh gra5g9imEBEipzPu7zI7k8UdXRLe2G3Q5IP0Nbr6AU423ZeeYzjyLt9UqSWm/Bn2FO6V UjWy73w3gdlSXQQ3K9LYenWYPcMnyiT3E1KOd1U+uAZVyLl2QqIQPC5jIPUgTenIAEmH gCEQ== X-Gm-Message-State: AOJu0Yw7GLV7+SRFa0iTsyCOYmS3CAG/WQ4wFvBAGlqlUNkhkdmhCoPI BUDNuwEBYDxBSUaYhGrO5j2TCDdXL1Q+FrWskabCYVlFLXmkawvSfAuNJ4o5gWgpV4BFZZyhffY j X-Gm-Gg: ASbGncsbkbu+bJ4B+xrSTfQEP+v1hT40KkFz+gsEMrzpDIYt4BNGIsoSo2n1G7D+QN/ BW499zpV3/arrMWM9+gV0QdLSy0lEqbQsNN9GPbss+YMo7nU8jiI5yntciTp0p2UWQI0gyvFp3s G+98ZS5GKhfzkT11YJeQ7xuR6+jkgkzJg6paust2rtEnlZ4oXA1CE7PtS7fMSjYnSbK1XWxpJSd b1307FhHPYAnEZFLM3ODCVbUCTp4VvvOKM0BLbEDw4MQFGDaT9LU/t4C7Jfop/q6O5iQjfcX6T0 9SJ3DxEeClehN+saLLl1rYN5ZOgzzVsmnjFKtigjuHwVnrFVchJFpG1TF7QLQg5rGH9ilMdRaRL jAjDq4oZxY28= X-Google-Smtp-Source: AGHT+IG4N+7WiuvIDandEcPzovNkmXfgq/TcqRVrXpj11lDtQ7xhMGhes7x5ifiW0Ulg+e23iehBtQ== X-Received: by 2002:a05:6808:120a:b0:3f8:3eeb:1192 with SMTP id 5614622812f47-3ff0f60ffd6mr111322b6e.27.1743184530162; Fri, 28 Mar 2025 10:55:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, chenhuacai@kernel.org, jiaxun.yang@flygoat.com, arikalo@gmail.com Subject: [PATCH 1/3] target/mips: Revert TARGET_PAGE_BITS_VARY Date: Fri, 28 Mar 2025 12:55:24 -0500 Message-ID: <20250328175526.368121-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250328175526.368121-1-richard.henderson@linaro.org> References: <20250328175526.368121-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1743184566134019000 Content-Type: text/plain; charset="utf-8" Revert ee3863b9d41 and a08d60bc6c2b. The logic behind changing the system page size because of what the Loongson kernel "prefers" is flawed. In the Loongson-2E manual, section 5.5, it is clear that the cpu supports a 4k page size (along with many others). Therefore we must continue to support a 4k page size. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu-param.h | 5 ----- hw/mips/fuloong2e.c | 1 - hw/mips/loongson3_virt.c | 1 - target/mips/tcg/system/cp0_helper.c | 7 +------ target/mips/tcg/system/tlb_helper.c | 2 +- 5 files changed, 2 insertions(+), 14 deletions(-) diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 11b3ac0ac6..8fcb1b4f5f 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -18,12 +18,7 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #endif -#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 -#else -#define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 -#endif =20 #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 646044e274..2a8507b8b0 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -334,7 +334,6 @@ static void mips_fuloong2e_machine_init(MachineClass *m= c) mc->default_cpu_type =3D MIPS_CPU_TYPE_NAME("Loongson-2E"); mc->default_ram_size =3D 256 * MiB; mc->default_ram_id =3D "fuloong2e.ram"; - mc->minimum_page_bits =3D 14; machine_add_audiodev_property(mc); } =20 diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index db1cc51314..1da20dccec 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -677,7 +677,6 @@ static void loongson3v_machine_class_init(ObjectClass *= oc, void *data) mc->max_cpus =3D LOONGSON_MAX_VCPUS; mc->default_ram_id =3D "loongson3.highram"; mc->default_ram_size =3D 1600 * MiB; - mc->minimum_page_bits =3D 14; mc->default_nic =3D "virtio-net-pci"; } =20 diff --git a/target/mips/tcg/system/cp0_helper.c b/target/mips/tcg/system/c= p0_helper.c index 01a07a169f..8c2114c58a 100644 --- a/target/mips/tcg/system/cp0_helper.c +++ b/target/mips/tcg/system/cp0_helper.c @@ -877,18 +877,13 @@ void update_pagemask(CPUMIPSState *env, target_ulong = arg1, int32_t *pagemask) if ((mask >> maskbits) !=3D 0) { goto invalid; } - /* We don't support VTLB entry smaller than target page */ - if ((maskbits + TARGET_PAGE_BITS_MIN) < TARGET_PAGE_BITS) { - goto invalid; - } env->CP0_PageMask =3D mask << CP0PM_MASK; =20 return; =20 invalid: /* When invalid, set to default target page size. */ - mask =3D (~TARGET_PAGE_MASK >> TARGET_PAGE_BITS_MIN); - env->CP0_PageMask =3D mask << CP0PM_MASK; + env->CP0_PageMask =3D 0; } =20 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index ca4d6b27bc..123639fa18 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -875,7 +875,7 @@ refill: break; } } - pw_pagemask =3D m >> TARGET_PAGE_BITS_MIN; + pw_pagemask =3D m >> TARGET_PAGE_BITS; update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask); pw_entryhi =3D (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF); { --=20 2.43.0