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This patch updates all the said link to point to correct location. Cc: qemu-stable@nongnu.org Cc: qemu-riscv@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808 Signed-off-by: hemanshu.khilari.foss Reviewed-by: Alistair Francis Message-ID: <20250323063404.13206-1-hemanshu.khilari.foss@gmail.com> Signed-off-by: Alistair Francis --- docs/specs/riscv-iommu.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst index 000c7e1f57..991d376fdc 100644 --- a/docs/specs/riscv-iommu.rst +++ b/docs/specs/riscv-iommu.rst @@ -4,7 +4,7 @@ RISC-V IOMMU support for RISC-V machines =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec -version 1.0 `iommu1.0`_. +version 1.0 `iommu1.0.0`_. =20 The emulation includes a PCI reference device (riscv-iommu-pci) and a plat= form bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' @@ -14,7 +14,7 @@ riscv-iommu-pci reference device -------------------------------- =20 This device implements the RISC-V IOMMU emulation as recommended by the se= ction -"Integrating an IOMMU as a PCIe device" of `iommu1.0`_: a PCI device with = base +"Integrating an IOMMU as a PCIe device" of `iommu1.0.0`_: a PCI device wit= h base class 08h, sub-class 06h and programming interface 00h. =20 As a reference device it doesn't implement anything outside of the specifi= cation, @@ -109,7 +109,7 @@ riscv-iommu options: - "s-stage": enabled - "g-stage": enabled =20 -.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/downlo= ad/v1.0/riscv-iommu.pdf +.. _iommu1.0.0: https://github.com/riscv-non-isa/riscv-iommu/releases/down= load/v1.0.0/riscv-iommu.pdf =20 .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tje= znach@rivosinc.com/ =20 --=20 2.48.1