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Subject: [PULL 1/3] docs: Added docs/specs/riscv-iommu.rst in MAINTAINERS
file.
Date: Fri, 28 Mar 2025 16:53:16 +1000
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From: "hemanshu.khilari.foss" <hemanshu.khilari.foss@gmail.com>
Added docs/specs/riscv-iommu.rst under `RISC-V TCG CPUs` section in
in MAINTAINERS file since
`scripts/get_maintainer.pl -f docs/specs/riscv-iommu.rst` doesn't list any
maintainers.
Signed-off-by: hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250323140151.9994-1-hemanshu.khilari.foss@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8f470a1c9b..27f2cfd833 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -319,6 +319,7 @@ L: qemu-riscv@nongnu.org
S: Supported
F: configs/targets/riscv*
F: docs/system/target-riscv.rst
+F: docs/specs/riscv-iommu.rst
F: target/riscv/
F: hw/char/riscv_htif.c
F: hw/riscv/
--=20
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From: Alistair Francis <alistair23@gmail.com>
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Subject: [PULL 2/3] docs/specs/riscv-iommu: Fixed broken link to external risv
iommu document
Date: Fri, 28 Mar 2025 16:53:17 +1000
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From: "hemanshu.khilari.foss" <hemanshu.khilari.foss@gmail.com>
The links to riscv iommu specification document are incorrect. This patch
updates all the said link to point to correct location.
Cc: qemu-stable@nongnu.org
Cc: qemu-riscv@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2808
Signed-off-by: hemanshu.khilari.foss <hemanshu.khilari.foss@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250323063404.13206-1-hemanshu.khilari.foss@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/specs/riscv-iommu.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst
index 000c7e1f57..991d376fdc 100644
--- a/docs/specs/riscv-iommu.rst
+++ b/docs/specs/riscv-iommu.rst
@@ -4,7 +4,7 @@ RISC-V IOMMU support for RISC-V machines
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
=20
QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
-version 1.0 `iommu1.0`_.
+version 1.0 `iommu1.0.0`_.
=20
The emulation includes a PCI reference device (riscv-iommu-pci) and a plat=
form
bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt'
@@ -14,7 +14,7 @@ riscv-iommu-pci reference device
--------------------------------
=20
This device implements the RISC-V IOMMU emulation as recommended by the se=
ction
-"Integrating an IOMMU as a PCIe device" of `iommu1.0`_: a PCI device with =
base
+"Integrating an IOMMU as a PCIe device" of `iommu1.0.0`_: a PCI device wit=
h base
class 08h, sub-class 06h and programming interface 00h.
=20
As a reference device it doesn't implement anything outside of the specifi=
cation,
@@ -109,7 +109,7 @@ riscv-iommu options:
- "s-stage": enabled
- "g-stage": enabled
=20
-.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/downlo=
ad/v1.0/riscv-iommu.pdf
+.. _iommu1.0.0: https://github.com/riscv-non-isa/riscv-iommu/releases/down=
load/v1.0.0/riscv-iommu.pdf
=20
.. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tje=
znach@rivosinc.com/
=20
--=20
2.48.1
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To: qemu-devel@nongnu.org
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Andrea Bolognani <abologna@redhat.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 3/3] Revert "target/riscv/kvm: add missing KVM CSRs"
Date: Fri, 28 Mar 2025 16:53:18 +1000
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From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
This commit breaks KVM boot on older kernels, like reported in [1], due
to senvcfg not being available in them.
There's also another problem related to scounteren. Using a recent
enough guest buildroot, 'ping' will be build with rdtime support. In
this case, doing a ping in a KVM guest while exposing scounteren will
result in an error. The root cause relates to how KVM handles
scounteren, but QEMU can work around it by initializing scounteren with
the host value during init().
Fixing these issues in a non-rushed-bandaid manner results in an amount
of design changes that I don't feel comfortable pushing during code
freeze, so for 10.0 we'll remove the CSRs and re-introduce them in 10.1
with the adequate support.
This reverts commit 4db19d5b21e058e6eb3474b6be470d1184afaa9e.
[1] https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBL=
bLKhfv=3D+jb0SYAw@mail.gmail.com/
Reported-by: Andrea Bolognani <abologna@redhat.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250327152052.707657-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm/kvm-cpu.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 4ffeeaa1c9..0f4997a918 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -624,8 +624,6 @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env)
env->stval =3D 0;
env->mip =3D 0;
env->satp =3D 0;
- env->scounteren =3D 0;
- env->senvcfg =3D 0;
}
=20
static int kvm_riscv_get_regs_csr(CPUState *cs)
@@ -641,8 +639,6 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
- KVM_RISCV_GET_CSR(cs, env, scounteren, env->scounteren);
- KVM_RISCV_GET_CSR(cs, env, senvcfg, env->senvcfg);
=20
return 0;
}
@@ -660,8 +656,6 @@ static int kvm_riscv_put_regs_csr(CPUState *cs)
KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
- KVM_RISCV_SET_CSR(cs, env, scounteren, env->scounteren);
- KVM_RISCV_SET_CSR(cs, env, senvcfg, env->senvcfg);
=20
return 0;
}
--=20
2.48.1